Jim Grosbach
4661d4cac3
Assembly parsing for 2-register sequential variant of VLD2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142691 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 22:21:10 +00:00
Jim Grosbach
b6310316db
Assembly parsing for 4-register variant of VLD1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142682 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 20:35:01 +00:00
Jim Grosbach
cdcfa28056
Assembly parsing for 3-register variant of VLD1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 20:02:19 +00:00
Jim Grosbach
280dfad489
ARM VLD parsing and encoding.
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Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142670 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 18:54:25 +00:00
Owen Anderson
7784f1d2d8
Don't automatically set the "fc" bits on MSR instructions if the user didn't ask for them. This is a divergence from gas' behavior, but it is correct per the documentation and allows us to forge ahead with roundtrip testing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142669 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 18:43:28 +00:00
Jim Grosbach
7926db8268
Nuke an #if0 that got accidentally left in.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142658 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 16:59:08 +00:00
Jim Grosbach
293a5f69fa
whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142657 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 16:56:40 +00:00
Jim Grosbach
fe7b4998c6
Remove some outdated comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142653 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 16:14:12 +00:00
Owen Anderson
cd20c58e98
Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142626 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 22:23:58 +00:00
Owen Anderson
a3a6f215d0
Separate out ARM MSR instructions into M-class versions and AR-class versions. This fixes some roundtripping failures.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142618 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 21:24:38 +00:00
Bill Wendling
767f8be9ee
Add missing operand. <rdar://problem/10313323>
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142615 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 20:37:11 +00:00
Jim Grosbach
01817c39a9
Tidy up. Trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142591 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 17:28:20 +00:00
Jim Grosbach
6b09c77b7a
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 15:04:25 +00:00
Jim Grosbach
d0b614754e
ARM VTBX (one register) assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142581 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 14:48:50 +00:00
Chad Rosier
6690bca623
Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :(
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142557 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 00:07:12 +00:00
James Molloy
cdd8e46bec
Use literal pool loads instead of MOVW/MOVT for materializing global addresses when optimizing for size.
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On spec/gcc, this caused a codesize improvement of ~1.9% for ARM mode and ~4.9% for Thumb(2) mode. This is
codesize including literal pools.
The pools themselves doubled in size for ARM mode and quintupled for Thumb mode, leaving suggestion that there
is still perhaps redundancy in LLVM's use of constant pools that could be decreased by sharing entries.
Fixes PR11087.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142530 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-19 14:11:07 +00:00
Bill Wendling
922ad78776
Make sure we emit the 'movw' and 'movt' only if it's supported. Otherwise, use a constant pool.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142485 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-19 09:24:02 +00:00
Bill Wendling
b677a135ac
Remove some dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142484 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-19 09:04:11 +00:00
Bill Wendling
15a1a226be
Emit the MOVT instruction only if the # LPads is > 64K.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142460 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 23:19:55 +00:00
Bill Wendling
a5871dc104
For Thumb mode, we need to use a constant pool if the value is too large to be
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used with the CMP instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142458 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 23:11:05 +00:00
Jim Grosbach
862019c37f
ARM VTBL (one register) assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142441 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 23:02:30 +00:00
Bill Wendling
85f3a0a4c4
Use the integer compare when the value is small enough. Use the "move into a
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register and then compare against that" method when it's too large. We have to
move the value into the register in the "movw, movt" pair of instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142440 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 22:52:20 +00:00
Bill Wendling
952cb50fee
Use the integer compare when the value is small enough. Use the "move into a
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register and then compare against that" method when it's too large. We have to
move the value into the register in the "movw, movt" pair of instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142437 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 22:49:07 +00:00
Bill Wendling
564392bd3f
The value we're comparing against may be too large for the ARM CMP
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instruction. Move the value into a register and then use that for the CMP.
<rdar://problem/10305266>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142431 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 22:11:18 +00:00
Bill Wendling
b9fecf4e07
The immediate may be too large for the CMP instruction. Move it into a register
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and use that in the CMP.
<rdar://problem/10305266>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142429 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 21:55:58 +00:00
Jim Grosbach
a7d2e759ee
Yet more ARM NEON assembly parsing for the lane index operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142416 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 20:21:17 +00:00
Jim Grosbach
aead579017
ARM vmla/vmls assembly parsing for the lane index operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142413 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 20:14:56 +00:00
Jim Grosbach
687656c630
ARM vmov assembly parsing for the lane index operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142412 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 20:10:47 +00:00
Andrew Trick
90b7b12f01
Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns.
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Clean up the patterns, fix comments, and avoid confusing both tools
and coders. Note that the special adds/subs SelectionDAG nodes no
longer have the dummy cc_out operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142397 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 19:18:52 +00:00
Bob Wilson
9d45de252c
Use isIntN and isUIntN to check for valid signed/unsigned numbers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142395 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 18:46:49 +00:00
Andrew Trick
7f5f0dae33
whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142394 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 18:40:53 +00:00
Bill Wendling
f7b0207f1e
A landing pad could have more than one predecessor. In that case, we want that
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predecessor to remove the jump to it as well. Delay clearing the 'landing pad'
flag until after the jumps have been removed. (There is an implicit assumption
in several modules that an MBB which jumps to a landing pad has only two
successors.)
<rdar://problem/10304224>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142390 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 18:30:49 +00:00
Jim Grosbach
9120088979
ARM vmla/vmls assembly parsing for the lane index operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142389 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 18:27:07 +00:00
Jim Grosbach
0a0374018f
ARM vqdmulh assembly parsing for the lane index operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142386 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 18:12:09 +00:00
Jim Grosbach
970f787a7e
ARM vmul assembly parsing for the lane index operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142381 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 18:01:52 +00:00
Bob Wilson
ad952ad8f0
Fix incorrect check for sign-extended constant BUILD_VECTOR.
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<rdar://problem/10298332>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142371 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 17:34:51 +00:00
Jim Grosbach
e873d2a148
ARM vqdmlal assembly parsing for the lane index operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142365 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 17:16:30 +00:00
Jim Grosbach
9858a48afc
Thumb2 parsing of 'mov.w' gets the cc_out operand wrong. Add an alias for it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142363 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 17:09:35 +00:00
Jim Grosbach
f2f5bc60f6
ARM assembly parsing and encoding for VMOV.i64.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142356 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 16:18:11 +00:00
Duncan Sands
17001ce25c
Fix a bunch of unused variable warnings when doing a release
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build with gcc-4.6.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142350 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 12:44:00 +00:00
David Meyer
928698b14e
Remove NaClMode
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142338 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 05:29:23 +00:00
Chad Rosier
fe04757f5e
Add support for dynamic stack realignment when in thumb1 mode.
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rdar://10288916
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142337 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 05:28:00 +00:00
Joe Abbey
895ede819f
Commit test, capitalizing store... keep it simple.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142336 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 04:44:36 +00:00
Eli Friedman
0851a29b6d
Fix misc warnings. Patch by Joe Abbey.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142332 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 03:17:34 +00:00
Jim Grosbach
6248a546f2
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142321 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 00:22:00 +00:00
Jim Grosbach
ea46110f57
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142303 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 23:09:09 +00:00
Chad Rosier
3a7572ff61
Add a few FIXME comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142299 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 22:54:23 +00:00
Jim Grosbach
fa1ee88052
Tidy up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142297 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 22:41:42 +00:00
Bill Wendling
13a7121858
Now Igor, throw the switch...give my creation life!
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Use the custom inserter for the ARM setjmp intrinsics. Instead of creating the
SjLj dispatch table in IR, where it frequently violates serveral assumptions --
in particular assumptions made by the landingpad instruction about what can
branch to a landing pad and what cannot. Performing this in the back-end allows
us to violate these assumptions without the IR getting angry at us.
It also allows us to perform a small optimization. We can shove the address of
the dispatch's basic block into the function context and not have to add code
around the setjmp to check for the return value and jump to the dispatch.
Neat, huh?
<rdar://problem/10116753>
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2011-10-17 22:26:23 +00:00
Jim Grosbach
0e387b2877
ARM NEON "vmov.i8" immediate assembly parsing and encoding.
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NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142293 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 22:26:03 +00:00
Bill Wendling
a48ed4fc8f
Don't renumber the blocks here. This could cause problems later on if another
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pass renumbers the blocks again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142258 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 21:32:56 +00:00
Cameron Zwarich
6f9c28060f
Pseudoinstructions should not be less constrained than the instruction they are
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lowered to. This fixes a lot of verifier failures on the test suite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142254 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 21:20:13 +00:00
Jim Grosbach
698f3b068f
Tidy up organization.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142248 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 21:00:11 +00:00
Bill Wendling
5bc85286ff
Add a call to EmitSjLjDispatchBlock.
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Once the intrinsics are marked as having a custom inserter, it will call this
method to emit the dispatch table into the machine function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142245 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 20:37:20 +00:00
Chad Rosier
c378015d1c
Removed set, but unused variables.
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Patch by Joe Abbey <jabbey@arxan.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142223 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 18:48:30 +00:00
Michael J. Spencer
9904056a70
Fix CMake build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142204 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 17:50:39 +00:00
Devang Patel
827454e6e2
svn mv Target/ARM/ARMGlobalMerge.cpp Transforms/Scalar/GlobalMerge.cpp
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There is no reason to have simple IR level pass in lib/Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142200 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 17:17:43 +00:00
Bill Wendling
24bb925566
Add comment explaining that the order of processing doesn't matter here.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142176 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 05:25:09 +00:00
Cameron Zwarich
daada347b5
Add flags on Thumb2 indexed stores paralleling the flags on the indexed loads.
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These missing flags show up as errors when running -verify-coalescing on
test-suite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142111 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 06:38:10 +00:00
Cameron Zwarich
d575137634
Fix an obvious typo found when looking at nearby code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142110 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 06:38:06 +00:00
Nadav Rotem
004a24b44c
ARM cannot select a pattern for trunc-store v4i8; /ARM/vrev.ll fails when promoting elements.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142080 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15 20:03:12 +00:00
Jakob Stoklund Olesen
534849687c
Mark tADDrSPi as having side effects again.
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It really doesn't, but when r141929 removed the hasSideEffects flag from
this instruction, it caused miscompilations. I am guessing that it got
moved across a stack pointer update.
Also clear isRematerializable after checking that this instruction is
in fact never rematerialized in the nightly test suite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142030 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15 00:57:13 +00:00
Chad Rosier
d73462a1c9
Thumb1 does not support dynamic stack realignment.
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rdar://10288916 is tracking this fix.
In the past, instcombine and other passes were promoting alloca alignment past
the natural alignment, resulting in dynamic stack realignment. Lang's work now
prevents this from happening (LLVM commit r141599). Now that this really
shouldn't happen report a fatal error rather than silently generate bad code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142028 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15 00:28:24 +00:00
Bill Wendling
918f2155e9
Mark registers as DEAD because they're really just clobbers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142027 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15 00:27:44 +00:00
Eli Friedman
46995fa7e2
Add missing correctness check to ARMTargetLowering::ReconstructShuffle. Fixes PR11129.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142022 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 23:58:49 +00:00
Bill Wendling
5d79859f66
Make sure that the register is in the register class before adding it as a machine op.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142021 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 23:55:44 +00:00
Bill Wendling
969c9ef0dd
Mark the invoke call instruction as implicitly defining the callee-saved registers.
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The callee-saved registers cannot be live across an invoke call because the
control flow may continue along the exceptional edge. When this happens, all of
the callee-saved registers are no longer valid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142018 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 23:34:37 +00:00
Richard Trieu
8223e45dff
Fix a non-firing assert. Change:
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assert("bad SymbolicOp.VariantKind");
To:
assert(0 && "bad SymbolicOp.VariantKind");
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142000 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 20:50:26 +00:00
Jakob Stoklund Olesen
ccbe603869
Ban rematerializable instructions with side effects.
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TableGen infers unmodeled side effects on instructions without a
pattern. Fix some instruction definitions where that was overlooked.
Also raise an error if a rematerializable instruction has unmodeled side
effects. That doen't make any sense.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141929 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 01:00:49 +00:00
Eli Friedman
ecb830e45c
Fix undefined shift. Patch by Ahmed Charles.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141914 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 23:36:06 +00:00
Eli Friedman
8e4d0429de
Simplify and avoid undefined shift. Based on patch by Ahmed Charles.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141903 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 22:40:23 +00:00
Owen Anderson
c18e940c5a
SETEND is not allowed in an IT block.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141874 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 17:58:39 +00:00
Jim Grosbach
81b2928d80
ARM addrmode5 represents the 'U' bit of the encoding backwards.
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The disassembler needs to use the AM5 factory methods instead of just
building up the immediate directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141819 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 21:59:02 +00:00
Jim Grosbach
c66e7afcf2
Thumb2 assembly parsing and encoding for LDC/STC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141811 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 20:54:17 +00:00
Jim Grosbach
b0786b33fa
addrmode2 is gone from these, so no need for the reg0 operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141794 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 18:11:24 +00:00
Jim Grosbach
9b8f2a0b36
ARM parsing and encoding for the <option> form of LDC/STC instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141786 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 17:34:41 +00:00
Jim Grosbach
01208d56e8
80 columns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141781 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 16:36:01 +00:00
Jim Grosbach
bc9c80240b
Tidy up. Formatting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141780 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 16:34:37 +00:00
Jakob Stoklund Olesen
1c062c24ab
Fix -widen-vmovs liveness issues.
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When widening a copy, we are reading a larger register that may not be
live. Use an <undef> flag to tell the register scavenger and machine
code verifier that we know the value isn't defined.
We now widen:
%S6<def> = COPY %S4<kill>, %D3<imp-def>
into:
%D3<def> = VMOVD %D2<undef>, pred:14, pred:%noreg, %S4<imp-use,kill>
This also keeps the <kill> flag on %S4 so we don't inadvertently kill a
live value in %S5.
Finally, ensure that ARMBaseInstrInfo::setExecutionDomain() preserves
the <undef> flag when converting VMOVD to VORR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141746 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 00:06:23 +00:00
Jim Grosbach
2bd0118472
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions.
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Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141721 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 21:55:36 +00:00
Bill Wendling
e575499d83
Revert r141529. This is causing failures in the test-suite, like bigstack and ReedSolomon. Boo...
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141716 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 21:40:47 +00:00
Jim Grosbach
2cf8dd384e
ARM addressing mode cleanup for LDC/STC.
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We parse at least some forms of the instructions now. Encoding is
pretty screwed up, still, though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141704 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 20:17:35 +00:00
Jim Grosbach
57dcb85a30
ARM parse alignment specifier for NEON load/store instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141682 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 17:29:55 +00:00
Jim Grosbach
e53c87b302
ARM Rename operand sub-structure 'Mem' to 'Memory' for a bit more clarity.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141671 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 15:59:20 +00:00
Jakob Stoklund Olesen
142bd1a54e
Move -widen-vmovs to ARMBaseInstrInfo::expandPostRAPseudo().
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The VMOVS widening needs to look at the implicit COPY operands. Trying
to dig out the COPY instruction from an iterator in copyPhysReg() is the
wrong approach.
The expandPostRAPseudo() hook gets to look at COPY instructions before
they are converted to copyPhysReg() calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141619 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 00:59:06 +00:00
Bill Wendling
3f56d4b957
Simplify check that optional def is there and is CPSR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141602 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 00:10:41 +00:00
Lang Hames
bb5b3f3359
Add a natural stack alignment field to TargetData, and prevent InstCombine from
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promoting allocas to preferred alignments that exceed the natural
alignment. This avoids some potentially expensive dynamic stack realignments.
The natural stack alignment is set in target data strings via the "S<size>"
option. Size is in bits and must be a multiple of 8. The natural stack alignment
defaults to "unspecified" (represented by a zero value), and the "unspecified"
value does not prevent any alignment promotions. Target maintainers that care
about avoiding promotions should explicitly add the "S<size>" option to their
target data strings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141599 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 23:42:08 +00:00
Jim Grosbach
f6c35c59f5
Simplify operand Kind checks a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141592 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 23:06:42 +00:00
Bill Wendling
ef2c86f876
Reapply r141365 now that PR11107 is fixed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141591 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 22:59:55 +00:00
Jim Grosbach
38fbe32315
Add a name to sub-operand for clarity.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141590 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 22:55:05 +00:00
Bill Wendling
721e1d2669
If the CPSR is defined by a copy, then we don't want to merge it into an IT
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block. E.g., if we have:
movs r1, r1
rsb r1, 0
movs r2, r2
rsb r2, 0
we don't want this to be converted to:
movs r1, r1
movs r2, r2
itt mi
rsb r1, 0
rsb r2, 0
PR11107 & <rdar://problem/10259534>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141589 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 22:52:53 +00:00
Bill Wendling
eba564ceac
Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to
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hang, and possibly SPEC/CINT2006/464_h264ref.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141560 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 18:27:30 +00:00
Bill Wendling
8129d21396
When getting the number of bits necessary for addressing mode
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ARMII::AddrModeT1_s, we need to take into account that if the frame register is
ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of
bits is 5.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141529 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 07:24:23 +00:00
Chad Rosier
29b9d7e4ea
Fix a regression from r138445. If we're loading from the frame/base pointer
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the tADDrSPi instruction can't be used. Make sure we're updating the opcode
to tADDi3 in all cases.
rdar://10254707
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141523 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 01:03:35 +00:00
Anton Korobeynikov
2d4b60f3a4
Disable ABS optimization for Thumb1 target, we don't have necessary instructions there.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141481 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 08:38:45 +00:00
Jim Grosbach
460a90540b
ARM NEON assembly parsing and encoding for VDUP(scalar).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141446 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 23:56:00 +00:00
Jim Grosbach
21ff17ce1b
ARM prefix asmparser operand kind enums for readability.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141438 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 23:24:09 +00:00
Bill Wendling
2acf638216
Take all of the invoke basic blocks and make the dispatch basic block their new
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successor. Remove the old landing pad from their successor list, because it's
now the successor of the dispatch block. Now that the landing pad blocks are no
longer the destination of invokes, we can mark them as normal basic blocks
instead of landing pads.
This more closely resembles what the CFG is actually doing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141436 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 23:18:02 +00:00
Bill Wendling
f1083d4139
Take the code that was emitted for the llvm.eh.dispatch.setup intrinsic and emit
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it with the new SjLj emitter stuff. This way there's no need to emit that
kind-of-hacky intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141419 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 22:08:37 +00:00
Bill Wendling
ce370cfd89
Thread the chain through the eh.sjlj.setjmp intrinsic, like it's documented to
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do. This will be useful later on with the new SJLJ stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141416 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 21:25:38 +00:00
Jim Grosbach
186ffac4d3
Improve ARM assembly parser diagnostic for unexpected tokens.
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Consider:
mov r8, r11 fred
Previously, we issued the not very informative:
x.s:6:1: error: unexpected token in argument list
^
Now we generate:
x.s:5:14: error: unexpected token in argument list
mov r8, r11 fred
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141380 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 18:27:04 +00:00
Bob Wilson
6d2f9cec71
Reenable tail calls for iOS 5.0 and later.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141370 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 17:17:49 +00:00
Bob Wilson
2fef4573df
Reenable use of divmod compiler_rt functions for iOS 5.0 and later.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141368 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 16:59:21 +00:00
Anton Korobeynikov
244455e6d6
Peephole optimization for ABS on ARM.
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Patch by Ana Pazos!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141365 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 16:15:08 +00:00
Bill Wendling
217f0e9ca4
Use the correct vreg here.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141342 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 23:41:14 +00:00
Bill Wendling
083a8eb063
Generate the dispatch code for a 'thumb' function. This is very similar to the
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others. They take the call site value. Determine if it's a proper value. And
then jumps to the correct call site via a jump table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141341 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 23:37:36 +00:00
Owen Anderson
7011eee9b5
Fix the check for nested IT instructions in the disassembler. We need to perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141339 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 23:33:11 +00:00
Bill Wendling
95ce2e9c52
Generate the dispatch table for ARM mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141327 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 22:53:00 +00:00
Bill Wendling
e29fa1df55
Refactor some of the code that sets up the entry block for SjLj EH. No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141323 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 22:18:16 +00:00
Bill Wendling
5e2cbc1133
Use a thumb ORR instead of thumb2 ORR when in thumb-only mode. (Picky! Picky!)
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Place the immediate to OR into a register so that it works.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141319 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 21:51:21 +00:00
Bill Wendling
04f15b4f2f
* Set the low bit of the return address when we are in thumb mode.
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* Some code cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141317 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 21:29:56 +00:00
Peter Collingbourne
de8f33c199
Build system infrastructure for multiple tblgens.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141266 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 01:51:51 +00:00
Bill Wendling
930193cb55
Add the MBBs before inserting the instructions. Doing it afterwards could lead
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to an infinite loop because of the def-use chains.
Also use a frame load instead of store for the LD instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141263 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 00:53:33 +00:00
Cameron Zwarich
8f8aa815b4
Always merge profitable shifts on A9, not just when they have a single use.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141248 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05 23:39:02 +00:00
Cameron Zwarich
d78ebe1e12
Remove a check from ARM shifted operand isel helper methods, which were blocking
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merging an lsl #2 that has multiple uses on A9. This shift is free, so there is
no problem merging it in multiple places. Other unprofitable shifts will not be
merged.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141247 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05 23:38:50 +00:00
Bill Wendling
5cbef19a1d
Get the proper call site numbers for the landing pads. Also remove a magic
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number (18) for the proper addressing mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141245 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05 23:28:57 +00:00
Owen Anderson
2dbb46a0a0
Support a valid, but not very useful, encoding of CPSIE where none of the AIF bits are set.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141190 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05 17:16:40 +00:00
Cameron Zwarich
fb77752253
Add braces around something that throws me for a loop.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141173 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05 08:59:10 +00:00
Cameron Zwarich
5ee0262014
There is no point in setting out-parameters for a ComplexPattern function when
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it returns false, at least as far as I could tell by reading the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141172 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05 08:59:05 +00:00
Bill Wendling
bb73468e2b
Look at the number of entries in the jump table and jump to a 'trap' block if
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the value exceeds that number.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141143 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05 00:39:32 +00:00
Bill Wendling
2a85015313
Checkpoint for SJLJ EH code.
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This is a first pass at generating the jump table for the sjlj dispatch. It
currently generates something plausible, but hasn't been tested thoroughly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141140 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05 00:02:33 +00:00
Owen Anderson
2fec6c5ff1
Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141135 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 23:26:17 +00:00
Kevin Enderby
9e5887b17e
Adding back support for printing operands symbolically to ARM's new disassembler
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using llvm's public 'C' disassembler API now including annotations.
Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
blx _puts
instead of this:
blx #-36
and includes support for annotations for branches to symbol stubs like:
bl 0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
ldr r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
movt r0, :upper16:((_foo-_bar)+1234)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141129 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 22:44:48 +00:00
Jim Grosbach
9d39036f62
ARM assembly parsing and encoding for VMOV immediate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141046 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 23:38:36 +00:00
Jim Grosbach
2a3f19d7e3
Tidy up. 80 columns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141043 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 23:03:26 +00:00
Bill Wendling
ff4216a68a
Use the PC label ID rather than '1'. Add support for thumb-2, because I heard that some people use it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141042 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 22:44:15 +00:00
Jim Grosbach
68259145d9
ARM parsing/encoding for VCMP/VCMPE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141038 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 22:30:24 +00:00
Bill Wendling
f7e4aefd0f
Check-pointing the new SjLj EH lowering.
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This code will replace the version in ARMAsmPrinter.cpp. It creates a new
machine basic block, which is the dispatch for the return from a longjmp
call. It then shoves the address of that machine basic block into the correct
place in the function context so that the EH runtime will jump to it directly
instead of having to go through a compare-and-jump-to-the-dispatch bit. This
should be more efficient in the common case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141031 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 21:25:38 +00:00
Jim Grosbach
5cd5ac6ad4
ARM assembly parsing and encoding for VMRS/FMSTAT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141025 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 21:12:43 +00:00
Jim Grosbach
b95ed6ec46
Thumb2 ADD/SUB can take SP as a destination register.
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It's documented as a separate instruction to line up with the Thumb1
encodings, for which it really is a distinct instruction encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141020 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 20:51:59 +00:00
Chad Rosier
2bfaf521ae
Revert r140924 "Attempt to fix dynamic stack realignment for thumb1 functions."
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to appease nightly testers. Not quite there yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140953 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 19:30:36 +00:00
Bill Wendling
2e6b97bbf8
No one should be using the method directly. Assert if they do.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140947 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 12:47:34 +00:00
Bill Wendling
405ca137a1
Add a convenience method to tell if two things are equal.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140946 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 12:44:28 +00:00
Bill Wendling
3320f2a3bf
Use the ARMConstantPoolMBB class to handle the MBB values.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140943 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 09:30:42 +00:00
Bill Wendling
9c18f51daa
Add ARMConstantPoolMBB to hold an MBB value in the constant pool.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140942 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 09:19:10 +00:00
Bill Wendling
14a1a6b018
Remove dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140941 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 09:05:12 +00:00
Bill Wendling
9aca75c4f8
Remove now dead methods and ivar.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140940 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 09:04:18 +00:00
Bill Wendling
fe31e67350
Use the new ARMConstantPoolSymbol class to handle external symbols.
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2011-10-01 08:58:29 +00:00
Bill Wendling
ff4a8023ec
Add an ARMConstantPool class for external symbols. This will split out the support for external symbols from the base class.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140938 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 08:36:59 +00:00
Bill Wendling
3f4e4592c3
Remove now dead methods and ivar from ARMConstantPoolValue.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140937 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 08:02:05 +00:00
Bill Wendling
5bb779976a
Switch over to using ARMConstantPoolConstant for global variables, functions,
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and block addresses.
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2011-10-01 08:00:54 +00:00
Bill Wendling
3e944e38ea
Some more refactoring.
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* Add a couple of Create methods to the ARMConstantPoolConstant class,
* Add its own version of getExistingMachineCPValue, and
* Modify hasSameValue to return false if the object isn't an ARMConstantPoolConstant.
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2011-10-01 07:52:37 +00:00
Bill Wendling
029e93888d
Add a Create method that accepts 'kind' and 'pcadj' arguments.
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2011-10-01 06:44:24 +00:00
Bill Wendling
f2b76aae2b
Refactoring: Separate out the ARM constant pool Constant from the ARM constant
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pool value.
It's not used right now, but will be soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140933 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 06:40:33 +00:00
Chad Rosier
5249041125
Attempt to fix dynamic stack realignment for thumb1 functions. It is in fact
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useful if an optimization assumes the stack has been realigned. Credit to
Eli for his assistance.
rdar://10043857
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2011-10-01 02:03:18 +00:00
Jakob Stoklund Olesen
c8e2bb68bb
Store sub-class lists as a bit vector.
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This uses less memory and it reduces the complexity of sub-class
operations:
- hasSubClassEq() and friends become O(1) instead of O(N).
- getCommonSubClass() becomes O(N) instead of O(N^2).
In the future, TableGen will infer register classes. This makes it
cheap to add them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140898 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 22:19:07 +00:00
Jim Grosbach
f391e9f696
Correct for my over-eager delete finger.
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2011-09-30 22:02:45 +00:00
Bill Wendling
d98f838284
Constify 'isLSDA' and move a method out-of-line.
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2011-09-30 18:42:06 +00:00
Jim Grosbach
6f09fcf5da
ARM Darwin default relocation model is PIC.
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This matches clang, so default options in llc and friends are now closer to
clang's defaults.
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2011-09-30 17:41:35 +00:00
Jim Grosbach
98602ac9a9
ARM Fixup valus for movt/movw are for the whole value.
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Remove an assert that was expecting only the relevant 16bit portion for
the fixup being handled. Also kill some dead code in the T2 portion.
rdar://9653509
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2011-09-30 17:23:05 +00:00
Jim Grosbach
4ebbf7b8a8
ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.
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Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.
rdar://10211428
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2011-09-30 00:50:06 +00:00
Bill Wendling
e00897c5a9
Create a machine basic block in the constant pool and retrieve the symbol for an MBB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140824 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 23:50:42 +00:00
Bill Wendling
4dd9b091cc
Support creating a constant pool value for a machine basic block.
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This is used when we want to take the address of a machine basic block, but it's
not associated with a BB in LLVM IR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140823 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 23:48:44 +00:00
NAKAMURA Takumi
13f4a6c940
Target/ARM: Unbreak! CMake! Build!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140774 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 03:32:49 +00:00
Jakob Stoklund Olesen
adcb634d85
Delete NEONMoveFix, now unused.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140773 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 02:56:45 +00:00
Jakob Stoklund Olesen
8bb3d3cb30
Use ExecutionDepsFix instead of NEONMoveFix.
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This enables NEON domain tracking across basic blocks, but should
otherwise do the same thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140772 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 02:48:41 +00:00
Bill Wendling
3511cedf36
Move to ISelLowering.
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2011-09-29 01:13:55 +00:00
Evan Cheng
9b88d2d782
Tighten a ARM dag combine condition to avoid an identity transformation, which
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ends up introducing a cycle in the DAG.
rdar://10196296
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2011-09-28 23:16:31 +00:00
Bill Wendling
b18abd077e
Perform the lowering only if there are invokes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140719 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 20:29:45 +00:00
Bill Wendling
39689c8154
Ahem...actually *add* the ARMSjLjLowering pass to the pass manager.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140718 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 20:29:28 +00:00
James Molloy
acad68da50
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
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Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.
Add decoder and disassembler tests.
Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 14:21:38 +00:00
Ted Kremenek
833217bfb9
Unbreak CMake build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140655 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 23:29:59 +00:00
Jakob Stoklund Olesen
13fd601e0f
Implement TII::get/setExecutionDomain() for ARM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140653 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 22:57:21 +00:00
Jim Grosbach
25ddc2bf7e
ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w.
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Add inst alias to handle these assembly forms. Add tests, too.
rdar://10178799
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2011-09-27 22:18:54 +00:00
Bill Wendling
0481d29d49
This is the start of the new SjLj EH preparation pass, which will replace the
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current IR-level pass.
The old SjLj EH pass has some problems, especially with the new EH model. Most
significantly, it violates some of the new restrictions the new model has. For
instance, the 'dispatch' table wants to jump to the landing pad, but we cannot
allow that because only an invoke's unwind edge can jump to a landing pad. This
requires us to mangle the code something awful. In addition, we need to keep the
now dead landingpad instructions around instead of CSE'ing them because the
DWARF emitter uses that information (they are dead because no control flow edge
will execute them - the control flow edge from an invoke's unwind is superceded
by the edge coming from the dispatch).
Basically, this pass belongs not at the IR level where SSA is king, but at the
code-gen level, where we have more flexibility.
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2011-09-27 22:14:12 +00:00
Jim Grosbach
5405d58e21
Rename AddSelectionDAGCSEId() to addSelectionDAGCSEId().
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Naming conventions consistency. No functional change.
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2011-09-27 20:59:33 +00:00
Jakob Stoklund Olesen
8e695eb5fa
Use existing function.
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2011-09-27 17:55:08 +00:00
Owen Anderson
2dafe200ca
Remove extraneous commit garbage.
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2011-09-26 23:14:02 +00:00
Owen Anderson
0afa0094af
ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140560 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 21:06:22 +00:00
David Meyer
8f418b11d2
PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL 2011-06-09-TailCallByVal and 2010-11-04-BigByval
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140516 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 06:13:20 +00:00
Owen Anderson
4d2a00147d
Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset of #-0.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140426 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 22:25:02 +00:00
Jakob Stoklund Olesen
11ebe3d7c1
Also match negative offsets for addrmode3 and addrmode5.
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Math is hard, and isScaledConstantInRange() always returned false for
negative constants. It was doing unsigned division of negative numbers
before casting back to signed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140425 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 22:10:33 +00:00
Owen Anderson
4a713570b6
Add more fixed bits to USAT16 encoding to filter out incorrect decodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140422 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 21:57:50 +00:00
Owen Anderson
0781c1f700
Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140420 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 21:26:40 +00:00
Owen Anderson
31d485ec9a
Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140415 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 21:07:25 +00:00
Owen Anderson
df0caeb6ec
Revert r140412. This affects more instructions than intended.
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2011-09-23 21:02:01 +00:00
Owen Anderson
d256056581
Thumb2 register-shifted-register loads cannot target the PC or the SP.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140412 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 21:00:32 +00:00
Owen Anderson
6126870193
Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused.
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2011-09-21 23:53:44 +00:00
Owen Anderson
e136872970
Print out immediate offset versions of PC-relative load/store instructions as [pc, #123 ] rather than simply #123 .
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2011-09-21 23:44:46 +00:00
Owen Anderson
519020adf1
These do not need to be conditional on the presence of CommentStream, as they have a fallback path now.
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2011-09-21 17:58:45 +00:00
Andrew Trick
3be654f808
Lower ARM adds/subs to add/sub after adding optional CPSR operand.
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This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.
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2011-09-21 02:20:46 +00:00
Andrew Trick
e23dc9c0ef
whitespace
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2011-09-21 02:17:37 +00:00
Owen Anderson
317eaf1993
In the disassembler C API, be careful not to confuse the comment streamer that the disassembler outputs annotations on with the streamer that the InstPrinter will print them on.
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2011-09-21 00:25:23 +00:00
Evan Cheng
0d18174f0f
Fix a bug introduced during refactoring a couple of months ago. Cortex-M3 does not support Thumb2 dsp instructions. rdar://10152911.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140181 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 21:38:18 +00:00
Andrew Trick
83a8031336
Restore hasPostISelHook tblgen flag.
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No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140160 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 18:22:31 +00:00
Andrew Trick
4815d56bb2
ARM isel bug fix for adds/subs operands.
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Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile
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2011-09-20 03:17:40 +00:00
Andrew Trick
3af7a67629
whitespace
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2011-09-20 03:06:13 +00:00
Jim Grosbach
50f1c37123
Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH.
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2011-09-20 00:46:54 +00:00
Jim Grosbach
6053cd956f
Thumb2 assembly parsing and encoding for USAX.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140119 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 00:30:45 +00:00
Jim Grosbach
8c9898454c
Remove incorrect comments. These are not disassmebly only patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140116 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 00:26:34 +00:00
Jim Grosbach
ab3bf97fe0
Thumb2 assembly parsing and encoding for UQASX/UQSAX.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140111 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 00:18:52 +00:00
Jim Grosbach
abb8aacef2
Thumb1 convenience aliases for disassembler round-trip testing. CPS instruction.
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2011-09-20 00:10:37 +00:00
Jim Grosbach
26215425da
Thumb CPS definition is not disassembler only.
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2011-09-20 00:00:06 +00:00
Jim Grosbach
0efe213ed5
Thumb2 range check on CPS mode immediate.
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2011-09-19 23:58:31 +00:00
Owen Anderson
d9346fbb06
tMOVSr is not allowed in an IT block either.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140104 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 23:57:20 +00:00
Owen Anderson
9f666b5f2e
CPS instructions are UNPREDICTABLE inside IT blocks.
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2011-09-19 23:47:10 +00:00
Jim Grosbach
32f36899e9
Tidy up comments.
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2011-09-19 23:38:34 +00:00
Jim Grosbach
d5d0e81a4b
Thumb2 assembly parsing and encoding for UMAAL/UMLAL/UMULL.
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2011-09-19 23:31:02 +00:00
Jim Grosbach
6729c48b94
Thumb2 assembly parsing and encoding for UHASX/UHSAX.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140088 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 23:13:25 +00:00
Jim Grosbach
4032eaf98c
Thumb2 assembly parsing and encoding for UASX.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140085 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 23:05:22 +00:00
Owen Anderson
04c7877894
Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not in the middle.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140079 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 22:34:23 +00:00
Jim Grosbach
7f739bee26
Thumb2 assembly parsing and encoding for TBB/TBH.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140078 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 22:21:13 +00:00
Jim Grosbach
bc80e94865
Tidy up a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140050 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 20:31:59 +00:00
Jim Grosbach
326efe5891
Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140047 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 20:29:33 +00:00
Owen Anderson
061c3c4506
Specify an additional fixed bit in the Thumb2 SSAT encoding to prevent the decoder from emitting gibberish for this invalid encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140041 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 20:00:02 +00:00
Jim Grosbach
fb12f35545
ARM asm parsing should handle pre-indexed writeback w/o immediate.
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For example, 'ldrb r9, [sp]!' is odd, but valid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140035 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 18:42:21 +00:00
Owen Anderson
ecd1c55790
Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140032 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 18:07:10 +00:00
Jim Grosbach
8a8d28b039
Thumb2 assembly parsing and encoding for SXTAB/SXTAB16/SXTAH.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140029 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 17:56:37 +00:00
Owen Anderson
cb77551927
Bitfield mask instructions are unpredictable if the encoded LSB is higher than the encoded MSB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139972 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 23:30:01 +00:00
Owen Anderson
8b22778431
Fix bitfield decoding based on Eli's feedback.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139969 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 23:04:48 +00:00
Jim Grosbach
f67e8554bf
Thumb2 assembly parsing and encoding for SUB(immediate).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139966 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 22:58:42 +00:00
Owen Anderson
e4f2df945a
Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139965 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 22:42:36 +00:00
Owen Anderson
89db0f690c
Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139964 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 22:29:48 +00:00
Owen Anderson
8a28bdcbcc
Add fixed bits to correctly distinguish Thumb2 SSAT/SSAT16's.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139958 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 22:17:02 +00:00
Jim Grosbach
ee2c2a4f98
Thumb2 assembly parsing and encoding for STR.
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More addressing mode encoding bits. Handle pre increment for STR/STRB/STRH
and STR(register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139949 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 21:55:56 +00:00
Jim Grosbach
947a24cd64
Tidy up. 80 columns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139944 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 21:09:00 +00:00
Owen Anderson
705b48ff86
Fix disassembly of Thumb2 LDRSH with a #-0 offset.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139943 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 21:08:33 +00:00
Jim Grosbach
642caea2c6
Thumb2 assembly parsing and encoding for STR(immediate).
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Add aliases for STRB/STRH while there. Tests forthcoming for those.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139942 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 21:06:12 +00:00
Jim Grosbach
8213c96655
Thumb2 assembly parsing and encoding for STMIA.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139938 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 20:50:13 +00:00
Jim Grosbach
50bd470d85
Thumb2 assembly parsing and encoding for SSAX.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139929 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 18:37:10 +00:00
Jim Grosbach
b105b997a4
Thumb2 assembly parsing and encoding for SSAT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139926 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 18:32:30 +00:00
Jim Grosbach
05ec8f7ac9
Thumb2 assembly parsing and encoding for SRS.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139925 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 18:25:22 +00:00
Jim Grosbach
3443ed525a
Thumb2 assembly parsing and encoding for SMMULL.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139921 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 18:05:48 +00:00
Jim Grosbach
7ff2472b82
Thumb2 assembly parsing and encoding for SMLSLD/SMLSLDX.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139909 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 17:10:44 +00:00
Jim Grosbach
231948f860
Thumb2 assembly parsing and encoding for SMLALD/SMLALDX.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139906 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 16:58:03 +00:00
Jim Grosbach
db7e2e59dd
Kill some dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139904 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 16:45:40 +00:00
Jim Grosbach
fb9cffea4a
Tidy up a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139903 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 16:39:25 +00:00
Jim Grosbach
837fc5e9d5
Thumb2 assembly parsing and encoding for SMLAL.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139902 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 16:38:00 +00:00
Jim Grosbach
eeca7582fa
Remove incorrect comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139877 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-15 23:45:50 +00:00
Owen Anderson
98c5ddabca
Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139876 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-15 23:38:46 +00:00
Jim Grosbach
c075d45364
Thumb2 assembly parsing and encoding for SHASX/SHSAX.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139870 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-15 22:34:29 +00:00
Eli Friedman
74bf18ccea
Minor cleanup.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139869 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-15 22:26:18 +00:00
Eli Friedman
7cc156647f
Use a more efficient lowering for Unordered/Monotonic atomic load/store on Thumb1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139865 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-15 22:18:49 +00:00
Jim Grosbach
e4e4a93e9e
Thumb2 assembly parsing and encoding for SASX.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139843 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-15 21:01:23 +00:00
Jim Grosbach
191d33fd6d
Thumb2 assembly parsing and encoding for RSB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139839 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-15 20:54:14 +00:00
Jim Grosbach
689b86ed2e
Thumb2 assembly parsing and encoding for REV16/REVSH.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139828 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-15 19:46:13 +00:00
Owen Anderson
ede042dc8d
Add support for stored annotations to MCInst, and provide facilities for MC-based InstPrinters to print them out. Enhance the ARM and X86 InstPrinter's to do so in verbose mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139820 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-15 18:36:29 +00:00
Jim Grosbach
1b69a128d6
Thumb2 assembly parsing and encoding for REV.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139813 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-15 18:13:30 +00:00
Jim Grosbach
b6e9a83349
ARM support the pre-UAL mnemonic 'qsubaddx' for 'qsax.'
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139796 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-15 16:16:50 +00:00
Jim Grosbach
57b21e437a
Thumb2 push/pop mnemonic recognition.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139794 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-15 15:55:04 +00:00
Jim Grosbach
0b69247b10
Thumb2 assembly parsing and encoding for PKH.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139754 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14 23:16:41 +00:00
Jim Grosbach
21a05e7017
ARMv7a has the PKH instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139753 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14 23:16:34 +00:00
Jim Grosbach
e1d58a6556
ARM tighten up the register classes for the PKH instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139748 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14 22:52:14 +00:00
Owen Anderson
8adf62034a
Fix a crasher in Thumb2 MOV-immediate encoding for certain inputs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139747 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14 22:46:14 +00:00
Jim Grosbach
d32872f9ca
Thumb2 assembly parsing and encoding for MVN.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139739 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14 21:24:41 +00:00
Owen Anderson
34626acf7f
Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139736 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14 21:06:21 +00:00
Jim Grosbach
64944f48a1
Thumb2 assembly parsing and encoding for MUL.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139735 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14 21:00:40 +00:00
Jim Grosbach
bf841cf336
Thumb2 assembly parsing and encoding for MSR/MRS.
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Fix a bug in handling default flags for both ARM and Thumb encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139721 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14 20:03:46 +00:00
Jim Grosbach
c2d3164ab4
Thumb2 assembly parsing for MOV in IT block.
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Select the right 16 vs. 32 bit encoding in an IT block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139714 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14 19:12:11 +00:00
Jim Grosbach
d0588e2a2e
ARM fix assembly parser handling of ranges in register lists.
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Clean up register list handling in general a bit to explicitly check things
like all the registers being from the same register class.
rdar://8883573
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139707 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14 18:08:35 +00:00