Thomas Harte
282c4121d6
CLR also follows the NEGX/NEG/NOT pattern.
2022-05-19 16:30:08 -04:00
Thomas Harte
6c2eee0e44
Implement CHK, and therefore the standard exception pattern.
2022-05-19 16:27:39 -04:00
Thomas Harte
eeb6a088b8
Add a tag to avoid duplication.
2022-05-19 15:49:42 -04:00
Thomas Harte
22b63fe1f8
Add EXT, and notes to self.
2022-05-19 15:41:02 -04:00
Thomas Harte
7ef526e2d3
Fix destination decrement.
2022-05-19 15:22:59 -04:00
Thomas Harte
ce7f94559b
Add EXG, ABCD, SBCD.
2022-05-19 15:19:00 -04:00
Thomas Harte
0471decfc8
Implement the complete set of fetch addressing modes.
...
Subject to observations: (1) MOVE uses slightly custom versions of many of these for its stores; and (2) PEA and LEA need to do the calculation but not the read, so some of this will be duplicated further. It's either that or include greater conditionality on the path.
2022-05-19 15:03:22 -04:00
Thomas Harte
084d6ca11d
Simplify address handling; add perform patterns for CMP, AND, OR, EOR.
2022-05-19 12:18:47 -04:00
Thomas Harte
274902c3c1
Add to-memory write-back. Am going to reconsider usage of temporary_address_ as noted.
2022-05-19 11:23:26 -04:00
Thomas Harte
f46e7c65c5
Add AddressRegisterIndirect fetches.
2022-05-19 10:47:57 -04:00
Thomas Harte
c6c6213460
Bifurcate the fetch-operand flow.
...
Address calculation will be the same, but the fetch will differ. I don't think there's a neat costless way to factor out the address calculations, alas, but I'll see whether macros can save the day.
2022-05-19 10:27:51 -04:00
Thomas Harte
1b87626b82
Move some way towards MOVE.
2022-05-18 21:00:10 -04:00
Thomas Harte
da9fb216b1
Remove setup_operation in favour of doing the equivalent inline.
...
... as it'll probably allow me a route to `goto` straight out of there, too. At least, if I can find a sufficiently neat macro formulation.
2022-05-18 16:45:40 -04:00
Thomas Harte
bef12f3d65
Move ExecutionState into Implementation.hpp; use goto to avoid some double switches.
...
Re: the latter, yuck. Yuck yuck yuck. But it does mean I can stop going back and forth on how to structure conditionality on effective address generation segueing into fetches without doubling up on tests.
2022-05-18 15:35:38 -04:00
Thomas Harte
aa9e7eb7a2
Codify MOVE's status somewhat, avoid reading write-only operands.
2022-05-17 16:57:33 -04:00
Thomas Harte
f3d3e588fd
Add enough of state to [sort-of] pass the first test.
...
i.e. until the processor overruns, as it is permitted to do, and can't handle the second instruction.
2022-05-17 16:51:26 -04:00
Thomas Harte
4a40581deb
Completes performance of NBCD D0.
2022-05-17 16:10:20 -04:00
Thomas Harte
eed2672db5
Add documentation, honour signal_will_perform.
2022-05-17 15:05:11 -04:00
Thomas Harte
84071ac6d0
Implement reset logic, advance as far as actually performing an NBCD on D0 (but not writing it back).
2022-05-17 14:51:49 -04:00
Thomas Harte
1a27eea46c
Establish general pattern for selecting a performance phase and obtaining operands.
2022-05-17 14:08:50 -04:00
Thomas Harte
d0b6451f02
Step gingerly on to fetching operands.
2022-05-17 08:26:35 -04:00
Thomas Harte
2147c5a5f2
Fill in missing #undefs.
2022-05-16 21:02:25 -04:00
Thomas Harte
c7aa4d8b6d
Fix state transitions.
...
Confirmed that the 68000 mk 2 now appears correctly to perform a reset.
2022-05-16 21:00:25 -04:00
Thomas Harte
e94efe887c
Switch to use of __COUNTER__.
2022-05-16 20:38:17 -04:00
Thomas Harte
3db2de7478
Works 68000 mk2 into the comparative tests.
...
... revealing that I've leant a little too hard on __LINE__.
2022-05-16 20:04:13 -04:00
Thomas Harte
345f7c3c62
Fill in just enough to attempt the reset exception, assuming DTACK rather than VPA or BERR.
2022-05-16 16:57:40 -04:00
Thomas Harte
6f6e466c08
Make a first sketch of the coroutine-esque structure I'm going to experiment with here.
2022-05-16 11:59:03 -04:00
Thomas Harte
b0518040b5
Plants the seek of a 68000 mark 2.
2022-05-16 11:44:16 -04:00
Thomas Harte
0af8660181
Remove add_pc and decline_branch in favour of operation-specific signals.
2022-05-09 16:19:25 -04:00
Thomas Harte
c61809f0c4
Add CMPAl.
2022-05-03 09:20:02 -04:00
Thomas Harte
17a2ce0464
Fix missung #undefs.
2022-05-02 21:29:46 -04:00
Thomas Harte
ef28d5512b
Annotate further.
2022-05-02 12:58:04 -04:00
Thomas Harte
fa49737538
Correct processor name.
2022-05-02 08:40:47 -04:00
Thomas Harte
8a18685902
Relocated RegisterSizes to Numeric.
2022-04-28 15:10:08 -04:00
Thomas Harte
ee625cb8a8
Minor style improvements; especially: don't assume value of NoBusProgram.
2021-12-25 14:05:38 -05:00
Thomas Harte
f20940a37b
Give Program full ownership of the sentinel value.
...
In case I want to reduce the size of this field later.
2021-12-23 16:32:21 -05:00
Thomas Harte
32e0a66610
Trust the compiler with this bit field.
2021-12-23 16:28:55 -05:00
Thomas Harte
d9598b35c2
Add some additional metrics.
2021-12-23 16:27:54 -05:00
Thomas Harte
0df8173536
Merge branch 'master' into Amiga
2021-11-24 08:58:03 -05:00
Thomas Harte
7e31658932
Remove accidental commit.
2021-10-26 21:49:32 -07:00
Thomas Harte
76767da300
Undo accidental change.
2021-10-25 21:48:19 -07:00
Thomas Harte
dc8701a929
Introduce some additional Blitter test cases.
2021-10-25 21:40:20 -07:00
Thomas Harte
313dbe05e0
Switch to more consistent inlining.
2021-09-23 22:36:15 -04:00
Thomas Harte
adf7124e2c
Eliminate 6502Base.cpp.
2021-09-23 22:33:33 -04:00
Thomas Harte
863971f944
68000: fix E alignment, expand Microcycle::apply.
2021-09-08 21:03:37 -04:00
Thomas Harte
fd70f7ad43
Attempts to make pixel content observeable.
2021-09-08 20:57:26 -04:00
Thomas Harte
5cc25d0846
Adds a further sanity assert.
2021-08-08 21:52:52 -04:00
Thomas Harte
e402e690b0
Assume and test that divide-by-zero posts the PC of the offending instruction.
2021-08-07 17:51:00 -04:00
Thomas Harte
dcbc9847a3
Attempts to get E synchronisation correct.
2021-08-05 20:08:34 -04:00
Thomas Harte
60b09d9bb0
Increases compile-time logging options.
2021-08-01 21:22:33 -04:00
Thomas Harte
f576baf214
I'm not yet sure this is the best approach, but starts trying to make use of Lorenz's 6526 tests.
2021-07-30 21:21:16 -04:00
Thomas Harte
8d2d4c850f
Revoke temporary debugging.
2021-07-25 19:59:10 -04:00
Thomas Harte
b7bed027d7
Ensures the value initially loaded to A7 is aligned.
...
This is a bit of a guess; it's likely to be true though per the rule that A7 is always kept aligned.
2021-07-25 19:55:23 -04:00
Thomas Harte
956a6dbd64
Improve commentary.
2021-07-23 19:23:54 -04:00
Thomas Harte
68fe19818e
Expose more information about the E clock state.
2021-07-23 19:22:00 -04:00
Thomas Harte
69d62560b4
Adds comment to avoid potential future error.
2021-07-22 22:00:33 -04:00
Thomas Harte
26f4758523
Makes a further accommodation for PermitRead/Write.
2021-07-22 21:11:25 -04:00
Thomas Harte
5401744dc0
Add additional asserts.
2021-07-21 21:47:44 -04:00
Thomas Harte
fe10a10ac2
Correct address on stack upon priviliege exception.
2021-07-21 21:46:55 -04:00
Thomas Harte
b2ae8e7a4a
Adds a type for the operation bitfield.
2021-07-18 20:54:54 -04:00
Thomas Harte
50b9d0e86d
Logically, I think this should be unsigned.
2021-07-18 20:25:22 -04:00
Thomas Harte
0cfc7f732c
Extends to support read/write permissions in apply.
2021-07-17 21:09:52 -04:00
Thomas Harte
51d98ef9ab
Add missing stddef header where size_t is used.
2021-07-01 23:15:32 -04:00
Thomas Harte
bdcab447f9
Add a further accessor.
2021-06-27 16:27:26 -04:00
Thomas Harte
d80f03e369
Corrects longstanding deviation from naming convention.
2021-04-25 14:11:36 -04:00
Thomas Harte
e7a9ae18a1
Introduce further default state.
2021-04-24 23:18:00 -04:00
Thomas Harte
77fcf52d27
Purely style: remove some redundant nullptrs.
2021-04-19 18:53:00 -04:00
Thomas Harte
79c2bc1fd7
Put the program counter on the bus during interrupt acknowledge.
2021-04-19 18:43:50 -04:00
Thomas Harte
7017324d60
r_step is obsolete now that I know that [DD/FD]CB don't have a refresh cycle.
2021-04-13 22:17:30 -04:00
Thomas Harte
deb5d69ac7
Consolidates macros.
2021-04-13 22:11:28 -04:00
Thomas Harte
5998f3b35b
Corrects LD[I/D/IR/DR] timing.
...
Macro cleanup to come.
2021-04-13 20:00:18 -04:00
Thomas Harte
869567fdd9
Corrects EX (SP), HL breakdown.
2021-04-13 19:45:48 -04:00
Thomas Harte
b42780173a
Establishes that there really is no Read4 and Read4Pre distinction.
...
Will finish these unit tests, then clean up.
2021-04-12 20:54:10 -04:00
Thomas Harte
947de2d54a
Switches five-cycle read to a post hoc pause.
2021-04-12 17:17:08 -04:00
Thomas Harte
e82367def3
Switches to test-conformant behaviour for (IX/IY+n) opcode fetches.
2021-04-11 23:01:00 -04:00
Thomas Harte
9cde7c12ba
Shifts responsibility for refresh into the fetch-decode-execute sequence.
2021-04-11 22:50:24 -04:00
Thomas Harte
015556cc91
Switch (ii+n) to Read4Pre.
2021-04-11 10:26:14 -04:00
Thomas Harte
b397059d5e
Moves read time in Read4Pre.
2021-04-10 17:54:20 -04:00
Thomas Harte
e0736435f8
Makes assumption that the address bus just holds its value during an internal operation.
2021-04-10 12:00:53 -04:00
Thomas Harte
eacffa49f5
Exposes IR during 'internal' operations.
2021-04-08 22:22:26 -04:00
Thomas Harte
29cf80339a
Corrects too-short buffer.
2021-04-08 22:15:03 -04:00
Thomas Harte
57a7e0834f
Corrects sampling of MREQ.
2021-04-08 19:21:35 -04:00
Thomas Harte
25b8c4c062
Provide clearer failure case.
2021-04-03 21:04:44 -04:00
Thomas Harte
1be88a5308
Remove first draft.
2021-04-02 07:39:22 -04:00
Thomas Harte
294280a94e
Spells out everything except interrupt acknowledge.
2021-04-02 07:38:06 -04:00
Thomas Harte
32aebfebe0
Starts spelling out meaning of the Z80's partial machine cycles.
2021-04-02 07:37:56 -04:00
Thomas Harte
76299a2add
Include AF' in Z80 state.
2021-03-29 22:58:52 -04:00
Thomas Harte
c8471eb993
Adds various asserts, some comments.
2021-03-03 20:47:45 -05:00
Thomas Harte
83d0cfc24e
Improves commentary.
2021-03-03 20:33:28 -05:00
Thomas Harte
f6466fd657
Remove temporary hackery.
2021-02-19 22:47:50 -05:00
Thomas Harte
72d7901c88
Takes a shot at the keyboard data full flag.
...
Just a guess. But likely?
2021-02-19 20:06:12 -05:00
Thomas Harte
992ee6d631
Don't zero out the program bank until after it has headed stackward.
2021-02-17 22:08:08 -05:00
Thomas Harte
3c887aff95
Improves consistency.
2021-01-21 18:58:22 -05:00
Thomas Harte
e0b36c9c3d
Corrects PBR/DBR resetting upon an exception.
2020-12-29 15:27:49 -05:00
Thomas Harte
574a37814c
Attempts to fix exception selection and timing.
2020-12-08 18:46:30 -05:00
Thomas Harte
c72bdd776e
Adds a new assert: I think this is the issue getting into GS/OS.
2020-12-07 22:43:24 -05:00
Thomas Harte
9e0e063f8a
Resolves one further GCC warning.
...
Technically this leaves one further, on a temporary printf I have in my IIgs. I'll fix that when I strip all this caveman stufff.
2020-11-22 21:57:48 -05:00
Thomas Harte
8ace258fbc
Tackles outstanding GCC warnings.
2020-11-22 21:43:56 -05:00
Thomas Harte
cdacf280e1
After much extra logging, corrects destination bank for MVN and MVP.
2020-11-15 16:08:29 -05:00
Thomas Harte
d3c7253981
Shifts size-limiting of X and Y to transitions and mutations, away from reads.
...
Primarily to remove potential bug-causing complexity — this is easier to debug. But let's see.
2020-11-04 20:35:41 -05:00
Thomas Harte
d50b059a17
Imports 6502-esque test for decimal SBC overflow.
...
All applicable krom tests now pass.
2020-11-03 20:37:30 -05:00
Thomas Harte
cc5ec78156
Provides something on WAI/STP; sizes STY by the x flag; disables MSC test.
2020-11-03 20:17:44 -05:00
Thomas Harte
ddc44ce0d1
Reshuffles enum to make macro tests marginally easier.
2020-11-03 20:17:09 -05:00
Thomas Harte
5cbb91f352
Fixes COP vector, ensures WDM skips a byte.
2020-11-03 20:01:02 -05:00
Thomas Harte
91ea2eff4c
Corrects MVN/MVP off-by-one and failure to store what was read.
2020-11-03 18:29:35 -05:00
Thomas Harte
bf85d71674
Brings ADC into conformance. Fixes JML.
2020-11-03 18:12:10 -05:00
Thomas Harte
3889646d6b
Takes a swing at incorporating krom's 65816 test suite. At least as far as ADC.
2020-11-02 21:09:32 -05:00
Thomas Harte
0178aaee2b
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte.
...
(Rather than a preserved but ignored top byte)
2020-11-02 18:55:28 -05:00
Thomas Harte
e8943618dc
Adds some extra commentary and distinguishes X/Y sizing from M.
2020-10-31 10:21:13 -04:00
Thomas Harte
1ae2f6f449
PHD and PLD should always be 16-bit; PLP 8-bit.
2020-10-31 09:22:35 -04:00
Thomas Harte
88e26b42f5
Fixed: PHP pushes only 8 bits regardless of mode.
2020-10-30 22:36:00 -04:00
Thomas Harte
7f3f6c339f
Corrects stacked program bank during native-mode exceptions.
2020-10-30 20:11:39 -04:00
Thomas Harte
266022b193
Fixes PEA.
2020-10-28 22:00:28 -04:00
Thomas Harte
1df2ce513a
Ensures that reset doesn't push to the stack.
2020-10-28 21:23:35 -04:00
Thomas Harte
1e4679ae14
Corrects JSL and RTL.
2020-10-28 17:25:40 -04:00
Thomas Harte
b3ab9fff9b
Imports a custom-built copy of Klaus Dormann's 65C02 test, with only 65816-compatible parts.
...
Thereby fixes another couple of 65816 issues — BRK(, etc) not clearing the decimal flag, and `TRB d` being mismapped.
2020-10-19 19:27:16 -04:00
Thomas Harte
14718b93a4
Improve commentary.
2020-10-19 09:32:50 -04:00
Thomas Harte
76d9893866
Declares address-bus sizes formally.
...
This allows me to fix the final two implicit conversion warnings, albeit that it would have been nice to find a templatey way just to get the type directly from the declaration of `perform_bus_operation`.
2020-10-18 15:08:21 -04:00
Thomas Harte
c3f8982c62
Resolves all internal implicit type-conversion warnings.
...
Chasing those down, it looks like flags were wrong for PLB and PLD. So it's official: warnings help.
2020-10-18 14:55:17 -04:00
Thomas Harte
99eba2f8ba
Ensures intended 65816 exception behaviour.
...
i.e. the relevant micro-op sequence exists, and its operation isn't lost. Also sets the 65816 by default to jump straight into power-on, not to execute an instruction first. That shouldn't make a functional difference, but it makes debugging easier because it makes startup fully deterministic.
2020-10-18 14:43:47 -04:00
Thomas Harte
e5f57ea743
Make isReadOperation more overt.
2020-10-17 22:27:04 -04:00
Thomas Harte
3b398f7a9a
Attempts to complete all 65816 bus signalling.
2020-10-16 21:56:20 -04:00
Thomas Harte
096add7551
Exposes non-BusOperation bus outputs.
2020-10-16 21:05:42 -04:00
Thomas Harte
334e0666b7
Reports ::Ready upon a WAI.
2020-10-15 21:37:37 -04:00
Thomas Harte
98c81749c8
Adds the conventional flush.
2020-10-15 21:36:04 -04:00
Thomas Harte
5dcf720bb5
Extends list of BusOperations.
...
Now to retest, widely.
2020-10-15 21:35:01 -04:00
Thomas Harte
9c0c0255f6
Ensures data/program bank can't accidentally be set to 16-bit values.
2020-10-15 21:10:32 -04:00
Thomas Harte
68c15bd605
Updates Qt project; catches another couple of issues via its compiler.
2020-10-15 21:09:22 -04:00
Thomas Harte
9a2f32795f
Revokes stack-local storage non-optimisation.
2020-10-15 21:03:10 -04:00
Thomas Harte
7aa6cf4c6b
Tidies up layout very slightly.
2020-10-15 20:51:23 -04:00
Thomas Harte
dfda2adf0d
Attempts implementations of both ready and abort.
...
Which I think concludes the inputs?
2020-10-15 20:46:18 -04:00
Thomas Harte
c0a1c34012
Wraps all registers into a struct, so that I can implement abort.
...
Makes some preparations for ready too.
2020-10-15 18:42:38 -04:00
Thomas Harte
3c6adc1ff4
Completes 65816 addressing mode tests and corresponding fixes.
2020-10-14 22:00:52 -04:00
Thomas Harte
e511d33a7c
Adds test for [d], y; fixes implementation.
2020-10-14 21:42:41 -04:00
Thomas Harte
27afb8f0a7
Adds direct indirect long test, and thereby fixes addressing mode.
...
Nine to go!
2020-10-14 21:26:20 -04:00
Thomas Harte
327ab81436
Fills in direct, x and (direct) tests, fixing implementation of the latter.
...
10 to go.
2020-10-14 21:17:28 -04:00
Thomas Harte
b22aa5d699
Starts transcribing the addressing examples I have into tests.
...
Correspondingly extends the exposed register set and test-machine addressing range.
2020-10-13 21:38:30 -04:00
Thomas Harte
3e6a2adaaf
Corrects absolute, x and absolute, y addressing modes.
2020-10-13 20:30:39 -04:00
Thomas Harte
8f5537aaaa
Attempts to resolve my direct-indirect addressing stumble.
2020-10-13 20:21:53 -04:00
Thomas Harte
a15d4a156b
Starts trying to ensure appropriate address wrapping.
2020-10-12 22:33:43 -04:00
Thomas Harte
7479dc74ed
Removes printf. It's no longer telling me anything.
2020-10-12 21:52:58 -04:00
Thomas Harte
28da1a724a
Introduces Jeek816 test case.
2020-10-12 21:43:44 -04:00
Thomas Harte
f529eadbec
Corrects 16-bit read-modify-write.
...
Subject to the TODO proviso on 'correct'; has my 6502 prejudice pushed me into unrealistic bus signalling?
2020-10-12 18:36:09 -04:00
Thomas Harte
5dc3cd3a2f
Starts using Jeek816 for a basic native-mode audit. Fixes absolute long addressing.
2020-10-11 22:02:46 -04:00
Thomas Harte
3039a445f0
Ups the 65816 test machine to a full 16mb RAM.
2020-10-11 21:18:01 -04:00
Thomas Harte
82797fd395
Attempts to do the proper thing for interrupts.
2020-10-11 21:10:44 -04:00
Thomas Harte
a0885ab7d0
Implements STP and WAI.
...
Albeit still without fully-implemented reactions to exceptions in general.
2020-10-11 17:56:55 -04:00
Thomas Harte
8eaf1303a3
Attempts proactively to ensure proper RTI behaviour on the 65816.
2020-10-11 15:25:13 -04:00
Thomas Harte
20cbe72985
Ties to 8- or 16-bit those instructions that aren't M/X-dependent.
...
This is technically redundant for PEI, PEA and PER since they have dedicated bus programs anyway, but it's good to be explicit.
2020-10-11 14:38:35 -04:00
Thomas Harte
071ad6b767
I don't think RTL is needed; JML looks like it covers it.
2020-10-10 22:16:35 -04:00
