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10,848 Commits 8 Branches 121 Tags 496 MiB
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3050 Commits

Author SHA1 Message Date
Thomas Harte
a8f1c72f5c Take a caveman run at debugging. 2023-11-19 16:05:44 -05:00
Thomas Harte
05e93f0eb3 Implementing counting for a couple of PIT modes. 2023-11-19 15:52:32 -05:00
Thomas Harte
af885ccf08 Decode PIT mode writes. 2023-11-19 15:01:21 -05:00
Thomas Harte
2b69081fff Start sketching the PIT. 2023-11-19 07:15:30 -05:00
Thomas Harte
a91449555f Add link for future self. 2023-11-17 17:38:17 -05:00
Thomas Harte
afc0ca3f1b Add XT roadmap. 2023-11-17 17:35:11 -05:00
Thomas Harte
f0ac62566c Add an 80286 BIOS, for later. 2023-11-17 17:15:57 -05:00
Thomas Harte
d202cfc2ca Add TODO. 2023-11-17 17:09:20 -05:00
Thomas Harte
ec2d878e3f End run around the template. 
I have yet to get any insight whatsoever on the reason for GCC's failure here and won't have access to a suitable test
machine for a while so all I have for testing is the arduous CI cycle.
 2023-11-17 17:02:46 -05:00
Thomas Harte
8af173c4bc Remove hopeful hit. 2023-11-16 15:48:27 -05:00
Thomas Harte
e1541543c3 Play hit and hope. 2023-11-16 15:40:47 -05:00
Thomas Harte
99e7de5a8b Colocate memory. 2023-11-16 15:24:35 -05:00
Thomas Harte
095359017f Log first unhandled port. 2023-11-16 13:02:35 -05:00
Thomas Harte
25f0a373f3 Don't sign-extend ports (!). 2023-11-16 11:17:12 -05:00
Thomas Harte
832e31f7e5 Add note to self. 2023-11-16 10:34:24 -05:00
Thomas Harte
164a7fe848 Log port IO. 2023-11-16 06:48:24 -05:00
Thomas Harte
62b6219763 Install BIOS, albeit in writeable storage. 2023-11-15 22:02:53 -05:00
Thomas Harte
2bc9dfbef9 Albeit with no BIOS present, execute. 2023-11-15 16:10:37 -05:00
Thomas Harte
3b84299a05 Edge closer to PCCompatible doing _something_. 2023-11-15 15:58:49 -05:00
Thomas Harte
6f48ffba16 Add enough of a ScanProducer to run. 2023-11-15 14:30:30 -05:00
Thomas Harte
1a3b2b0620 Add necessary wiring for File -> New... 2023-11-15 14:27:04 -05:00
Thomas Harte
af7069ac21 Include and fetch a BIOS. 2023-11-15 11:32:23 -05:00
Thomas Harte
e927fd00d8 Do just enough to include x86 code in the main build. 2023-11-15 11:01:28 -05:00
Ryan Carsten Schmidt
234292f163 Fix Apple II/II+/IIe first eight non-hbl vbl bytes 
Closes #1196
 2023-11-13 00:51:34 -06:00
Ryan Schmidt
18ed36d090 Update get_last_read_value source documentation 2023-10-25 03:25:52 -05:00
Ryan Schmidt
c206c7e2cb Fix Apple II/II+ text/lores hbl read addresses 
Closes #1181
 2023-10-25 03:25:48 -05:00
Ryan Schmidt
98730f1f90 Fix Apple II/II+/IIe first hbl byte read addresses 
Closes #1180
 2023-10-25 03:21:22 -05:00
Ryan Schmidt
c272632b5a Fix Apple II/II+/IIe hbl row < 64 read addresses 
See #1180
 2023-10-25 03:21:17 -05:00
Ryan Schmidt
577b01e80b Fix Apple II/II+/IIe vbl rows read addresses 
See #1180
 2023-10-25 03:21:06 -05:00
Thomas Harte
8efb6a9226 Simplify 'get_next_sequence_point' -> 'next_sequence_point'. 2023-09-10 18:00:49 -04:00
Thomas Harte
e5d3140cd1 Avoid flurry of startup events, repeats. 2023-08-22 09:28:57 -04:00
Thomas Harte
79e9de34b6 Flip order of byte usage in double high res mono. 2023-08-21 22:20:42 -04:00
Thomas Harte
2b58f64161 Switch to maximal signalling rate. 2023-08-21 22:12:55 -04:00
Thomas Harte
bb84a5a474 Enable various ADB-controller interrupts. 2023-08-21 15:35:13 -04:00
Thomas Harte
357a324e87 Add exposition. 2023-08-20 15:34:40 -04:00
Thomas Harte
b8e7c2b8ac Remove printf. 2023-08-20 15:33:30 -04:00
Thomas Harte
3e2a82b638 Add delta capper. 2023-08-20 15:32:48 -04:00
Thomas Harte
1125286b96 Add note to self. 2023-08-20 15:03:28 -04:00
Thomas Harte
17f1f05064 Hit and hope appears to have fixed mouse input. 2023-08-20 15:02:25 -04:00
Thomas Harte
b34403164e Abstract out VGC interrupt register; fix clearing bug. 2023-08-18 14:30:40 -04:00
Adrian Perez de Castro
1de2631877
Add missing <cstdint> includes for GCC 13 
Sprinkle includes of the <cstdint> header as needed to make the
build succeed with GCC 13, this fixes both with SDL and Qt builds.
 2023-05-25 23:06:13 +03:00
Thomas Harte
8578dfbf22 Eliminate various other errant spaces. 2023-05-16 16:40:09 -04:00
Thomas Harte
7f8f1d7e61 Avoid BASIC 2.1 requirement when running 1.1. 2023-05-15 10:17:27 -04:00
Thomas Harte
a1a7c0e253 Apply maybe_unused judiciously. 2023-05-15 10:17:04 -04:00
Thomas Harte
22ac13d3f2 Set proper number of volumes. 2023-05-13 22:29:09 -04:00
Thomas Harte
876fc6d1e0 Eliminate redundant line break. 2023-05-13 22:18:40 -04:00
Thomas Harte
e1d671daf7 Avoid paying for an OPLL if not connected. 2023-05-13 22:16:42 -04:00
Thomas Harte
4989701de9 Install MSX-MUSIC ROM. 2023-05-12 23:50:43 -04:00
Thomas Harte
fed97b8d26 Add MSX-MUSIC entry. 2023-05-12 23:33:28 -04:00
Thomas Harte
e7888497b7 Add an OPLL. 2023-05-12 23:30:03 -04:00
Thomas Harte
0b53c73da8 Add additional consts. 2023-05-12 22:13:55 -04:00
Thomas Harte
a6ebfe2ce2 Add has_msx_music flag. 2023-05-12 22:09:15 -04:00
Thomas Harte
50343dec43 Eliminate all whitespace-only lines. 2023-05-12 14:16:39 -04:00
Thomas Harte
28c79b2885 Eliminate redundant [space][tab] pairs. 2023-05-12 14:14:45 -04:00
Thomas Harte
f6acee18cc Eliminate type-in-function-name from 6502-world. 2023-05-10 18:53:38 -05:00
Thomas Harte
10cd2a36cf Avoid type-in-function-name, Z80 edition. 2023-05-10 18:42:19 -05:00
Thomas Harte
809cd7bca9 Remove the 68000's Mk2 suffix. 2023-05-10 17:13:01 -05:00
Thomas Harte
e56db3c4e5 Eliminate the old 68000 implementation. 2023-05-10 17:06:27 -05:00
Thomas Harte
2b56b7be0d Simplify namespace syntax. 2023-05-10 16:02:18 -05:00
Thomas Harte
0cb4fec504
Merge pull request #1129 from TomHarte/FarewellCodecvt 
Eliminate use of deprecated codecvt.
 2023-04-30 17:21:43 -04:00
Thomas Harte
ec81cdd388 Eliminate codecvt. 2023-04-30 17:17:40 -04:00
Thomas Harte
1f4d526ea5 Permit MSX RAM mapper readback. 2023-04-29 23:48:22 -04:00
Thomas Harte
201a7c17ae Avoid VDP race condition. 2023-03-12 23:20:48 -04:00
Thomas Harte
9836a108da Avoid VDP access races. 2023-03-10 21:04:55 -05:00
Thomas Harte
1edf747f9f Avoid flushes for video output changes. 2023-02-14 20:13:34 -05:00
Thomas Harte
4c93d01fe2 Reduce logging. 2023-01-29 21:30:57 -05:00
Thomas Harte
c9643c4145 Log memory control meaningfully. 2023-01-21 14:13:02 -05:00
Thomas Harte
339086d597 The Yamaha chips have more ports. 2023-01-17 22:29:17 -05:00
Thomas Harte
055e9cdf8d Differentiate unmapped and mapped-for-handler. 2023-01-16 19:52:40 -05:00
Thomas Harte
a5b9bdc18c Eliminate speculative apply_mapping. 2023-01-16 11:53:04 -05:00
Thomas Harte
eb51ff5cdf Add RAM paging. 2023-01-16 11:52:08 -05:00
Thomas Harte
1769c24531 Avoid ambiguous naming. 2023-01-16 11:43:43 -05:00
Thomas Harte
1a58ddaa67 Increase notes for future self. 2023-01-15 23:12:36 -05:00
Thomas Harte
183cb519e7 Give autonomy to secondary slots. 2023-01-15 22:51:17 -05:00
Thomas Harte
68361913ee Substitute VDP for the MSX 2. 2023-01-14 22:05:59 -05:00
Thomas Harte
1e17fc71ab Add an RP-5C01 to the MSX 2. 2023-01-14 14:52:07 -05:00
Thomas Harte
18def0c97d Correct extension ROM visibility. 2023-01-13 22:22:58 -05:00
Thomas Harte
f0a4d1d8ec Wire up did-page notifications. 2023-01-13 21:54:59 -05:00
Thomas Harte
50b5122969 For an MSX 2, the extension ROM is obligatory. 2023-01-13 14:18:39 -05:00
Thomas Harte
9f450b3ccb Expose the extension ROM to an MSX 2. 2023-01-13 14:16:12 -05:00
Thomas Harte
4190d25698 Ensure RAM is properly sized and available. 2023-01-13 14:07:54 -05:00
Thomas Harte
befc81743a Fix base RAM mapping. 2023-01-13 09:31:56 -05:00
Thomas Harte
23ff3fc366 Ensure all routes go somewhere. 2023-01-13 08:05:12 -05:00
Thomas Harte
78ce439b9b Add missing header; correct type. 2023-01-12 23:08:01 -05:00
Thomas Harte
ce440d52b3 Standardise name. 2023-01-12 23:02:24 -05:00
Thomas Harte
2e7e5ea12b Fleshes out most of a cleaner memory slot layout. 2023-01-12 23:01:11 -05:00
Thomas Harte
0d8c014099 Secondary slot selections are per primary slot. 2023-01-11 13:15:00 -05:00
Thomas Harte
fee82d3baa Fix typo. 2023-01-11 13:14:42 -05:00
Thomas Harte
76ad465030 Also seek the extension ROM for the MSX 2. 2023-01-11 12:56:09 -05:00
Thomas Harte
483ee8a74f Add a catch for the secondary paging register. 2023-01-10 22:24:40 -05:00
Thomas Harte
520ae7f2b2 Pick generic BIOS based on machine type. 2023-01-10 22:15:01 -05:00
Thomas Harte
ae5b81c0ab Add MSX 2 to the ROM catalogue. 2023-01-10 18:17:17 -05:00
Thomas Harte
6bd261b222 Add storage for secondary paging. 2023-01-10 18:07:31 -05:00
Thomas Harte
53bb17c848 Use model as a compile-time MSX configurator. 2023-01-10 14:55:57 -05:00
Thomas Harte
73549eb38c Document quite a bit more, to refresh my memory. 2023-01-10 14:40:03 -05:00
Thomas Harte
ef67205ce8 Set pixel count per mode. 2023-01-08 21:31:00 -05:00
Thomas Harte
794adf470b Break assumption that cycles = pixels; fix pixel clocking. 2023-01-08 21:25:22 -05:00
Thomas Harte
e8aab1fd2a Restore proper VDP selection. 2022-12-31 21:54:14 -05:00
Thomas Harte
ffb0b2ce0b Eliminate runtime duplication of personality. 2022-12-31 21:50:57 -05:00
Thomas Harte
7d6eac2895 Template the TMS on its personality. 
Template parameter currently unused, but preparatory to other improvements.
 2022-12-31 15:08:33 -05:00
Thomas Harte
ee22a98c17 Add note to future self. 2022-12-27 20:23:25 -05:00
Thomas Harte
28b4f51cb3 Add a SCSI activity indicator. 2022-11-16 11:31:10 -05:00
Thomas Harte
2f78a1c7af Add SCSI controller inclusion logic. 2022-09-15 12:17:50 -04:00
Thomas Harte
dc35ec8fa0 Merge branch 'master' into AppleIISCSI 2022-09-15 12:05:58 -04:00
Thomas Harte
36c3cb1f70 Deal with pre-ROM03 case, now that it's easy. 2022-09-13 16:31:06 -04:00
Thomas Harte
6773a321c1 Switch to portable direct bitwise logic. 2022-09-13 16:02:49 -04:00
Thomas Harte
ffdf44ad4f Switch to overt use of std::fill. 2022-09-13 15:39:17 -04:00
Thomas Harte
cbfd8e18e8 Eliminate repetitive magic constants. 2022-09-02 15:54:16 -04:00
Thomas Harte
8dc1aca67c Add TODO shout-outs. 2022-08-31 21:20:08 -04:00
Thomas Harte
df29a50738 Attempt to support the DMA interface. 2022-08-31 15:33:48 -04:00
Thomas Harte
7996fe6dab 'Clock' the SCSI bus (i.e. make it aware of passing time). 2022-08-30 16:40:25 -04:00
Thomas Harte
4df2a29a1f Add storage to the bus. 2022-08-24 15:23:50 -04:00
Thomas Harte
6010c971a1 Provide a volume to the SCSI card if one is received. 2022-08-23 15:11:56 -04:00
Thomas Harte
ea4bf5f31a Provide card's SCSI ID. 2022-08-23 15:05:36 -04:00
Thomas Harte
f4c242d5e9 Attempt to offer centralised C8 region decoding. 2022-08-23 14:50:44 -04:00
Thomas Harte
0595773355 Invents a new virtual select line for extended handling card ROM areas. 2022-08-23 14:41:45 -04:00
Thomas Harte
f89ca84902 Add missing include. 2022-08-22 21:44:33 -04:00
Thomas Harte
246bd5a6ac Merge branch 'master' into AppleIISCSI 2022-08-22 17:09:57 -04:00
Thomas Harte
3c2d01451a Remove dead comment. 2022-08-22 17:01:52 -04:00
Thomas Harte
c2c81162a1 Sketch out some of the easy stuff. 2022-08-22 16:48:51 -04:00
Thomas Harte
3d234147a6 Add in collected specs. 2022-08-22 10:22:19 -04:00
Thomas Harte
8e7f53751d Add Apple II SCSI ROM to the catalogue. 2022-08-21 22:03:52 -04:00
Thomas Harte
bfc77f1606 Add workaround that further isolates whatever bug Spindizzy reveals. 2022-08-19 16:38:42 -04:00
Thomas Harte
a6b8285d9c Factor out the blitter sequencer. 2022-08-19 16:38:15 -04:00
Thomas Harte
837acdcf60 Experimentally decline immediate blits. 2022-08-16 21:51:13 -04:00
Thomas Harte
7289192130 Fix refresh slots: they're taken, not open. 2022-08-16 21:51:02 -04:00
Thomas Harte
bb54ac14b8 Prove that new output errors are [probably] external to the Blitter. 2022-08-15 11:10:17 -04:00
Thomas Harte
856e3d97bf Merge branch 'master' into SerialisedBlitter 2022-08-15 10:54:36 -04:00
Thomas Harte
94231ca3e3 Put word-sizing responsibility on the caller. 2022-08-10 16:41:45 -04:00
Thomas Harte
e2a8b26b57 Display properly from greater RAM sizes. 2022-08-10 16:36:11 -04:00
Thomas Harte
6d1c954623 Make ST RAM size selectable, default to 1MB. 2022-08-10 12:00:06 -04:00
Thomas Harte
bdb35b6191 Add an easier hook for debugging. 2022-08-08 21:00:28 -04:00
Thomas Harte
892580c183 Clarify test. 2022-08-08 15:57:36 -04:00
Thomas Harte
d4b7d73fc4 Further reduces lines to one access per slot, max. 2022-08-07 19:19:00 -04:00
Thomas Harte
867769f6e7 Reduces line drawing to two accesses per slot. 
Still a fiction, but a better one.
 2022-08-07 19:15:03 -04:00
Thomas Harte
3781b5eb0e Provide further context. 2022-08-06 14:40:12 -04:00
Thomas Harte
318cea4ccd Attempt a full bus-transaction comparison. 2022-08-06 10:06:49 -04:00
Thomas Harte
45892f3584 Add optional transaction records to the Blitter. 2022-08-06 09:51:20 -04:00
Thomas Harte
612413cb1c Remove redundant state. 2022-08-04 10:06:14 -04:00
Thomas Harte
511ec5a736 Apply modulos at end of final line. 
Possibly I need to rethink the sequence logic?
 2022-07-30 21:35:26 -04:00
Thomas Harte
4fb9dec381 Fix use of bool. 2022-07-30 21:02:44 -04:00
Thomas Harte
82476bdabe Avoid 'complete' repetition. 2022-07-30 21:02:04 -04:00
Thomas Harte
58ee8e2460 Minor tidy-up. No fixes. 2022-07-30 21:00:50 -04:00
Thomas Harte
94a90b7a89 Attempt a real slot-by-slot blit. 2022-07-30 20:34:37 -04:00
Thomas Harte
5d992758f8 Ensure blitter with all flags disabled terminates. 2022-07-30 20:13:37 -04:00
Thomas Harte
27b8c29096 Apply modulos at end of line, not beginning. 2022-07-30 10:27:53 -04:00
Thomas Harte
93d2a612ee Add an explicit flush-pipeline step; some tests now pass. 2022-07-29 16:33:46 -04:00
Thomas Harte
03d4960a03 Begin a full-synchronous usage of the sequencer, at least exposing poor handling of the pipeline. 2022-07-29 16:15:18 -04:00
Thomas Harte
1ac0a4e924 Provide a loop count directly from the sequencer. 
This avoids the caller having to take a guess at iterations.
 2022-07-29 12:14:59 -04:00
Thomas Harte
d85d70a133 Add documentation, formal begin function. 2022-07-26 22:01:43 -04:00