180 Commits

Author	SHA1	Message	Date
Thomas Harte	7733fef3bd	DSKLEN has to be written twice.	2021-10-11 06:16:01 -07:00
Thomas Harte	6acddfdb98	Add the sync match interrupt. ... Albeit that it doesn't yet unblock disk DMA.	2021-10-11 03:37:56 -07:00
Thomas Harte	99492c2ec2	Further tweak logging.	2021-10-10 18:19:50 -07:00
Thomas Harte	846b505d27	Reduce logging; disk data probably isn't the immediate obstacle.	2021-10-10 13:04:10 -07:00
Thomas Harte	8d43b4a98d	Expands Disk DMA access window.	2021-10-10 11:47:02 -07:00
Thomas Harte	9336ffe216	Take a stab at index-hole sync.	2021-10-09 08:01:02 -07:00
Thomas Harte	eb157f15f3	Adds index hole interrupt.	2021-10-09 04:08:59 -07:00
Thomas Harte	d6e2a3f425	Make a first attempt to spool into RAM.	2021-10-08 18:11:47 -07:00
Thomas Harte	b47ca13ed3	Push disk data onwards.	2021-10-08 17:18:11 -07:00
Thomas Harte	67546c4d6e	Per the HRM, the index hole is connected to CIA B, potentially to raise an interrupt.	2021-10-08 17:12:37 -07:00
Thomas Harte	f72deb0a5c	Correct RDY position.	2021-10-08 04:32:13 -07:00
Thomas Harte	616ccbb878	Correct ID bit placement, multiplex with motor state. ... The latter per my reading of http://www.primrosebank.net/computers/amiga/upgrades/amiga_upgrades_storage_fdis.htm	2021-10-08 04:05:57 -07:00
Thomas Harte	5899af0038	Starts accumulating disk data.	2021-10-07 05:11:32 -07:00
Thomas Harte	33ff4f3b5c	Eliminate drive copies.	2021-10-06 13:40:28 -07:00
Thomas Harte	20bad38d42	Add drive activity lights.	2021-10-06 04:54:40 -07:00
Thomas Harte	92a07398cd	I think CHNG works the other way around.	2021-10-06 04:47:52 -07:00
Thomas Harte	e961d0b4a3	Switch RDY type.	2021-10-06 04:41:09 -07:00
Thomas Harte	2253ff656a	Adds route for inserting disks.	2021-10-05 16:12:30 -07:00
Thomas Harte	18631399ad	Attempts to clock the disk controller.	2021-10-05 15:38:56 -07:00
Thomas Harte	ad4afcdcd5	Switch stepping direction. ... Empirically, based on the actions of Kickstart, and assuming my confusion is because the relevant signal is active low.	2021-10-05 15:23:48 -07:00
Thomas Harte	2cf5bcc5db	Clarify logic somewhat.	2021-10-05 15:20:05 -07:00
Thomas Harte	1180ad7662	Disables a couple of now-trustworthy LOGs.	2021-10-05 06:51:47 -07:00
Thomas Harte	5463cd1ae3	Attempts to support stepping and head selection.	2021-10-05 06:36:17 -07:00
Thomas Harte	647ec770ce	Implements motor latching, drive ID shift registers.	2021-10-05 05:12:01 -07:00
Thomas Harte	e47bec2e65	Switch CIA B ports over.	2021-10-05 03:38:11 -07:00
Thomas Harte	674941abdf	Starts to add a disk controller.	2021-10-04 16:45:05 -07:00
Thomas Harte	b3f0ca39ed	Adds some unused drives.	2021-10-04 08:12:13 -07:00
Thomas Harte	5ccb512883	Moves the CIAs into the Chipset class. ... This reflects the routing of interrupt signals for now, but also prepares for the addition of disk drives.	2021-10-04 06:44:54 -07:00
Thomas Harte	0b9ebafc0f	Flip bit deserialisation order.	2021-09-28 22:12:13 -04:00
Thomas Harte	ffcd2ea10c	Attempts more properly to implement line mode.	2021-09-28 21:39:09 -04:00
Thomas Harte	c4ab2bbeed	Hard-code fetch window width. For now.	2021-09-23 22:06:13 -04:00
Thomas Harte	f1d514470d	Add note to future self.	2021-09-23 20:29:39 -04:00
Thomas Harte	60bad22a91	Correct fetch window.	2021-09-23 18:13:24 -04:00
Thomas Harte	e15f1103a0	Takes a shot at low resolution shifting.	2021-09-20 19:00:52 -04:00
Thomas Harte	a4263b5a8c	Ties bitplane collection to line position. ... Outgoing bug: incrementing the video relative offset too often, due to cycles that are discovered to be CPU-targetted.	2021-09-19 21:55:45 -04:00
Thomas Harte	245b7baa61	Moves the Copper into its own file.	2021-09-16 21:17:23 -04:00
Thomas Harte	0eeaaa150a	Correct Copper start address.	2021-09-16 21:01:37 -04:00
Thomas Harte	692d87f446	Attempts to restrict blitter slot allocation.	2021-09-16 19:56:28 -04:00
Thomas Harte	6572efe2a7	Clarifies word addressing.	2021-09-16 08:24:52 -04:00
Thomas Harte	8aac2bd029	Stubs in serial port status.	2021-09-14 21:53:07 -04:00
Thomas Harte	add11db369	Factors out DMADevice, which is now a parent of Blitter.	2021-09-14 20:51:32 -04:00
Thomas Harte	fd70f7ad43	Attempts to make pixel content observeable.	2021-09-08 20:57:26 -04:00
Thomas Harte	6e034c9b7f	At least manages to place a pixel region on screen. ... Albeit that I've suddenly realised that I've failed properly to think about high-res versus low-res.	2021-08-11 20:31:37 -04:00
Thomas Harte	52e375a985	Move towards playfield decoding.	2021-08-11 18:47:35 -04:00
Thomas Harte	10a5e7313f	Makes a buggy first attempt at bitplane data collection.	2021-08-10 21:28:48 -04:00
Thomas Harte	ec9cb21fae	Starts towards bitplane collection.	2021-08-10 19:01:41 -04:00
Thomas Harte	fdd02ad6a6	Neaten, slightly.	2021-08-10 09:20:34 -04:00
Thomas Harte	76e9fcc94a	Obey blitter DMA-enable mask.	2021-08-10 09:19:15 -04:00
Thomas Harte	e412927415	Logs a bit more from the Blitter, gives it access to slots.	2021-08-10 07:17:01 -04:00
Thomas Harte	dda154c7c6	Adds nonsense disk reads, which seems to lead to bitplane and blitter requests. ... Progress, at last!	2021-08-09 20:31:14 -04:00
Thomas Harte	9215535bee	Adds a container for the disk controller. ... Thereby appears to prove that my Amiga is getting as far as attempting to load from floppy.	2021-08-09 17:35:09 -04:00
Thomas Harte	1502c4530e	Takes a further step towards real timing.	2021-08-08 21:52:28 -04:00
Thomas Harte	db3c158215	Further increases logging.	2021-08-05 20:07:14 -04:00
Thomas Harte	1bae4973bc	Post the serial control write onwards.	2021-07-30 18:24:27 -04:00
Thomas Harte	b78090ec76	Fixes IOPortsAndTimers classification.	2021-07-28 19:39:42 -04:00
Thomas Harte	759007ffc1	Attempts to route CIA interrupts.	2021-07-28 19:36:30 -04:00
Thomas Harte	69ae9d72c8	Remove dead non-access.	2021-07-27 22:27:20 -04:00
Thomas Harte	82205d71cc	Breaks up loop for arithmetic simplicity.	2021-07-27 21:59:27 -04:00
Thomas Harte	402eab10f8	Breaks video output while attempting to pull it into the main loop.	2021-07-27 21:33:07 -04:00
Thomas Harte	b6bf4d73ad	Blitter-finished bit aside, attempts to complete the Copper.	2021-07-27 21:10:14 -04:00
Thomas Harte	5425b5c423	Adds some form of WAITing to the Copper.	2021-07-27 19:32:55 -04:00
Thomas Harte	29cd8504ca	Implements enough Copper to get a first store.	2021-07-27 19:06:16 -04:00
Thomas Harte	3544746934	Modifies interface, starts on scheduler. ... Probably corrects the pixel clock, which I think was scaled up by a factor of 4.	2021-07-27 16:41:18 -04:00
Thomas Harte	d8f814f1c4	If I'm going to push only a single colour, might as well make it fast.	2021-07-26 21:19:43 -04:00
Thomas Harte	a43175125a	Assuming I'm going to keep this synchronous, extends function signature.	2021-07-26 20:13:06 -04:00
Thomas Harte	1d03bc560a	Stores the colour palette, uses entry 0 as my new always output.	2021-07-26 18:59:11 -04:00
Thomas Harte	3832acf6e3	Produces a static white box, at least.	2021-07-26 18:51:01 -04:00
Thomas Harte	7894b50321	Starts towards an actual pixel output loop.	2021-07-26 18:44:20 -04:00
Thomas Harte	bcb7bb5cce	Improves logging further. ... To investigate the new perpetual loop.	2021-07-26 17:02:30 -04:00
Thomas Harte	87dcd82f69	Makes a first attempt at some sort of interrupt functionality.	2021-07-26 16:40:42 -04:00
Thomas Harte	e671cc6056	Add stubs for joystick/mouse querying.	2021-07-26 16:21:51 -04:00
Thomas Harte	5da89b88a6	Add missing space.	2021-07-25 22:17:55 -04:00
Thomas Harte	5d60c1f20b	Stubs in Paula.	2021-07-25 22:16:31 -04:00
Thomas Harte	7fd00165c9	Switch to [hard-coded] PAL, for now. ... In the hope that I get to see some graphics soon, this should better conform to my expectations.	2021-07-25 20:41:51 -04:00
Thomas Harte	20da194fab	Log slightly more accurately.	2021-07-25 19:59:24 -04:00
Thomas Harte	e3bb9fc1d7	Increase logging.	2021-07-23 23:10:00 -04:00
Thomas Harte	d898a43dff	Implements time-of-day counters, provisionally. ... Interrupts to do.	2021-07-23 21:24:07 -04:00
Thomas Harte	de208ead4e	Stubs in enough to get back into a persistent loop.	2021-07-22 22:00:53 -04:00
Thomas Harte	87d2fc1491	Adds enough raster position to return something.	2021-07-22 21:45:51 -04:00
Thomas Harte	2bc9af09e1	Factors out the chipset.	2021-07-22 21:16:23 -04:00