2012-02-18 12:03:15 +00:00
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//===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
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//
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2004-06-21 16:55:25 +00:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2012-02-18 12:03:15 +00:00
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//
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2004-06-21 16:55:25 +00:00
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//===----------------------------------------------------------------------===//
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//
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2004-08-09 17:24:04 +00:00
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// This file describes the subset of the 32-bit PowerPC instruction set, as used
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// by the PowerPC instruction selector.
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2004-06-21 16:55:25 +00:00
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//
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//===----------------------------------------------------------------------===//
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2005-10-14 23:40:39 +00:00
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include "PPCInstrFormats.td"
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2004-06-21 16:55:25 +00:00
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2006-03-01 05:50:56 +00:00
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//===----------------------------------------------------------------------===//
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// PowerPC specific type constraints.
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//
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def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
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SDTCisVT<0, f64>, SDTCisPtrTy<1>
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]>;
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2013-04-01 17:52:07 +00:00
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def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
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2013-03-31 10:12:51 +00:00
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SDTCisVT<0, f64>, SDTCisPtrTy<1>
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]>;
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2007-11-13 09:19:02 +00:00
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def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
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def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
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SDTCisVT<1, i32> ]>;
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2006-03-20 01:53:53 +00:00
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def SDT_PPCvperm : SDTypeProfile<1, 3, [
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SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
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]>;
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2006-03-31 05:13:27 +00:00
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def SDT_PPCvcmp : SDTypeProfile<1, 3, [
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2006-03-26 10:06:40 +00:00
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SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
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]>;
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Implement an important entry from README_ALTIVEC:
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27804 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 17:59:36 +00:00
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def SDT_PPCcondbr : SDTypeProfile<0, 3, [
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2006-11-17 22:37:34 +00:00
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SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
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Implement an important entry from README_ALTIVEC:
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27804 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 17:59:36 +00:00
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]>;
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2009-09-25 20:36:54 +00:00
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def SDT_PPClbrx : SDTypeProfile<1, 2, [
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2013-03-28 19:25:55 +00:00
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SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
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2006-07-10 20:56:58 +00:00
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]>;
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2009-09-25 20:36:54 +00:00
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def SDT_PPCstbrx : SDTypeProfile<0, 3, [
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2013-03-28 19:25:55 +00:00
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SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
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2006-07-10 20:56:58 +00:00
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]>;
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2008-07-12 02:23:19 +00:00
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def SDT_PPClarx : SDTypeProfile<1, 1, [
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SDTCisInt<0>, SDTCisPtrTy<1>
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2008-04-19 01:30:48 +00:00
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]>;
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2008-07-12 02:23:19 +00:00
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def SDT_PPCstcx : SDTypeProfile<0, 2, [
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SDTCisInt<0>, SDTCisPtrTy<1>
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2008-04-19 01:30:48 +00:00
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]>;
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2008-04-30 09:16:33 +00:00
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def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
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SDTCisPtrTy<0>, SDTCisVT<1, i32>
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]>;
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2009-08-15 11:54:46 +00:00
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2005-10-25 20:41:46 +00:00
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//===----------------------------------------------------------------------===//
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// PowerPC specific DAG Nodes.
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//
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2013-04-03 04:01:11 +00:00
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def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
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def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
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2013-04-01 17:52:07 +00:00
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def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
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def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
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def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
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def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
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2005-10-25 20:41:46 +00:00
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def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
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def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
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2013-04-01 17:52:07 +00:00
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def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
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def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
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2008-01-06 06:44:58 +00:00
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def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
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[SDNPHasChain, SDNPMayStore]>;
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2013-04-01 17:52:07 +00:00
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def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
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[SDNPHasChain, SDNPMayLoad]>;
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def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
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2013-03-31 10:12:51 +00:00
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[SDNPHasChain, SDNPMayLoad]>;
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2005-10-25 20:41:46 +00:00
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2013-03-26 10:56:22 +00:00
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// Extract FPSCR (not modeled at the DAG level).
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def PPCmffs : SDNode<"PPCISD::MFFS",
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SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
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// Perform FADD in round-to-zero mode.
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def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
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2007-10-10 01:01:31 +00:00
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2005-10-25 20:55:47 +00:00
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def PPCfsel : SDNode<"PPCISD::FSEL",
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// Type constraint for fsel.
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SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
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SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
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2005-09-08 19:50:41 +00:00
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2005-12-13 22:55:22 +00:00
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def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
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def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
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2009-08-15 11:54:46 +00:00
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def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
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2005-12-13 22:55:22 +00:00
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def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
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def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
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2005-11-17 07:30:41 +00:00
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2013-12-20 18:08:54 +00:00
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def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
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This patch improves the 64-bit PowerPC InitialExec TLS support by providing
for a wider range of GOT entries that can hold thread-relative offsets.
This matches the behavior of GCC, which was not documented in the PPC64 TLS
ABI. The ABI will be updated with the new code sequence.
Former sequence:
ld 9,x@got@tprel(2)
add 9,9,x@tls
New sequence:
addis 9,2,x@got@tprel@ha
ld 9,x@got@tprel@l(9)
add 9,9,x@tls
Note that a linker optimization exists to transform the new sequence into
the shorter sequence when appropriate, by replacing the addis with a nop
and modifying the base register and relocation type of the ld.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170209 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-14 17:02:38 +00:00
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def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
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def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
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[SDNPMayLoad]>;
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2012-12-04 16:18:08 +00:00
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def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
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This patch implements the general dynamic TLS model for 64-bit PowerPC.
Given a thread-local symbol x with global-dynamic access, the generated
code to obtain x's address is:
Instruction Relocation Symbol
addis ra,r2,x@got@tlsgd@ha R_PPC64_GOT_TLSGD16_HA x
addi r3,ra,x@got@tlsgd@l R_PPC64_GOT_TLSGD16_L x
bl __tls_get_addr(x@tlsgd) R_PPC64_TLSGD x
R_PPC64_REL24 __tls_get_addr
nop
<use address in r3>
The implementation borrows from the medium code model work for introducing
special forms of ADDIS and ADDI into the DAG representation. This is made
slightly more complicated by having to introduce a call to the external
function __tls_get_addr. Using the full call machinery is overkill and,
more importantly, makes it difficult to add a special relocation. So I've
introduced another opcode GET_TLS_ADDR to represent the function call, and
surrounded it with register copies to set up the parameter and return value.
Most of the code is pretty straightforward. I ran into one peculiarity
when I introduced a new PPC opcode BL8_NOP_ELF_TLSGD, which is just like
BL8_NOP_ELF except that it takes another parameter to represent the symbol
("x" above) that requires a relocation on the call. Something in the
TblGen machinery causes BL8_NOP_ELF and BL8_NOP_ELF_TLSGD to be treated
identically during the emit phase, so this second operand was never
visited to generate relocations. This is the reason for the slightly
messy workaround in PPCMCCodeEmitter.cpp:getDirectBrEncoding().
Two new tests are included to demonstrate correct external assembly and
correct generation of relocations using the integrated assembler.
Comments welcome!
Thanks,
Bill
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169910 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 20:30:11 +00:00
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def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
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def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
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def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
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2012-12-12 19:29:35 +00:00
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def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
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def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
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def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
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def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp,
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[SDNPHasChain]>;
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def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
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2012-12-04 16:18:08 +00:00
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2006-03-20 01:53:53 +00:00
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def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
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2006-03-19 06:55:52 +00:00
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2005-12-06 02:10:38 +00:00
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// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
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// amounts. These nodes are generated by the multi-precision shift code.
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2008-03-07 20:18:24 +00:00
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def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
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def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
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def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
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2005-12-06 02:10:38 +00:00
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2005-12-04 19:01:59 +00:00
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// These are target-independent nodes, but have target-specific formats.
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2007-11-13 09:19:02 +00:00
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
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2010-12-23 18:28:41 +00:00
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[SDNPHasChain, SDNPOutGlue]>;
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2007-11-13 09:19:02 +00:00
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
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2010-12-23 18:28:41 +00:00
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
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2005-12-04 19:01:59 +00:00
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2006-06-27 18:36:44 +00:00
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def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
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2013-03-22 15:24:13 +00:00
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def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
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SDNPVariadic]>;
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def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
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SDNPVariadic]>;
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2009-12-18 13:00:15 +00:00
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def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
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2010-12-23 18:28:41 +00:00
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
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2009-12-18 13:00:15 +00:00
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def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
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2012-08-24 14:43:27 +00:00
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[SDNPHasChain, SDNPSideEffect,
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SDNPInGlue, SDNPOutGlue]>;
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2009-12-18 13:00:15 +00:00
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def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>,
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2012-08-24 14:43:27 +00:00
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[SDNPHasChain, SDNPSideEffect,
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SDNPInGlue, SDNPOutGlue]>;
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2006-05-17 19:00:46 +00:00
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def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
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2010-12-23 18:28:41 +00:00
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
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2013-03-22 15:24:13 +00:00
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def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
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SDNPVariadic]>;
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2006-05-17 06:01:33 +00:00
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2008-01-15 22:02:54 +00:00
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def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
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2010-12-23 18:28:41 +00:00
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[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
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2005-12-20 00:26:01 +00:00
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2008-04-30 09:16:33 +00:00
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def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
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2010-12-23 18:28:41 +00:00
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[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
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2008-04-30 09:16:33 +00:00
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2013-03-21 21:37:52 +00:00
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def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
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SDTypeProfile<1, 1, [SDTCisInt<0>,
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SDTCisPtrTy<1>]>,
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[SDNPHasChain, SDNPSideEffect]>;
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def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
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SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
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[SDNPHasChain, SDNPSideEffect]>;
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2013-05-14 19:35:45 +00:00
|
|
|
def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
|
|
|
|
def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
|
|
|
|
[SDNPHasChain, SDNPSideEffect]>;
|
|
|
|
|
2006-03-31 05:13:27 +00:00
|
|
|
def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
|
2010-12-23 18:28:41 +00:00
|
|
|
def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
|
2006-03-26 10:06:40 +00:00
|
|
|
|
Implement an important entry from README_ALTIVEC:
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27804 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 17:59:36 +00:00
|
|
|
def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
|
2010-12-23 18:28:41 +00:00
|
|
|
[SDNPHasChain, SDNPOptInGlue]>;
|
Implement an important entry from README_ALTIVEC:
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27804 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 17:59:36 +00:00
|
|
|
|
2008-01-10 05:12:37 +00:00
|
|
|
def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
|
|
|
|
[SDNPHasChain, SDNPMayLoad]>;
|
2008-01-06 06:44:58 +00:00
|
|
|
def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
|
|
|
|
[SDNPHasChain, SDNPMayStore]>;
|
2006-07-10 20:56:58 +00:00
|
|
|
|
2012-08-28 02:10:27 +00:00
|
|
|
// Instructions to set/unset CR bit 6 for SVR4 vararg calls
|
|
|
|
def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
|
|
|
|
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
|
|
|
|
def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
|
|
|
|
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
|
|
|
|
|
2008-07-12 02:23:19 +00:00
|
|
|
// Instructions to support atomic operations
|
2008-04-19 02:30:38 +00:00
|
|
|
def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
|
|
|
|
[SDNPHasChain, SDNPMayLoad]>;
|
|
|
|
def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
|
|
|
|
[SDNPHasChain, SDNPMayStore]>;
|
2008-04-19 01:30:48 +00:00
|
|
|
|
2013-02-21 17:12:27 +00:00
|
|
|
// Instructions to support medium and large code model
|
This patch implements medium code model support for 64-bit PowerPC.
The default for 64-bit PowerPC is small code model, in which TOC entries
must be addressable using a 16-bit offset from the TOC pointer. Additionally,
only TOC entries are addressed via the TOC pointer.
With medium code model, TOC entries and data sections can all be addressed
via the TOC pointer using a 32-bit offset. Cooperation with the linker
allows 16-bit offsets to be used when these are sufficient, reducing the
number of extra instructions that need to be executed. Medium code model
also does not generate explicit TOC entries in ".section toc" for variables
that are wholly internal to the compilation unit.
Consider a load of an external 4-byte integer. With small code model, the
compiler generates:
ld 3, .LC1@toc(2)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc ei[TC],ei
With medium model, it instead generates:
addis 3, 2, .LC1@toc@ha
ld 3, .LC1@toc@l(3)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc ei[TC],ei
Here .LC1@toc@ha is a relocation requesting the upper 16 bits of the
32-bit offset of ei's TOC entry from the TOC base pointer. Similarly,
.LC1@toc@l is a relocation requesting the lower 16 bits. Note that if
the linker determines that ei's TOC entry is within a 16-bit offset of
the TOC base pointer, it will replace the "addis" with a "nop", and
replace the "ld" with the identical "ld" instruction from the small
code model example.
Consider next a load of a function-scope static integer. For small code
model, the compiler generates:
ld 3, .LC1@toc(2)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc test_fn_static.si[TC],test_fn_static.si
.type test_fn_static.si,@object
.local test_fn_static.si
.comm test_fn_static.si,4,4
For medium code model, the compiler generates:
addis 3, 2, test_fn_static.si@toc@ha
addi 3, 3, test_fn_static.si@toc@l
lwz 4, 0(3)
.type test_fn_static.si,@object
.local test_fn_static.si
.comm test_fn_static.si,4,4
Again, the linker may replace the "addis" with a "nop", calculating only
a 16-bit offset when this is sufficient.
Note that it would be more efficient for the compiler to generate:
addis 3, 2, test_fn_static.si@toc@ha
lwz 4, test_fn_static.si@toc@l(3)
The current patch does not perform this optimization yet. This will be
addressed as a peephole optimization in a later patch.
For the moment, the default code model for 64-bit PowerPC will remain the
small code model. We plan to eventually change the default to medium code
model, which matches current upstream GCC behavior. Note that the different
code models are ABI-compatible, so code compiled with different models will
be linked and execute correctly.
I've tested the regression suite and the application/benchmark test suite in
two ways: Once with the patch as submitted here, and once with additional
logic to force medium code model as the default. The tests all compile
cleanly, with one exception. The mandel-2 application test fails due to an
unrelated ABI compatibility with passing complex numbers. It just so happens
that small code model was incredibly lucky, in that temporary values in
floating-point registers held the expected values needed by the external
library routine that was called incorrectly. My current thought is to correct
the ABI problems with _Complex before making medium code model the default,
to avoid introducing this "regression."
Here are a few comments on how the patch works, since the selection code
can be difficult to follow:
The existing logic for small code model defines three pseudo-instructions:
LDtoc for most uses, LDtocJTI for jump table addresses, and LDtocCPT for
constant pool addresses. These are expanded by SelectCodeCommon(). The
pseudo-instruction approach doesn't work for medium code model, because
we need to generate two instructions when we match the same pattern.
Instead, new logic in PPCDAGToDAGISel::Select() intercepts the TOC_ENTRY
node for medium code model, and generates an ADDIStocHA followed by either
a LDtocL or an ADDItocL. These new node types correspond naturally to
the sequences described above.
The addis/ld sequence is generated for the following cases:
* Jump table addresses
* Function addresses
* External global variables
* Tentative definitions of global variables (common linkage)
The addis/addi sequence is generated for the following cases:
* Constant pool entries
* File-scope static global variables
* Function-scope static variables
Expanding to the two-instruction sequences at select time exposes the
instructions to subsequent optimization, particularly scheduling.
The rest of the processing occurs at assembly time, in
PPCAsmPrinter::EmitInstruction. Each of the instructions is converted to
a "real" PowerPC instruction. When a TOC entry needs to be created, this
is done here in the same manner as for the existing LDtoc, LDtocJTI, and
LDtocCPT pseudo-instructions (I factored out a new routine to handle this).
I had originally thought that if a TOC entry was needed for LDtocL or
ADDItocL, it would already have been generated for the previous ADDIStocHA.
However, at higher optimization levels, the ADDIStocHA may appear in a
different block, which may be assembled textually following the block
containing the LDtocL or ADDItocL. So it is necessary to include the
possibility of creating a new TOC entry for those two instructions.
Note that for LDtocL, we generate a new form of LD called LDrs. This
allows specifying the @toc@l relocation for the offset field of the LD
instruction (i.e., the offset is replaced by a SymbolLo relocation).
When the peephole optimization described above is added, we will need
to do similar things for all immediate-form load and store operations.
The seven "mcm-n.ll" test cases are kept separate because otherwise the
intermingling of various TOC entries and so forth makes the tests fragile
and hard to understand.
The above assumes use of an external assembler. For use of the
integrated assembler, new relocations are added and used by
PPCELFObjectWriter. Testing is done with "mcm-obj.ll", which tests for
proper generation of the various relocations for the same sequences
tested with the external assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168708 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-27 17:35:46 +00:00
|
|
|
def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
|
|
|
|
def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
|
|
|
|
def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
|
|
|
|
|
|
|
|
|
2006-11-16 22:43:37 +00:00
|
|
|
// Instructions to support dynamic alloca.
|
|
|
|
def SDTDynOp : SDTypeProfile<1, 2, []>;
|
|
|
|
def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
|
|
|
|
|
2005-09-08 19:50:41 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2005-09-09 00:39:56 +00:00
|
|
|
// PowerPC specific transformation functions and pattern fragments.
|
|
|
|
//
|
Woo, it kinda works. We now generate this atrociously bad, but correct,
code for long long foo(long long a, long long b) { return a + b; }
_foo:
or r2, r3, r3
or r3, r4, r4
or r4, r5, r5
or r5, r6, r6
rldicr r2, r2, 32, 31
rldicl r3, r3, 0, 32
rldicr r4, r4, 32, 31
rldicl r5, r5, 0, 32
or r2, r3, r2
or r3, r5, r4
add r4, r3, r2
rldicl r2, r4, 32, 32
or r4, r4, r4
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23809 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-19 01:12:32 +00:00
|
|
|
|
2005-10-19 18:42:01 +00:00
|
|
|
def SHL32 : SDNodeXForm<imm, [{
|
|
|
|
// Transformation function: 31 - imm
|
2008-09-12 16:56:44 +00:00
|
|
|
return getI32Imm(31 - N->getZExtValue());
|
2005-10-19 18:42:01 +00:00
|
|
|
}]>;
|
|
|
|
|
|
|
|
def SRL32 : SDNodeXForm<imm, [{
|
|
|
|
// Transformation function: 32 - imm
|
2008-09-12 16:56:44 +00:00
|
|
|
return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
|
2005-10-19 18:42:01 +00:00
|
|
|
}]>;
|
|
|
|
|
2005-09-09 00:39:56 +00:00
|
|
|
def LO16 : SDNodeXForm<imm, [{
|
|
|
|
// Transformation function: get the low 16 bits.
|
2008-09-12 16:56:44 +00:00
|
|
|
return getI32Imm((unsigned short)N->getZExtValue());
|
2005-09-09 00:39:56 +00:00
|
|
|
}]>;
|
|
|
|
|
|
|
|
def HI16 : SDNodeXForm<imm, [{
|
|
|
|
// Transformation function: shift the immediate value down into the low bits.
|
2008-09-12 16:56:44 +00:00
|
|
|
return getI32Imm((unsigned)N->getZExtValue() >> 16);
|
2005-09-09 00:39:56 +00:00
|
|
|
}]>;
|
2005-09-08 17:33:10 +00:00
|
|
|
|
2005-09-28 23:07:13 +00:00
|
|
|
def HA16 : SDNodeXForm<imm, [{
|
|
|
|
// Transformation function: shift the immediate value down into the low bits.
|
2008-09-12 16:56:44 +00:00
|
|
|
signed int Val = N->getZExtValue();
|
2005-09-28 23:07:13 +00:00
|
|
|
return getI32Imm((Val - (signed short)Val) >> 16);
|
|
|
|
}]>;
|
2006-09-22 05:01:56 +00:00
|
|
|
def MB : SDNodeXForm<imm, [{
|
|
|
|
// Transformation function: get the start bit of a mask
|
2008-10-16 13:02:33 +00:00
|
|
|
unsigned mb = 0, me;
|
2008-09-12 16:56:44 +00:00
|
|
|
(void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
|
2006-09-22 05:01:56 +00:00
|
|
|
return getI32Imm(mb);
|
|
|
|
}]>;
|
2005-09-28 23:07:13 +00:00
|
|
|
|
2006-09-22 05:01:56 +00:00
|
|
|
def ME : SDNodeXForm<imm, [{
|
|
|
|
// Transformation function: get the end bit of a mask
|
2008-10-16 13:02:33 +00:00
|
|
|
unsigned mb, me = 0;
|
2008-09-12 16:56:44 +00:00
|
|
|
(void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
|
2006-09-22 05:01:56 +00:00
|
|
|
return getI32Imm(me);
|
|
|
|
}]>;
|
|
|
|
def maskimm32 : PatLeaf<(imm), [{
|
|
|
|
// maskImm predicate - True if immediate is a run of ones.
|
|
|
|
unsigned mb, me;
|
2009-08-11 20:47:22 +00:00
|
|
|
if (N->getValueType(0) == MVT::i32)
|
2008-09-12 16:56:44 +00:00
|
|
|
return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
|
2006-09-22 05:01:56 +00:00
|
|
|
else
|
|
|
|
return false;
|
|
|
|
}]>;
|
2005-09-28 23:07:13 +00:00
|
|
|
|
Change some PowerPC PatLeaf definitions to ImmLeaf for fast-isel.
Using PatLeaf rather than ImmLeaf when defining immediate predicates
prevents simple patterns using those predicates from being recognized
for fast instruction selection. This patch replaces the immSExt16
PatLeaf predicate with two ImmLeaf predicates, imm32SExt16 and
imm64SExt16, allowing a few more patterns to be recognized (ADDI,
ADDIC, MULLI, ADDI8, and ADDIC8). Using the new predicates does not
help for LI, LI8, SUBFIC, and SUBFIC8 because these are rejected for
other reasons, but I see no reason to retain the PatLeaf predicate.
No functional change intended, and thus no test cases yet. This is
preliminary work for enabling fast-isel support for PowerPC. When
that support is ready, we'll be able to test this function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182510 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 20:09:24 +00:00
|
|
|
def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
|
|
|
|
// imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
|
|
|
|
// sign extended field. Used by instructions like 'addi'.
|
|
|
|
return (int32_t)Imm == (short)Imm;
|
|
|
|
}]>;
|
|
|
|
def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
|
|
|
|
// imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
|
|
|
|
// sign extended field. Used by instructions like 'addi'.
|
|
|
|
return (int64_t)Imm == (short)Imm;
|
2005-09-08 17:33:10 +00:00
|
|
|
}]>;
|
2005-09-08 17:40:49 +00:00
|
|
|
def immZExt16 : PatLeaf<(imm), [{
|
|
|
|
// immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
|
|
|
|
// field. Used by instructions like 'ori'.
|
2008-09-12 16:56:44 +00:00
|
|
|
return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
|
2005-09-09 00:39:56 +00:00
|
|
|
}], LO16>;
|
|
|
|
|
Add some 64-bit logical ops.
Split imm16Shifted into a sext/zext form for 64-bit support.
Add some patterns for immediate formation. For example, we now compile this:
static unsigned long long Y;
void test3() {
Y = 0xF0F00F00;
}
into:
_test3:
li r2, 3840
lis r3, ha16(_Y)
xoris r2, r2, 61680
std r2, lo16(_Y)(r3)
blr
GCC produces:
_test3:
li r0,0
lis r2,ha16(_Y)
ori r0,r0,61680
sldi r0,r0,16
ori r0,r0,3840
std r0,lo16(_Y)(r2)
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28883 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-20 22:34:10 +00:00
|
|
|
// imm16Shifted* - These match immediates where the low 16-bits are zero. There
|
|
|
|
// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
|
|
|
|
// identical in 32-bit mode, but in 64-bit mode, they return true if the
|
|
|
|
// immediate fits into a sign/zero extended 32-bit immediate (with the low bits
|
|
|
|
// clear).
|
|
|
|
def imm16ShiftedZExt : PatLeaf<(imm), [{
|
|
|
|
// imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
|
|
|
|
// immediate are set. Used by instructions like 'xoris'.
|
2008-09-12 16:56:44 +00:00
|
|
|
return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
|
Add some 64-bit logical ops.
Split imm16Shifted into a sext/zext form for 64-bit support.
Add some patterns for immediate formation. For example, we now compile this:
static unsigned long long Y;
void test3() {
Y = 0xF0F00F00;
}
into:
_test3:
li r2, 3840
lis r3, ha16(_Y)
xoris r2, r2, 61680
std r2, lo16(_Y)(r3)
blr
GCC produces:
_test3:
li r0,0
lis r2,ha16(_Y)
ori r0,r0,61680
sldi r0,r0,16
ori r0,r0,3840
std r0,lo16(_Y)(r2)
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28883 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-20 22:34:10 +00:00
|
|
|
}], HI16>;
|
|
|
|
|
|
|
|
def imm16ShiftedSExt : PatLeaf<(imm), [{
|
|
|
|
// imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
|
|
|
|
// immediate are set. Used by instructions like 'addis'. Identical to
|
|
|
|
// imm16ShiftedZExt in 32-bit mode.
|
2008-09-12 16:56:44 +00:00
|
|
|
if (N->getZExtValue() & 0xFFFF) return false;
|
2009-08-11 20:47:22 +00:00
|
|
|
if (N->getValueType(0) == MVT::i32)
|
2006-06-20 21:39:30 +00:00
|
|
|
return true;
|
|
|
|
// For 64-bit, make sure it is sext right.
|
2008-09-12 16:56:44 +00:00
|
|
|
return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
|
2005-09-09 00:39:56 +00:00
|
|
|
}], HI16>;
|
2005-09-08 17:33:10 +00:00
|
|
|
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{
|
|
|
|
// imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit
|
|
|
|
// zero extended field.
|
|
|
|
return isUInt<32>(Imm);
|
|
|
|
}]>;
|
|
|
|
|
2013-03-18 23:00:58 +00:00
|
|
|
// Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
|
2013-05-16 17:58:02 +00:00
|
|
|
// restricted memrix (4-aligned) constants are alignment sensitive. If these
|
2013-03-18 23:00:58 +00:00
|
|
|
// offsets are hidden behind TOC entries than the values of the lower-order
|
|
|
|
// bits cannot be checked directly. As a result, we need to also incorporate
|
|
|
|
// an alignment check into the relevant patterns.
|
|
|
|
|
|
|
|
def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
|
|
|
|
return cast<LoadSDNode>(N)->getAlignment() >= 4;
|
|
|
|
}]>;
|
|
|
|
def aligned4store : PatFrag<(ops node:$val, node:$ptr),
|
|
|
|
(store node:$val, node:$ptr), [{
|
|
|
|
return cast<StoreSDNode>(N)->getAlignment() >= 4;
|
|
|
|
}]>;
|
|
|
|
def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
|
|
|
|
return cast<LoadSDNode>(N)->getAlignment() >= 4;
|
|
|
|
}]>;
|
|
|
|
def aligned4pre_store : PatFrag<
|
|
|
|
(ops node:$val, node:$base, node:$offset),
|
|
|
|
(pre_store node:$val, node:$base, node:$offset), [{
|
|
|
|
return cast<StoreSDNode>(N)->getAlignment() >= 4;
|
|
|
|
}]>;
|
|
|
|
|
|
|
|
def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
|
|
|
|
return cast<LoadSDNode>(N)->getAlignment() < 4;
|
|
|
|
}]>;
|
|
|
|
def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
|
|
|
|
(store node:$val, node:$ptr), [{
|
|
|
|
return cast<StoreSDNode>(N)->getAlignment() < 4;
|
|
|
|
}]>;
|
|
|
|
def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
|
|
|
|
return cast<LoadSDNode>(N)->getAlignment() < 4;
|
|
|
|
}]>;
|
2006-03-25 06:12:06 +00:00
|
|
|
|
2005-09-08 19:50:41 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// PowerPC Flag Definitions.
|
|
|
|
|
2005-04-19 04:32:54 +00:00
|
|
|
class isPPC64 { bit PPC64 = 1; }
|
2013-04-12 18:17:57 +00:00
|
|
|
class isDOT { bit RC = 1; }
|
2005-04-19 04:32:54 +00:00
|
|
|
|
2006-11-08 02:13:12 +00:00
|
|
|
class RegConstraint<string C> {
|
|
|
|
string Constraints = C;
|
|
|
|
}
|
2006-11-15 23:24:18 +00:00
|
|
|
class NoEncode<string E> {
|
|
|
|
string DisableEncoding = E;
|
|
|
|
}
|
2005-09-08 19:50:41 +00:00
|
|
|
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// PowerPC Operand Definitions.
|
2004-08-14 23:27:29 +00:00
|
|
|
|
2013-04-26 16:53:15 +00:00
|
|
|
// In the default PowerPC assembler syntax, registers are specified simply
|
|
|
|
// by number, so they cannot be distinguished from immediate values (without
|
|
|
|
// looking at the opcode). This means that the default operand matching logic
|
|
|
|
// for the asm parser does not work, and we need to specify custom matchers.
|
|
|
|
// Since those can only be specified with RegisterOperand classes and not
|
|
|
|
// directly on the RegisterClass, all instructions patterns used by the asm
|
|
|
|
// parser need to use a RegisterOperand (instead of a RegisterClass) for
|
|
|
|
// all their register operands.
|
|
|
|
// For this purpose, we define one RegisterOperand for each RegisterClass,
|
|
|
|
// using the same name as the class, just in lower case.
|
|
|
|
|
2013-05-03 19:49:39 +00:00
|
|
|
def PPCRegGPRCAsmOperand : AsmOperandClass {
|
|
|
|
let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
|
|
|
|
}
|
|
|
|
def gprc : RegisterOperand<GPRC> {
|
|
|
|
let ParserMatchClass = PPCRegGPRCAsmOperand;
|
|
|
|
}
|
|
|
|
def PPCRegG8RCAsmOperand : AsmOperandClass {
|
|
|
|
let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
|
|
|
|
}
|
|
|
|
def g8rc : RegisterOperand<G8RC> {
|
|
|
|
let ParserMatchClass = PPCRegG8RCAsmOperand;
|
|
|
|
}
|
|
|
|
def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
|
|
|
|
let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
|
|
|
|
}
|
|
|
|
def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
|
|
|
|
let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
|
|
|
|
}
|
|
|
|
def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
|
|
|
|
let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
|
|
|
|
}
|
|
|
|
def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
|
|
|
|
let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
|
|
|
|
}
|
|
|
|
def PPCRegF8RCAsmOperand : AsmOperandClass {
|
|
|
|
let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
|
|
|
|
}
|
|
|
|
def f8rc : RegisterOperand<F8RC> {
|
|
|
|
let ParserMatchClass = PPCRegF8RCAsmOperand;
|
|
|
|
}
|
|
|
|
def PPCRegF4RCAsmOperand : AsmOperandClass {
|
|
|
|
let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
|
|
|
|
}
|
|
|
|
def f4rc : RegisterOperand<F4RC> {
|
|
|
|
let ParserMatchClass = PPCRegF4RCAsmOperand;
|
|
|
|
}
|
|
|
|
def PPCRegVRRCAsmOperand : AsmOperandClass {
|
|
|
|
let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
|
|
|
|
}
|
|
|
|
def vrrc : RegisterOperand<VRRC> {
|
|
|
|
let ParserMatchClass = PPCRegVRRCAsmOperand;
|
|
|
|
}
|
|
|
|
def PPCRegCRBITRCAsmOperand : AsmOperandClass {
|
2013-07-04 14:24:00 +00:00
|
|
|
let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
|
2013-05-03 19:49:39 +00:00
|
|
|
}
|
|
|
|
def crbitrc : RegisterOperand<CRBITRC> {
|
|
|
|
let ParserMatchClass = PPCRegCRBITRCAsmOperand;
|
|
|
|
}
|
|
|
|
def PPCRegCRRCAsmOperand : AsmOperandClass {
|
|
|
|
let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
|
|
|
|
}
|
|
|
|
def crrc : RegisterOperand<CRRC> {
|
|
|
|
let ParserMatchClass = PPCRegCRRCAsmOperand;
|
|
|
|
}
|
|
|
|
|
[PowerPC] Initial support for the VSX instruction set
VSX is an ISA extension supported on the POWER7 and later cores that enhances
floating-point vector and scalar capabilities. Among other things, this adds
<2 x double> support and generally helps to reduce register pressure.
The interesting part of this ISA feature is the register configuration: there
are 64 new 128-bit vector registers, the 32 of which are super-registers of the
existing 32 scalar floating-point registers, and the second 32 of which overlap
with the 32 Altivec vector registers. This makes things like vector insertion
and extraction tricky: this can be free but only if we force a restriction to
the right register subclass when needed. A new "minipass" PPCVSXCopy takes care
of this (although it could do a more-optimal job of it; see the comment about
unnecessary copies below).
Please note that, currently, VSX is not enabled by default when targeting
anything because it is not yet ready for that. The assembler and disassembler
are fully implemented and tested. However:
- CodeGen support causes miscompiles; test-suite runtime failures:
MultiSource/Benchmarks/FreeBench/distray/distray
MultiSource/Benchmarks/McCat/08-main/main
MultiSource/Benchmarks/Olden/voronoi/voronoi
MultiSource/Benchmarks/mafft/pairlocalalign
MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4
SingleSource/Benchmarks/CoyoteBench/almabench
SingleSource/Benchmarks/Misc/matmul_f64_4x4
- The lowering currently falls back to using Altivec instructions far more
than it should. Worse, there are some things that are scalarized through the
stack that shouldn't be.
- A lot of unnecessary copies make it past the optimizers, and this needs to
be fixed.
- Many more regression tests are needed.
Normally, I'd fix these things prior to committing, but there are some
students and other contributors who would like to work this, and so it makes
sense to move this development process upstream where it can be subject to the
regular code-review procedures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203768 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-13 07:58:58 +00:00
|
|
|
def PPCU2ImmAsmOperand : AsmOperandClass {
|
|
|
|
let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
|
|
|
|
let RenderMethod = "addImmOperands";
|
|
|
|
}
|
|
|
|
def u2imm : Operand<i32> {
|
|
|
|
let PrintMethod = "printU2ImmOperand";
|
|
|
|
let ParserMatchClass = PPCU2ImmAsmOperand;
|
|
|
|
}
|
2013-05-03 19:49:39 +00:00
|
|
|
def PPCS5ImmAsmOperand : AsmOperandClass {
|
|
|
|
let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
|
|
|
|
let RenderMethod = "addImmOperands";
|
|
|
|
}
|
2006-03-25 06:12:06 +00:00
|
|
|
def s5imm : Operand<i32> {
|
|
|
|
let PrintMethod = "printS5ImmOperand";
|
2013-05-03 19:49:39 +00:00
|
|
|
let ParserMatchClass = PPCS5ImmAsmOperand;
|
2013-12-19 16:13:01 +00:00
|
|
|
let DecoderMethod = "decodeSImmOperand<5>";
|
2013-05-03 19:49:39 +00:00
|
|
|
}
|
|
|
|
def PPCU5ImmAsmOperand : AsmOperandClass {
|
|
|
|
let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
|
|
|
|
let RenderMethod = "addImmOperands";
|
2006-03-25 06:12:06 +00:00
|
|
|
}
|
2005-09-14 20:53:05 +00:00
|
|
|
def u5imm : Operand<i32> {
|
2004-08-21 05:56:39 +00:00
|
|
|
let PrintMethod = "printU5ImmOperand";
|
2013-05-03 19:49:39 +00:00
|
|
|
let ParserMatchClass = PPCU5ImmAsmOperand;
|
2013-12-19 16:13:01 +00:00
|
|
|
let DecoderMethod = "decodeUImmOperand<5>";
|
2013-05-03 19:49:39 +00:00
|
|
|
}
|
|
|
|
def PPCU6ImmAsmOperand : AsmOperandClass {
|
|
|
|
let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
|
|
|
|
let RenderMethod = "addImmOperands";
|
2004-08-21 05:56:39 +00:00
|
|
|
}
|
2005-09-14 20:53:05 +00:00
|
|
|
def u6imm : Operand<i32> {
|
2004-08-30 02:28:06 +00:00
|
|
|
let PrintMethod = "printU6ImmOperand";
|
2013-05-03 19:49:39 +00:00
|
|
|
let ParserMatchClass = PPCU6ImmAsmOperand;
|
2013-12-19 16:13:01 +00:00
|
|
|
let DecoderMethod = "decodeUImmOperand<6>";
|
2013-05-03 19:49:39 +00:00
|
|
|
}
|
|
|
|
def PPCS16ImmAsmOperand : AsmOperandClass {
|
|
|
|
let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
|
|
|
|
let RenderMethod = "addImmOperands";
|
2004-08-30 02:28:06 +00:00
|
|
|
}
|
2005-09-14 20:53:05 +00:00
|
|
|
def s16imm : Operand<i32> {
|
2004-09-04 05:00:00 +00:00
|
|
|
let PrintMethod = "printS16ImmOperand";
|
2013-06-26 13:49:15 +00:00
|
|
|
let EncoderMethod = "getImm16Encoding";
|
2013-05-03 19:49:39 +00:00
|
|
|
let ParserMatchClass = PPCS16ImmAsmOperand;
|
2013-12-19 16:13:01 +00:00
|
|
|
let DecoderMethod = "decodeSImmOperand<16>";
|
2013-05-03 19:49:39 +00:00
|
|
|
}
|
|
|
|
def PPCU16ImmAsmOperand : AsmOperandClass {
|
|
|
|
let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
|
|
|
|
let RenderMethod = "addImmOperands";
|
2004-09-04 05:00:00 +00:00
|
|
|
}
|
2005-09-14 20:53:05 +00:00
|
|
|
def u16imm : Operand<i32> {
|
2004-08-15 05:20:16 +00:00
|
|
|
let PrintMethod = "printU16ImmOperand";
|
2013-06-26 13:49:15 +00:00
|
|
|
let EncoderMethod = "getImm16Encoding";
|
2013-05-03 19:49:39 +00:00
|
|
|
let ParserMatchClass = PPCU16ImmAsmOperand;
|
2013-12-19 16:13:01 +00:00
|
|
|
let DecoderMethod = "decodeUImmOperand<16>";
|
2004-08-15 05:20:16 +00:00
|
|
|
}
|
2013-06-26 13:49:53 +00:00
|
|
|
def PPCS17ImmAsmOperand : AsmOperandClass {
|
|
|
|
let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
|
|
|
|
let RenderMethod = "addImmOperands";
|
|
|
|
}
|
|
|
|
def s17imm : Operand<i32> {
|
|
|
|
// This operand type is used for addis/lis to allow the assembler parser
|
|
|
|
// to accept immediates in the range -65536..65535 for compatibility with
|
|
|
|
// the GNU assembler. The operand is treated as 16-bit otherwise.
|
|
|
|
let PrintMethod = "printS16ImmOperand";
|
|
|
|
let EncoderMethod = "getImm16Encoding";
|
|
|
|
let ParserMatchClass = PPCS17ImmAsmOperand;
|
2013-12-19 16:13:01 +00:00
|
|
|
let DecoderMethod = "decodeSImmOperand<16>";
|
2013-06-26 13:49:53 +00:00
|
|
|
}
|
2013-06-24 11:03:33 +00:00
|
|
|
def PPCDirectBrAsmOperand : AsmOperandClass {
|
|
|
|
let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
|
|
|
|
let RenderMethod = "addBranchTargetOperands";
|
|
|
|
}
|
2010-11-15 06:09:35 +00:00
|
|
|
def directbrtarget : Operand<OtherVT> {
|
2004-09-02 08:13:00 +00:00
|
|
|
let PrintMethod = "printBranchOperand";
|
2010-11-15 06:09:35 +00:00
|
|
|
let EncoderMethod = "getDirectBrEncoding";
|
2013-06-24 11:03:33 +00:00
|
|
|
let ParserMatchClass = PPCDirectBrAsmOperand;
|
|
|
|
}
|
|
|
|
def absdirectbrtarget : Operand<OtherVT> {
|
|
|
|
let PrintMethod = "printAbsBranchOperand";
|
|
|
|
let EncoderMethod = "getAbsDirectBrEncoding";
|
|
|
|
let ParserMatchClass = PPCDirectBrAsmOperand;
|
|
|
|
}
|
|
|
|
def PPCCondBrAsmOperand : AsmOperandClass {
|
|
|
|
let Name = "CondBr"; let PredicateMethod = "isCondBr";
|
|
|
|
let RenderMethod = "addBranchTargetOperands";
|
2010-11-15 06:09:35 +00:00
|
|
|
}
|
|
|
|
def condbrtarget : Operand<OtherVT> {
|
2010-11-16 01:45:05 +00:00
|
|
|
let PrintMethod = "printBranchOperand";
|
2010-11-15 06:09:35 +00:00
|
|
|
let EncoderMethod = "getCondBrEncoding";
|
2013-06-24 11:03:33 +00:00
|
|
|
let ParserMatchClass = PPCCondBrAsmOperand;
|
|
|
|
}
|
|
|
|
def abscondbrtarget : Operand<OtherVT> {
|
|
|
|
let PrintMethod = "printAbsBranchOperand";
|
|
|
|
let EncoderMethod = "getAbsCondBrEncoding";
|
|
|
|
let ParserMatchClass = PPCCondBrAsmOperand;
|
2004-09-02 08:13:00 +00:00
|
|
|
}
|
2006-06-16 21:01:35 +00:00
|
|
|
def calltarget : Operand<iPTR> {
|
2013-06-24 11:03:33 +00:00
|
|
|
let PrintMethod = "printBranchOperand";
|
2010-11-15 06:09:35 +00:00
|
|
|
let EncoderMethod = "getDirectBrEncoding";
|
2013-06-24 11:03:33 +00:00
|
|
|
let ParserMatchClass = PPCDirectBrAsmOperand;
|
2005-11-17 19:16:08 +00:00
|
|
|
}
|
2013-06-24 11:03:33 +00:00
|
|
|
def abscalltarget : Operand<iPTR> {
|
|
|
|
let PrintMethod = "printAbsBranchOperand";
|
|
|
|
let EncoderMethod = "getAbsDirectBrEncoding";
|
|
|
|
let ParserMatchClass = PPCDirectBrAsmOperand;
|
2005-11-16 00:48:01 +00:00
|
|
|
}
|
2013-05-03 19:49:39 +00:00
|
|
|
def PPCCRBitMaskOperand : AsmOperandClass {
|
|
|
|
let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
|
2004-09-04 05:00:00 +00:00
|
|
|
}
|
2005-07-20 22:42:00 +00:00
|
|
|
def crbitm: Operand<i8> {
|
|
|
|
let PrintMethod = "printcrbitm";
|
2010-11-15 05:19:25 +00:00
|
|
|
let EncoderMethod = "get_crbitm_encoding";
|
2013-12-19 16:13:01 +00:00
|
|
|
let DecoderMethod = "decodeCRBitMOperand";
|
2013-05-03 19:49:39 +00:00
|
|
|
let ParserMatchClass = PPCCRBitMaskOperand;
|
2005-07-20 22:42:00 +00:00
|
|
|
}
|
2005-12-19 23:25:09 +00:00
|
|
|
// Address operands
|
Prepare to make r0 an allocatable register on PPC
Currently the PPC r0 register is unconditionally reserved. There are two reasons
for this:
1. r0 is treated specially (as the constant 0) by certain instructions, and so
cannot be used with those instructions as a regular register.
2. r0 is used as a temporary register in the CR-register spilling process
(where, under some circumstances, we require two GPRs).
This change addresses the first reason by introducing a restricted register
class (without r0) for use by those instructions that treat r0 specially. These
register classes have a new pseudo-register, ZERO, which represents the r0-as-0
use. This has the side benefit of making the existing target code simpler (and
easier to understand), and will make it clear to the register allocator that
uses of r0 as 0 don't conflict will real uses of the r0 register.
Once the CR spilling code is improved, we'll be able to allocate r0.
Adding these extra register classes, for some reason unclear to me, causes
requests to the target to copy 32-bit registers to 64-bit registers. The
resulting code seems correct (and causes no test-suite failures), and the new
test case covers this new kind of asymmetric copy.
As r0 is still reserved, no functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177423 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19 18:51:05 +00:00
|
|
|
// A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
|
2013-05-03 19:49:39 +00:00
|
|
|
def PPCRegGxRCNoR0Operand : AsmOperandClass {
|
|
|
|
let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
|
|
|
|
}
|
|
|
|
def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
|
|
|
|
let ParserMatchClass = PPCRegGxRCNoR0Operand;
|
|
|
|
}
|
|
|
|
// A version of ptr_rc usable with the asm parser.
|
|
|
|
def PPCRegGxRCOperand : AsmOperandClass {
|
|
|
|
let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
|
|
|
|
}
|
|
|
|
def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
|
|
|
|
let ParserMatchClass = PPCRegGxRCOperand;
|
|
|
|
}
|
Prepare to make r0 an allocatable register on PPC
Currently the PPC r0 register is unconditionally reserved. There are two reasons
for this:
1. r0 is treated specially (as the constant 0) by certain instructions, and so
cannot be used with those instructions as a regular register.
2. r0 is used as a temporary register in the CR-register spilling process
(where, under some circumstances, we require two GPRs).
This change addresses the first reason by introducing a restricted register
class (without r0) for use by those instructions that treat r0 specially. These
register classes have a new pseudo-register, ZERO, which represents the r0-as-0
use. This has the side benefit of making the existing target code simpler (and
easier to understand), and will make it clear to the register allocator that
uses of r0 as 0 don't conflict will real uses of the r0 register.
Once the CR spilling code is improved, we'll be able to allocate r0.
Adding these extra register classes, for some reason unclear to me, causes
requests to the target to copy 32-bit registers to 64-bit registers. The
resulting code seems correct (and causes no test-suite failures), and the new
test case covers this new kind of asymmetric copy.
As r0 is still reserved, no functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177423 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19 18:51:05 +00:00
|
|
|
|
2013-05-03 19:49:39 +00:00
|
|
|
def PPCDispRIOperand : AsmOperandClass {
|
|
|
|
let Name = "DispRI"; let PredicateMethod = "isS16Imm";
|
2013-05-16 17:58:02 +00:00
|
|
|
let RenderMethod = "addImmOperands";
|
2013-05-03 19:49:39 +00:00
|
|
|
}
|
|
|
|
def dispRI : Operand<iPTR> {
|
|
|
|
let ParserMatchClass = PPCDispRIOperand;
|
|
|
|
}
|
|
|
|
def PPCDispRIXOperand : AsmOperandClass {
|
|
|
|
let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
|
2013-05-16 17:58:02 +00:00
|
|
|
let RenderMethod = "addImmOperands";
|
2013-05-03 19:49:39 +00:00
|
|
|
}
|
|
|
|
def dispRIX : Operand<iPTR> {
|
|
|
|
let ParserMatchClass = PPCDispRIXOperand;
|
|
|
|
}
|
2013-03-26 10:55:45 +00:00
|
|
|
|
2006-06-16 21:01:35 +00:00
|
|
|
def memri : Operand<iPTR> {
|
2005-12-19 23:25:09 +00:00
|
|
|
let PrintMethod = "printMemRegImm";
|
2013-03-26 10:55:45 +00:00
|
|
|
let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
|
split out an encoder for memri operands, allowing a relocation to be plopped
into the immediate field. This allows us to encode stuff like this:
lbz r3, lo16(__ZL4init)(r4) ; globalopt.cpp:5
; encoding: [0x88,0x64,A,A]
; fixup A - offset: 0, value: lo16(__ZL4init), kind: fixup_ppc_lo16
stw r3, lo16(__ZL1s)(r5) ; globalopt.cpp:6
; encoding: [0x90,0x65,A,A]
; fixup A - offset: 0, value: lo16(__ZL1s), kind: fixup_ppc_lo16
With this, we should have a completely function MCCodeEmitter for PPC, wewt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119134 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 08:22:03 +00:00
|
|
|
let EncoderMethod = "getMemRIEncoding";
|
2013-12-19 16:13:01 +00:00
|
|
|
let DecoderMethod = "decodeMemRIOperands";
|
2005-12-19 23:25:09 +00:00
|
|
|
}
|
2006-06-16 21:01:35 +00:00
|
|
|
def memrr : Operand<iPTR> {
|
2005-12-19 23:25:09 +00:00
|
|
|
let PrintMethod = "printMemRegReg";
|
2013-05-03 19:49:39 +00:00
|
|
|
let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
|
2005-12-19 23:25:09 +00:00
|
|
|
}
|
2013-05-16 17:58:02 +00:00
|
|
|
def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
|
|
|
|
let PrintMethod = "printMemRegImm";
|
2013-03-26 10:55:45 +00:00
|
|
|
let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
|
2010-11-15 08:02:41 +00:00
|
|
|
let EncoderMethod = "getMemRIXEncoding";
|
2013-12-19 16:13:01 +00:00
|
|
|
let DecoderMethod = "decodeMemRIXOperands";
|
When possible, custom lower 32-bit SINT_TO_FP to this:
_foo2:
extsw r2, r3
std r2, -8(r1)
lfd f0, -8(r1)
fcfid f0, f0
frsp f1, f0
blr
instead of this:
_foo2:
lis r2, ha16(LCPI2_0)
lis r4, 17200
xoris r3, r3, 32768
stw r3, -4(r1)
stw r4, -8(r1)
lfs f0, lo16(LCPI2_0)(r2)
lfd f1, -8(r1)
fsub f0, f1, f0
frsp f1, f0
blr
This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26943 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 05:30:33 +00:00
|
|
|
}
|
2005-12-19 23:25:09 +00:00
|
|
|
|
2013-03-21 21:37:52 +00:00
|
|
|
// A single-register address. This is used with the SjLj
|
|
|
|
// pseudo-instructions.
|
|
|
|
def memr : Operand<iPTR> {
|
|
|
|
let MIOperandInfo = (ops ptr_rc:$ptrreg);
|
|
|
|
}
|
2013-12-20 18:08:54 +00:00
|
|
|
def PPCTLSRegOperand : AsmOperandClass {
|
|
|
|
let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
|
|
|
|
let RenderMethod = "addTLSRegOperands";
|
|
|
|
}
|
|
|
|
def tlsreg32 : Operand<i32> {
|
|
|
|
let EncoderMethod = "getTLSRegEncoding";
|
|
|
|
let ParserMatchClass = PPCTLSRegOperand;
|
|
|
|
}
|
2013-03-21 21:37:52 +00:00
|
|
|
|
2013-03-26 10:53:27 +00:00
|
|
|
// PowerPC Predicate operand.
|
|
|
|
def pred : Operand<OtherVT> {
|
2006-11-04 05:27:39 +00:00
|
|
|
let PrintMethod = "printPredicateOperand";
|
2013-04-26 16:53:15 +00:00
|
|
|
let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
|
2006-11-04 05:27:39 +00:00
|
|
|
}
|
2006-11-03 23:53:25 +00:00
|
|
|
|
2006-01-12 02:05:36 +00:00
|
|
|
// Define PowerPC specific addressing mode.
|
2006-10-11 21:03:53 +00:00
|
|
|
def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
|
|
|
|
def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
|
|
|
|
def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
|
2013-05-16 17:58:02 +00:00
|
|
|
def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"
|
2004-08-15 05:20:16 +00:00
|
|
|
|
2013-03-21 21:37:52 +00:00
|
|
|
// The address in a single register. This is used with the SjLj
|
|
|
|
// pseudo-instructions.
|
|
|
|
def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
|
|
|
|
|
2006-11-16 00:41:37 +00:00
|
|
|
/// This is just the offset part of iaddr, used for preinc.
|
|
|
|
def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
|
2006-11-15 02:43:19 +00:00
|
|
|
|
2005-12-14 22:07:12 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// PowerPC Instruction Predicate Definitions.
|
2007-10-23 06:42:42 +00:00
|
|
|
def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
|
|
|
|
def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
|
2011-10-17 04:03:49 +00:00
|
|
|
def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
|
2014-01-22 20:20:52 +00:00
|
|
|
def IsNotBookE : Predicate<"!PPCSubTarget.isBookE()">;
|
2006-11-14 18:44:47 +00:00
|
|
|
|
2013-04-12 02:18:09 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// PowerPC Multiclass Definitions.
|
|
|
|
|
|
|
|
multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
|
|
|
|
string asmbase, string asmstr, InstrItinClass itin,
|
|
|
|
list<dag> pattern> {
|
|
|
|
let BaseName = asmbase in {
|
|
|
|
def NAME : XForm_6<opcode, xo, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(" ", asmstr)), itin,
|
|
|
|
pattern>, RecFormRel;
|
2013-04-12 18:17:57 +00:00
|
|
|
let Defs = [CR0] in
|
|
|
|
def o : XForm_6<opcode, xo, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(". ", asmstr)), itin,
|
|
|
|
[]>, isDOT, RecFormRel;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
|
|
|
|
string asmbase, string asmstr, InstrItinClass itin,
|
|
|
|
list<dag> pattern> {
|
|
|
|
let BaseName = asmbase in {
|
|
|
|
let Defs = [CARRY] in
|
|
|
|
def NAME : XForm_6<opcode, xo, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(" ", asmstr)), itin,
|
|
|
|
pattern>, RecFormRel;
|
|
|
|
let Defs = [CARRY, CR0] in
|
2013-04-12 02:18:09 +00:00
|
|
|
def o : XForm_6<opcode, xo, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(". ", asmstr)), itin,
|
|
|
|
[]>, isDOT, RecFormRel;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-04-12 18:17:57 +00:00
|
|
|
multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
|
|
|
|
string asmbase, string asmstr, InstrItinClass itin,
|
|
|
|
list<dag> pattern> {
|
|
|
|
let BaseName = asmbase in {
|
|
|
|
let Defs = [CARRY] in
|
|
|
|
def NAME : XForm_10<opcode, xo, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(" ", asmstr)), itin,
|
|
|
|
pattern>, RecFormRel;
|
|
|
|
let Defs = [CARRY, CR0] in
|
2013-04-12 02:18:09 +00:00
|
|
|
def o : XForm_10<opcode, xo, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(". ", asmstr)), itin,
|
|
|
|
[]>, isDOT, RecFormRel;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
|
|
|
|
string asmbase, string asmstr, InstrItinClass itin,
|
|
|
|
list<dag> pattern> {
|
|
|
|
let BaseName = asmbase in {
|
|
|
|
def NAME : XForm_11<opcode, xo, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(" ", asmstr)), itin,
|
|
|
|
pattern>, RecFormRel;
|
2013-04-12 18:17:57 +00:00
|
|
|
let Defs = [CR0] in
|
2013-04-12 02:18:09 +00:00
|
|
|
def o : XForm_11<opcode, xo, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(". ", asmstr)), itin,
|
|
|
|
[]>, isDOT, RecFormRel;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
|
|
|
|
string asmbase, string asmstr, InstrItinClass itin,
|
|
|
|
list<dag> pattern> {
|
|
|
|
let BaseName = asmbase in {
|
|
|
|
def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(" ", asmstr)), itin,
|
|
|
|
pattern>, RecFormRel;
|
2013-04-12 18:17:57 +00:00
|
|
|
let Defs = [CR0] in
|
|
|
|
def o : XOForm_1<opcode, xo, oe, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(". ", asmstr)), itin,
|
|
|
|
[]>, isDOT, RecFormRel;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
|
|
|
|
string asmbase, string asmstr, InstrItinClass itin,
|
|
|
|
list<dag> pattern> {
|
|
|
|
let BaseName = asmbase in {
|
|
|
|
let Defs = [CARRY] in
|
|
|
|
def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(" ", asmstr)), itin,
|
|
|
|
pattern>, RecFormRel;
|
|
|
|
let Defs = [CARRY, CR0] in
|
2013-04-12 02:18:09 +00:00
|
|
|
def o : XOForm_1<opcode, xo, oe, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(". ", asmstr)), itin,
|
|
|
|
[]>, isDOT, RecFormRel;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
|
|
|
|
string asmbase, string asmstr, InstrItinClass itin,
|
|
|
|
list<dag> pattern> {
|
|
|
|
let BaseName = asmbase in {
|
|
|
|
def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(" ", asmstr)), itin,
|
|
|
|
pattern>, RecFormRel;
|
2013-04-12 18:17:57 +00:00
|
|
|
let Defs = [CR0] in
|
|
|
|
def o : XOForm_3<opcode, xo, oe, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(". ", asmstr)), itin,
|
|
|
|
[]>, isDOT, RecFormRel;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
|
|
|
|
string asmbase, string asmstr, InstrItinClass itin,
|
|
|
|
list<dag> pattern> {
|
|
|
|
let BaseName = asmbase in {
|
|
|
|
let Defs = [CARRY] in
|
|
|
|
def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(" ", asmstr)), itin,
|
|
|
|
pattern>, RecFormRel;
|
|
|
|
let Defs = [CARRY, CR0] in
|
2013-04-12 02:18:09 +00:00
|
|
|
def o : XOForm_3<opcode, xo, oe, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(". ", asmstr)), itin,
|
|
|
|
[]>, isDOT, RecFormRel;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
|
|
|
|
string asmbase, string asmstr, InstrItinClass itin,
|
|
|
|
list<dag> pattern> {
|
|
|
|
let BaseName = asmbase in {
|
|
|
|
def NAME : MForm_2<opcode, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(" ", asmstr)), itin,
|
|
|
|
pattern>, RecFormRel;
|
2013-04-12 18:17:57 +00:00
|
|
|
let Defs = [CR0] in
|
2013-04-12 02:18:09 +00:00
|
|
|
def o : MForm_2<opcode, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(". ", asmstr)), itin,
|
|
|
|
[]>, isDOT, RecFormRel;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
|
|
|
|
string asmbase, string asmstr, InstrItinClass itin,
|
|
|
|
list<dag> pattern> {
|
|
|
|
let BaseName = asmbase in {
|
|
|
|
def NAME : MDForm_1<opcode, xo, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(" ", asmstr)), itin,
|
|
|
|
pattern>, RecFormRel;
|
2013-04-12 18:17:57 +00:00
|
|
|
let Defs = [CR0] in
|
2013-04-12 02:18:09 +00:00
|
|
|
def o : MDForm_1<opcode, xo, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(". ", asmstr)), itin,
|
|
|
|
[]>, isDOT, RecFormRel;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-04-26 15:39:12 +00:00
|
|
|
multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
|
|
|
|
string asmbase, string asmstr, InstrItinClass itin,
|
|
|
|
list<dag> pattern> {
|
|
|
|
let BaseName = asmbase in {
|
|
|
|
def NAME : MDSForm_1<opcode, xo, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(" ", asmstr)), itin,
|
|
|
|
pattern>, RecFormRel;
|
|
|
|
let Defs = [CR0] in
|
|
|
|
def o : MDSForm_1<opcode, xo, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(". ", asmstr)), itin,
|
|
|
|
[]>, isDOT, RecFormRel;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-04-12 18:17:57 +00:00
|
|
|
multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
|
|
|
|
string asmbase, string asmstr, InstrItinClass itin,
|
|
|
|
list<dag> pattern> {
|
2013-04-12 02:18:09 +00:00
|
|
|
let BaseName = asmbase in {
|
2013-04-12 18:17:57 +00:00
|
|
|
let Defs = [CARRY] in
|
2013-04-12 02:18:09 +00:00
|
|
|
def NAME : XSForm_1<opcode, xo, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(" ", asmstr)), itin,
|
|
|
|
pattern>, RecFormRel;
|
2013-04-12 18:17:57 +00:00
|
|
|
let Defs = [CARRY, CR0] in
|
2013-04-12 02:18:09 +00:00
|
|
|
def o : XSForm_1<opcode, xo, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(". ", asmstr)), itin,
|
|
|
|
[]>, isDOT, RecFormRel;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
|
|
|
|
string asmbase, string asmstr, InstrItinClass itin,
|
|
|
|
list<dag> pattern> {
|
|
|
|
let BaseName = asmbase in {
|
|
|
|
def NAME : XForm_26<opcode, xo, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(" ", asmstr)), itin,
|
|
|
|
pattern>, RecFormRel;
|
2013-04-12 18:17:57 +00:00
|
|
|
let Defs = [CR1] in
|
2013-04-12 02:18:09 +00:00
|
|
|
def o : XForm_26<opcode, xo, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(". ", asmstr)), itin,
|
2013-04-12 18:17:57 +00:00
|
|
|
[]>, isDOT, RecFormRel;
|
2013-04-12 02:18:09 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-08-19 05:01:02 +00:00
|
|
|
multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
|
|
|
|
string asmbase, string asmstr, InstrItinClass itin,
|
|
|
|
list<dag> pattern> {
|
|
|
|
let BaseName = asmbase in {
|
|
|
|
def NAME : XForm_28<opcode, xo, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(" ", asmstr)), itin,
|
|
|
|
pattern>, RecFormRel;
|
|
|
|
let Defs = [CR1] in
|
|
|
|
def o : XForm_28<opcode, xo, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(". ", asmstr)), itin,
|
|
|
|
[]>, isDOT, RecFormRel;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-04-12 02:18:09 +00:00
|
|
|
multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
|
|
|
|
string asmbase, string asmstr, InstrItinClass itin,
|
|
|
|
list<dag> pattern> {
|
|
|
|
let BaseName = asmbase in {
|
|
|
|
def NAME : AForm_1<opcode, xo, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(" ", asmstr)), itin,
|
|
|
|
pattern>, RecFormRel;
|
2013-04-12 18:17:57 +00:00
|
|
|
let Defs = [CR1] in
|
2013-04-12 02:18:09 +00:00
|
|
|
def o : AForm_1<opcode, xo, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(". ", asmstr)), itin,
|
2013-04-12 18:17:57 +00:00
|
|
|
[]>, isDOT, RecFormRel;
|
2013-04-12 02:18:09 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
|
|
|
|
string asmbase, string asmstr, InstrItinClass itin,
|
|
|
|
list<dag> pattern> {
|
|
|
|
let BaseName = asmbase in {
|
|
|
|
def NAME : AForm_2<opcode, xo, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(" ", asmstr)), itin,
|
|
|
|
pattern>, RecFormRel;
|
2013-04-12 18:17:57 +00:00
|
|
|
let Defs = [CR1] in
|
2013-04-12 02:18:09 +00:00
|
|
|
def o : AForm_2<opcode, xo, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(". ", asmstr)), itin,
|
2013-04-12 18:17:57 +00:00
|
|
|
[]>, isDOT, RecFormRel;
|
2013-04-12 02:18:09 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
|
|
|
|
string asmbase, string asmstr, InstrItinClass itin,
|
|
|
|
list<dag> pattern> {
|
|
|
|
let BaseName = asmbase in {
|
|
|
|
def NAME : AForm_3<opcode, xo, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(" ", asmstr)), itin,
|
|
|
|
pattern>, RecFormRel;
|
2013-04-12 18:17:57 +00:00
|
|
|
let Defs = [CR1] in
|
2013-04-12 02:18:09 +00:00
|
|
|
def o : AForm_3<opcode, xo, OOL, IOL,
|
|
|
|
!strconcat(asmbase, !strconcat(". ", asmstr)), itin,
|
2013-04-12 18:17:57 +00:00
|
|
|
[]>, isDOT, RecFormRel;
|
2013-04-12 02:18:09 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-09-08 19:50:41 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// PowerPC Instruction Definitions.
|
|
|
|
|
2004-06-21 16:55:25 +00:00
|
|
|
// Pseudo-instructions:
|
2005-09-08 19:50:41 +00:00
|
|
|
|
2006-03-12 09:13:49 +00:00
|
|
|
let hasCtrlDep = 1 in {
|
2007-09-11 19:55:27 +00:00
|
|
|
let Defs = [R1], Uses = [R1] in {
|
2012-10-04 18:14:28 +00:00
|
|
|
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
|
2008-10-11 22:08:30 +00:00
|
|
|
[(callseq_start timm:$amt)]>;
|
2012-10-04 18:14:28 +00:00
|
|
|
def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
|
2008-10-11 22:08:30 +00:00
|
|
|
[(callseq_end timm:$amt1, timm:$amt2)]>;
|
2007-09-11 19:55:27 +00:00
|
|
|
}
|
For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26733 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-13 21:52:10 +00:00
|
|
|
|
2013-04-26 16:53:15 +00:00
|
|
|
def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
|
For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26733 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-13 21:52:10 +00:00
|
|
|
"UPDATE_VRSAVE $rD, $rS", []>;
|
2004-10-07 22:30:03 +00:00
|
|
|
}
|
2006-11-16 22:43:37 +00:00
|
|
|
|
2007-09-11 19:55:27 +00:00
|
|
|
let Defs = [R1], Uses = [R1] in
|
2013-04-26 16:53:15 +00:00
|
|
|
def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$result,
|
|
|
|
(PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
|
2006-11-16 22:43:37 +00:00
|
|
|
|
2009-10-29 18:10:34 +00:00
|
|
|
// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
|
|
|
|
// instruction selection into a branch sequence.
|
|
|
|
let usesCustomInserter = 1, // Expanded after instruction selection.
|
2006-03-12 09:13:49 +00:00
|
|
|
PPC970_Single = 1 in {
|
2013-03-27 05:57:58 +00:00
|
|
|
// Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
|
|
|
|
// because either operand might become the first operand in an isel, and
|
|
|
|
// that operand cannot be r0.
|
2013-04-26 16:53:15 +00:00
|
|
|
def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
|
|
|
|
gprc_nor0:$T, gprc_nor0:$F,
|
2012-10-04 18:14:28 +00:00
|
|
|
i32imm:$BROPC), "#SELECT_CC_I4",
|
2006-09-27 02:55:21 +00:00
|
|
|
[]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
|
|
|
|
g8rc_nox0:$T, g8rc_nox0:$F,
|
2012-10-04 18:14:28 +00:00
|
|
|
i32imm:$BROPC), "#SELECT_CC_I8",
|
2006-09-27 02:55:21 +00:00
|
|
|
[]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
|
2012-10-04 18:14:28 +00:00
|
|
|
i32imm:$BROPC), "#SELECT_CC_F4",
|
2006-09-27 02:55:21 +00:00
|
|
|
[]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
|
2012-10-04 18:14:28 +00:00
|
|
|
i32imm:$BROPC), "#SELECT_CC_F8",
|
2006-09-27 02:55:21 +00:00
|
|
|
[]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
|
2012-10-04 18:14:28 +00:00
|
|
|
i32imm:$BROPC), "#SELECT_CC_VRRC",
|
2006-09-27 02:55:21 +00:00
|
|
|
[]>;
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
|
|
|
|
// SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
|
|
|
|
// register bit directly.
|
|
|
|
def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
|
|
|
|
gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
|
|
|
|
[(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
|
|
|
|
def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
|
|
|
|
g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
|
|
|
|
[(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
|
|
|
|
def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
|
|
|
|
f4rc:$T, f4rc:$F), "#SELECT_F4",
|
|
|
|
[(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
|
|
|
|
def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
|
|
|
|
f8rc:$T, f8rc:$F), "#SELECT_F8",
|
|
|
|
[(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
|
|
|
|
def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
|
|
|
|
vrrc:$T, vrrc:$F), "#SELECT_VRRC",
|
|
|
|
[(set v4i32:$dst,
|
|
|
|
(select i1:$cond, v4i32:$T, v4i32:$F))]>;
|
2005-08-26 21:23:58 +00:00
|
|
|
}
|
|
|
|
|
2008-03-03 22:19:16 +00:00
|
|
|
// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
|
|
|
|
// scavenge a register for it.
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
let mayStore = 1 in {
|
2013-04-26 16:53:15 +00:00
|
|
|
def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
|
2012-10-04 18:14:28 +00:00
|
|
|
"#SPILL_CR", []>;
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F),
|
|
|
|
"#SPILL_CRBIT", []>;
|
|
|
|
}
|
2008-03-03 22:19:16 +00:00
|
|
|
|
2011-12-06 20:55:36 +00:00
|
|
|
// RESTORE_CR - Indicate that we're restoring the CR register (previously
|
|
|
|
// spilled), so we'll need to scavenge a register for it.
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
let mayLoad = 1 in {
|
2013-04-26 16:53:15 +00:00
|
|
|
def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
|
2012-10-04 18:14:28 +00:00
|
|
|
"#RESTORE_CR", []>;
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
|
|
|
|
"#RESTORE_CRBIT", []>;
|
|
|
|
}
|
2011-12-06 20:55:36 +00:00
|
|
|
|
2007-07-21 00:34:19 +00:00
|
|
|
let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
|
2013-03-26 10:53:27 +00:00
|
|
|
let isReturn = 1, Uses = [LR, RM] in
|
2013-11-27 23:26:09 +00:00
|
|
|
def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
|
2013-03-26 10:53:27 +00:00
|
|
|
[(retflag)]>;
|
PPC: Prep for if conversion of bctr[l]
This adds in-principle support for if-converting the bctr[l] instructions.
These instructions are used for indirect branching. It seems, however, that the
current if converter will never actually predicate these. To do so, it would
need the ability to hoist a few setup insts. out of the conditionally-executed
block. For example, code like this:
void foo(int a, int (*bar)()) { if (a != 0) bar(); }
becomes:
...
beq 0, .LBB0_2
std 2, 40(1)
mr 12, 4
ld 3, 0(4)
ld 11, 16(4)
ld 2, 8(4)
mtctr 3
bctrl
ld 2, 40(1)
.LBB0_2:
...
and it would be safe to do all of this unconditionally with a predicated
beqctrl instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179156 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10 06:42:34 +00:00
|
|
|
let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
|
2013-11-27 23:26:09 +00:00
|
|
|
def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
|
|
|
|
[]>;
|
PPC: Prep for if conversion of bctr[l]
This adds in-principle support for if-converting the bctr[l] instructions.
These instructions are used for indirect branching. It seems, however, that the
current if converter will never actually predicate these. To do so, it would
need the ability to hoist a few setup insts. out of the conditionally-executed
block. For example, code like this:
void foo(int a, int (*bar)()) { if (a != 0) bar(); }
becomes:
...
beq 0, .LBB0_2
std 2, 40(1)
mr 12, 4
ld 3, 0(4)
ld 11, 16(4)
ld 2, 8(4)
mtctr 3
bctrl
ld 2, 40(1)
.LBB0_2:
...
and it would be safe to do all of this unconditionally with a predicated
beqctrl instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179156 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10 06:42:34 +00:00
|
|
|
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
let isCodeGenOnly = 1 in {
|
|
|
|
def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
|
|
|
|
"b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
|
|
|
|
[]>;
|
|
|
|
|
|
|
|
def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
|
|
|
|
"bcctr 12, $bi, 0", IIC_BrB, []>;
|
|
|
|
def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
|
|
|
|
"bcctr 4, $bi, 0", IIC_BrB, []>;
|
|
|
|
}
|
PPC: Prep for if conversion of bctr[l]
This adds in-principle support for if-converting the bctr[l] instructions.
These instructions are used for indirect branching. It seems, however, that the
current if converter will never actually predicate these. To do so, it would
need the ability to hoist a few setup insts. out of the conditionally-executed
block. For example, code like this:
void foo(int a, int (*bar)()) { if (a != 0) bar(); }
becomes:
...
beq 0, .LBB0_2
std 2, 40(1)
mr 12, 4
ld 3, 0(4)
ld 11, 16(4)
ld 2, 8(4)
mtctr 3
bctrl
ld 2, 40(1)
.LBB0_2:
...
and it would be safe to do all of this unconditionally with a predicated
beqctrl instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179156 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10 06:42:34 +00:00
|
|
|
}
|
2005-09-08 19:50:41 +00:00
|
|
|
}
|
|
|
|
|
2005-02-15 20:26:49 +00:00
|
|
|
let Defs = [LR] in
|
2012-10-04 18:14:28 +00:00
|
|
|
def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
|
2006-03-12 09:13:49 +00:00
|
|
|
PPC970_Unit_BRU;
|
2004-06-21 16:55:25 +00:00
|
|
|
|
2007-07-21 00:34:19 +00:00
|
|
|
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
|
2006-10-13 19:10:34 +00:00
|
|
|
let isBarrier = 1 in {
|
2010-11-15 06:09:35 +00:00
|
|
|
def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
|
2013-11-27 23:26:09 +00:00
|
|
|
"b $dst", IIC_BrB,
|
2005-12-04 18:42:54 +00:00
|
|
|
[(br bb:$dst)]>;
|
2013-06-24 11:03:33 +00:00
|
|
|
def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
|
2013-11-27 23:26:09 +00:00
|
|
|
"ba $dst", IIC_BrB, []>;
|
2006-10-13 19:10:34 +00:00
|
|
|
}
|
2004-11-22 23:07:01 +00:00
|
|
|
|
2006-11-17 22:37:34 +00:00
|
|
|
// BCC represents an arbitrary conditional branch on a predicate.
|
|
|
|
// FIXME: should be able to write a pattern for PPCcondbranch, but can't use
|
2012-10-05 15:16:11 +00:00
|
|
|
// a two-value operand where a dag node expects two operands. :(
|
2013-04-08 16:24:03 +00:00
|
|
|
let isCodeGenOnly = 1 in {
|
2012-10-05 15:16:11 +00:00
|
|
|
def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
|
2013-06-24 16:52:04 +00:00
|
|
|
"b${cond:cc}${cond:pm} ${cond:reg}, $dst"
|
2013-04-26 16:53:15 +00:00
|
|
|
/*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
|
2013-06-24 11:03:33 +00:00
|
|
|
def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
|
2013-06-24 16:52:04 +00:00
|
|
|
"b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
|
2013-06-24 11:03:33 +00:00
|
|
|
|
2013-04-08 16:24:03 +00:00
|
|
|
let isReturn = 1, Uses = [LR, RM] in
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
|
2013-11-27 23:26:09 +00:00
|
|
|
"b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
|
2013-06-24 16:52:04 +00:00
|
|
|
}
|
2013-04-09 22:58:37 +00:00
|
|
|
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
let isCodeGenOnly = 1 in {
|
|
|
|
let Pattern = [(brcond i1:$bi, bb:$dst)] in
|
|
|
|
def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
|
|
|
|
"bc 12, $bi, $dst">;
|
|
|
|
|
|
|
|
let Pattern = [(brcond (not i1:$bi), bb:$dst)] in
|
|
|
|
def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
|
|
|
|
"bc 4, $bi, $dst">;
|
|
|
|
|
|
|
|
let isReturn = 1, Uses = [LR, RM] in
|
|
|
|
def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
|
|
|
|
"bclr 12, $bi, 0", IIC_BrB, []>;
|
|
|
|
def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
|
|
|
|
"bclr 4, $bi, 0", IIC_BrB, []>;
|
|
|
|
}
|
|
|
|
|
2013-06-24 16:52:04 +00:00
|
|
|
let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
|
|
|
|
def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
|
2013-11-27 23:26:09 +00:00
|
|
|
"bdzlr", IIC_BrB, []>;
|
2013-06-24 16:52:04 +00:00
|
|
|
def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
|
2013-11-27 23:26:09 +00:00
|
|
|
"bdnzlr", IIC_BrB, []>;
|
2013-06-24 16:52:04 +00:00
|
|
|
def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
|
2013-11-27 23:26:09 +00:00
|
|
|
"bdzlr+", IIC_BrB, []>;
|
2013-06-24 16:52:04 +00:00
|
|
|
def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
|
2013-11-27 23:26:09 +00:00
|
|
|
"bdnzlr+", IIC_BrB, []>;
|
2013-06-24 16:52:04 +00:00
|
|
|
def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
|
2013-11-27 23:26:09 +00:00
|
|
|
"bdzlr-", IIC_BrB, []>;
|
2013-06-24 16:52:04 +00:00
|
|
|
def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
|
2013-11-27 23:26:09 +00:00
|
|
|
"bdnzlr-", IIC_BrB, []>;
|
2013-04-08 16:24:03 +00:00
|
|
|
}
|
2012-06-08 15:38:21 +00:00
|
|
|
|
|
|
|
let Defs = [CTR], Uses = [CTR] in {
|
2012-11-13 19:15:52 +00:00
|
|
|
def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
|
|
|
|
"bdz $dst">;
|
|
|
|
def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
|
|
|
|
"bdnz $dst">;
|
2013-06-24 11:03:33 +00:00
|
|
|
def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
|
|
|
|
"bdza $dst">;
|
|
|
|
def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
|
|
|
|
"bdnza $dst">;
|
2013-06-24 16:52:04 +00:00
|
|
|
def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
|
|
|
|
"bdz+ $dst">;
|
|
|
|
def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
|
|
|
|
"bdnz+ $dst">;
|
|
|
|
def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
|
|
|
|
"bdza+ $dst">;
|
|
|
|
def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
|
|
|
|
"bdnza+ $dst">;
|
|
|
|
def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
|
|
|
|
"bdz- $dst">;
|
|
|
|
def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
|
|
|
|
"bdnz- $dst">;
|
|
|
|
def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
|
|
|
|
"bdza- $dst">;
|
|
|
|
def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
|
|
|
|
"bdnza- $dst">;
|
2012-06-08 15:38:21 +00:00
|
|
|
}
|
2004-06-28 18:23:35 +00:00
|
|
|
}
|
|
|
|
|
2013-04-04 22:55:54 +00:00
|
|
|
// The unconditional BCL used by the SjLj setjmp code.
|
2013-03-26 10:57:16 +00:00
|
|
|
let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
|
2013-03-21 21:37:52 +00:00
|
|
|
let Defs = [LR], Uses = [RM] in {
|
2013-04-04 22:55:54 +00:00
|
|
|
def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
|
|
|
|
"bcl 20, 31, $dst">;
|
2013-03-21 21:37:52 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-03-06 16:41:49 +00:00
|
|
|
let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
|
2007-02-25 05:34:32 +00:00
|
|
|
// Convenient aliases for call instructions
|
2008-10-29 18:26:45 +00:00
|
|
|
let Uses = [RM] in {
|
2013-03-22 15:24:13 +00:00
|
|
|
def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
|
2013-11-27 23:26:09 +00:00
|
|
|
"bl $func", IIC_BrB, []>; // See Pat patterns below.
|
2013-06-24 11:03:33 +00:00
|
|
|
def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
|
2013-11-27 23:26:09 +00:00
|
|
|
"bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
|
2013-06-24 11:02:19 +00:00
|
|
|
|
2013-06-24 11:03:33 +00:00
|
|
|
let isCodeGenOnly = 1 in {
|
|
|
|
def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
|
2013-06-24 16:52:04 +00:00
|
|
|
"b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
|
2013-06-24 11:03:33 +00:00
|
|
|
def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
|
2013-06-24 16:52:04 +00:00
|
|
|
"b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
|
|
|
|
def BCL : BForm_4<16, 12, 0, 1, (outs),
|
|
|
|
(ins crbitrc:$bi, condbrtarget:$dst),
|
|
|
|
"bcl 12, $bi, $dst">;
|
|
|
|
def BCLn : BForm_4<16, 4, 0, 1, (outs),
|
|
|
|
(ins crbitrc:$bi, condbrtarget:$dst),
|
|
|
|
"bcl 4, $bi, $dst">;
|
2013-06-24 11:03:33 +00:00
|
|
|
}
|
2008-10-29 18:26:45 +00:00
|
|
|
}
|
|
|
|
let Uses = [CTR, RM] in {
|
2013-03-22 15:24:13 +00:00
|
|
|
def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
|
2013-11-27 23:26:09 +00:00
|
|
|
"bctrl", IIC_BrB, [(PPCbctrl)]>,
|
2013-03-22 15:24:13 +00:00
|
|
|
Requires<[In32BitMode]>;
|
2013-04-17 17:19:05 +00:00
|
|
|
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
let isCodeGenOnly = 1 in {
|
|
|
|
def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
|
|
|
|
"b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
|
|
|
|
[]>;
|
|
|
|
|
|
|
|
def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
|
|
|
|
"bcctrl 12, $bi, 0", IIC_BrB, []>;
|
|
|
|
def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
|
|
|
|
"bcctrl 4, $bi, 0", IIC_BrB, []>;
|
|
|
|
}
|
2008-10-23 20:41:28 +00:00
|
|
|
}
|
2013-06-24 11:01:55 +00:00
|
|
|
let Uses = [LR, RM] in {
|
|
|
|
def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
|
2013-11-27 23:26:09 +00:00
|
|
|
"blrl", IIC_BrB, []>;
|
2013-06-24 11:01:55 +00:00
|
|
|
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
let isCodeGenOnly = 1 in {
|
|
|
|
def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
|
|
|
|
"b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
|
|
|
|
[]>;
|
|
|
|
|
|
|
|
def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi),
|
|
|
|
"bclrl 12, $bi, 0", IIC_BrB, []>;
|
|
|
|
def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi),
|
|
|
|
"bclrl 4, $bi, 0", IIC_BrB, []>;
|
|
|
|
}
|
2013-06-24 11:01:55 +00:00
|
|
|
}
|
2013-06-24 11:02:38 +00:00
|
|
|
let Defs = [CTR], Uses = [CTR, RM] in {
|
|
|
|
def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
|
|
|
|
"bdzl $dst">;
|
|
|
|
def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
|
|
|
|
"bdnzl $dst">;
|
2013-06-24 11:03:33 +00:00
|
|
|
def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
|
|
|
|
"bdzla $dst">;
|
|
|
|
def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
|
|
|
|
"bdnzla $dst">;
|
2013-06-24 16:52:04 +00:00
|
|
|
def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
|
|
|
|
"bdzl+ $dst">;
|
|
|
|
def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
|
|
|
|
"bdnzl+ $dst">;
|
|
|
|
def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
|
|
|
|
"bdzla+ $dst">;
|
|
|
|
def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
|
|
|
|
"bdnzla+ $dst">;
|
|
|
|
def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
|
|
|
|
"bdzl- $dst">;
|
|
|
|
def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
|
|
|
|
"bdnzl- $dst">;
|
|
|
|
def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
|
|
|
|
"bdzla- $dst">;
|
|
|
|
def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
|
|
|
|
"bdnzla- $dst">;
|
2013-06-24 11:02:38 +00:00
|
|
|
}
|
|
|
|
let Defs = [CTR], Uses = [CTR, LR, RM] in {
|
|
|
|
def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
|
2013-11-27 23:26:09 +00:00
|
|
|
"bdzlrl", IIC_BrB, []>;
|
2013-06-24 11:02:38 +00:00
|
|
|
def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
|
2013-11-27 23:26:09 +00:00
|
|
|
"bdnzlrl", IIC_BrB, []>;
|
2013-06-24 16:52:04 +00:00
|
|
|
def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
|
2013-11-27 23:26:09 +00:00
|
|
|
"bdzlrl+", IIC_BrB, []>;
|
2013-06-24 16:52:04 +00:00
|
|
|
def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
|
2013-11-27 23:26:09 +00:00
|
|
|
"bdnzlrl+", IIC_BrB, []>;
|
2013-06-24 16:52:04 +00:00
|
|
|
def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
|
2013-11-27 23:26:09 +00:00
|
|
|
"bdzlrl-", IIC_BrB, []>;
|
2013-06-24 16:52:04 +00:00
|
|
|
def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
|
2013-11-27 23:26:09 +00:00
|
|
|
"bdnzlrl-", IIC_BrB, []>;
|
2013-06-24 11:02:38 +00:00
|
|
|
}
|
2004-06-29 23:37:36 +00:00
|
|
|
}
|
|
|
|
|
2008-10-29 18:26:45 +00:00
|
|
|
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
|
2008-04-30 09:16:33 +00:00
|
|
|
def TCRETURNdi :Pseudo< (outs),
|
2012-07-13 20:44:29 +00:00
|
|
|
(ins calltarget:$dst, i32imm:$offset),
|
2008-04-30 09:16:33 +00:00
|
|
|
"#TC_RETURNd $dst $offset",
|
|
|
|
[]>;
|
|
|
|
|
|
|
|
|
2008-10-29 18:26:45 +00:00
|
|
|
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
|
2013-06-24 11:03:33 +00:00
|
|
|
def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
|
2008-04-30 09:16:33 +00:00
|
|
|
"#TC_RETURNa $func $offset",
|
|
|
|
[(PPCtc_return (i32 imm:$func), imm:$offset)]>;
|
|
|
|
|
2008-10-29 18:26:45 +00:00
|
|
|
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
|
2012-07-13 20:44:29 +00:00
|
|
|
def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
|
2008-04-30 09:16:33 +00:00
|
|
|
"#TC_RETURNr $dst $offset",
|
|
|
|
[]>;
|
|
|
|
|
|
|
|
|
2013-03-26 10:57:16 +00:00
|
|
|
let isCodeGenOnly = 1 in {
|
|
|
|
|
2008-04-30 09:16:33 +00:00
|
|
|
let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
|
2008-10-29 18:26:45 +00:00
|
|
|
isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
|
2013-11-27 23:26:09 +00:00
|
|
|
def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
|
|
|
|
[]>, Requires<[In32BitMode]>;
|
2008-04-30 09:16:33 +00:00
|
|
|
|
|
|
|
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
|
2008-10-29 18:26:45 +00:00
|
|
|
isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
|
2008-04-30 09:16:33 +00:00
|
|
|
def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
|
2013-11-27 23:26:09 +00:00
|
|
|
"b $dst", IIC_BrB,
|
2008-04-30 09:16:33 +00:00
|
|
|
[]>;
|
|
|
|
|
|
|
|
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
|
2008-10-29 18:26:45 +00:00
|
|
|
isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
|
2013-06-24 11:03:33 +00:00
|
|
|
def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
|
2013-11-27 23:26:09 +00:00
|
|
|
"ba $dst", IIC_BrB,
|
2008-04-30 09:16:33 +00:00
|
|
|
[]>;
|
|
|
|
|
2013-06-24 11:03:33 +00:00
|
|
|
}
|
|
|
|
|
2013-03-26 10:57:16 +00:00
|
|
|
let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
|
2013-07-17 05:35:44 +00:00
|
|
|
let Defs = [CTR] in
|
2013-04-26 16:53:15 +00:00
|
|
|
def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
|
2013-03-21 21:37:52 +00:00
|
|
|
"#EH_SJLJ_SETJMP32",
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
|
2013-03-21 21:37:52 +00:00
|
|
|
Requires<[In32BitMode]>;
|
|
|
|
let isTerminator = 1 in
|
|
|
|
def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
|
|
|
|
"#EH_SJLJ_LONGJMP32",
|
|
|
|
[(PPCeh_sjlj_longjmp addr:$buf)]>,
|
|
|
|
Requires<[In32BitMode]>;
|
|
|
|
}
|
|
|
|
|
2013-03-26 10:57:16 +00:00
|
|
|
let isBranch = 1, isTerminator = 1 in {
|
2013-03-21 21:37:52 +00:00
|
|
|
def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
|
|
|
|
"#EH_SjLj_Setup\t$dst", []>;
|
|
|
|
}
|
2008-04-30 09:16:33 +00:00
|
|
|
|
2013-05-14 19:35:45 +00:00
|
|
|
// System call.
|
|
|
|
let PPC970_Unit = 7 in {
|
|
|
|
def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
|
2013-11-27 23:26:09 +00:00
|
|
|
"sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
|
2013-05-14 19:35:45 +00:00
|
|
|
}
|
|
|
|
|
2006-06-06 21:29:23 +00:00
|
|
|
// DCB* instructions.
|
2013-11-27 23:26:09 +00:00
|
|
|
def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
|
|
|
|
IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
|
2006-10-24 01:08:42 +00:00
|
|
|
PPC970_DGroup_Single;
|
2013-11-27 23:26:09 +00:00
|
|
|
def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst",
|
|
|
|
IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
|
2006-10-24 01:08:42 +00:00
|
|
|
PPC970_DGroup_Single;
|
2013-11-27 23:26:09 +00:00
|
|
|
def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
|
|
|
|
IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
|
2006-10-24 01:08:42 +00:00
|
|
|
PPC970_DGroup_Single;
|
2013-11-27 23:26:09 +00:00
|
|
|
def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
|
|
|
|
IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
|
2006-10-24 01:08:42 +00:00
|
|
|
PPC970_DGroup_Single;
|
2013-11-27 23:26:09 +00:00
|
|
|
def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), "dcbt $dst",
|
|
|
|
IIC_LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
|
2006-10-24 01:08:42 +00:00
|
|
|
PPC970_DGroup_Single;
|
2013-11-27 23:26:09 +00:00
|
|
|
def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), "dcbtst $dst",
|
|
|
|
IIC_LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
|
2006-10-24 01:08:42 +00:00
|
|
|
PPC970_DGroup_Single;
|
2013-11-27 23:26:09 +00:00
|
|
|
def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
|
|
|
|
IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
|
2006-10-24 01:08:42 +00:00
|
|
|
PPC970_DGroup_Single;
|
2013-11-27 23:26:09 +00:00
|
|
|
def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
|
|
|
|
IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
|
2006-10-24 01:08:42 +00:00
|
|
|
PPC970_DGroup_Single;
|
2006-11-14 19:19:53 +00:00
|
|
|
|
2012-04-01 20:08:17 +00:00
|
|
|
def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
|
|
|
|
(DCBT xoaddr:$dst)>;
|
|
|
|
|
2008-07-12 02:23:19 +00:00
|
|
|
// Atomic operations
|
2009-10-29 18:10:34 +00:00
|
|
|
let usesCustomInserter = 1 in {
|
2011-04-04 17:07:09 +00:00
|
|
|
let Defs = [CR0] in {
|
2008-08-28 17:53:09 +00:00
|
|
|
def ATOMIC_LOAD_ADD_I8 : Pseudo<
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
|
2008-08-28 17:53:09 +00:00
|
|
|
def ATOMIC_LOAD_SUB_I8 : Pseudo<
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
|
2008-08-28 17:53:09 +00:00
|
|
|
def ATOMIC_LOAD_AND_I8 : Pseudo<
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
|
2008-08-28 17:53:09 +00:00
|
|
|
def ATOMIC_LOAD_OR_I8 : Pseudo<
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
|
2008-08-28 17:53:09 +00:00
|
|
|
def ATOMIC_LOAD_XOR_I8 : Pseudo<
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
|
2008-08-28 17:53:09 +00:00
|
|
|
def ATOMIC_LOAD_NAND_I8 : Pseudo<
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
|
2008-08-28 17:53:09 +00:00
|
|
|
def ATOMIC_LOAD_ADD_I16 : Pseudo<
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
|
2008-08-28 17:53:09 +00:00
|
|
|
def ATOMIC_LOAD_SUB_I16 : Pseudo<
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
|
2008-08-28 17:53:09 +00:00
|
|
|
def ATOMIC_LOAD_AND_I16 : Pseudo<
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
|
2008-08-28 17:53:09 +00:00
|
|
|
def ATOMIC_LOAD_OR_I16 : Pseudo<
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
|
2008-08-28 17:53:09 +00:00
|
|
|
def ATOMIC_LOAD_XOR_I16 : Pseudo<
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
|
2008-08-28 17:53:09 +00:00
|
|
|
def ATOMIC_LOAD_NAND_I16 : Pseudo<
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
|
2008-07-12 02:23:19 +00:00
|
|
|
def ATOMIC_LOAD_ADD_I32 : Pseudo<
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
|
2008-08-25 22:34:37 +00:00
|
|
|
def ATOMIC_LOAD_SUB_I32 : Pseudo<
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
|
2008-08-25 22:34:37 +00:00
|
|
|
def ATOMIC_LOAD_AND_I32 : Pseudo<
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
|
2008-08-25 22:34:37 +00:00
|
|
|
def ATOMIC_LOAD_OR_I32 : Pseudo<
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
|
2008-08-25 22:34:37 +00:00
|
|
|
def ATOMIC_LOAD_XOR_I32 : Pseudo<
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
|
2008-08-25 22:34:37 +00:00
|
|
|
def ATOMIC_LOAD_NAND_I32 : Pseudo<
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
|
2008-08-25 22:34:37 +00:00
|
|
|
|
2008-08-28 17:53:09 +00:00
|
|
|
def ATOMIC_CMP_SWAP_I8 : Pseudo<
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
|
2008-08-28 17:53:09 +00:00
|
|
|
def ATOMIC_CMP_SWAP_I16 : Pseudo<
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
|
2008-08-22 03:49:10 +00:00
|
|
|
def ATOMIC_CMP_SWAP_I32 : Pseudo<
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
|
2008-08-25 22:34:37 +00:00
|
|
|
|
2008-08-28 17:53:09 +00:00
|
|
|
def ATOMIC_SWAP_I8 : Pseudo<
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
|
2008-08-28 17:53:09 +00:00
|
|
|
def ATOMIC_SWAP_I16 : Pseudo<
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
|
2008-08-25 21:09:52 +00:00
|
|
|
def ATOMIC_SWAP_I32 : Pseudo<
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
|
2008-08-22 03:49:10 +00:00
|
|
|
}
|
2008-04-19 01:30:48 +00:00
|
|
|
}
|
|
|
|
|
2008-07-12 02:23:19 +00:00
|
|
|
// Instructions to support atomic operations
|
2013-04-26 16:53:15 +00:00
|
|
|
def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
|
2013-11-27 23:26:09 +00:00
|
|
|
"lwarx $rD, $src", IIC_LdStLWARX,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$rD, (PPClarx xoaddr:$src))]>;
|
2008-07-12 02:23:19 +00:00
|
|
|
|
|
|
|
let Defs = [CR0] in
|
2013-04-26 16:53:15 +00:00
|
|
|
def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
|
2013-11-27 23:26:09 +00:00
|
|
|
"stwcx. $rS, $dst", IIC_LdStSTWCX,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(PPCstcx i32:$rS, xoaddr:$dst)]>,
|
2008-07-12 02:23:19 +00:00
|
|
|
isDOT;
|
|
|
|
|
2010-05-14 16:46:02 +00:00
|
|
|
let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
|
2013-11-27 23:26:09 +00:00
|
|
|
def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
|
2008-08-11 17:36:31 +00:00
|
|
|
|
2013-07-04 14:40:12 +00:00
|
|
|
def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
|
2013-11-27 23:26:09 +00:00
|
|
|
"twi $to, $rA, $imm", IIC_IntTrapW, []>;
|
2013-07-04 14:40:12 +00:00
|
|
|
def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"tw $to, $rA, $rB", IIC_IntTrapW, []>;
|
2013-07-04 14:40:12 +00:00
|
|
|
def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
|
2013-11-27 23:26:09 +00:00
|
|
|
"tdi $to, $rA, $imm", IIC_IntTrapD, []>;
|
2013-07-04 14:40:12 +00:00
|
|
|
def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"td $to, $rA, $rB", IIC_IntTrapD, []>;
|
2013-07-04 14:40:12 +00:00
|
|
|
|
2006-11-14 19:19:53 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// PPC32 Load Instructions.
|
2004-08-30 02:28:06 +00:00
|
|
|
//
|
2006-11-14 19:19:53 +00:00
|
|
|
|
2006-11-15 02:43:19 +00:00
|
|
|
// Unindexed (r+i) Loads.
|
2008-12-03 18:15:48 +00:00
|
|
|
let canFoldAsLoad = 1, PPC970_Unit = 2 in {
|
2013-04-26 16:53:15 +00:00
|
|
|
def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
|
2013-11-27 23:26:09 +00:00
|
|
|
"lbz $rD, $src", IIC_LdStLoad,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$rD, (zextloadi8 iaddr:$src))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
|
2013-11-27 23:26:09 +00:00
|
|
|
"lha $rD, $src", IIC_LdStLHA,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$rD, (sextloadi16 iaddr:$src))]>,
|
2006-03-13 05:15:10 +00:00
|
|
|
PPC970_DGroup_Cracked;
|
2013-04-26 16:53:15 +00:00
|
|
|
def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
|
2013-11-27 23:26:09 +00:00
|
|
|
"lhz $rD, $src", IIC_LdStLoad,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$rD, (zextloadi16 iaddr:$src))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
|
2013-11-27 23:26:09 +00:00
|
|
|
"lwz $rD, $src", IIC_LdStLoad,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$rD, (load iaddr:$src))]>;
|
2006-11-08 02:13:12 +00:00
|
|
|
|
2013-04-26 16:53:15 +00:00
|
|
|
def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
|
2013-11-27 23:26:09 +00:00
|
|
|
"lfs $rD, $src", IIC_LdStLFD,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set f32:$rD, (load iaddr:$src))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
|
2013-11-27 23:26:09 +00:00
|
|
|
"lfd $rD, $src", IIC_LdStLFD,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set f64:$rD, (load iaddr:$src))]>;
|
2006-11-10 02:08:47 +00:00
|
|
|
|
|
|
|
|
2006-11-15 02:43:19 +00:00
|
|
|
// Unindexed (r+i) Loads with Update (preinc).
|
2013-04-07 05:46:58 +00:00
|
|
|
let mayLoad = 1, neverHasSideEffects = 1 in {
|
2013-04-26 16:53:15 +00:00
|
|
|
def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
|
2013-11-27 23:26:09 +00:00
|
|
|
"lbzu $rD, $addr", IIC_LdStLoadUpd,
|
2006-11-15 23:24:18 +00:00
|
|
|
[]>, RegConstraint<"$addr.reg = $ea_result">,
|
|
|
|
NoEncode<"$ea_result">;
|
2006-11-15 02:43:19 +00:00
|
|
|
|
2013-04-26 16:53:15 +00:00
|
|
|
def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
|
2013-11-27 23:26:09 +00:00
|
|
|
"lhau $rD, $addr", IIC_LdStLHAU,
|
2006-11-15 23:24:18 +00:00
|
|
|
[]>, RegConstraint<"$addr.reg = $ea_result">,
|
|
|
|
NoEncode<"$ea_result">;
|
2006-11-15 02:43:19 +00:00
|
|
|
|
2013-04-26 16:53:15 +00:00
|
|
|
def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
|
2013-11-27 23:26:09 +00:00
|
|
|
"lhzu $rD, $addr", IIC_LdStLoadUpd,
|
2006-11-15 23:24:18 +00:00
|
|
|
[]>, RegConstraint<"$addr.reg = $ea_result">,
|
|
|
|
NoEncode<"$ea_result">;
|
2006-11-15 02:43:19 +00:00
|
|
|
|
2013-04-26 16:53:15 +00:00
|
|
|
def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
|
2013-11-27 23:26:09 +00:00
|
|
|
"lwzu $rD, $addr", IIC_LdStLoadUpd,
|
2006-11-15 23:24:18 +00:00
|
|
|
[]>, RegConstraint<"$addr.reg = $ea_result">,
|
|
|
|
NoEncode<"$ea_result">;
|
2006-11-15 02:43:19 +00:00
|
|
|
|
2013-04-26 16:53:15 +00:00
|
|
|
def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
|
2013-11-27 23:26:09 +00:00
|
|
|
"lfsu $rD, $addr", IIC_LdStLFDU,
|
2006-11-15 23:24:18 +00:00
|
|
|
[]>, RegConstraint<"$addr.reg = $ea_result">,
|
|
|
|
NoEncode<"$ea_result">;
|
|
|
|
|
2013-04-26 16:53:15 +00:00
|
|
|
def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
|
2013-11-27 23:26:09 +00:00
|
|
|
"lfdu $rD, $addr", IIC_LdStLFDU,
|
2006-11-15 23:24:18 +00:00
|
|
|
[]>, RegConstraint<"$addr.reg = $ea_result">,
|
|
|
|
NoEncode<"$ea_result">;
|
2012-06-20 15:43:03 +00:00
|
|
|
|
|
|
|
|
|
|
|
// Indexed (r+r) Loads with Update (preinc).
|
2013-04-26 16:53:15 +00:00
|
|
|
def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
|
2012-06-20 15:43:03 +00:00
|
|
|
(ins memrr:$addr),
|
2013-11-30 20:41:13 +00:00
|
|
|
"lbzux $rD, $addr", IIC_LdStLoadUpdX,
|
2013-03-22 14:59:13 +00:00
|
|
|
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
|
2012-06-20 15:43:03 +00:00
|
|
|
NoEncode<"$ea_result">;
|
|
|
|
|
2013-04-26 16:53:15 +00:00
|
|
|
def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
|
2012-06-20 15:43:03 +00:00
|
|
|
(ins memrr:$addr),
|
2013-11-30 20:41:13 +00:00
|
|
|
"lhaux $rD, $addr", IIC_LdStLHAUX,
|
2013-03-22 14:59:13 +00:00
|
|
|
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
|
2012-06-20 15:43:03 +00:00
|
|
|
NoEncode<"$ea_result">;
|
|
|
|
|
2013-04-26 16:53:15 +00:00
|
|
|
def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
|
2012-06-20 15:43:03 +00:00
|
|
|
(ins memrr:$addr),
|
2013-11-30 20:41:13 +00:00
|
|
|
"lhzux $rD, $addr", IIC_LdStLoadUpdX,
|
2013-03-22 14:59:13 +00:00
|
|
|
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
|
2012-06-20 15:43:03 +00:00
|
|
|
NoEncode<"$ea_result">;
|
|
|
|
|
2013-04-26 16:53:15 +00:00
|
|
|
def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
|
2012-06-20 15:43:03 +00:00
|
|
|
(ins memrr:$addr),
|
2013-11-30 20:41:13 +00:00
|
|
|
"lwzux $rD, $addr", IIC_LdStLoadUpdX,
|
2013-03-22 14:59:13 +00:00
|
|
|
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
|
2012-06-20 15:43:03 +00:00
|
|
|
NoEncode<"$ea_result">;
|
|
|
|
|
2013-04-26 16:53:15 +00:00
|
|
|
def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
|
2012-06-20 15:43:03 +00:00
|
|
|
(ins memrr:$addr),
|
2013-11-30 20:41:13 +00:00
|
|
|
"lfsux $rD, $addr", IIC_LdStLFDUX,
|
2013-03-22 14:59:13 +00:00
|
|
|
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
|
2012-06-20 15:43:03 +00:00
|
|
|
NoEncode<"$ea_result">;
|
|
|
|
|
2013-04-26 16:53:15 +00:00
|
|
|
def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
|
2012-06-20 15:43:03 +00:00
|
|
|
(ins memrr:$addr),
|
2013-11-30 20:41:13 +00:00
|
|
|
"lfdux $rD, $addr", IIC_LdStLFDUX,
|
2013-03-22 14:59:13 +00:00
|
|
|
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
|
2012-06-20 15:43:03 +00:00
|
|
|
NoEncode<"$ea_result">;
|
2004-10-07 22:30:03 +00:00
|
|
|
}
|
2008-12-03 02:30:17 +00:00
|
|
|
}
|
2006-11-08 02:13:12 +00:00
|
|
|
|
2006-11-15 02:43:19 +00:00
|
|
|
// Indexed (r+r) Loads.
|
2006-11-14 19:19:53 +00:00
|
|
|
//
|
2008-12-03 18:15:48 +00:00
|
|
|
let canFoldAsLoad = 1, PPC970_Unit = 2 in {
|
2013-04-26 16:53:15 +00:00
|
|
|
def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
|
2013-11-27 23:26:09 +00:00
|
|
|
"lbzx $rD, $src", IIC_LdStLoad,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$rD, (zextloadi8 xaddr:$src))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
|
2013-11-27 23:26:09 +00:00
|
|
|
"lhax $rD, $src", IIC_LdStLHA,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$rD, (sextloadi16 xaddr:$src))]>,
|
2006-11-14 19:19:53 +00:00
|
|
|
PPC970_DGroup_Cracked;
|
2013-04-26 16:53:15 +00:00
|
|
|
def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
|
2013-11-27 23:26:09 +00:00
|
|
|
"lhzx $rD, $src", IIC_LdStLoad,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$rD, (zextloadi16 xaddr:$src))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
|
2013-11-27 23:26:09 +00:00
|
|
|
"lwzx $rD, $src", IIC_LdStLoad,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$rD, (load xaddr:$src))]>;
|
2006-11-14 19:19:53 +00:00
|
|
|
|
|
|
|
|
2013-04-26 16:53:15 +00:00
|
|
|
def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
|
2013-11-27 23:26:09 +00:00
|
|
|
"lhbrx $rD, $src", IIC_LdStLoad,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
|
2013-11-27 23:26:09 +00:00
|
|
|
"lwbrx $rD, $src", IIC_LdStLoad,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
|
2006-11-14 19:19:53 +00:00
|
|
|
|
2013-04-26 16:53:15 +00:00
|
|
|
def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
|
2013-11-27 23:26:09 +00:00
|
|
|
"lfsx $frD, $src", IIC_LdStLFD,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set f32:$frD, (load xaddr:$src))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
|
2013-11-27 23:26:09 +00:00
|
|
|
"lfdx $frD, $src", IIC_LdStLFD,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set f64:$frD, (load xaddr:$src))]>;
|
2013-03-31 10:12:51 +00:00
|
|
|
|
2013-04-26 16:53:15 +00:00
|
|
|
def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
|
2013-11-27 23:26:09 +00:00
|
|
|
"lfiwax $frD, $src", IIC_LdStLFD,
|
2013-03-31 10:12:51 +00:00
|
|
|
[(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
|
2013-11-27 23:26:09 +00:00
|
|
|
"lfiwzx $frD, $src", IIC_LdStLFD,
|
2013-04-01 17:52:07 +00:00
|
|
|
[(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
|
2006-11-14 19:19:53 +00:00
|
|
|
}
|
|
|
|
|
2013-07-03 18:29:47 +00:00
|
|
|
// Load Multiple
|
|
|
|
def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
|
2013-11-27 23:26:09 +00:00
|
|
|
"lmw $rD, $src", IIC_LdStLMW, []>;
|
2013-07-03 18:29:47 +00:00
|
|
|
|
2006-11-14 19:19:53 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// PPC32 Store Instructions.
|
|
|
|
//
|
|
|
|
|
2006-11-15 02:43:19 +00:00
|
|
|
// Unindexed (r+i) Stores.
|
2008-01-06 05:53:26 +00:00
|
|
|
let PPC970_Unit = 2 in {
|
2013-04-26 16:53:15 +00:00
|
|
|
def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
|
2013-11-27 23:26:09 +00:00
|
|
|
"stb $rS, $src", IIC_LdStStore,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(truncstorei8 i32:$rS, iaddr:$src)]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
|
2013-11-27 23:26:09 +00:00
|
|
|
"sth $rS, $src", IIC_LdStStore,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(truncstorei16 i32:$rS, iaddr:$src)]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
|
2013-11-27 23:26:09 +00:00
|
|
|
"stw $rS, $src", IIC_LdStStore,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(store i32:$rS, iaddr:$src)]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
|
2013-11-27 23:26:09 +00:00
|
|
|
"stfs $rS, $dst", IIC_LdStSTFD,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(store f32:$rS, iaddr:$dst)]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
|
2013-11-27 23:26:09 +00:00
|
|
|
"stfd $rS, $dst", IIC_LdStSTFD,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(store f64:$rS, iaddr:$dst)]>;
|
2006-11-14 19:19:53 +00:00
|
|
|
}
|
|
|
|
|
2006-11-15 02:43:19 +00:00
|
|
|
// Unindexed (r+i) Stores with Update (preinc).
|
2013-03-19 19:52:04 +00:00
|
|
|
let PPC970_Unit = 2, mayStore = 1 in {
|
2013-04-26 16:53:15 +00:00
|
|
|
def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
|
2013-11-27 23:26:09 +00:00
|
|
|
"stbu $rS, $dst", IIC_LdStStoreUpd, []>,
|
2013-03-19 19:52:04 +00:00
|
|
|
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
|
2013-04-26 16:53:15 +00:00
|
|
|
def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
|
2013-11-27 23:26:09 +00:00
|
|
|
"sthu $rS, $dst", IIC_LdStStoreUpd, []>,
|
2013-03-19 19:52:04 +00:00
|
|
|
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
|
2013-04-26 16:53:15 +00:00
|
|
|
def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
|
2013-11-27 23:26:09 +00:00
|
|
|
"stwu $rS, $dst", IIC_LdStStoreUpd, []>,
|
2013-03-19 19:52:04 +00:00
|
|
|
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
|
2013-04-26 16:53:15 +00:00
|
|
|
def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
|
2013-11-27 23:26:09 +00:00
|
|
|
"stfsu $rS, $dst", IIC_LdStSTFDU, []>,
|
2013-03-19 19:52:04 +00:00
|
|
|
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
|
2013-04-26 16:53:15 +00:00
|
|
|
def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
|
2013-11-27 23:26:09 +00:00
|
|
|
"stfdu $rS, $dst", IIC_LdStSTFDU, []>,
|
2013-03-19 19:52:04 +00:00
|
|
|
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Patterns to match the pre-inc stores. We can't put the patterns on
|
|
|
|
// the instruction definitions directly as ISel wants the address base
|
|
|
|
// and offset to be separate operands, not a single complex operand.
|
2013-03-25 19:04:58 +00:00
|
|
|
def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
|
|
|
|
(STBU $rS, iaddroff:$ptroff, $ptrreg)>;
|
|
|
|
def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
|
|
|
|
(STHU $rS, iaddroff:$ptroff, $ptrreg)>;
|
|
|
|
def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
|
|
|
|
(STWU $rS, iaddroff:$ptroff, $ptrreg)>;
|
|
|
|
def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
|
|
|
|
(STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
|
|
|
|
def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
|
|
|
|
(STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
|
2006-11-15 02:43:19 +00:00
|
|
|
|
2006-11-14 19:19:53 +00:00
|
|
|
// Indexed (r+r) Stores.
|
2008-01-06 05:53:26 +00:00
|
|
|
let PPC970_Unit = 2 in {
|
2013-04-26 16:53:15 +00:00
|
|
|
def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
|
2013-11-27 23:26:09 +00:00
|
|
|
"stbx $rS, $dst", IIC_LdStStore,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(truncstorei8 i32:$rS, xaddr:$dst)]>,
|
2006-11-14 19:19:53 +00:00
|
|
|
PPC970_DGroup_Cracked;
|
2013-04-26 16:53:15 +00:00
|
|
|
def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
|
2013-11-27 23:26:09 +00:00
|
|
|
"sthx $rS, $dst", IIC_LdStStore,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(truncstorei16 i32:$rS, xaddr:$dst)]>,
|
2006-11-14 19:19:53 +00:00
|
|
|
PPC970_DGroup_Cracked;
|
2013-04-26 16:53:15 +00:00
|
|
|
def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
|
2013-11-27 23:26:09 +00:00
|
|
|
"stwx $rS, $dst", IIC_LdStStore,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(store i32:$rS, xaddr:$dst)]>,
|
2006-11-14 19:19:53 +00:00
|
|
|
PPC970_DGroup_Cracked;
|
2012-06-19 02:34:32 +00:00
|
|
|
|
2013-04-26 16:53:15 +00:00
|
|
|
def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
|
2013-11-27 23:26:09 +00:00
|
|
|
"sthbrx $rS, $dst", IIC_LdStStore,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
|
2006-11-14 19:19:53 +00:00
|
|
|
PPC970_DGroup_Cracked;
|
2013-04-26 16:53:15 +00:00
|
|
|
def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
|
2013-11-27 23:26:09 +00:00
|
|
|
"stwbrx $rS, $dst", IIC_LdStStore,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
|
2006-11-14 19:19:53 +00:00
|
|
|
PPC970_DGroup_Cracked;
|
|
|
|
|
2013-04-26 16:53:15 +00:00
|
|
|
def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
|
2013-11-27 23:26:09 +00:00
|
|
|
"stfiwx $frS, $dst", IIC_LdStSTFD,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
|
2008-01-06 06:44:58 +00:00
|
|
|
|
2013-04-26 16:53:15 +00:00
|
|
|
def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
|
2013-11-27 23:26:09 +00:00
|
|
|
"stfsx $frS, $dst", IIC_LdStSTFD,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(store f32:$frS, xaddr:$dst)]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
|
2013-11-27 23:26:09 +00:00
|
|
|
"stfdx $frS, $dst", IIC_LdStSTFD,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(store f64:$frS, xaddr:$dst)]>;
|
2006-11-14 19:19:53 +00:00
|
|
|
}
|
|
|
|
|
2013-03-19 19:52:04 +00:00
|
|
|
// Indexed (r+r) Stores with Update (preinc).
|
|
|
|
let PPC970_Unit = 2, mayStore = 1 in {
|
2013-04-26 16:53:15 +00:00
|
|
|
def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
|
2013-11-27 23:26:09 +00:00
|
|
|
"stbux $rS, $dst", IIC_LdStStoreUpd, []>,
|
2013-03-22 14:59:13 +00:00
|
|
|
RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
|
2013-03-19 19:52:04 +00:00
|
|
|
PPC970_DGroup_Cracked;
|
2013-04-26 16:53:15 +00:00
|
|
|
def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
|
2013-11-27 23:26:09 +00:00
|
|
|
"sthux $rS, $dst", IIC_LdStStoreUpd, []>,
|
2013-03-22 14:59:13 +00:00
|
|
|
RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
|
2013-03-19 19:52:04 +00:00
|
|
|
PPC970_DGroup_Cracked;
|
2013-04-26 16:53:15 +00:00
|
|
|
def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
|
2013-11-27 23:26:09 +00:00
|
|
|
"stwux $rS, $dst", IIC_LdStStoreUpd, []>,
|
2013-03-22 14:59:13 +00:00
|
|
|
RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
|
2013-03-19 19:52:04 +00:00
|
|
|
PPC970_DGroup_Cracked;
|
2013-04-26 16:53:15 +00:00
|
|
|
def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
|
2013-11-27 23:26:09 +00:00
|
|
|
"stfsux $rS, $dst", IIC_LdStSTFDU, []>,
|
2013-03-22 14:59:13 +00:00
|
|
|
RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
|
2013-03-19 19:52:04 +00:00
|
|
|
PPC970_DGroup_Cracked;
|
2013-04-26 16:53:15 +00:00
|
|
|
def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
|
2013-11-27 23:26:09 +00:00
|
|
|
"stfdux $rS, $dst", IIC_LdStSTFDU, []>,
|
2013-03-22 14:59:13 +00:00
|
|
|
RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
|
2013-03-19 19:52:04 +00:00
|
|
|
PPC970_DGroup_Cracked;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Patterns to match the pre-inc stores. We can't put the patterns on
|
|
|
|
// the instruction definitions directly as ISel wants the address base
|
|
|
|
// and offset to be separate operands, not a single complex operand.
|
2013-03-25 19:04:58 +00:00
|
|
|
def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
|
|
|
|
(STBUX $rS, $ptrreg, $ptroff)>;
|
|
|
|
def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
|
|
|
|
(STHUX $rS, $ptrreg, $ptroff)>;
|
|
|
|
def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
|
|
|
|
(STWUX $rS, $ptrreg, $ptroff)>;
|
|
|
|
def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
|
|
|
|
(STFSUX $rS, $ptrreg, $ptroff)>;
|
|
|
|
def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
|
|
|
|
(STFDUX $rS, $ptrreg, $ptroff)>;
|
2013-03-19 19:52:04 +00:00
|
|
|
|
2013-07-03 18:29:47 +00:00
|
|
|
// Store Multiple
|
|
|
|
def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
|
2013-11-27 23:26:09 +00:00
|
|
|
"stmw $rS, $dst", IIC_LdStLMW, []>;
|
2013-07-03 18:29:47 +00:00
|
|
|
|
2013-07-01 16:37:52 +00:00
|
|
|
def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
|
2014-01-22 20:20:52 +00:00
|
|
|
"sync $L", IIC_LdStSync, []>, Requires<[IsNotBookE]>;
|
|
|
|
|
|
|
|
let isCodeGenOnly = 1 in {
|
|
|
|
def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
|
|
|
|
"msync", IIC_LdStSync, []>, Requires<[IsBookE]> {
|
|
|
|
let L = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[IsNotBookE]>;
|
|
|
|
def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[IsBookE]>;
|
2006-11-14 19:19:53 +00:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// PPC32 Arithmetic Instructions.
|
|
|
|
//
|
2006-11-08 02:13:12 +00:00
|
|
|
|
2006-03-12 09:13:49 +00:00
|
|
|
let PPC970_Unit = 1 in { // FXU Operations.
|
2013-05-23 22:48:06 +00:00
|
|
|
def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
|
2013-11-27 23:26:09 +00:00
|
|
|
"addi $rD, $rA, $imm", IIC_IntSimple,
|
Change some PowerPC PatLeaf definitions to ImmLeaf for fast-isel.
Using PatLeaf rather than ImmLeaf when defining immediate predicates
prevents simple patterns using those predicates from being recognized
for fast instruction selection. This patch replaces the immSExt16
PatLeaf predicate with two ImmLeaf predicates, imm32SExt16 and
imm64SExt16, allowing a few more patterns to be recognized (ADDI,
ADDIC, MULLI, ADDI8, and ADDIC8). Using the new predicates does not
help for LI, LI8, SUBFIC, and SUBFIC8 because these are rejected for
other reasons, but I see no reason to retain the PatLeaf predicate.
No functional change intended, and thus no test cases yet. This is
preliminary work for enabling fast-isel support for PowerPC. When
that support is ready, we'll be able to test this function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182510 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 20:09:24 +00:00
|
|
|
[(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
|
2013-04-12 18:17:57 +00:00
|
|
|
let BaseName = "addic" in {
|
|
|
|
let Defs = [CARRY] in
|
2013-04-26 16:53:15 +00:00
|
|
|
def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
|
2013-11-27 23:26:09 +00:00
|
|
|
"addic $rD, $rA, $imm", IIC_IntGeneral,
|
Change some PowerPC PatLeaf definitions to ImmLeaf for fast-isel.
Using PatLeaf rather than ImmLeaf when defining immediate predicates
prevents simple patterns using those predicates from being recognized
for fast instruction selection. This patch replaces the immSExt16
PatLeaf predicate with two ImmLeaf predicates, imm32SExt16 and
imm64SExt16, allowing a few more patterns to be recognized (ADDI,
ADDIC, MULLI, ADDI8, and ADDIC8). Using the new predicates does not
help for LI, LI8, SUBFIC, and SUBFIC8 because these are rejected for
other reasons, but I see no reason to retain the PatLeaf predicate.
No functional change intended, and thus no test cases yet. This is
preliminary work for enabling fast-isel support for PowerPC. When
that support is ready, we'll be able to test this function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182510 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 20:09:24 +00:00
|
|
|
[(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
|
2013-04-12 02:18:09 +00:00
|
|
|
RecFormRel, PPC970_DGroup_Cracked;
|
2013-04-12 18:17:57 +00:00
|
|
|
let Defs = [CARRY, CR0] in
|
2013-04-26 16:53:15 +00:00
|
|
|
def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
|
2013-11-27 23:26:09 +00:00
|
|
|
"addic. $rD, $rA, $imm", IIC_IntGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[]>, isDOT, RecFormRel;
|
2009-09-18 20:15:22 +00:00
|
|
|
}
|
2013-06-26 13:49:53 +00:00
|
|
|
def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
|
2013-11-27 23:26:09 +00:00
|
|
|
"addis $rD, $rA, $imm", IIC_IntSimple,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
|
2013-03-26 10:57:16 +00:00
|
|
|
let isCodeGenOnly = 1 in
|
2013-05-23 22:48:06 +00:00
|
|
|
def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
|
2013-11-27 23:26:09 +00:00
|
|
|
"la $rD, $sym($rA)", IIC_IntGeneral,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$rD, (add i32:$rA,
|
2005-11-17 17:52:01 +00:00
|
|
|
(PPClo tglobaladdr:$sym, 0)))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
|
2013-11-27 23:26:09 +00:00
|
|
|
"mulli $rD, $rA, $imm", IIC_IntMulLI,
|
Change some PowerPC PatLeaf definitions to ImmLeaf for fast-isel.
Using PatLeaf rather than ImmLeaf when defining immediate predicates
prevents simple patterns using those predicates from being recognized
for fast instruction selection. This patch replaces the immSExt16
PatLeaf predicate with two ImmLeaf predicates, imm32SExt16 and
imm64SExt16, allowing a few more patterns to be recognized (ADDI,
ADDIC, MULLI, ADDI8, and ADDIC8). Using the new predicates does not
help for LI, LI8, SUBFIC, and SUBFIC8 because these are rejected for
other reasons, but I see no reason to retain the PatLeaf predicate.
No functional change intended, and thus no test cases yet. This is
preliminary work for enabling fast-isel support for PowerPC. When
that support is ready, we'll be able to test this function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182510 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 20:09:24 +00:00
|
|
|
[(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
|
2013-04-12 18:17:57 +00:00
|
|
|
let Defs = [CARRY] in
|
2013-04-26 16:53:15 +00:00
|
|
|
def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
|
2013-11-27 23:26:09 +00:00
|
|
|
"subfic $rD, $rA, $imm", IIC_IntGeneral,
|
Change some PowerPC PatLeaf definitions to ImmLeaf for fast-isel.
Using PatLeaf rather than ImmLeaf when defining immediate predicates
prevents simple patterns using those predicates from being recognized
for fast instruction selection. This patch replaces the immSExt16
PatLeaf predicate with two ImmLeaf predicates, imm32SExt16 and
imm64SExt16, allowing a few more patterns to be recognized (ADDI,
ADDIC, MULLI, ADDI8, and ADDIC8). Using the new predicates does not
help for LI, LI8, SUBFIC, and SUBFIC8 because these are rejected for
other reasons, but I see no reason to retain the PatLeaf predicate.
No functional change intended, and thus no test cases yet. This is
preliminary work for enabling fast-isel support for PowerPC. When
that support is ready, we'll be able to test this function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182510 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 20:09:24 +00:00
|
|
|
[(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44687 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-07 21:42:31 +00:00
|
|
|
|
2012-08-28 02:10:33 +00:00
|
|
|
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
|
2013-05-23 22:48:06 +00:00
|
|
|
def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
|
2013-11-27 23:26:09 +00:00
|
|
|
"li $rD, $imm", IIC_IntSimple,
|
Change some PowerPC PatLeaf definitions to ImmLeaf for fast-isel.
Using PatLeaf rather than ImmLeaf when defining immediate predicates
prevents simple patterns using those predicates from being recognized
for fast instruction selection. This patch replaces the immSExt16
PatLeaf predicate with two ImmLeaf predicates, imm32SExt16 and
imm64SExt16, allowing a few more patterns to be recognized (ADDI,
ADDIC, MULLI, ADDI8, and ADDIC8). Using the new predicates does not
help for LI, LI8, SUBFIC, and SUBFIC8 because these are rejected for
other reasons, but I see no reason to retain the PatLeaf predicate.
No functional change intended, and thus no test cases yet. This is
preliminary work for enabling fast-isel support for PowerPC. When
that support is ready, we'll be able to test this function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182510 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 20:09:24 +00:00
|
|
|
[(set i32:$rD, imm32SExt16:$imm)]>;
|
2013-06-26 13:49:53 +00:00
|
|
|
def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
|
2013-11-27 23:26:09 +00:00
|
|
|
"lis $rD, $imm", IIC_IntSimple,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$rD, imm16ShiftedSExt:$imm)]>;
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44687 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-07 21:42:31 +00:00
|
|
|
}
|
2006-03-12 09:13:49 +00:00
|
|
|
}
|
2006-11-14 19:19:53 +00:00
|
|
|
|
2006-03-12 09:13:49 +00:00
|
|
|
let PPC970_Unit = 1 in { // FXU Operations.
|
2013-04-12 18:17:57 +00:00
|
|
|
let Defs = [CR0] in {
|
2013-04-26 16:53:15 +00:00
|
|
|
def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
|
2013-11-27 23:26:09 +00:00
|
|
|
"andi. $dst, $src1, $src2", IIC_IntGeneral,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
|
2006-02-12 09:09:52 +00:00
|
|
|
isDOT;
|
2013-04-26 16:53:15 +00:00
|
|
|
def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
|
2013-11-27 23:26:09 +00:00
|
|
|
"andis. $dst, $src1, $src2", IIC_IntGeneral,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
|
2006-02-12 09:09:52 +00:00
|
|
|
isDOT;
|
2013-04-12 18:17:57 +00:00
|
|
|
}
|
2013-04-26 16:53:15 +00:00
|
|
|
def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
|
2013-11-27 23:26:09 +00:00
|
|
|
"ori $dst, $src1, $src2", IIC_IntSimple,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
|
2013-11-27 23:26:09 +00:00
|
|
|
"oris $dst, $src1, $src2", IIC_IntSimple,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
|
2013-11-27 23:26:09 +00:00
|
|
|
"xori $dst, $src1, $src2", IIC_IntSimple,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
|
2013-11-27 23:26:09 +00:00
|
|
|
"xoris $dst, $src1, $src2", IIC_IntSimple,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
|
2013-12-12 00:19:11 +00:00
|
|
|
|
2013-11-27 23:26:09 +00:00
|
|
|
def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
|
2005-12-09 23:54:18 +00:00
|
|
|
[]>;
|
2013-12-12 00:19:11 +00:00
|
|
|
let isCodeGenOnly = 1 in {
|
|
|
|
// The POWER6 and POWER7 have special group-terminating nops.
|
|
|
|
def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
|
|
|
|
"ori 1, 1, 0", IIC_IntSimple, []>;
|
|
|
|
def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
|
|
|
|
"ori 2, 2, 0", IIC_IntSimple, []>;
|
|
|
|
}
|
|
|
|
|
2013-04-15 02:37:46 +00:00
|
|
|
let isCompare = 1, neverHasSideEffects = 1 in {
|
2013-04-26 16:53:15 +00:00
|
|
|
def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
|
2013-11-27 23:26:09 +00:00
|
|
|
"cmpwi $crD, $rA, $imm", IIC_IntCompare>;
|
2013-04-26 16:53:15 +00:00
|
|
|
def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
|
2013-11-27 23:26:09 +00:00
|
|
|
"cmplwi $dst, $src1, $src2", IIC_IntCompare>;
|
2013-04-15 02:37:46 +00:00
|
|
|
}
|
2006-03-12 09:13:49 +00:00
|
|
|
}
|
2006-07-10 20:56:58 +00:00
|
|
|
|
2013-04-12 02:18:09 +00:00
|
|
|
let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
|
2014-03-24 15:07:28 +00:00
|
|
|
let isCommutable = 1 in {
|
2013-04-26 16:53:15 +00:00
|
|
|
defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"nand", "$rA, $rS, $rB", IIC_IntSimple,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"and", "$rA, $rS, $rB", IIC_IntSimple,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set i32:$rA, (and i32:$rS, i32:$rB))]>;
|
2014-03-24 15:07:28 +00:00
|
|
|
} // isCommutable
|
2013-04-26 16:53:15 +00:00
|
|
|
defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"andc", "$rA, $rS, $rB", IIC_IntSimple,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
|
2014-03-24 15:07:28 +00:00
|
|
|
let isCommutable = 1 in {
|
2013-04-26 16:53:15 +00:00
|
|
|
defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"or", "$rA, $rS, $rB", IIC_IntSimple,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set i32:$rA, (or i32:$rS, i32:$rB))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"nor", "$rA, $rS, $rB", IIC_IntSimple,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
|
2014-03-24 15:07:28 +00:00
|
|
|
} // isCommutable
|
2013-04-26 16:53:15 +00:00
|
|
|
defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"orc", "$rA, $rS, $rB", IIC_IntSimple,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
|
2014-03-24 15:07:28 +00:00
|
|
|
let isCommutable = 1 in {
|
2013-04-26 16:53:15 +00:00
|
|
|
defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"eqv", "$rA, $rS, $rB", IIC_IntSimple,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"xor", "$rA, $rS, $rB", IIC_IntSimple,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
|
2014-03-24 15:07:28 +00:00
|
|
|
} // isCommutable
|
2013-04-26 16:53:15 +00:00
|
|
|
defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"slw", "$rA, $rS, $rB", IIC_IntGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"srw", "$rA, $rS, $rB", IIC_IntGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"sraw", "$rA, $rS, $rB", IIC_IntShift,
|
2013-04-12 18:17:57 +00:00
|
|
|
[(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
|
2009-09-18 20:15:22 +00:00
|
|
|
}
|
2006-11-14 19:19:53 +00:00
|
|
|
|
2006-03-12 09:13:49 +00:00
|
|
|
let PPC970_Unit = 1 in { // FXU Operations.
|
2013-04-12 02:18:09 +00:00
|
|
|
let neverHasSideEffects = 1 in {
|
2013-04-26 16:53:15 +00:00
|
|
|
defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
|
2013-11-27 23:26:09 +00:00
|
|
|
"srawi", "$rA, $rS, $SH", IIC_IntShift,
|
2013-04-12 18:17:57 +00:00
|
|
|
[(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
|
2013-11-27 23:26:09 +00:00
|
|
|
"cntlzw", "$rA, $rS", IIC_IntGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set i32:$rA, (ctlz i32:$rS))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
|
2013-11-27 23:26:09 +00:00
|
|
|
"extsb", "$rA, $rS", IIC_IntSimple,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
|
2013-11-27 23:26:09 +00:00
|
|
|
"extsh", "$rA, $rS", IIC_IntSimple,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
|
|
|
|
}
|
2013-04-15 02:37:46 +00:00
|
|
|
let isCompare = 1, neverHasSideEffects = 1 in {
|
2013-04-26 16:53:15 +00:00
|
|
|
def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"cmpw $crD, $rA, $rB", IIC_IntCompare>;
|
2013-04-26 16:53:15 +00:00
|
|
|
def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"cmplw $crD, $rA, $rB", IIC_IntCompare>;
|
2013-04-15 02:37:46 +00:00
|
|
|
}
|
2006-03-12 09:13:49 +00:00
|
|
|
}
|
|
|
|
let PPC970_Unit = 3 in { // FPU Operations.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
//def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
|
2013-11-27 23:26:09 +00:00
|
|
|
// "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
|
2013-04-15 02:37:46 +00:00
|
|
|
let isCompare = 1, neverHasSideEffects = 1 in {
|
2013-04-26 16:53:15 +00:00
|
|
|
def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fcmpu $crD, $fA, $fB", IIC_FPCompare>;
|
2013-12-17 23:05:18 +00:00
|
|
|
let Interpretation64Bit = 1, isCodeGenOnly = 1 in
|
2013-04-26 16:53:15 +00:00
|
|
|
def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fcmpu $crD, $fA, $fB", IIC_FPCompare>;
|
2013-04-15 02:37:46 +00:00
|
|
|
}
|
2006-11-14 19:19:53 +00:00
|
|
|
|
2008-10-29 18:26:45 +00:00
|
|
|
let Uses = [RM] in {
|
2013-04-12 02:18:09 +00:00
|
|
|
let neverHasSideEffects = 1 in {
|
2013-09-26 04:11:24 +00:00
|
|
|
defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fctiw", "$frD, $frB", IIC_FPGeneral,
|
2013-09-26 05:22:11 +00:00
|
|
|
[]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fctiwz", "$frD, $frB", IIC_FPGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set f64:$frD, (PPCfctiwz f64:$frB))]>;
|
2013-03-29 08:57:48 +00:00
|
|
|
|
2013-04-26 16:53:15 +00:00
|
|
|
defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"frsp", "$frD, $frB", IIC_FPGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set f32:$frD, (fround f64:$frB))]>;
|
2013-03-29 08:57:48 +00:00
|
|
|
|
2013-12-17 23:05:18 +00:00
|
|
|
let Interpretation64Bit = 1, isCodeGenOnly = 1 in
|
2013-04-26 16:53:15 +00:00
|
|
|
defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"frin", "$frD, $frB", IIC_FPGeneral,
|
2013-08-08 04:31:34 +00:00
|
|
|
[(set f64:$frD, (frnd f64:$frB))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"frin", "$frD, $frB", IIC_FPGeneral,
|
2013-08-08 04:31:34 +00:00
|
|
|
[(set f32:$frD, (frnd f32:$frB))]>;
|
2013-03-29 19:41:55 +00:00
|
|
|
}
|
|
|
|
|
2013-04-12 02:18:09 +00:00
|
|
|
let neverHasSideEffects = 1 in {
|
2013-12-17 23:05:18 +00:00
|
|
|
let Interpretation64Bit = 1, isCodeGenOnly = 1 in
|
2013-04-26 16:53:15 +00:00
|
|
|
defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"frip", "$frD, $frB", IIC_FPGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set f64:$frD, (fceil f64:$frB))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"frip", "$frD, $frB", IIC_FPGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set f32:$frD, (fceil f32:$frB))]>;
|
2013-12-17 23:05:18 +00:00
|
|
|
let Interpretation64Bit = 1, isCodeGenOnly = 1 in
|
2013-04-26 16:53:15 +00:00
|
|
|
defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"friz", "$frD, $frB", IIC_FPGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set f64:$frD, (ftrunc f64:$frB))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"friz", "$frD, $frB", IIC_FPGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set f32:$frD, (ftrunc f32:$frB))]>;
|
2013-12-17 23:05:18 +00:00
|
|
|
let Interpretation64Bit = 1, isCodeGenOnly = 1 in
|
2013-04-26 16:53:15 +00:00
|
|
|
defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"frim", "$frD, $frB", IIC_FPGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set f64:$frD, (ffloor f64:$frB))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"frim", "$frD, $frB", IIC_FPGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set f32:$frD, (ffloor f32:$frB))]>;
|
|
|
|
|
2013-04-26 16:53:15 +00:00
|
|
|
defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
|
2013-11-30 20:41:13 +00:00
|
|
|
"fsqrt", "$frD, $frB", IIC_FPSqrtD,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set f64:$frD, (fsqrt f64:$frB))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
|
2013-11-30 20:41:13 +00:00
|
|
|
"fsqrts", "$frD, $frB", IIC_FPSqrtS,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set f32:$frD, (fsqrt f32:$frB))]>;
|
|
|
|
}
|
2008-10-29 18:26:45 +00:00
|
|
|
}
|
2006-03-12 09:13:49 +00:00
|
|
|
}
|
2005-10-01 01:35:02 +00:00
|
|
|
|
2010-07-16 21:03:52 +00:00
|
|
|
/// Note that FMR is defined as pseudo-ops on the PPC970 because they are
|
2006-03-24 07:12:19 +00:00
|
|
|
/// often coalesced away and we don't want the dispatch group builder to think
|
2006-03-12 09:13:49 +00:00
|
|
|
/// that they will fill slots (which could cause the load of a LSU reject to
|
|
|
|
/// sneak into a d-group with a store).
|
2013-04-07 04:56:16 +00:00
|
|
|
let neverHasSideEffects = 1 in
|
2013-04-26 16:53:15 +00:00
|
|
|
defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fmr", "$frD, $frB", IIC_FPGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[]>, // (set f32:$frD, f32:$frB)
|
|
|
|
PPC970_Unit_Pseudo;
|
2005-10-01 01:35:02 +00:00
|
|
|
|
2013-04-12 02:18:09 +00:00
|
|
|
let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
|
2005-10-01 01:35:02 +00:00
|
|
|
// These are artificially split into two different forms, for 4/8 byte FP.
|
2013-04-26 16:53:15 +00:00
|
|
|
defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fabs", "$frD, $frB", IIC_FPGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set f32:$frD, (fabs f32:$frB))]>;
|
2013-12-17 23:05:18 +00:00
|
|
|
let Interpretation64Bit = 1, isCodeGenOnly = 1 in
|
2013-04-26 16:53:15 +00:00
|
|
|
defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fabs", "$frD, $frB", IIC_FPGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set f64:$frD, (fabs f64:$frB))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fnabs", "$frD, $frB", IIC_FPGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set f32:$frD, (fneg (fabs f32:$frB)))]>;
|
2013-12-17 23:05:18 +00:00
|
|
|
let Interpretation64Bit = 1, isCodeGenOnly = 1 in
|
2013-04-26 16:53:15 +00:00
|
|
|
defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fnabs", "$frD, $frB", IIC_FPGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set f64:$frD, (fneg (fabs f64:$frB)))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fneg", "$frD, $frB", IIC_FPGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set f32:$frD, (fneg f32:$frB))]>;
|
2013-12-17 23:05:18 +00:00
|
|
|
let Interpretation64Bit = 1, isCodeGenOnly = 1 in
|
2013-04-26 16:53:15 +00:00
|
|
|
defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fneg", "$frD, $frB", IIC_FPGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set f64:$frD, (fneg f64:$frB))]>;
|
2013-04-03 04:01:11 +00:00
|
|
|
|
2013-08-19 05:01:02 +00:00
|
|
|
defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
|
2013-08-19 05:01:02 +00:00
|
|
|
[(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
|
2013-12-17 23:05:18 +00:00
|
|
|
let Interpretation64Bit = 1, isCodeGenOnly = 1 in
|
2013-08-19 05:01:02 +00:00
|
|
|
defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
|
2013-08-19 05:01:02 +00:00
|
|
|
[(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
|
|
|
|
|
2013-04-03 04:01:11 +00:00
|
|
|
// Reciprocal estimates.
|
2013-04-26 16:53:15 +00:00
|
|
|
defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fre", "$frD, $frB", IIC_FPGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set f64:$frD, (PPCfre f64:$frB))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fres", "$frD, $frB", IIC_FPGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set f32:$frD, (PPCfre f32:$frB))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"frsqrte", "$frD, $frB", IIC_FPGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"frsqrtes", "$frD, $frB", IIC_FPGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
|
2006-03-12 09:13:49 +00:00
|
|
|
}
|
2004-08-29 22:45:13 +00:00
|
|
|
|
2004-08-30 02:28:06 +00:00
|
|
|
// XL-Form instructions. condition register logical ops.
|
|
|
|
//
|
2013-04-07 05:16:57 +00:00
|
|
|
let neverHasSideEffects = 1 in
|
2013-04-26 16:53:15 +00:00
|
|
|
def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
|
2013-11-27 23:26:09 +00:00
|
|
|
"mcrf $BF, $BFA", IIC_BrMCR>,
|
2006-03-12 09:13:49 +00:00
|
|
|
PPC970_DGroup_First, PPC970_Unit_CRU;
|
2004-08-30 02:28:06 +00:00
|
|
|
|
2014-03-24 15:07:28 +00:00
|
|
|
let isCommutable = 1 in {
|
2013-07-01 21:40:54 +00:00
|
|
|
def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD),
|
|
|
|
(ins crbitrc:$CRA, crbitrc:$CRB),
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
"crand $CRD, $CRA, $CRB", IIC_BrCR,
|
|
|
|
[(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>;
|
2013-07-01 21:40:54 +00:00
|
|
|
|
|
|
|
def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
|
|
|
|
(ins crbitrc:$CRA, crbitrc:$CRB),
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
"crnand $CRD, $CRA, $CRB", IIC_BrCR,
|
|
|
|
[(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>;
|
2013-07-01 21:40:54 +00:00
|
|
|
|
|
|
|
def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
|
|
|
|
(ins crbitrc:$CRA, crbitrc:$CRB),
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
"cror $CRD, $CRA, $CRB", IIC_BrCR,
|
|
|
|
[(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>;
|
2013-07-01 21:40:54 +00:00
|
|
|
|
|
|
|
def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD),
|
|
|
|
(ins crbitrc:$CRA, crbitrc:$CRB),
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
"crxor $CRD, $CRA, $CRB", IIC_BrCR,
|
|
|
|
[(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;
|
2013-07-01 21:40:54 +00:00
|
|
|
|
|
|
|
def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD),
|
|
|
|
(ins crbitrc:$CRA, crbitrc:$CRB),
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
"crnor $CRD, $CRA, $CRB", IIC_BrCR,
|
|
|
|
[(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
|
2013-07-01 21:40:54 +00:00
|
|
|
|
2013-04-26 16:53:15 +00:00
|
|
|
def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
|
|
|
|
(ins crbitrc:$CRA, crbitrc:$CRB),
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
"creqv $CRD, $CRA, $CRB", IIC_BrCR,
|
|
|
|
[(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
|
2014-03-24 15:07:28 +00:00
|
|
|
} // isCommutable
|
2007-02-25 05:34:32 +00:00
|
|
|
|
2013-07-01 21:40:54 +00:00
|
|
|
def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
|
2013-04-26 16:53:15 +00:00
|
|
|
(ins crbitrc:$CRA, crbitrc:$CRB),
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
"crandc $CRD, $CRA, $CRB", IIC_BrCR,
|
|
|
|
[(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;
|
2013-07-01 21:40:54 +00:00
|
|
|
|
|
|
|
def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD),
|
|
|
|
(ins crbitrc:$CRA, crbitrc:$CRB),
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
"crorc $CRD, $CRA, $CRB", IIC_BrCR,
|
|
|
|
[(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;
|
2008-03-10 14:12:10 +00:00
|
|
|
|
2013-03-26 10:57:16 +00:00
|
|
|
let isCodeGenOnly = 1 in {
|
2013-04-26 16:53:15 +00:00
|
|
|
def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
|
2013-11-27 23:26:09 +00:00
|
|
|
"creqv $dst, $dst, $dst", IIC_BrCR,
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
[(set i1:$dst, 1)]>;
|
2007-02-25 05:34:32 +00:00
|
|
|
|
2013-04-26 16:53:15 +00:00
|
|
|
def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
|
2013-11-27 23:26:09 +00:00
|
|
|
"crxor $dst, $dst, $dst", IIC_BrCR,
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
[(set i1:$dst, 0)]>;
|
2011-08-30 17:04:16 +00:00
|
|
|
|
2012-08-28 02:10:27 +00:00
|
|
|
let Defs = [CR1EQ], CRD = 6 in {
|
|
|
|
def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
|
2013-11-27 23:26:09 +00:00
|
|
|
"creqv 6, 6, 6", IIC_BrCR,
|
2012-08-28 02:10:27 +00:00
|
|
|
[(PPCcr6set)]>;
|
|
|
|
|
|
|
|
def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
|
2013-11-27 23:26:09 +00:00
|
|
|
"crxor 6, 6, 6", IIC_BrCR,
|
2012-08-28 02:10:27 +00:00
|
|
|
[(PPCcr6unset)]>;
|
|
|
|
}
|
2013-03-26 10:57:16 +00:00
|
|
|
}
|
2012-08-28 02:10:27 +00:00
|
|
|
|
2006-03-12 09:13:49 +00:00
|
|
|
// XFX-Form instructions. Instructions that deal with SPRs.
|
2004-08-30 02:28:06 +00:00
|
|
|
//
|
2013-07-03 12:32:41 +00:00
|
|
|
|
|
|
|
def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
|
2013-11-27 23:26:09 +00:00
|
|
|
"mfspr $RT, $SPR", IIC_SprMFSPR>;
|
2013-07-03 12:32:41 +00:00
|
|
|
def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
|
2013-11-27 23:26:09 +00:00
|
|
|
"mtspr $SPR, $RT", IIC_SprMTSPR>;
|
2013-07-03 12:32:41 +00:00
|
|
|
|
2013-07-08 15:20:38 +00:00
|
|
|
def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
|
2013-11-27 23:26:09 +00:00
|
|
|
"mftb $RT, $SPR", IIC_SprMFTB>, Deprecated<DeprecatedMFTB>;
|
2013-07-08 15:20:38 +00:00
|
|
|
|
2008-10-23 20:41:28 +00:00
|
|
|
let Uses = [CTR] in {
|
2013-04-26 16:53:15 +00:00
|
|
|
def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
|
2013-11-27 23:26:09 +00:00
|
|
|
"mfctr $rT", IIC_SprMFSPR>,
|
2006-03-12 09:13:49 +00:00
|
|
|
PPC970_DGroup_First, PPC970_Unit_FXU;
|
2008-10-23 20:41:28 +00:00
|
|
|
}
|
2013-03-25 19:05:30 +00:00
|
|
|
let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
|
2013-04-26 16:53:15 +00:00
|
|
|
def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
|
2013-11-27 23:26:09 +00:00
|
|
|
"mtctr $rS", IIC_SprMTSPR>,
|
For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26733 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-13 21:52:10 +00:00
|
|
|
PPC970_DGroup_First, PPC970_Unit_FXU;
|
2006-05-17 19:00:46 +00:00
|
|
|
}
|
Implement PPC counter loops as a late IR-level pass
The old PPCCTRLoops pass, like the Hexagon pass version from which it was
derived, could only handle some simple loops in canonical form. We cannot
directly adapt the new Hexagon hardware loops pass, however, because the
Hexagon pass contains a fundamental assumption that non-constant-trip-count
loops will contain a guard, and this is not always true (the result being that
incorrect negative counts can be generated). With this commit, we replace the
pass with a late IR-level pass which makes use of SE to calculate the
backedge-taken counts and safely generate the loop-count expressions (including
any necessary max() parts). This IR level pass inserts custom intrinsics that
are lowered into the desired decrement-and-branch instructions.
The most fragile part of this new implementation is that interfering uses of
the counter register must be detected on the IR level (and, on PPC, this also
includes any indirect branches in addition to function calls). Also, to make
all of this work, we need a variant of the mtctr instruction that is marked
as having side effects. Without this, machine-code level CSE, DCE, etc.
illegally transform the resulting code. Hopefully, this can be improved
in the future.
This new pass is smaller than the original (and much smaller than the new
Hexagon hardware loops pass), and can handle many additional cases correctly.
In addition, the preheader-creation code has been copied from LoopSimplify, and
after we decide on where it belongs, this code will be refactored so that it
can be explicitly shared (making this implementation even smaller).
The new test-case files ctrloop-{le,lt,ne}.ll have been adapted from tests for
the new Hexagon pass. There are a few classes of loops that this pass does not
transform (noted by FIXMEs in the files), but these deficiencies can be
addressed within the SE infrastructure (thus helping many other passes as well).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181927 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-15 21:37:41 +00:00
|
|
|
let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
|
|
|
|
let Pattern = [(int_ppc_mtctr i32:$rS)] in
|
2013-05-20 16:08:37 +00:00
|
|
|
def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
|
2013-11-27 23:26:09 +00:00
|
|
|
"mtctr $rS", IIC_SprMTSPR>,
|
2013-05-20 16:08:37 +00:00
|
|
|
PPC970_DGroup_First, PPC970_Unit_FXU;
|
Implement PPC counter loops as a late IR-level pass
The old PPCCTRLoops pass, like the Hexagon pass version from which it was
derived, could only handle some simple loops in canonical form. We cannot
directly adapt the new Hexagon hardware loops pass, however, because the
Hexagon pass contains a fundamental assumption that non-constant-trip-count
loops will contain a guard, and this is not always true (the result being that
incorrect negative counts can be generated). With this commit, we replace the
pass with a late IR-level pass which makes use of SE to calculate the
backedge-taken counts and safely generate the loop-count expressions (including
any necessary max() parts). This IR level pass inserts custom intrinsics that
are lowered into the desired decrement-and-branch instructions.
The most fragile part of this new implementation is that interfering uses of
the counter register must be detected on the IR level (and, on PPC, this also
includes any indirect branches in addition to function calls). Also, to make
all of this work, we need a variant of the mtctr instruction that is marked
as having side effects. Without this, machine-code level CSE, DCE, etc.
illegally transform the resulting code. Hopefully, this can be improved
in the future.
This new pass is smaller than the original (and much smaller than the new
Hexagon hardware loops pass), and can handle many additional cases correctly.
In addition, the preheader-creation code has been copied from LoopSimplify, and
after we decide on where it belongs, this code will be refactored so that it
can be explicitly shared (making this implementation even smaller).
The new test-case files ctrloop-{le,lt,ne}.ll have been adapted from tests for
the new Hexagon pass. There are a few classes of loops that this pass does not
transform (noted by FIXMEs in the files), but these deficiencies can be
addressed within the SE infrastructure (thus helping many other passes as well).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181927 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-15 21:37:41 +00:00
|
|
|
}
|
For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26733 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-13 21:52:10 +00:00
|
|
|
|
2008-10-23 20:41:28 +00:00
|
|
|
let Defs = [LR] in {
|
2013-04-26 16:53:15 +00:00
|
|
|
def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
|
2013-11-27 23:26:09 +00:00
|
|
|
"mtlr $rS", IIC_SprMTSPR>,
|
For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26733 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-13 21:52:10 +00:00
|
|
|
PPC970_DGroup_First, PPC970_Unit_FXU;
|
2008-10-23 20:41:28 +00:00
|
|
|
}
|
|
|
|
let Uses = [LR] in {
|
2013-04-26 16:53:15 +00:00
|
|
|
def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
|
2013-11-27 23:26:09 +00:00
|
|
|
"mflr $rT", IIC_SprMFSPR>,
|
2006-03-12 09:13:49 +00:00
|
|
|
PPC970_DGroup_First, PPC970_Unit_FXU;
|
2008-10-23 20:41:28 +00:00
|
|
|
}
|
For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26733 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-13 21:52:10 +00:00
|
|
|
|
2013-03-21 19:03:21 +00:00
|
|
|
let isCodeGenOnly = 1 in {
|
2013-07-03 12:32:41 +00:00
|
|
|
// Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
|
|
|
|
// like a GPR on the PPC970. As such, copies in and out have the same
|
|
|
|
// performance characteristics as an OR instruction.
|
|
|
|
def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
|
2013-11-27 23:26:09 +00:00
|
|
|
"mtspr 256, $rS", IIC_IntGeneral>,
|
2013-07-03 12:32:41 +00:00
|
|
|
PPC970_DGroup_Single, PPC970_Unit_FXU;
|
|
|
|
def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
|
2013-11-27 23:26:09 +00:00
|
|
|
"mfspr $rT, 256", IIC_IntGeneral>,
|
2013-07-03 12:32:41 +00:00
|
|
|
PPC970_DGroup_First, PPC970_Unit_FXU;
|
|
|
|
|
2013-03-21 19:03:21 +00:00
|
|
|
def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs VRSAVERC:$reg), (ins gprc:$rS),
|
2013-11-27 23:26:09 +00:00
|
|
|
"mtspr 256, $rS", IIC_IntGeneral>,
|
2013-03-21 19:03:21 +00:00
|
|
|
PPC970_DGroup_Single, PPC970_Unit_FXU;
|
2013-04-26 16:53:15 +00:00
|
|
|
def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
|
2013-03-21 19:03:21 +00:00
|
|
|
(ins VRSAVERC:$reg),
|
2013-11-27 23:26:09 +00:00
|
|
|
"mfspr $rT, 256", IIC_IntGeneral>,
|
2013-03-21 19:03:21 +00:00
|
|
|
PPC970_DGroup_First, PPC970_Unit_FXU;
|
|
|
|
}
|
|
|
|
|
|
|
|
// SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
|
|
|
|
// so we'll need to scavenge a register for it.
|
|
|
|
let mayStore = 1 in
|
|
|
|
def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
|
|
|
|
"#SPILL_VRSAVE", []>;
|
|
|
|
|
|
|
|
// RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
|
|
|
|
// spilled), so we'll need to scavenge a register for it.
|
|
|
|
let mayLoad = 1 in
|
|
|
|
def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
|
|
|
|
"#RESTORE_VRSAVE", []>;
|
|
|
|
|
2013-04-07 14:33:13 +00:00
|
|
|
let neverHasSideEffects = 1 in {
|
2013-07-03 17:59:07 +00:00
|
|
|
def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
|
2013-11-27 23:26:09 +00:00
|
|
|
"mtocrf $FXM, $ST", IIC_BrMCRX>,
|
2013-07-03 17:59:07 +00:00
|
|
|
PPC970_DGroup_First, PPC970_Unit_CRU;
|
|
|
|
|
|
|
|
def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
|
2013-11-27 23:26:09 +00:00
|
|
|
"mtcrf $FXM, $rS", IIC_BrMCRX>,
|
2006-03-12 09:13:49 +00:00
|
|
|
PPC970_MicroCode, PPC970_Unit_CRU;
|
2010-05-20 17:48:26 +00:00
|
|
|
|
2013-09-12 05:24:49 +00:00
|
|
|
let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
|
2013-04-26 16:53:15 +00:00
|
|
|
def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
|
2013-11-30 20:41:13 +00:00
|
|
|
"mfocrf $rT, $FXM", IIC_SprMFCRF>,
|
2006-03-12 09:13:49 +00:00
|
|
|
PPC970_DGroup_First, PPC970_Unit_CRU;
|
2013-04-07 14:33:13 +00:00
|
|
|
|
2013-04-26 16:53:15 +00:00
|
|
|
def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
|
2013-11-27 23:26:09 +00:00
|
|
|
"mfcr $rT", IIC_SprMFCR>,
|
2013-04-07 14:33:13 +00:00
|
|
|
PPC970_MicroCode, PPC970_Unit_CRU;
|
[PowerPC] Always use mfocrf if available
When accessing just a single CR register, it is always preferable to
use mfocrf instead of mfcr, if the former is available on the CPU.
Current code makes that distinction in many, but not all places
where a single CR register value is retrieved. One missing
location is PPCRegisterInfo::lowerCRSpilling.
To fix this and make this simpler in the future, this patch changes
the bulk of the back-end to always assume mfocrf is available and
simply generate it when needed.
On machines that actually do not support mfocrf, the instruction
is replaced by mfcr at the very end, in EmitInstruction.
This has the additional benefit that we no longer need the
MFCRpseud hack, since before EmitInstruction we always have
a MFOCRF instruction pattern, which already models data flow
as required.
The patch also adds the MFOCRF8 version of the instruction,
which was missing so far.
Except for the PPCRegisterInfo::lowerCRSpilling case, no change
in generated code intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185556 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 17:05:42 +00:00
|
|
|
} // neverHasSideEffects = 1
|
2004-08-30 02:28:06 +00:00
|
|
|
|
2013-03-26 10:56:22 +00:00
|
|
|
// Pseudo instruction to perform FADD in round-to-zero mode.
|
|
|
|
let usesCustomInserter = 1, Uses = [RM] in {
|
2013-04-26 16:53:15 +00:00
|
|
|
def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
|
2013-03-26 10:56:22 +00:00
|
|
|
[(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
|
|
|
|
}
|
2007-10-10 01:01:31 +00:00
|
|
|
|
2013-03-26 10:56:22 +00:00
|
|
|
// The above pseudo gets expanded to make use of the following instructions
|
|
|
|
// to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
|
2008-10-29 18:26:45 +00:00
|
|
|
let Uses = [RM], Defs = [RM] in {
|
|
|
|
def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
|
2013-11-27 23:26:09 +00:00
|
|
|
"mtfsb0 $FM", IIC_IntMTFSB0, []>,
|
2008-10-29 18:26:45 +00:00
|
|
|
PPC970_DGroup_Single, PPC970_Unit_FPU;
|
|
|
|
def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
|
2013-11-27 23:26:09 +00:00
|
|
|
"mtfsb1 $FM", IIC_IntMTFSB0, []>,
|
2008-10-29 18:26:45 +00:00
|
|
|
PPC970_DGroup_Single, PPC970_Unit_FPU;
|
2013-04-26 16:53:15 +00:00
|
|
|
def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
|
2013-11-27 23:26:09 +00:00
|
|
|
"mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
|
2008-10-29 18:26:45 +00:00
|
|
|
PPC970_DGroup_Single, PPC970_Unit_FPU;
|
|
|
|
}
|
|
|
|
let Uses = [RM] in {
|
2013-04-26 16:53:15 +00:00
|
|
|
def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
|
2013-11-27 23:26:09 +00:00
|
|
|
"mffs $rT", IIC_IntMFFS,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set f64:$rT, (PPCmffs))]>,
|
2008-10-29 18:26:45 +00:00
|
|
|
PPC970_DGroup_Single, PPC970_Unit_FPU;
|
|
|
|
}
|
|
|
|
|
2007-10-10 01:01:31 +00:00
|
|
|
|
2013-04-12 02:18:09 +00:00
|
|
|
let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
|
2004-08-30 02:28:06 +00:00
|
|
|
// XO-Form instructions. Arithmetic instructions that can set overflow bit
|
2014-03-24 15:07:28 +00:00
|
|
|
let isCommutable = 1 in
|
2013-04-26 16:53:15 +00:00
|
|
|
defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"add", "$rT, $rA, $rB", IIC_IntSimple,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set i32:$rT, (add i32:$rA, i32:$rB))]>;
|
2013-12-20 18:08:54 +00:00
|
|
|
let isCodeGenOnly = 1 in
|
|
|
|
def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
|
|
|
|
"add $rT, $rA, $rB", IIC_IntSimple,
|
|
|
|
[(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
|
2014-03-24 15:07:28 +00:00
|
|
|
let isCommutable = 1 in
|
2013-04-26 16:53:15 +00:00
|
|
|
defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"addc", "$rT, $rA, $rB", IIC_IntGeneral,
|
2013-04-12 18:17:57 +00:00
|
|
|
[(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
|
|
|
|
PPC970_DGroup_Cracked;
|
2014-03-24 15:07:28 +00:00
|
|
|
|
2013-04-26 16:53:15 +00:00
|
|
|
defm DIVW : XOForm_1r<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"divw", "$rT, $rA, $rB", IIC_IntDivW,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
|
|
|
|
PPC970_DGroup_First, PPC970_DGroup_Cracked;
|
2013-04-26 16:53:15 +00:00
|
|
|
defm DIVWU : XOForm_1r<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"divwu", "$rT, $rA, $rB", IIC_IntDivW,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
|
|
|
|
PPC970_DGroup_First, PPC970_DGroup_Cracked;
|
2014-03-24 15:07:28 +00:00
|
|
|
let isCommutable = 1 in {
|
2013-04-26 16:53:15 +00:00
|
|
|
defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"mullw", "$rT, $rA, $rB", IIC_IntMulHW,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
|
2014-03-24 15:07:28 +00:00
|
|
|
} // isCommutable
|
2013-04-26 16:53:15 +00:00
|
|
|
defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"subf", "$rT, $rA, $rB", IIC_IntGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"subfc", "$rT, $rA, $rB", IIC_IntGeneral,
|
2013-04-12 18:17:57 +00:00
|
|
|
[(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
|
|
|
|
PPC970_DGroup_Cracked;
|
2013-04-26 16:53:15 +00:00
|
|
|
defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
|
2013-11-27 23:26:09 +00:00
|
|
|
"neg", "$rT, $rA", IIC_IntSimple,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set i32:$rT, (ineg i32:$rA))]>;
|
2013-04-12 18:17:57 +00:00
|
|
|
let Uses = [CARRY] in {
|
2014-03-24 15:07:28 +00:00
|
|
|
let isCommutable = 1 in
|
2013-04-26 16:53:15 +00:00
|
|
|
defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"adde", "$rT, $rA, $rB", IIC_IntGeneral,
|
2013-04-12 18:17:57 +00:00
|
|
|
[(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
|
2013-11-27 23:26:09 +00:00
|
|
|
"addme", "$rT, $rA", IIC_IntGeneral,
|
2013-04-12 18:17:57 +00:00
|
|
|
[(set i32:$rT, (adde i32:$rA, -1))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
|
2013-11-27 23:26:09 +00:00
|
|
|
"addze", "$rT, $rA", IIC_IntGeneral,
|
2013-04-12 18:17:57 +00:00
|
|
|
[(set i32:$rT, (adde i32:$rA, 0))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"subfe", "$rT, $rA, $rB", IIC_IntGeneral,
|
2013-04-12 18:17:57 +00:00
|
|
|
[(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
|
2013-11-27 23:26:09 +00:00
|
|
|
"subfme", "$rT, $rA", IIC_IntGeneral,
|
2013-04-12 18:17:57 +00:00
|
|
|
[(set i32:$rT, (sube -1, i32:$rA))]>;
|
2013-04-26 16:53:15 +00:00
|
|
|
defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
|
2013-11-27 23:26:09 +00:00
|
|
|
"subfze", "$rT, $rA", IIC_IntGeneral,
|
2013-04-12 18:17:57 +00:00
|
|
|
[(set i32:$rT, (sube 0, i32:$rA))]>;
|
2006-03-12 09:13:49 +00:00
|
|
|
}
|
2009-09-18 20:15:22 +00:00
|
|
|
}
|
2004-08-30 02:28:06 +00:00
|
|
|
|
|
|
|
// A-Form instructions. Most of the instructions executed in the FPU are of
|
|
|
|
// this type.
|
|
|
|
//
|
2013-04-12 02:18:09 +00:00
|
|
|
let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
|
2008-10-29 18:26:45 +00:00
|
|
|
let Uses = [RM] in {
|
2014-03-24 15:07:28 +00:00
|
|
|
let isCommutable = 1 in {
|
2013-04-12 02:18:09 +00:00
|
|
|
defm FMADD : AForm_1r<63, 29,
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
|
2013-04-12 02:18:09 +00:00
|
|
|
defm FMADDS : AForm_1r<59, 29,
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
|
2013-04-12 02:18:09 +00:00
|
|
|
defm FMSUB : AForm_1r<63, 28,
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set f64:$FRT,
|
|
|
|
(fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
|
2013-04-12 02:18:09 +00:00
|
|
|
defm FMSUBS : AForm_1r<59, 28,
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set f32:$FRT,
|
|
|
|
(fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
|
2013-04-12 02:18:09 +00:00
|
|
|
defm FNMADD : AForm_1r<63, 31,
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set f64:$FRT,
|
|
|
|
(fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
|
2013-04-12 02:18:09 +00:00
|
|
|
defm FNMADDS : AForm_1r<59, 31,
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set f32:$FRT,
|
|
|
|
(fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
|
2013-04-12 02:18:09 +00:00
|
|
|
defm FNMSUB : AForm_1r<63, 30,
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
|
|
|
|
(fneg f64:$FRB))))]>;
|
2013-04-12 02:18:09 +00:00
|
|
|
defm FNMSUBS : AForm_1r<59, 30,
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
|
2013-03-25 19:05:30 +00:00
|
|
|
[(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
|
|
|
|
(fneg f32:$FRB))))]>;
|
2014-03-24 15:07:28 +00:00
|
|
|
} // isCommutable
|
2008-10-29 18:26:45 +00:00
|
|
|
}
|
2005-10-02 07:07:49 +00:00
|
|
|
// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
|
|
|
|
// having 4 of these, force the comparison to always be an 8-byte double (code
|
|
|
|
// should use an FMRSD if the input comparison value really wants to be a float)
|
2005-10-02 06:58:23 +00:00
|
|
|
// and 4/8 byte forms for the result and operand type..
|
2013-12-17 23:05:18 +00:00
|
|
|
let Interpretation64Bit = 1, isCodeGenOnly = 1 in
|
2013-04-12 02:18:09 +00:00
|
|
|
defm FSELD : AForm_1r<63, 23,
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
|
|
|
|
defm FSELS : AForm_1r<63, 23,
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
|
2008-10-29 18:26:45 +00:00
|
|
|
let Uses = [RM] in {
|
2014-03-24 15:07:28 +00:00
|
|
|
let isCommutable = 1 in {
|
2013-04-12 02:18:09 +00:00
|
|
|
defm FADD : AForm_2r<63, 21,
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
|
|
|
|
defm FADDS : AForm_2r<59, 21,
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
|
2014-03-24 15:07:28 +00:00
|
|
|
} // isCommutable
|
2013-04-12 02:18:09 +00:00
|
|
|
defm FDIV : AForm_2r<63, 18,
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
|
|
|
|
defm FDIVS : AForm_2r<59, 18,
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
|
2014-03-24 15:07:28 +00:00
|
|
|
let isCommutable = 1 in {
|
2013-04-12 02:18:09 +00:00
|
|
|
defm FMUL : AForm_3r<63, 25,
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
|
|
|
|
defm FMULS : AForm_3r<59, 25,
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
|
2014-03-24 15:07:28 +00:00
|
|
|
} // isCommutable
|
2013-04-12 02:18:09 +00:00
|
|
|
defm FSUB : AForm_2r<63, 20,
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
|
|
|
|
defm FSUBS : AForm_2r<59, 20,
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
|
2008-10-29 18:26:45 +00:00
|
|
|
}
|
2006-03-12 09:13:49 +00:00
|
|
|
}
|
2004-08-30 02:28:06 +00:00
|
|
|
|
2013-04-07 15:06:53 +00:00
|
|
|
let neverHasSideEffects = 1 in {
|
2012-06-22 23:10:08 +00:00
|
|
|
let PPC970_Unit = 1 in { // FXU Operations.
|
2013-04-07 15:06:53 +00:00
|
|
|
let isSelect = 1 in
|
2012-11-13 19:14:19 +00:00
|
|
|
def ISEL : AForm_4<31, 15,
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
|
2013-11-27 23:26:09 +00:00
|
|
|
"isel $rT, $rA, $rB, $cond", IIC_IntGeneral,
|
2012-06-22 23:10:08 +00:00
|
|
|
[]>;
|
|
|
|
}
|
|
|
|
|
2006-03-12 09:13:49 +00:00
|
|
|
let PPC970_Unit = 1 in { // FXU Operations.
|
2004-08-31 02:28:08 +00:00
|
|
|
// M-Form instructions. rotate and mask instructions.
|
|
|
|
//
|
2006-11-15 23:24:18 +00:00
|
|
|
let isCommutable = 1 in {
|
2005-09-09 18:17:41 +00:00
|
|
|
// RLWIMI can be commuted if the rotate amount is zero.
|
2013-04-26 16:53:15 +00:00
|
|
|
defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
|
|
|
|
(ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
|
2013-11-27 23:26:09 +00:00
|
|
|
u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
|
|
|
|
IIC_IntRotate, []>, PPC970_DGroup_Cracked,
|
|
|
|
RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
|
2004-10-16 20:43:38 +00:00
|
|
|
}
|
2013-04-12 02:18:09 +00:00
|
|
|
let BaseName = "rlwinm" in {
|
2005-04-19 05:21:30 +00:00
|
|
|
def RLWINM : MForm_2<21,
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
|
2013-11-27 23:26:09 +00:00
|
|
|
"rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[]>, RecFormRel;
|
2013-04-12 18:17:57 +00:00
|
|
|
let Defs = [CR0] in
|
2005-04-19 05:21:30 +00:00
|
|
|
def RLWINMo : MForm_2<21,
|
2013-04-26 16:53:15 +00:00
|
|
|
(outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
|
2013-11-27 23:26:09 +00:00
|
|
|
"rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[]>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
|
|
|
|
}
|
2013-04-26 16:53:15 +00:00
|
|
|
defm RLWNM : MForm_2r<23, (outs gprc:$rA),
|
|
|
|
(ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
|
2013-11-27 23:26:09 +00:00
|
|
|
"rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
|
2013-04-12 02:18:09 +00:00
|
|
|
[]>;
|
2006-03-12 09:13:49 +00:00
|
|
|
}
|
2013-04-07 15:06:53 +00:00
|
|
|
} // neverHasSideEffects = 1
|
2006-03-20 06:15:45 +00:00
|
|
|
|
2005-09-09 00:39:56 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// PowerPC Instruction Patterns
|
|
|
|
//
|
|
|
|
|
2005-09-26 22:20:16 +00:00
|
|
|
// Arbitrary immediate support. Implement in terms of LIS/ORI.
|
|
|
|
def : Pat<(i32 imm:$imm),
|
|
|
|
(ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
|
2005-09-28 17:13:15 +00:00
|
|
|
|
|
|
|
// Implement the 'not' operation with the NOR instruction.
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
def i32not : OutPatFrag<(ops node:$in),
|
|
|
|
(NOR $in, $in)>;
|
|
|
|
def : Pat<(not i32:$in),
|
|
|
|
(i32not $in)>;
|
2005-09-28 17:13:15 +00:00
|
|
|
|
2005-09-28 23:07:13 +00:00
|
|
|
// ADD an arbitrary immediate.
|
2013-03-25 19:04:58 +00:00
|
|
|
def : Pat<(add i32:$in, imm:$imm),
|
|
|
|
(ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
|
2005-09-28 23:07:13 +00:00
|
|
|
// OR an arbitrary immediate.
|
2013-03-25 19:04:58 +00:00
|
|
|
def : Pat<(or i32:$in, imm:$imm),
|
|
|
|
(ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
|
2005-09-28 23:07:13 +00:00
|
|
|
// XOR an arbitrary immediate.
|
2013-03-25 19:04:58 +00:00
|
|
|
def : Pat<(xor i32:$in, imm:$imm),
|
|
|
|
(XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
|
2006-02-17 05:43:56 +00:00
|
|
|
// SUBFIC
|
Change some PowerPC PatLeaf definitions to ImmLeaf for fast-isel.
Using PatLeaf rather than ImmLeaf when defining immediate predicates
prevents simple patterns using those predicates from being recognized
for fast instruction selection. This patch replaces the immSExt16
PatLeaf predicate with two ImmLeaf predicates, imm32SExt16 and
imm64SExt16, allowing a few more patterns to be recognized (ADDI,
ADDIC, MULLI, ADDI8, and ADDIC8). Using the new predicates does not
help for LI, LI8, SUBFIC, and SUBFIC8 because these are rejected for
other reasons, but I see no reason to retain the PatLeaf predicate.
No functional change intended, and thus no test cases yet. This is
preliminary work for enabling fast-isel support for PowerPC. When
that support is ready, we'll be able to test this function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182510 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 20:09:24 +00:00
|
|
|
def : Pat<(sub imm32SExt16:$imm, i32:$in),
|
2013-03-25 19:04:58 +00:00
|
|
|
(SUBFIC $in, imm:$imm)>;
|
2005-10-19 01:38:02 +00:00
|
|
|
|
2006-06-16 20:22:01 +00:00
|
|
|
// SHL/SRL
|
2013-03-25 19:04:58 +00:00
|
|
|
def : Pat<(shl i32:$in, (i32 imm:$imm)),
|
|
|
|
(RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
|
|
|
|
def : Pat<(srl i32:$in, (i32 imm:$imm)),
|
|
|
|
(RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
|
2005-10-19 18:42:01 +00:00
|
|
|
|
2006-01-11 21:21:00 +00:00
|
|
|
// ROTL
|
2013-03-25 19:04:58 +00:00
|
|
|
def : Pat<(rotl i32:$in, i32:$sh),
|
|
|
|
(RLWNM $in, $sh, 0, 31)>;
|
|
|
|
def : Pat<(rotl i32:$in, (i32 imm:$imm)),
|
|
|
|
(RLWINM $in, imm:$imm, 0, 31)>;
|
2006-05-17 19:00:46 +00:00
|
|
|
|
2006-09-22 05:01:56 +00:00
|
|
|
// RLWNM
|
2013-03-25 19:04:58 +00:00
|
|
|
def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
|
|
|
|
(RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
|
2006-09-22 05:01:56 +00:00
|
|
|
|
2006-05-17 19:00:46 +00:00
|
|
|
// Calls
|
2013-03-22 15:24:13 +00:00
|
|
|
def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
|
|
|
|
(BL tglobaladdr:$dst)>;
|
|
|
|
def : Pat<(PPCcall (i32 texternalsym:$dst)),
|
|
|
|
(BL texternalsym:$dst)>;
|
2006-05-17 19:00:46 +00:00
|
|
|
|
2008-04-30 09:16:33 +00:00
|
|
|
|
|
|
|
def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
|
|
|
|
(TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
|
|
|
|
|
|
|
|
def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
|
|
|
|
(TCRETURNdi texternalsym:$dst, imm:$imm)>;
|
|
|
|
|
|
|
|
def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
|
|
|
|
(TCRETURNri CTRRC:$dst, imm:$imm)>;
|
|
|
|
|
|
|
|
|
|
|
|
|
2005-11-17 07:30:41 +00:00
|
|
|
// Hi and Lo for Darwin Global Addresses.
|
2005-12-11 07:45:47 +00:00
|
|
|
def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
|
|
|
|
def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
|
|
|
|
def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
|
|
|
|
def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
|
2006-04-22 18:53:45 +00:00
|
|
|
def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
|
|
|
|
def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
|
2009-11-04 21:31:18 +00:00
|
|
|
def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
|
|
|
|
def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
|
2013-03-25 19:04:58 +00:00
|
|
|
def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
|
|
|
|
(ADDIS $in, tglobaltlsaddr:$g)>;
|
|
|
|
def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
|
2013-03-26 10:55:20 +00:00
|
|
|
(ADDI $in, tglobaltlsaddr:$g)>;
|
2013-03-25 19:04:58 +00:00
|
|
|
def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
|
|
|
|
(ADDIS $in, tglobaladdr:$g)>;
|
|
|
|
def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
|
|
|
|
(ADDIS $in, tconstpool:$g)>;
|
|
|
|
def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
|
|
|
|
(ADDIS $in, tjumptable:$g)>;
|
|
|
|
def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
|
|
|
|
(ADDIS $in, tblockaddress:$g)>;
|
2005-11-17 07:30:41 +00:00
|
|
|
|
2013-12-20 18:08:54 +00:00
|
|
|
// Support for thread-local storage.
|
|
|
|
def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
|
|
|
|
[(set i32:$rD, (PPCppc32GOT))]>;
|
|
|
|
|
|
|
|
def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
|
|
|
|
"#LDgotTprelL32",
|
|
|
|
[(set i32:$rD,
|
|
|
|
(PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
|
|
|
|
def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
|
|
|
|
(ADD4TLS $in, tglobaltlsaddr:$g)>;
|
|
|
|
|
2005-12-06 02:10:38 +00:00
|
|
|
// Standard shifts. These are represented separately from the real shifts above
|
|
|
|
// so that we can distinguish between shifts that allow 5-bit and 6-bit shift
|
|
|
|
// amounts.
|
2013-03-25 19:04:58 +00:00
|
|
|
def : Pat<(sra i32:$rS, i32:$rB),
|
|
|
|
(SRAW $rS, $rB)>;
|
|
|
|
def : Pat<(srl i32:$rS, i32:$rB),
|
|
|
|
(SRW $rS, $rB)>;
|
|
|
|
def : Pat<(shl i32:$rS, i32:$rB),
|
|
|
|
(SLW $rS, $rB)>;
|
2005-12-06 02:10:38 +00:00
|
|
|
|
2006-10-09 20:57:25 +00:00
|
|
|
def : Pat<(zextloadi1 iaddr:$src),
|
2005-12-19 23:25:09 +00:00
|
|
|
(LBZ iaddr:$src)>;
|
2006-10-09 20:57:25 +00:00
|
|
|
def : Pat<(zextloadi1 xaddr:$src),
|
2005-12-19 23:25:09 +00:00
|
|
|
(LBZX xaddr:$src)>;
|
2006-10-09 20:57:25 +00:00
|
|
|
def : Pat<(extloadi1 iaddr:$src),
|
2005-12-19 23:25:09 +00:00
|
|
|
(LBZ iaddr:$src)>;
|
2006-10-09 20:57:25 +00:00
|
|
|
def : Pat<(extloadi1 xaddr:$src),
|
2005-12-19 23:25:09 +00:00
|
|
|
(LBZX xaddr:$src)>;
|
2006-10-09 20:57:25 +00:00
|
|
|
def : Pat<(extloadi8 iaddr:$src),
|
2005-12-19 23:25:09 +00:00
|
|
|
(LBZ iaddr:$src)>;
|
2006-10-09 20:57:25 +00:00
|
|
|
def : Pat<(extloadi8 xaddr:$src),
|
2005-12-19 23:25:09 +00:00
|
|
|
(LBZX xaddr:$src)>;
|
2006-10-09 20:57:25 +00:00
|
|
|
def : Pat<(extloadi16 iaddr:$src),
|
2005-12-19 23:25:09 +00:00
|
|
|
(LHZ iaddr:$src)>;
|
2006-10-09 20:57:25 +00:00
|
|
|
def : Pat<(extloadi16 xaddr:$src),
|
2005-12-19 23:25:09 +00:00
|
|
|
(LHZX xaddr:$src)>;
|
2010-07-16 21:03:52 +00:00
|
|
|
def : Pat<(f64 (extloadf32 iaddr:$src)),
|
|
|
|
(COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
|
|
|
|
def : Pat<(f64 (extloadf32 xaddr:$src)),
|
|
|
|
(COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
|
|
|
|
|
2013-03-25 19:04:58 +00:00
|
|
|
def : Pat<(f64 (fextend f32:$src)),
|
|
|
|
(COPY_TO_REGCLASS $src, F8RC)>;
|
2005-12-19 23:25:09 +00:00
|
|
|
|
2014-01-22 20:20:52 +00:00
|
|
|
def : Pat<(atomic_fence (imm), (imm)), (SYNC 0)>, Requires<[IsNotBookE]>;
|
|
|
|
def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[IsBookE]>;
|
2011-07-27 22:21:52 +00:00
|
|
|
|
2013-04-03 04:01:11 +00:00
|
|
|
// Additional FNMSUB patterns: -a*c + b == -(a*c - b)
|
|
|
|
def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
|
|
|
|
(FNMSUB $A, $C, $B)>;
|
|
|
|
def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
|
|
|
|
(FNMSUB $A, $C, $B)>;
|
|
|
|
def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
|
|
|
|
(FNMSUBS $A, $C, $B)>;
|
|
|
|
def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
|
|
|
|
(FNMSUBS $A, $C, $B)>;
|
|
|
|
|
2013-08-19 05:01:02 +00:00
|
|
|
// FCOPYSIGN's operand types need not agree.
|
|
|
|
def : Pat<(fcopysign f64:$frB, f32:$frA),
|
|
|
|
(FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
|
|
|
|
def : Pat<(fcopysign f32:$frB, f64:$frA),
|
|
|
|
(FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
|
|
|
|
|
2006-03-25 07:51:43 +00:00
|
|
|
include "PPCInstrAltivec.td"
|
2006-06-16 20:22:01 +00:00
|
|
|
include "PPCInstr64Bit.td"
|
[PowerPC] Initial support for the VSX instruction set
VSX is an ISA extension supported on the POWER7 and later cores that enhances
floating-point vector and scalar capabilities. Among other things, this adds
<2 x double> support and generally helps to reduce register pressure.
The interesting part of this ISA feature is the register configuration: there
are 64 new 128-bit vector registers, the 32 of which are super-registers of the
existing 32 scalar floating-point registers, and the second 32 of which overlap
with the 32 Altivec vector registers. This makes things like vector insertion
and extraction tricky: this can be free but only if we force a restriction to
the right register subclass when needed. A new "minipass" PPCVSXCopy takes care
of this (although it could do a more-optimal job of it; see the comment about
unnecessary copies below).
Please note that, currently, VSX is not enabled by default when targeting
anything because it is not yet ready for that. The assembler and disassembler
are fully implemented and tested. However:
- CodeGen support causes miscompiles; test-suite runtime failures:
MultiSource/Benchmarks/FreeBench/distray/distray
MultiSource/Benchmarks/McCat/08-main/main
MultiSource/Benchmarks/Olden/voronoi/voronoi
MultiSource/Benchmarks/mafft/pairlocalalign
MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4
SingleSource/Benchmarks/CoyoteBench/almabench
SingleSource/Benchmarks/Misc/matmul_f64_4x4
- The lowering currently falls back to using Altivec instructions far more
than it should. Worse, there are some things that are scalarized through the
stack that shouldn't be.
- A lot of unnecessary copies make it past the optimizers, and this needs to
be fixed.
- Many more regression tests are needed.
Normally, I'd fix these things prior to committing, but there are some
students and other contributors who would like to work this, and so it makes
sense to move this development process upstream where it can be subject to the
regular code-review procedures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203768 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-13 07:58:58 +00:00
|
|
|
include "PPCInstrVSX.td"
|
2013-05-03 19:50:27 +00:00
|
|
|
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
def crnot : OutPatFrag<(ops node:$in),
|
|
|
|
(CRNOR $in, $in)>;
|
|
|
|
def : Pat<(not i1:$in),
|
|
|
|
(crnot $in)>;
|
|
|
|
|
|
|
|
// Patterns for arithmetic i1 operations.
|
|
|
|
def : Pat<(add i1:$a, i1:$b),
|
|
|
|
(CRXOR $a, $b)>;
|
|
|
|
def : Pat<(sub i1:$a, i1:$b),
|
|
|
|
(CRXOR $a, $b)>;
|
|
|
|
def : Pat<(mul i1:$a, i1:$b),
|
|
|
|
(CRAND $a, $b)>;
|
|
|
|
|
|
|
|
// We're sometimes asked to materialize i1 -1, which is just 1 in this case
|
|
|
|
// (-1 is used to mean all bits set).
|
|
|
|
def : Pat<(i1 -1), (CRSET)>;
|
|
|
|
|
|
|
|
// i1 extensions, implemented in terms of isel.
|
|
|
|
def : Pat<(i32 (zext i1:$in)),
|
|
|
|
(SELECT_I4 $in, (LI 1), (LI 0))>;
|
|
|
|
def : Pat<(i32 (sext i1:$in)),
|
|
|
|
(SELECT_I4 $in, (LI -1), (LI 0))>;
|
|
|
|
|
|
|
|
def : Pat<(i64 (zext i1:$in)),
|
|
|
|
(SELECT_I8 $in, (LI8 1), (LI8 0))>;
|
|
|
|
def : Pat<(i64 (sext i1:$in)),
|
|
|
|
(SELECT_I8 $in, (LI8 -1), (LI8 0))>;
|
|
|
|
|
|
|
|
// FIXME: We should choose either a zext or a sext based on other constants
|
|
|
|
// already around.
|
|
|
|
def : Pat<(i32 (anyext i1:$in)),
|
|
|
|
(SELECT_I4 $in, (LI 1), (LI 0))>;
|
|
|
|
def : Pat<(i64 (anyext i1:$in)),
|
|
|
|
(SELECT_I8 $in, (LI8 1), (LI8 0))>;
|
|
|
|
|
|
|
|
// match setcc on i1 variables.
|
|
|
|
def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
|
|
|
|
(CRANDC $s2, $s1)>;
|
|
|
|
def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
|
|
|
|
(CRANDC $s2, $s1)>;
|
|
|
|
def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
|
|
|
|
(CRORC $s2, $s1)>;
|
|
|
|
def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
|
|
|
|
(CRORC $s2, $s1)>;
|
|
|
|
def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
|
|
|
|
(CREQV $s1, $s2)>;
|
|
|
|
def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
|
|
|
|
(CRORC $s1, $s2)>;
|
|
|
|
def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
|
|
|
|
(CRORC $s1, $s2)>;
|
|
|
|
def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
|
|
|
|
(CRANDC $s1, $s2)>;
|
|
|
|
def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
|
|
|
|
(CRANDC $s1, $s2)>;
|
|
|
|
def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
|
|
|
|
(CRXOR $s1, $s2)>;
|
|
|
|
|
|
|
|
// match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
|
|
|
|
// SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
|
|
|
|
// floating-point types.
|
|
|
|
|
|
|
|
multiclass CRNotPat<dag pattern, dag result> {
|
|
|
|
def : Pat<pattern, (crnot result)>;
|
|
|
|
def : Pat<(not pattern), result>;
|
|
|
|
|
|
|
|
// We can also fold the crnot into an extension:
|
|
|
|
def : Pat<(i32 (zext pattern)),
|
|
|
|
(SELECT_I4 result, (LI 0), (LI 1))>;
|
|
|
|
def : Pat<(i32 (sext pattern)),
|
|
|
|
(SELECT_I4 result, (LI 0), (LI -1))>;
|
|
|
|
|
|
|
|
// We can also fold the crnot into an extension:
|
|
|
|
def : Pat<(i64 (zext pattern)),
|
|
|
|
(SELECT_I8 result, (LI8 0), (LI8 1))>;
|
|
|
|
def : Pat<(i64 (sext pattern)),
|
|
|
|
(SELECT_I8 result, (LI8 0), (LI8 -1))>;
|
|
|
|
|
|
|
|
// FIXME: We should choose either a zext or a sext based on other constants
|
|
|
|
// already around.
|
|
|
|
def : Pat<(i32 (anyext pattern)),
|
|
|
|
(SELECT_I4 result, (LI 0), (LI 1))>;
|
|
|
|
|
|
|
|
def : Pat<(i64 (anyext pattern)),
|
|
|
|
(SELECT_I8 result, (LI8 0), (LI8 1))>;
|
|
|
|
}
|
|
|
|
|
|
|
|
// FIXME: Because of what seems like a bug in TableGen's type-inference code,
|
|
|
|
// we need to write imm:$imm in the output patterns below, not just $imm, or
|
|
|
|
// else the resulting matcher will not correctly add the immediate operand
|
|
|
|
// (making it a register operand instead).
|
|
|
|
|
|
|
|
// extended SETCC.
|
|
|
|
multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,
|
|
|
|
OutPatFrag rfrag, OutPatFrag rfrag8> {
|
|
|
|
def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))),
|
|
|
|
(rfrag $s1)>;
|
|
|
|
def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))),
|
|
|
|
(rfrag8 $s1)>;
|
|
|
|
def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))),
|
|
|
|
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
|
|
|
|
def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))),
|
|
|
|
(EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
|
|
|
|
|
|
|
|
def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))),
|
|
|
|
(rfrag $s1)>;
|
|
|
|
def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),
|
|
|
|
(rfrag8 $s1)>;
|
|
|
|
def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),
|
|
|
|
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
|
|
|
|
def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),
|
|
|
|
(EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Note that we do all inversions below with i(32|64)not, instead of using
|
|
|
|
// (xori x, 1) because on the A2 nor has single-cycle latency while xori
|
|
|
|
// has 2-cycle latency.
|
|
|
|
|
|
|
|
defm : ExtSetCCPat<SETEQ,
|
|
|
|
PatFrag<(ops node:$in, node:$cc),
|
|
|
|
(setcc $in, 0, $cc)>,
|
|
|
|
OutPatFrag<(ops node:$in),
|
|
|
|
(RLWINM (CNTLZW $in), 27, 31, 31)>,
|
|
|
|
OutPatFrag<(ops node:$in),
|
|
|
|
(RLDICL (CNTLZD $in), 58, 63)> >;
|
|
|
|
|
|
|
|
defm : ExtSetCCPat<SETNE,
|
|
|
|
PatFrag<(ops node:$in, node:$cc),
|
|
|
|
(setcc $in, 0, $cc)>,
|
|
|
|
OutPatFrag<(ops node:$in),
|
|
|
|
(RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>,
|
|
|
|
OutPatFrag<(ops node:$in),
|
|
|
|
(RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
|
|
|
|
|
|
|
|
defm : ExtSetCCPat<SETLT,
|
|
|
|
PatFrag<(ops node:$in, node:$cc),
|
|
|
|
(setcc $in, 0, $cc)>,
|
|
|
|
OutPatFrag<(ops node:$in),
|
|
|
|
(RLWINM $in, 1, 31, 31)>,
|
|
|
|
OutPatFrag<(ops node:$in),
|
|
|
|
(RLDICL $in, 1, 63)> >;
|
|
|
|
|
|
|
|
defm : ExtSetCCPat<SETGE,
|
|
|
|
PatFrag<(ops node:$in, node:$cc),
|
|
|
|
(setcc $in, 0, $cc)>,
|
|
|
|
OutPatFrag<(ops node:$in),
|
|
|
|
(RLWINM (i32not $in), 1, 31, 31)>,
|
|
|
|
OutPatFrag<(ops node:$in),
|
|
|
|
(RLDICL (i64not $in), 1, 63)> >;
|
|
|
|
|
|
|
|
defm : ExtSetCCPat<SETGT,
|
|
|
|
PatFrag<(ops node:$in, node:$cc),
|
|
|
|
(setcc $in, 0, $cc)>,
|
|
|
|
OutPatFrag<(ops node:$in),
|
|
|
|
(RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>,
|
|
|
|
OutPatFrag<(ops node:$in),
|
|
|
|
(RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
|
|
|
|
|
|
|
|
defm : ExtSetCCPat<SETLE,
|
|
|
|
PatFrag<(ops node:$in, node:$cc),
|
|
|
|
(setcc $in, 0, $cc)>,
|
|
|
|
OutPatFrag<(ops node:$in),
|
|
|
|
(RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,
|
|
|
|
OutPatFrag<(ops node:$in),
|
|
|
|
(RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
|
|
|
|
|
|
|
|
defm : ExtSetCCPat<SETLT,
|
|
|
|
PatFrag<(ops node:$in, node:$cc),
|
|
|
|
(setcc $in, -1, $cc)>,
|
|
|
|
OutPatFrag<(ops node:$in),
|
|
|
|
(RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>,
|
|
|
|
OutPatFrag<(ops node:$in),
|
|
|
|
(RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
|
|
|
|
|
|
|
|
defm : ExtSetCCPat<SETGE,
|
|
|
|
PatFrag<(ops node:$in, node:$cc),
|
|
|
|
(setcc $in, -1, $cc)>,
|
|
|
|
OutPatFrag<(ops node:$in),
|
|
|
|
(RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>,
|
|
|
|
OutPatFrag<(ops node:$in),
|
|
|
|
(RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
|
|
|
|
|
|
|
|
defm : ExtSetCCPat<SETGT,
|
|
|
|
PatFrag<(ops node:$in, node:$cc),
|
|
|
|
(setcc $in, -1, $cc)>,
|
|
|
|
OutPatFrag<(ops node:$in),
|
|
|
|
(RLWINM (i32not $in), 1, 31, 31)>,
|
|
|
|
OutPatFrag<(ops node:$in),
|
|
|
|
(RLDICL (i64not $in), 1, 63)> >;
|
|
|
|
|
|
|
|
defm : ExtSetCCPat<SETLE,
|
|
|
|
PatFrag<(ops node:$in, node:$cc),
|
|
|
|
(setcc $in, -1, $cc)>,
|
|
|
|
OutPatFrag<(ops node:$in),
|
|
|
|
(RLWINM $in, 1, 31, 31)>,
|
|
|
|
OutPatFrag<(ops node:$in),
|
|
|
|
(RLDICL $in, 1, 63)> >;
|
|
|
|
|
|
|
|
// SETCC for i32.
|
|
|
|
def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
|
|
|
|
(EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
|
|
|
|
def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
|
|
|
|
(EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
|
|
|
|
def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
|
|
|
|
(EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
|
|
|
|
def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
|
|
|
|
(EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
|
|
|
|
def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
|
|
|
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(EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
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|
def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
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(EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
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|
// For non-equality comparisons, the default code would materialize the
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|
|
// constant, then compare against it, like this:
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// lis r2, 4660
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|
// ori r2, r2, 22136
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|
// cmpw cr0, r3, r2
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|
// beq cr0,L6
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|
// Since we are just comparing for equality, we can emit this instead:
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|
// xoris r0,r3,0x1234
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|
// cmplwi cr0,r0,0x5678
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// beq cr0,L6
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def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
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(EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
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(LO16 imm:$imm)), sub_eq)>;
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defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
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(EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
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defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
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(EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
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defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
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(EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
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defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)),
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(EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
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defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
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(EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
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defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
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(EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
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defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
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(EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
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|
(LO16 imm:$imm)), sub_eq)>;
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def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
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(EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
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def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
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(EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
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def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
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(EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
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def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
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(EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
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def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
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(EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
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defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
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(EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
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|
defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
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(EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
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|
defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
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|
|
(EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
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|
defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)),
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|
|
(EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
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|
defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
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(EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
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|
// SETCC for i64.
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|
def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
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(EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
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|
def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
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|
|
|
(EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
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|
|
|
def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
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|
|
(EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
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|
def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
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|
|
|
(EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
|
|
|
|
def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
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|
|
|
(EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
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|
|
|
def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
|
|
|
|
(EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
|
|
|
|
|
|
|
|
// For non-equality comparisons, the default code would materialize the
|
|
|
|
// constant, then compare against it, like this:
|
|
|
|
// lis r2, 4660
|
|
|
|
// ori r2, r2, 22136
|
|
|
|
// cmpd cr0, r3, r2
|
|
|
|
// beq cr0,L6
|
|
|
|
// Since we are just comparing for equality, we can emit this instead:
|
|
|
|
// xoris r0,r3,0x1234
|
|
|
|
// cmpldi cr0,r0,0x5678
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|
|
|
// beq cr0,L6
|
|
|
|
|
|
|
|
def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
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|
|
|
(EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
|
|
|
|
(LO16 imm:$imm)), sub_eq)>;
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|
|
|
|
|
|
|
defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
|
|
|
|
(EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
|
|
|
|
defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
|
|
|
|
(EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
|
|
|
|
defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
|
|
|
|
(EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
|
|
|
|
defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)),
|
|
|
|
(EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
|
|
|
|
defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
|
|
|
|
(EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
|
|
|
|
defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
|
|
|
|
(EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
|
|
|
|
|
|
|
|
defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
|
|
|
|
(EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
|
|
|
|
(LO16 imm:$imm)), sub_eq)>;
|
|
|
|
|
|
|
|
def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
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|
|
|
(EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
|
|
|
|
def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
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|
|
|
(EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
|
|
|
|
def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
|
|
|
|
(EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
|
|
|
|
def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
|
|
|
|
(EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
|
|
|
|
def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
|
|
|
|
(EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
|
|
|
|
|
|
|
|
defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
|
|
|
|
(EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
|
|
|
|
defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
|
|
|
|
(EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
|
|
|
|
defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
|
|
|
|
(EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
|
|
|
|
defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
|
|
|
|
(EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
|
|
|
|
defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
|
|
|
|
(EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
|
|
|
|
|
|
|
|
// SETCC for f32.
|
|
|
|
def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
|
|
|
|
(EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
|
|
|
|
def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
|
|
|
|
(EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
|
|
|
|
def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
|
|
|
|
(EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
|
|
|
|
def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
|
|
|
|
(EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
|
|
|
|
def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
|
|
|
|
(EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
|
|
|
|
def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
|
|
|
|
(EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
|
|
|
|
def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)),
|
|
|
|
(EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
|
|
|
|
|
|
|
|
defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
|
|
|
|
(EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
|
|
|
|
defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
|
|
|
|
(EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
|
|
|
|
defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
|
|
|
|
(EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
|
|
|
|
defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
|
|
|
|
(EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
|
|
|
|
defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
|
|
|
|
(EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
|
|
|
|
defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
|
|
|
|
(EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
|
|
|
|
defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)),
|
|
|
|
(EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
|
|
|
|
|
|
|
|
// SETCC for f64.
|
|
|
|
def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
|
|
|
|
(EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
|
|
|
|
def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
|
|
|
|
(EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
|
|
|
|
def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
|
|
|
|
(EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
|
|
|
|
def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
|
|
|
|
(EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
|
|
|
|
def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
|
|
|
|
(EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
|
|
|
|
def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
|
|
|
|
(EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
|
|
|
|
def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)),
|
|
|
|
(EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
|
|
|
|
|
|
|
|
defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
|
|
|
|
(EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
|
|
|
|
defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
|
|
|
|
(EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
|
|
|
|
defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
|
|
|
|
(EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
|
|
|
|
defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
|
|
|
|
(EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
|
|
|
|
defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
|
|
|
|
(EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
|
|
|
|
defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
|
|
|
|
(EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
|
|
|
|
defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
|
|
|
|
(EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
|
|
|
|
|
|
|
|
// match select on i1 variables:
|
|
|
|
def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
|
|
|
|
(CROR (CRAND $cond , $tval),
|
|
|
|
(CRAND (crnot $cond), $fval))>;
|
|
|
|
|
|
|
|
// match selectcc on i1 variables:
|
|
|
|
// select (lhs == rhs), tval, fval is:
|
|
|
|
// ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
|
|
|
|
def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
|
|
|
|
(CROR (CRAND (CRANDC $rhs, $lhs), $tval),
|
|
|
|
(CRAND (CRORC $lhs, $rhs), $fval))>;
|
|
|
|
def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),
|
|
|
|
(CROR (CRAND (CRORC $rhs, $lhs), $tval),
|
|
|
|
(CRAND (CRANDC $lhs, $rhs), $fval))>;
|
|
|
|
def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),
|
|
|
|
(CROR (CRAND (CREQV $lhs, $rhs), $tval),
|
|
|
|
(CRAND (CRXOR $lhs, $rhs), $fval))>;
|
|
|
|
def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
|
|
|
|
(CROR (CRAND (CRORC $lhs, $rhs), $tval),
|
|
|
|
(CRAND (CRANDC $rhs, $lhs), $fval))>;
|
|
|
|
def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),
|
|
|
|
(CROR (CRAND (CRANDC $lhs, $rhs), $tval),
|
|
|
|
(CRAND (CRORC $rhs, $lhs), $fval))>;
|
|
|
|
def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),
|
|
|
|
(CROR (CRAND (CREQV $lhs, $rhs), $fval),
|
|
|
|
(CRAND (CRXOR $lhs, $rhs), $tval))>;
|
|
|
|
|
|
|
|
// match selectcc on i1 variables with non-i1 output.
|
|
|
|
def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),
|
|
|
|
(SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
|
|
|
|
def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),
|
|
|
|
(SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>;
|
|
|
|
def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),
|
|
|
|
(SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;
|
|
|
|
def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),
|
|
|
|
(SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>;
|
|
|
|
def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),
|
|
|
|
(SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
|
|
|
|
def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),
|
|
|
|
(SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;
|
|
|
|
|
|
|
|
def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),
|
|
|
|
(SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
|
|
|
|
def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),
|
|
|
|
(SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>;
|
|
|
|
def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),
|
|
|
|
(SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;
|
|
|
|
def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),
|
|
|
|
(SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>;
|
|
|
|
def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
|
|
|
|
(SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
|
|
|
|
def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
|
|
|
|
(SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
|
|
|
|
|
|
|
|
def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
|
|
|
|
(SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
|
|
|
|
def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
|
|
|
|
(SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>;
|
|
|
|
def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
|
|
|
|
(SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;
|
|
|
|
def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
|
|
|
|
(SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>;
|
|
|
|
def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
|
|
|
|
(SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
|
|
|
|
def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
|
|
|
|
(SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;
|
|
|
|
|
|
|
|
def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
|
|
|
|
(SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
|
|
|
|
def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
|
|
|
|
(SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>;
|
|
|
|
def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
|
|
|
|
(SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;
|
|
|
|
def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
|
|
|
|
(SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>;
|
|
|
|
def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
|
|
|
|
(SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
|
|
|
|
def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
|
|
|
|
(SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
|
|
|
|
|
|
|
|
def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
|
|
|
|
(SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
|
|
|
|
def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),
|
|
|
|
(SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>;
|
|
|
|
def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),
|
|
|
|
(SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;
|
|
|
|
def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),
|
|
|
|
(SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>;
|
|
|
|
def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
|
|
|
|
(SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
|
|
|
|
def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
|
|
|
|
(SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
|
|
|
|
|
|
|
|
let usesCustomInserter = 1 in {
|
|
|
|
def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
|
|
|
|
"#ANDIo_1_EQ_BIT",
|
|
|
|
[(set i1:$dst, (trunc (not i32:$in)))]>;
|
|
|
|
def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
|
|
|
|
"#ANDIo_1_GT_BIT",
|
|
|
|
[(set i1:$dst, (trunc i32:$in))]>;
|
|
|
|
|
|
|
|
def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
|
|
|
|
"#ANDIo_1_EQ_BIT8",
|
|
|
|
[(set i1:$dst, (trunc (not i64:$in)))]>;
|
|
|
|
def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
|
|
|
|
"#ANDIo_1_GT_BIT8",
|
|
|
|
[(set i1:$dst, (trunc i64:$in))]>;
|
|
|
|
}
|
|
|
|
|
|
|
|
def : Pat<(i1 (not (trunc i32:$in))),
|
|
|
|
(ANDIo_1_EQ_BIT $in)>;
|
|
|
|
def : Pat<(i1 (not (trunc i64:$in))),
|
|
|
|
(ANDIo_1_EQ_BIT8 $in)>;
|
2013-05-03 19:51:09 +00:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// PowerPC Instructions used for assembler/disassembler only
|
|
|
|
//
|
|
|
|
|
|
|
|
def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
|
2013-11-27 23:26:09 +00:00
|
|
|
"isync", IIC_SprISYNC, []>;
|
2013-05-03 19:51:09 +00:00
|
|
|
|
|
|
|
def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
|
2013-11-27 23:26:09 +00:00
|
|
|
"icbi $src", IIC_LdStICBI, []>;
|
2013-05-03 19:51:09 +00:00
|
|
|
|
2013-07-01 17:06:26 +00:00
|
|
|
def EIEIO : XForm_24_eieio<31, 854, (outs), (ins),
|
2013-11-27 23:26:09 +00:00
|
|
|
"eieio", IIC_LdStLoad, []>;
|
2013-07-01 17:06:26 +00:00
|
|
|
|
2013-07-01 17:21:23 +00:00
|
|
|
def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
|
2013-11-27 23:26:09 +00:00
|
|
|
"wait $L", IIC_LdStLoad, []>;
|
2013-07-01 17:21:23 +00:00
|
|
|
|
2013-09-12 17:50:54 +00:00
|
|
|
def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
|
2013-11-27 23:26:09 +00:00
|
|
|
"mtmsr $RS, $L", IIC_SprMTMSR>;
|
2013-09-12 17:50:54 +00:00
|
|
|
|
|
|
|
def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
|
2013-11-27 23:26:09 +00:00
|
|
|
"mfmsr $RT", IIC_SprMFMSR, []>;
|
2013-09-12 17:50:54 +00:00
|
|
|
|
|
|
|
def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
|
2013-11-27 23:26:09 +00:00
|
|
|
"mtmsrd $RS, $L", IIC_SprMTMSRD>;
|
2013-09-12 17:50:54 +00:00
|
|
|
|
|
|
|
def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"slbie $RB", IIC_SprSLBIE, []>;
|
2013-09-12 17:50:54 +00:00
|
|
|
|
|
|
|
def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"slbmte $RS, $RB", IIC_SprSLBMTE, []>;
|
2013-09-12 17:50:54 +00:00
|
|
|
|
|
|
|
def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
|
2013-09-12 17:50:54 +00:00
|
|
|
|
2013-11-27 23:26:09 +00:00
|
|
|
def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
|
2013-09-12 17:50:54 +00:00
|
|
|
|
|
|
|
def TLBSYNC : XForm_0<31, 566, (outs), (ins),
|
2013-11-27 23:26:09 +00:00
|
|
|
"tlbsync", IIC_SprTLBSYNC, []>;
|
2013-09-12 17:50:54 +00:00
|
|
|
|
|
|
|
def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"tlbiel $RB", IIC_SprTLBIEL, []>;
|
2013-09-12 17:50:54 +00:00
|
|
|
|
|
|
|
def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
|
2013-11-27 23:26:09 +00:00
|
|
|
"tlbie $RB,$RS", IIC_SprTLBIE, []>;
|
2013-09-12 17:50:54 +00:00
|
|
|
|
2013-05-03 19:50:27 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// PowerPC Assembler Instruction Aliases
|
|
|
|
//
|
|
|
|
|
|
|
|
// Pseudo-instructions for alternate assembly syntax (never used by codegen).
|
|
|
|
// These are aliases that require C++ handling to convert to the target
|
|
|
|
// instruction, while InstAliases can be handled directly by tblgen.
|
|
|
|
class PPCAsmPseudo<string asm, dag iops>
|
|
|
|
: Instruction {
|
|
|
|
let Namespace = "PPC";
|
|
|
|
bit PPC64 = 0; // Default value, override with isPPC64
|
|
|
|
|
|
|
|
let OutOperandList = (outs);
|
|
|
|
let InOperandList = iops;
|
|
|
|
let Pattern = [];
|
|
|
|
let AsmString = asm;
|
|
|
|
let isAsmParserOnly = 1;
|
|
|
|
let isPseudo = 1;
|
|
|
|
}
|
|
|
|
|
2013-06-10 17:19:43 +00:00
|
|
|
def : InstAlias<"sc", (SC 0)>;
|
|
|
|
|
2014-01-22 20:20:52 +00:00
|
|
|
def : InstAlias<"sync", (SYNC 0)>, Requires<[IsNotBookE]>;
|
|
|
|
def : InstAlias<"msync", (SYNC 0)>, Requires<[IsNotBookE]>;
|
|
|
|
def : InstAlias<"lwsync", (SYNC 1)>, Requires<[IsNotBookE]>;
|
|
|
|
def : InstAlias<"ptesync", (SYNC 2)>, Requires<[IsNotBookE]>;
|
2013-07-01 16:37:52 +00:00
|
|
|
|
2013-07-01 17:21:23 +00:00
|
|
|
def : InstAlias<"wait", (WAIT 0)>;
|
|
|
|
def : InstAlias<"waitrsv", (WAIT 1)>;
|
|
|
|
def : InstAlias<"waitimpl", (WAIT 2)>;
|
|
|
|
|
2013-07-01 21:40:54 +00:00
|
|
|
def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
|
|
|
|
def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
|
|
|
|
def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
|
|
|
|
def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
|
|
|
|
|
2013-07-03 12:32:41 +00:00
|
|
|
def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
|
|
|
|
def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
|
|
|
|
|
2013-07-08 15:20:38 +00:00
|
|
|
def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
|
|
|
|
def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
|
|
|
|
|
2013-06-24 18:08:03 +00:00
|
|
|
def : InstAlias<"xnop", (XORI R0, R0, 0)>;
|
|
|
|
|
2013-05-03 19:50:27 +00:00
|
|
|
def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
|
2013-06-24 18:08:03 +00:00
|
|
|
def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
|
|
|
|
|
|
|
|
def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
|
|
|
|
def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
|
|
|
|
|
2013-07-03 17:59:07 +00:00
|
|
|
def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
|
|
|
|
|
2013-06-24 18:08:03 +00:00
|
|
|
def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
|
2013-05-03 19:50:27 +00:00
|
|
|
|
2013-06-25 13:16:48 +00:00
|
|
|
def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
|
|
|
|
(ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
|
|
|
|
def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
|
|
|
|
(ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
|
|
|
|
def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
|
|
|
|
(ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
|
|
|
|
def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
|
|
|
|
(ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
|
|
|
|
|
|
|
|
def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
|
|
|
|
def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
|
|
|
|
def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
|
|
|
|
def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
|
|
|
|
|
2013-09-12 17:50:54 +00:00
|
|
|
def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
|
|
|
|
def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
|
|
|
|
|
|
|
|
def : InstAlias<"mfsprg $RT, 0", (MFSPR gprc:$RT, 272)>;
|
|
|
|
def : InstAlias<"mfsprg $RT, 1", (MFSPR gprc:$RT, 273)>;
|
|
|
|
def : InstAlias<"mfsprg $RT, 2", (MFSPR gprc:$RT, 274)>;
|
|
|
|
def : InstAlias<"mfsprg $RT, 3", (MFSPR gprc:$RT, 275)>;
|
|
|
|
|
|
|
|
def : InstAlias<"mfsprg0 $RT", (MFSPR gprc:$RT, 272)>;
|
|
|
|
def : InstAlias<"mfsprg1 $RT", (MFSPR gprc:$RT, 273)>;
|
|
|
|
def : InstAlias<"mfsprg2 $RT", (MFSPR gprc:$RT, 274)>;
|
|
|
|
def : InstAlias<"mfsprg3 $RT", (MFSPR gprc:$RT, 275)>;
|
|
|
|
|
|
|
|
def : InstAlias<"mtsprg 0, $RT", (MTSPR 272, gprc:$RT)>;
|
|
|
|
def : InstAlias<"mtsprg 1, $RT", (MTSPR 273, gprc:$RT)>;
|
|
|
|
def : InstAlias<"mtsprg 2, $RT", (MTSPR 274, gprc:$RT)>;
|
|
|
|
def : InstAlias<"mtsprg 3, $RT", (MTSPR 275, gprc:$RT)>;
|
|
|
|
|
|
|
|
def : InstAlias<"mtsprg0 $RT", (MTSPR 272, gprc:$RT)>;
|
|
|
|
def : InstAlias<"mtsprg1 $RT", (MTSPR 273, gprc:$RT)>;
|
|
|
|
def : InstAlias<"mtsprg2 $RT", (MTSPR 274, gprc:$RT)>;
|
|
|
|
def : InstAlias<"mtsprg3 $RT", (MTSPR 275, gprc:$RT)>;
|
|
|
|
|
|
|
|
def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
|
|
|
|
|
|
|
|
def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
|
|
|
|
def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
|
|
|
|
|
|
|
|
def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
|
|
|
|
|
|
|
|
def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
|
|
|
|
def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
|
|
|
|
|
|
|
|
def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
|
|
|
|
def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
|
|
|
|
def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
|
|
|
|
def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
|
|
|
|
|
|
|
|
def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
|
|
|
|
|
2013-06-25 13:17:41 +00:00
|
|
|
def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
|
|
|
|
(ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
|
|
|
|
def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
|
|
|
|
(ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
|
|
|
|
def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
|
|
|
|
(ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
|
|
|
|
def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
|
|
|
|
(ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
|
|
|
|
def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
|
|
|
|
(ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
|
|
|
|
def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
|
|
|
|
(ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
|
|
|
|
def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
|
|
|
|
(ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
|
|
|
|
def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
|
|
|
|
(ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
|
|
|
|
def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
|
|
|
|
(ins gprc:$rA, gprc:$rS, u5imm:$n)>;
|
|
|
|
def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
|
|
|
|
(ins gprc:$rA, gprc:$rS, u5imm:$n)>;
|
2013-05-03 19:50:27 +00:00
|
|
|
def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
|
|
|
|
(ins gprc:$rA, gprc:$rS, u5imm:$n)>;
|
2013-06-25 13:17:41 +00:00
|
|
|
def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
|
|
|
|
(ins gprc:$rA, gprc:$rS, u5imm:$n)>;
|
2013-05-03 19:50:27 +00:00
|
|
|
def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
|
|
|
|
(ins gprc:$rA, gprc:$rS, u5imm:$n)>;
|
2013-06-25 13:17:41 +00:00
|
|
|
def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
|
|
|
|
(ins gprc:$rA, gprc:$rS, u5imm:$n)>;
|
|
|
|
def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
|
|
|
|
(ins gprc:$rA, gprc:$rS, u5imm:$n)>;
|
|
|
|
def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
|
|
|
|
(ins gprc:$rA, gprc:$rS, u5imm:$n)>;
|
|
|
|
def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
|
|
|
|
(ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
|
|
|
|
def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
|
|
|
|
(ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
|
|
|
|
|
|
|
|
def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
|
|
|
|
def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
|
|
|
|
def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
|
|
|
|
def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
|
|
|
|
def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
|
|
|
|
def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
|
|
|
|
|
|
|
|
def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
|
|
|
|
(ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
|
|
|
|
def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
|
|
|
|
(ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
|
|
|
|
def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
|
|
|
|
(ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
|
|
|
|
def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
|
|
|
|
(ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
|
|
|
|
def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
|
|
|
|
(ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
|
|
|
|
def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
|
|
|
|
(ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
|
|
|
|
def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
|
|
|
|
(ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
|
|
|
|
def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
|
|
|
|
(ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
|
2013-05-03 19:50:27 +00:00
|
|
|
def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
|
|
|
|
(ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
|
2013-06-25 13:17:41 +00:00
|
|
|
def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
|
|
|
|
(ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
|
2013-05-03 19:50:27 +00:00
|
|
|
def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
|
|
|
|
(ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
|
2013-06-25 13:17:41 +00:00
|
|
|
def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
|
|
|
|
(ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
|
|
|
|
def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
|
|
|
|
(ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
|
|
|
|
def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
|
|
|
|
(ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
|
|
|
|
def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
|
|
|
|
(ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
|
|
|
|
def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
|
|
|
|
(ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
|
|
|
|
|
|
|
|
def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
|
|
|
|
def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
|
|
|
|
def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
|
|
|
|
def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
|
|
|
|
def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
|
|
|
|
def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
|
2013-05-03 19:50:27 +00:00
|
|
|
|
2013-06-24 11:55:21 +00:00
|
|
|
// These generic branch instruction forms are used for the assembler parser only.
|
|
|
|
// Defs and Uses are conservative, since we don't know the BO value.
|
|
|
|
let PPC970_Unit = 7 in {
|
|
|
|
let Defs = [CTR], Uses = [CTR, RM] in {
|
|
|
|
def gBC : BForm_3<16, 0, 0, (outs),
|
|
|
|
(ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
|
|
|
|
"bc $bo, $bi, $dst">;
|
|
|
|
def gBCA : BForm_3<16, 1, 0, (outs),
|
|
|
|
(ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
|
|
|
|
"bca $bo, $bi, $dst">;
|
|
|
|
}
|
|
|
|
let Defs = [LR, CTR], Uses = [CTR, RM] in {
|
|
|
|
def gBCL : BForm_3<16, 0, 1, (outs),
|
|
|
|
(ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
|
|
|
|
"bcl $bo, $bi, $dst">;
|
|
|
|
def gBCLA : BForm_3<16, 1, 1, (outs),
|
|
|
|
(ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
|
|
|
|
"bcla $bo, $bi, $dst">;
|
|
|
|
}
|
|
|
|
let Defs = [CTR], Uses = [CTR, LR, RM] in
|
|
|
|
def gBCLR : XLForm_2<19, 16, 0, (outs),
|
|
|
|
(ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
|
2013-11-27 23:26:09 +00:00
|
|
|
"bclr $bo, $bi, $bh", IIC_BrB, []>;
|
2013-06-24 11:55:21 +00:00
|
|
|
let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
|
|
|
|
def gBCLRL : XLForm_2<19, 16, 1, (outs),
|
|
|
|
(ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
|
2013-11-27 23:26:09 +00:00
|
|
|
"bclrl $bo, $bi, $bh", IIC_BrB, []>;
|
2013-06-24 11:55:21 +00:00
|
|
|
let Defs = [CTR], Uses = [CTR, LR, RM] in
|
|
|
|
def gBCCTR : XLForm_2<19, 528, 0, (outs),
|
|
|
|
(ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
|
2013-11-27 23:26:09 +00:00
|
|
|
"bcctr $bo, $bi, $bh", IIC_BrB, []>;
|
2013-06-24 11:55:21 +00:00
|
|
|
let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
|
|
|
|
def gBCCTRL : XLForm_2<19, 528, 1, (outs),
|
|
|
|
(ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
|
2013-11-27 23:26:09 +00:00
|
|
|
"bcctrl $bo, $bi, $bh", IIC_BrB, []>;
|
2013-06-24 11:55:21 +00:00
|
|
|
}
|
|
|
|
def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
|
|
|
|
def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
|
|
|
|
def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
|
|
|
|
def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
|
|
|
|
|
2013-06-24 16:52:04 +00:00
|
|
|
multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
|
|
|
|
def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
|
|
|
|
def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
|
|
|
|
def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
|
|
|
|
def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
|
|
|
|
def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
|
|
|
|
def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
|
|
|
|
}
|
|
|
|
multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
|
|
|
|
: BranchSimpleMnemonic1<name, pm, bo> {
|
|
|
|
def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
|
|
|
|
def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
|
|
|
|
}
|
|
|
|
defm : BranchSimpleMnemonic2<"t", "", 12>;
|
|
|
|
defm : BranchSimpleMnemonic2<"f", "", 4>;
|
|
|
|
defm : BranchSimpleMnemonic2<"t", "-", 14>;
|
|
|
|
defm : BranchSimpleMnemonic2<"f", "-", 6>;
|
|
|
|
defm : BranchSimpleMnemonic2<"t", "+", 15>;
|
|
|
|
defm : BranchSimpleMnemonic2<"f", "+", 7>;
|
|
|
|
defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
|
|
|
|
defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
|
|
|
|
defm : BranchSimpleMnemonic1<"dzt", "", 10>;
|
|
|
|
defm : BranchSimpleMnemonic1<"dzf", "", 2>;
|
|
|
|
|
|
|
|
multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
|
|
|
|
def : InstAlias<"b"#name#pm#" $cc, $dst",
|
2013-06-10 17:18:29 +00:00
|
|
|
(BCC bibo, crrc:$cc, condbrtarget:$dst)>;
|
2013-06-24 16:52:04 +00:00
|
|
|
def : InstAlias<"b"#name#pm#" $dst",
|
2013-06-10 17:19:15 +00:00
|
|
|
(BCC bibo, CR0, condbrtarget:$dst)>;
|
|
|
|
|
2013-06-24 16:52:04 +00:00
|
|
|
def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
|
2013-06-24 11:03:33 +00:00
|
|
|
(BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
|
2013-06-24 16:52:04 +00:00
|
|
|
def : InstAlias<"b"#name#"a"#pm#" $dst",
|
2013-06-24 11:03:33 +00:00
|
|
|
(BCCA bibo, CR0, abscondbrtarget:$dst)>;
|
|
|
|
|
2013-06-24 16:52:04 +00:00
|
|
|
def : InstAlias<"b"#name#"lr"#pm#" $cc",
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
(BCCLR bibo, crrc:$cc)>;
|
2013-06-24 16:52:04 +00:00
|
|
|
def : InstAlias<"b"#name#"lr"#pm,
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
(BCCLR bibo, CR0)>;
|
2013-06-10 17:19:15 +00:00
|
|
|
|
2013-06-24 16:52:04 +00:00
|
|
|
def : InstAlias<"b"#name#"ctr"#pm#" $cc",
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
(BCCCTR bibo, crrc:$cc)>;
|
2013-06-24 16:52:04 +00:00
|
|
|
def : InstAlias<"b"#name#"ctr"#pm,
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
(BCCCTR bibo, CR0)>;
|
2013-06-10 17:19:15 +00:00
|
|
|
|
2013-06-24 16:52:04 +00:00
|
|
|
def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
|
2013-06-24 11:02:19 +00:00
|
|
|
(BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
|
2013-06-24 16:52:04 +00:00
|
|
|
def : InstAlias<"b"#name#"l"#pm#" $dst",
|
2013-06-24 11:02:19 +00:00
|
|
|
(BCCL bibo, CR0, condbrtarget:$dst)>;
|
|
|
|
|
2013-06-24 16:52:04 +00:00
|
|
|
def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
|
2013-06-24 11:03:33 +00:00
|
|
|
(BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
|
2013-06-24 16:52:04 +00:00
|
|
|
def : InstAlias<"b"#name#"la"#pm#" $dst",
|
2013-06-24 11:03:33 +00:00
|
|
|
(BCCLA bibo, CR0, abscondbrtarget:$dst)>;
|
|
|
|
|
2013-06-24 16:52:04 +00:00
|
|
|
def : InstAlias<"b"#name#"lrl"#pm#" $cc",
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
(BCCLRL bibo, crrc:$cc)>;
|
2013-06-24 16:52:04 +00:00
|
|
|
def : InstAlias<"b"#name#"lrl"#pm,
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
(BCCLRL bibo, CR0)>;
|
2013-06-24 11:01:55 +00:00
|
|
|
|
2013-06-24 16:52:04 +00:00
|
|
|
def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
(BCCCTRL bibo, crrc:$cc)>;
|
2013-06-24 16:52:04 +00:00
|
|
|
def : InstAlias<"b"#name#"ctrl"#pm,
|
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
|
|
|
(BCCCTRL bibo, CR0)>;
|
2013-06-10 17:18:29 +00:00
|
|
|
}
|
2013-06-24 16:52:04 +00:00
|
|
|
multiclass BranchExtendedMnemonic<string name, int bibo> {
|
|
|
|
defm : BranchExtendedMnemonicPM<name, "", bibo>;
|
|
|
|
defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
|
|
|
|
defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
|
|
|
|
}
|
2013-06-10 17:18:29 +00:00
|
|
|
defm : BranchExtendedMnemonic<"lt", 12>;
|
|
|
|
defm : BranchExtendedMnemonic<"gt", 44>;
|
|
|
|
defm : BranchExtendedMnemonic<"eq", 76>;
|
|
|
|
defm : BranchExtendedMnemonic<"un", 108>;
|
|
|
|
defm : BranchExtendedMnemonic<"so", 108>;
|
|
|
|
defm : BranchExtendedMnemonic<"ge", 4>;
|
|
|
|
defm : BranchExtendedMnemonic<"nl", 4>;
|
|
|
|
defm : BranchExtendedMnemonic<"le", 36>;
|
|
|
|
defm : BranchExtendedMnemonic<"ng", 36>;
|
|
|
|
defm : BranchExtendedMnemonic<"ne", 68>;
|
|
|
|
defm : BranchExtendedMnemonic<"nu", 100>;
|
|
|
|
defm : BranchExtendedMnemonic<"ns", 100>;
|
2013-05-03 19:50:27 +00:00
|
|
|
|
[PowerPC] Support compare mnemonics with implied CR0
Just like for branch mnemonics (where support was recently added), the
assembler is supposed to support extended mnemonics for the compare
instructions where no condition register is specified explicitly
(and CR0 is assumed implicitly).
This patch adds support for those extended compare mnemonics.
Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
===================================================================
--- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s
+++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
@@ -449,21 +449,37 @@
# CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80]
cmpdi 2, 3, 128
+# CHECK: cmpdi 0, 3, 128 # encoding: [0x2c,0x23,0x00,0x80]
+ cmpdi 3, 128
# CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00]
cmpd 2, 3, 4
+# CHECK: cmpd 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x00]
+ cmpd 3, 4
# CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80]
cmpldi 2, 3, 128
+# CHECK: cmpldi 0, 3, 128 # encoding: [0x28,0x23,0x00,0x80]
+ cmpldi 3, 128
# CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40]
cmpld 2, 3, 4
+# CHECK: cmpld 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x40]
+ cmpld 3, 4
# CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80]
cmpwi 2, 3, 128
+# CHECK: cmpwi 0, 3, 128 # encoding: [0x2c,0x03,0x00,0x80]
+ cmpwi 3, 128
# CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00]
cmpw 2, 3, 4
+# CHECK: cmpw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x00]
+ cmpw 3, 4
# CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80]
cmplwi 2, 3, 128
+# CHECK: cmplwi 0, 3, 128 # encoding: [0x28,0x03,0x00,0x80]
+ cmplwi 3, 128
# CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40]
cmplw 2, 3, 4
+# CHECK: cmplw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x40]
+ cmplw 3, 4
# FIXME: Trap mnemonics
Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>;
defm : BranchExtendedMnemonic<"nu", 100>;
defm : BranchExtendedMnemonic<"ns", 100>;
+def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
+
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184435 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-20 16:15:12 +00:00
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def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
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def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
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def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
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def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
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2014-01-02 21:26:59 +00:00
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def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
|
[PowerPC] Support compare mnemonics with implied CR0
Just like for branch mnemonics (where support was recently added), the
assembler is supposed to support extended mnemonics for the compare
instructions where no condition register is specified explicitly
(and CR0 is assumed implicitly).
This patch adds support for those extended compare mnemonics.
Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
===================================================================
--- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s
+++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
@@ -449,21 +449,37 @@
# CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80]
cmpdi 2, 3, 128
+# CHECK: cmpdi 0, 3, 128 # encoding: [0x2c,0x23,0x00,0x80]
+ cmpdi 3, 128
# CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00]
cmpd 2, 3, 4
+# CHECK: cmpd 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x00]
+ cmpd 3, 4
# CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80]
cmpldi 2, 3, 128
+# CHECK: cmpldi 0, 3, 128 # encoding: [0x28,0x23,0x00,0x80]
+ cmpldi 3, 128
# CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40]
cmpld 2, 3, 4
+# CHECK: cmpld 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x40]
+ cmpld 3, 4
# CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80]
cmpwi 2, 3, 128
+# CHECK: cmpwi 0, 3, 128 # encoding: [0x2c,0x03,0x00,0x80]
+ cmpwi 3, 128
# CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00]
cmpw 2, 3, 4
+# CHECK: cmpw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x00]
+ cmpw 3, 4
# CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80]
cmplwi 2, 3, 128
+# CHECK: cmplwi 0, 3, 128 # encoding: [0x28,0x03,0x00,0x80]
+ cmplwi 3, 128
# CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40]
cmplw 2, 3, 4
+# CHECK: cmplw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x40]
+ cmplw 3, 4
# FIXME: Trap mnemonics
Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>;
defm : BranchExtendedMnemonic<"nu", 100>;
defm : BranchExtendedMnemonic<"ns", 100>;
+def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
+
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184435 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-20 16:15:12 +00:00
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def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
|
2014-01-02 21:26:59 +00:00
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def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
|
[PowerPC] Support compare mnemonics with implied CR0
Just like for branch mnemonics (where support was recently added), the
assembler is supposed to support extended mnemonics for the compare
instructions where no condition register is specified explicitly
(and CR0 is assumed implicitly).
This patch adds support for those extended compare mnemonics.
Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
===================================================================
--- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s
+++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
@@ -449,21 +449,37 @@
# CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80]
cmpdi 2, 3, 128
+# CHECK: cmpdi 0, 3, 128 # encoding: [0x2c,0x23,0x00,0x80]
+ cmpdi 3, 128
# CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00]
cmpd 2, 3, 4
+# CHECK: cmpd 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x00]
+ cmpd 3, 4
# CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80]
cmpldi 2, 3, 128
+# CHECK: cmpldi 0, 3, 128 # encoding: [0x28,0x23,0x00,0x80]
+ cmpldi 3, 128
# CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40]
cmpld 2, 3, 4
+# CHECK: cmpld 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x40]
+ cmpld 3, 4
# CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80]
cmpwi 2, 3, 128
+# CHECK: cmpwi 0, 3, 128 # encoding: [0x2c,0x03,0x00,0x80]
+ cmpwi 3, 128
# CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00]
cmpw 2, 3, 4
+# CHECK: cmpw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x00]
+ cmpw 3, 4
# CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80]
cmplwi 2, 3, 128
+# CHECK: cmplwi 0, 3, 128 # encoding: [0x28,0x03,0x00,0x80]
+ cmplwi 3, 128
# CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40]
cmplw 2, 3, 4
+# CHECK: cmplw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x40]
+ cmplw 3, 4
# FIXME: Trap mnemonics
Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>;
defm : BranchExtendedMnemonic<"nu", 100>;
defm : BranchExtendedMnemonic<"ns", 100>;
+def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
+
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184435 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-20 16:15:12 +00:00
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def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
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2013-07-08 14:49:37 +00:00
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def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
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def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
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def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
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def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
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2014-01-02 21:26:59 +00:00
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def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
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2013-07-08 14:49:37 +00:00
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def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
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2014-01-02 21:26:59 +00:00
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def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
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2013-07-08 14:49:37 +00:00
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def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
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2013-07-04 14:40:12 +00:00
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multiclass TrapExtendedMnemonic<string name, int to> {
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def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
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def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
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def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
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def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
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}
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defm : TrapExtendedMnemonic<"lt", 16>;
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defm : TrapExtendedMnemonic<"le", 20>;
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defm : TrapExtendedMnemonic<"eq", 4>;
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defm : TrapExtendedMnemonic<"ge", 12>;
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defm : TrapExtendedMnemonic<"gt", 8>;
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defm : TrapExtendedMnemonic<"nl", 12>;
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defm : TrapExtendedMnemonic<"ne", 24>;
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defm : TrapExtendedMnemonic<"ng", 20>;
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defm : TrapExtendedMnemonic<"llt", 2>;
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defm : TrapExtendedMnemonic<"lle", 6>;
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defm : TrapExtendedMnemonic<"lge", 5>;
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defm : TrapExtendedMnemonic<"lgt", 1>;
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defm : TrapExtendedMnemonic<"lnl", 5>;
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defm : TrapExtendedMnemonic<"lng", 6>;
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defm : TrapExtendedMnemonic<"u", 31>;
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