2011-09-24 01:40:18 +00:00
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//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes Mips64 instructions.
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//
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//===----------------------------------------------------------------------===//
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2011-09-28 17:50:27 +00:00
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2011-09-30 02:08:54 +00:00
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//===----------------------------------------------------------------------===//
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// Mips Operand, Complex Patterns and Transformations Definitions.
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//===----------------------------------------------------------------------===//
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// Unsigned Operand
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2015-01-20 16:10:51 +00:00
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def uimm5_64 : Operand<i64> {
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let PrintMethod = "printUnsignedImm";
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}
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2011-09-30 02:08:54 +00:00
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def uimm16_64 : Operand<i64> {
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let PrintMethod = "printUnsignedImm";
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}
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2014-04-04 16:21:59 +00:00
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// Signed Operand
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def simm10_64 : Operand<i64>;
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2014-06-19 15:08:04 +00:00
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def imm64: Operand<i64>;
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2011-09-30 03:18:46 +00:00
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// Transformation Function - get Imm - 32.
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def Subtract32 : SDNodeXForm<imm, [{
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2011-12-07 20:10:24 +00:00
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return getImm(N, (unsigned)N->getZExtValue() - 32);
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2011-09-30 03:18:46 +00:00
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}]>;
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2011-12-19 19:44:09 +00:00
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// shamt must fit in 6 bits.
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def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
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2011-09-30 03:18:46 +00:00
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2014-04-04 16:21:59 +00:00
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// Node immediate fits as 10-bit sign extended on target immediate.
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// e.g. seqi, snei
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def immSExt10_64 : PatLeaf<(i64 imm),
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[{ return isInt<10>(N->getSExtValue()); }]>;
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2014-06-12 13:39:06 +00:00
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def immZExt16_64 : PatLeaf<(i64 imm),
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[{ return isInt<16>(N->getZExtValue()); }]>;
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2015-01-20 16:10:51 +00:00
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def immZExt5_64 : ImmLeaf<i64, [{ return Imm == (Imm & 0x1f); }]>;
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// Transformation function: get log2 of low 32 bits of immediate
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def Log2LO : SDNodeXForm<imm, [{
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return getImm(N, Log2_64((unsigned) N->getZExtValue()));
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}]>;
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// Transformation function: get log2 of high 32 bits of immediate
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def Log2HI : SDNodeXForm<imm, [{
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return getImm(N, Log2_64((unsigned) (N->getZExtValue() >> 32)));
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}]>;
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// Predicate: True if immediate is a power of 2 and fits 32 bits
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def PowerOf2LO : PatLeaf<(imm), [{
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if (N->getValueType(0) == MVT::i64) {
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uint64_t Imm = N->getZExtValue();
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return isPowerOf2_64(Imm) && (Imm & 0xffffffff) == Imm;
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}
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else
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return false;
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}]>;
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// Predicate: True if immediate is a power of 2 and exceeds 32 bits
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def PowerOf2HI : PatLeaf<(imm), [{
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if (N->getValueType(0) == MVT::i64) {
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uint64_t Imm = N->getZExtValue();
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return isPowerOf2_64(Imm) && (Imm & 0xffffffff00000000) == Imm;
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}
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else
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return false;
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}]>;
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2011-09-29 20:37:56 +00:00
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//===----------------------------------------------------------------------===//
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// Instructions specific format
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//===----------------------------------------------------------------------===//
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2013-08-20 21:08:22 +00:00
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let usesCustomInserter = 1 in {
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def ATOMIC_LOAD_ADD_I64 : Atomic2Ops<atomic_load_add_64, GPR64>;
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def ATOMIC_LOAD_SUB_I64 : Atomic2Ops<atomic_load_sub_64, GPR64>;
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def ATOMIC_LOAD_AND_I64 : Atomic2Ops<atomic_load_and_64, GPR64>;
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def ATOMIC_LOAD_OR_I64 : Atomic2Ops<atomic_load_or_64, GPR64>;
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def ATOMIC_LOAD_XOR_I64 : Atomic2Ops<atomic_load_xor_64, GPR64>;
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def ATOMIC_LOAD_NAND_I64 : Atomic2Ops<atomic_load_nand_64, GPR64>;
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def ATOMIC_SWAP_I64 : Atomic2Ops<atomic_swap_64, GPR64>;
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def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<atomic_cmp_swap_64, GPR64>;
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2011-11-11 04:14:30 +00:00
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}
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2013-04-30 23:22:09 +00:00
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/// Pseudo instructions for loading and storing accumulator registers.
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2013-08-01 23:14:16 +00:00
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let isPseudo = 1, isCodeGenOnly = 1 in {
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2013-08-20 21:08:22 +00:00
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def LOAD_ACC128 : Load<"", ACC128>;
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def STORE_ACC128 : Store<"", ACC128>;
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2013-03-30 00:54:52 +00:00
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}
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2011-09-29 20:37:56 +00:00
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//===----------------------------------------------------------------------===//
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// Instruction definition
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//===----------------------------------------------------------------------===//
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2012-04-17 18:03:21 +00:00
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let DecoderNamespace = "Mips64" in {
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2011-09-30 02:08:54 +00:00
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/// Arithmetic Instructions (ALU Immediate)
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2014-05-09 13:02:27 +00:00
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def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd>, ADDI_FM<0x18>,
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2014-06-13 12:49:06 +00:00
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ISA_MIPS3_NOT_32R6_64R6;
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[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199391 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 14:27:20 +00:00
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def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU,
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2013-07-31 00:55:34 +00:00
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immSExt16, add>,
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2014-05-09 13:02:27 +00:00
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ADDI_FM<0x19>, IsAsCheapAsAMove, ISA_MIPS3;
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2013-08-06 23:01:10 +00:00
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let isCodeGenOnly = 1 in {
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2013-08-06 23:08:38 +00:00
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def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>,
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2012-12-20 04:27:52 +00:00
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SLTI_FM<0xa>;
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2013-08-06 23:08:38 +00:00
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def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>,
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2012-12-20 04:27:52 +00:00
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SLTI_FM<0xb>;
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2014-01-16 15:57:05 +00:00
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def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, II_AND, immZExt16, and>,
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2013-07-31 00:57:41 +00:00
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ADDI_FM<0xc>;
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2014-01-16 15:57:05 +00:00
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def ORi64 : ArithLogicI<"ori", uimm16_64, GPR64Opnd, II_OR, immZExt16, or>,
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2012-12-20 03:40:03 +00:00
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ADDI_FM<0xd>;
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2014-01-16 15:57:05 +00:00
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def XORi64 : ArithLogicI<"xori", uimm16_64, GPR64Opnd, II_XOR, immZExt16, xor>,
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2012-12-20 03:40:03 +00:00
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ADDI_FM<0xe>;
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2013-08-06 23:08:38 +00:00
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def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64>, LUI_FM;
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2013-08-06 23:01:10 +00:00
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}
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2011-09-30 02:08:54 +00:00
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2011-09-29 20:37:56 +00:00
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/// Arithmetic Instructions (3-Operand, R-Type)
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2014-05-09 13:02:27 +00:00
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def DADD : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, ADD_FM<0, 0x2c>,
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ISA_MIPS3;
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def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>, ADD_FM<0, 0x2d>,
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ISA_MIPS3;
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def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, ADD_FM<0, 0x2f>,
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ISA_MIPS3;
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def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>,
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ISA_MIPS3;
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2013-08-06 22:35:29 +00:00
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let isCodeGenOnly = 1 in {
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2013-08-06 23:08:38 +00:00
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def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
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def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>;
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[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199391 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 14:27:20 +00:00
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def AND64 : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>;
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def OR64 : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>;
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def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>;
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2013-08-06 23:08:38 +00:00
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def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>;
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2013-08-06 22:35:29 +00:00
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}
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2011-09-30 03:18:46 +00:00
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/// Shift Instructions
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[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199391 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 14:27:20 +00:00
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def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, shl, immZExt6>,
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2014-05-09 13:02:27 +00:00
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SRA_FM<0x38, 0>, ISA_MIPS3;
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[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199391 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 14:27:20 +00:00
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def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl, immZExt6>,
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2014-05-09 13:02:27 +00:00
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SRA_FM<0x3a, 0>, ISA_MIPS3;
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[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199391 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 14:27:20 +00:00
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def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, sra, immZExt6>,
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2014-05-09 13:02:27 +00:00
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SRA_FM<0x3b, 0>, ISA_MIPS3;
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[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199391 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 14:27:20 +00:00
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def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
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2014-05-09 13:02:27 +00:00
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SRLV_FM<0x14, 0>, ISA_MIPS3;
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[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199391 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 14:27:20 +00:00
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|
def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
|
2014-05-09 13:02:27 +00:00
|
|
|
SRLV_FM<0x16, 0>, ISA_MIPS3;
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199391 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 14:27:20 +00:00
|
|
|
def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
|
2014-05-09 13:02:27 +00:00
|
|
|
SRLV_FM<0x17, 0>, ISA_MIPS3;
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199391 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 14:27:20 +00:00
|
|
|
def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>,
|
2014-05-09 13:02:27 +00:00
|
|
|
SRA_FM<0x3c, 0>, ISA_MIPS3;
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199391 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 14:27:20 +00:00
|
|
|
def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>,
|
2014-05-09 13:02:27 +00:00
|
|
|
SRA_FM<0x3e, 0>, ISA_MIPS3;
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199391 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 14:27:20 +00:00
|
|
|
def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
|
2014-05-09 13:02:27 +00:00
|
|
|
SRA_FM<0x3f, 0>, ISA_MIPS3;
|
2013-08-06 23:01:10 +00:00
|
|
|
|
2011-09-30 18:51:46 +00:00
|
|
|
// Rotate Instructions
|
2014-05-07 13:57:22 +00:00
|
|
|
def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
|
|
|
|
|
immZExt6>,
|
|
|
|
|
SRA_FM<0x3a, 1>, ISA_MIPS64R2;
|
|
|
|
|
def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>,
|
|
|
|
|
SRLV_FM<0x16, 1>, ISA_MIPS64R2;
|
|
|
|
|
def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>,
|
|
|
|
|
SRA_FM<0x3e, 1>, ISA_MIPS64R2;
|
2011-09-30 18:51:46 +00:00
|
|
|
|
2011-10-11 00:27:28 +00:00
|
|
|
/// Load and Store Instructions
|
2012-02-28 07:46:26 +00:00
|
|
|
/// aligned
|
2013-08-06 23:01:10 +00:00
|
|
|
let isCodeGenOnly = 1 in {
|
2014-01-21 15:21:14 +00:00
|
|
|
def LB64 : Load<"lb", GPR64Opnd, sextloadi8, II_LB>, LW_FM<0x20>;
|
|
|
|
|
def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, II_LBU>, LW_FM<0x24>;
|
|
|
|
|
def LH64 : Load<"lh", GPR64Opnd, sextloadi16, II_LH>, LW_FM<0x21>;
|
|
|
|
|
def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, II_LHU>, LW_FM<0x25>;
|
|
|
|
|
def LW64 : Load<"lw", GPR64Opnd, sextloadi32, II_LW>, LW_FM<0x23>;
|
2014-01-23 10:31:31 +00:00
|
|
|
def SB64 : Store<"sb", GPR64Opnd, truncstorei8, II_SB>, LW_FM<0x28>;
|
|
|
|
|
def SH64 : Store<"sh", GPR64Opnd, truncstorei16, II_SH>, LW_FM<0x29>;
|
|
|
|
|
def SW64 : Store<"sw", GPR64Opnd, truncstorei32, II_SW>, LW_FM<0x2b>;
|
2013-08-06 23:01:10 +00:00
|
|
|
}
|
|
|
|
|
|
2014-05-09 13:02:27 +00:00
|
|
|
def LWu : Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>, LW_FM<0x27>, ISA_MIPS3;
|
|
|
|
|
def LD : Load<"ld", GPR64Opnd, load, II_LD>, LW_FM<0x37>, ISA_MIPS3;
|
|
|
|
|
def SD : Store<"sd", GPR64Opnd, store, II_SD>, LW_FM<0x3f>, ISA_MIPS3;
|
2011-10-11 00:27:28 +00:00
|
|
|
|
2012-06-02 00:04:19 +00:00
|
|
|
/// load/store left/right
|
2013-08-06 23:01:10 +00:00
|
|
|
let isCodeGenOnly = 1 in {
|
2014-01-21 15:21:14 +00:00
|
|
|
def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, II_LWL>, LW_FM<0x22>;
|
|
|
|
|
def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, II_LWR>, LW_FM<0x26>;
|
2014-01-23 10:31:31 +00:00
|
|
|
def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, II_SWL>, LW_FM<0x2a>;
|
|
|
|
|
def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, II_SWR>, LW_FM<0x2e>;
|
2013-08-06 23:01:10 +00:00
|
|
|
}
|
2013-01-12 01:03:14 +00:00
|
|
|
|
2014-05-09 13:02:27 +00:00
|
|
|
def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, II_LDL>, LW_FM<0x1a>,
|
2014-05-23 13:18:02 +00:00
|
|
|
ISA_MIPS3_NOT_32R6_64R6;
|
2014-05-09 13:02:27 +00:00
|
|
|
def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, II_LDR>, LW_FM<0x1b>,
|
2014-05-23 13:18:02 +00:00
|
|
|
ISA_MIPS3_NOT_32R6_64R6;
|
2014-05-09 13:02:27 +00:00
|
|
|
def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, II_SDL>, LW_FM<0x2c>,
|
2014-05-23 13:18:02 +00:00
|
|
|
ISA_MIPS3_NOT_32R6_64R6;
|
2014-05-09 13:02:27 +00:00
|
|
|
def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, II_SDR>, LW_FM<0x2d>,
|
2014-05-23 13:18:02 +00:00
|
|
|
ISA_MIPS3_NOT_32R6_64R6;
|
2012-06-02 00:04:19 +00:00
|
|
|
|
2011-11-11 04:14:30 +00:00
|
|
|
/// Load-linked, Store-conditional
|
2014-06-16 13:13:03 +00:00
|
|
|
def LLD : LLBase<"lld", GPR64Opnd>, LW_FM<0x34>, ISA_MIPS3_NOT_32R6_64R6;
|
|
|
|
|
def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3_NOT_32R6_64R6;
|
2011-11-11 04:14:30 +00:00
|
|
|
|
2011-10-11 18:49:17 +00:00
|
|
|
/// Jump and Branch Instructions
|
2013-08-06 23:01:10 +00:00
|
|
|
let isCodeGenOnly = 1 in {
|
2014-07-09 10:21:59 +00:00
|
|
|
def JR64 : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>;
|
|
|
|
|
def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>;
|
|
|
|
|
def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>;
|
|
|
|
|
def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>;
|
|
|
|
|
def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>;
|
|
|
|
|
def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>;
|
|
|
|
|
def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>;
|
|
|
|
|
def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM;
|
|
|
|
|
def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>;
|
|
|
|
|
def TAILCALL64_R : TailCallReg<GPR64Opnd, JR, GPR32Opnd>;
|
2013-08-06 23:01:10 +00:00
|
|
|
}
|
2012-01-04 03:02:47 +00:00
|
|
|
|
[mips][mips64r6] Use JALR for returns instead of JR (which is not available on MIPS32r6/MIPS64r6)
Summary:
RET, and RET_MM have been replaced by a pseudo named PseudoReturn.
In addition a version with a 64-bit GPR named PseudoReturn64 has been
added.
Instruction selection for a return matches RetRA, which is expanded post
register allocation to PseudoReturn/PseudoReturn64. During MipsAsmPrinter,
this PseudoReturn/PseudoReturn64 are emitted as:
- (JALR64 $zero, $rs) on MIPS64r6
- (JALR $zero, $rs) on MIPS32r6
- (JR_MM $rs) on microMIPS
- (JR $rs) otherwise
On MIPS32r6/MIPS64r6, 'jr $rs' is an alias for 'jalr $zero, $rs'. To aid
development and review (specifically, to ensure all cases of jr are
updated), these aliases are temporarily named 'r6.jr' instead of 'jr'.
A follow up patch will change them back to the correct mnemonic.
Added (JALR $zero, $rs) to MipsNaClELFStreamer's definition of an indirect
jump, and removed it from its definition of a call.
Note: I haven't accounted for MIPS64 in MipsNaClELFStreamer since it's
doesn't appear to account for any MIPS64-specifics.
The return instruction created as part of eh_return expansion is now expanded
using expandRetRA() so we use the right return instruction on MIPS32r6/MIPS64r6
('jalr $zero, $rs').
Also, fixed a misuse of isABI_N64() to detect 64-bit wide registers in
expandEhReturn().
Reviewers: jkolek, vmedic, mseaborn, zoran.jovanovic, dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D4268
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212604 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-09 10:16:07 +00:00
|
|
|
def PseudoReturn64 : PseudoReturnBase<GPR64Opnd>;
|
2014-07-09 10:21:59 +00:00
|
|
|
def PseudoIndirectBranch64 : PseudoIndirectBranchBase<GPR64Opnd>;
|
[mips][mips64r6] Use JALR for returns instead of JR (which is not available on MIPS32r6/MIPS64r6)
Summary:
RET, and RET_MM have been replaced by a pseudo named PseudoReturn.
In addition a version with a 64-bit GPR named PseudoReturn64 has been
added.
Instruction selection for a return matches RetRA, which is expanded post
register allocation to PseudoReturn/PseudoReturn64. During MipsAsmPrinter,
this PseudoReturn/PseudoReturn64 are emitted as:
- (JALR64 $zero, $rs) on MIPS64r6
- (JALR $zero, $rs) on MIPS32r6
- (JR_MM $rs) on microMIPS
- (JR $rs) otherwise
On MIPS32r6/MIPS64r6, 'jr $rs' is an alias for 'jalr $zero, $rs'. To aid
development and review (specifically, to ensure all cases of jr are
updated), these aliases are temporarily named 'r6.jr' instead of 'jr'.
A follow up patch will change them back to the correct mnemonic.
Added (JALR $zero, $rs) to MipsNaClELFStreamer's definition of an indirect
jump, and removed it from its definition of a call.
Note: I haven't accounted for MIPS64 in MipsNaClELFStreamer since it's
doesn't appear to account for any MIPS64-specifics.
The return instruction created as part of eh_return expansion is now expanded
using expandRetRA() so we use the right return instruction on MIPS32r6/MIPS64r6
('jalr $zero, $rs').
Also, fixed a misuse of isABI_N64() to detect 64-bit wide registers in
expandEhReturn().
Reviewers: jkolek, vmedic, mseaborn, zoran.jovanovic, dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D4268
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212604 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-09 10:16:07 +00:00
|
|
|
|
2011-10-03 20:01:11 +00:00
|
|
|
/// Multiply and Divide Instructions.
|
2014-01-17 14:32:41 +00:00
|
|
|
def DMULT : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>,
|
[mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64.
Summary:
The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have
been removed and replaced with GPR-based equivalents. For example:
div $1, $2
mflo $3
is now:
div $3, $1, $2
This patch disables the accumulator-based multiplies and divides for
MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead.
Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the
behaviour of the function.
MipsDelaySlotFiller now invalidates the liveness information when moving
instructions to the delay slot. Without this, divrem.ll will abort since
%GP ends up used before it is defined.
Reviewers: vmedic, zoran.jovanovic, jkolek
Reviewed By: jkolek
Differential Revision: http://reviews.llvm.org/D3896
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210760 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-12 10:44:10 +00:00
|
|
|
MULT_FM<0, 0x1c>, ISA_MIPS3_NOT_32R6_64R6;
|
2014-01-17 14:32:41 +00:00
|
|
|
def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>,
|
[mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64.
Summary:
The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have
been removed and replaced with GPR-based equivalents. For example:
div $1, $2
mflo $3
is now:
div $3, $1, $2
This patch disables the accumulator-based multiplies and divides for
MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead.
Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the
behaviour of the function.
MipsDelaySlotFiller now invalidates the liveness information when moving
instructions to the delay slot. Without this, divrem.ll will abort since
%GP ends up used before it is defined.
Reviewers: vmedic, zoran.jovanovic, jkolek
Reviewed By: jkolek
Differential Revision: http://reviews.llvm.org/D3896
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210760 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-12 10:44:10 +00:00
|
|
|
MULT_FM<0, 0x1d>, ISA_MIPS3_NOT_32R6_64R6;
|
2013-08-08 21:54:26 +00:00
|
|
|
def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult,
|
[mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64.
Summary:
The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have
been removed and replaced with GPR-based equivalents. For example:
div $1, $2
mflo $3
is now:
div $3, $1, $2
This patch disables the accumulator-based multiplies and divides for
MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead.
Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the
behaviour of the function.
MipsDelaySlotFiller now invalidates the liveness information when moving
instructions to the delay slot. Without this, divrem.ll will abort since
%GP ends up used before it is defined.
Reviewers: vmedic, zoran.jovanovic, jkolek
Reviewed By: jkolek
Differential Revision: http://reviews.llvm.org/D3896
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210760 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-12 10:44:10 +00:00
|
|
|
II_DMULT>, ISA_MIPS3_NOT_32R6_64R6;
|
2013-08-08 21:54:26 +00:00
|
|
|
def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu,
|
[mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64.
Summary:
The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have
been removed and replaced with GPR-based equivalents. For example:
div $1, $2
mflo $3
is now:
div $3, $1, $2
This patch disables the accumulator-based multiplies and divides for
MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead.
Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the
behaviour of the function.
MipsDelaySlotFiller now invalidates the liveness information when moving
instructions to the delay slot. Without this, divrem.ll will abort since
%GP ends up used before it is defined.
Reviewers: vmedic, zoran.jovanovic, jkolek
Reviewed By: jkolek
Differential Revision: http://reviews.llvm.org/D3896
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210760 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-12 10:44:10 +00:00
|
|
|
II_DMULTU>, ISA_MIPS3_NOT_32R6_64R6;
|
2014-01-17 14:48:06 +00:00
|
|
|
def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>,
|
[mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64.
Summary:
The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have
been removed and replaced with GPR-based equivalents. For example:
div $1, $2
mflo $3
is now:
div $3, $1, $2
This patch disables the accumulator-based multiplies and divides for
MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead.
Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the
behaviour of the function.
MipsDelaySlotFiller now invalidates the liveness information when moving
instructions to the delay slot. Without this, divrem.ll will abort since
%GP ends up used before it is defined.
Reviewers: vmedic, zoran.jovanovic, jkolek
Reviewed By: jkolek
Differential Revision: http://reviews.llvm.org/D3896
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210760 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-12 10:44:10 +00:00
|
|
|
MULT_FM<0, 0x1e>, ISA_MIPS3_NOT_32R6_64R6;
|
2014-01-17 14:48:06 +00:00
|
|
|
def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>,
|
[mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64.
Summary:
The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have
been removed and replaced with GPR-based equivalents. For example:
div $1, $2
mflo $3
is now:
div $3, $1, $2
This patch disables the accumulator-based multiplies and divides for
MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead.
Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the
behaviour of the function.
MipsDelaySlotFiller now invalidates the liveness information when moving
instructions to the delay slot. Without this, divrem.ll will abort since
%GP ends up used before it is defined.
Reviewers: vmedic, zoran.jovanovic, jkolek
Reviewed By: jkolek
Differential Revision: http://reviews.llvm.org/D3896
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210760 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-12 10:44:10 +00:00
|
|
|
MULT_FM<0, 0x1f>, ISA_MIPS3_NOT_32R6_64R6;
|
2013-08-08 21:54:26 +00:00
|
|
|
def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem,
|
[mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64.
Summary:
The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have
been removed and replaced with GPR-based equivalents. For example:
div $1, $2
mflo $3
is now:
div $3, $1, $2
This patch disables the accumulator-based multiplies and divides for
MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead.
Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the
behaviour of the function.
MipsDelaySlotFiller now invalidates the liveness information when moving
instructions to the delay slot. Without this, divrem.ll will abort since
%GP ends up used before it is defined.
Reviewers: vmedic, zoran.jovanovic, jkolek
Reviewed By: jkolek
Differential Revision: http://reviews.llvm.org/D3896
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210760 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-12 10:44:10 +00:00
|
|
|
II_DDIV, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6;
|
2013-08-08 21:54:26 +00:00
|
|
|
def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU,
|
[mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64.
Summary:
The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have
been removed and replaced with GPR-based equivalents. For example:
div $1, $2
mflo $3
is now:
div $3, $1, $2
This patch disables the accumulator-based multiplies and divides for
MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead.
Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the
behaviour of the function.
MipsDelaySlotFiller now invalidates the liveness information when moving
instructions to the delay slot. Without this, divrem.ll will abort since
%GP ends up used before it is defined.
Reviewers: vmedic, zoran.jovanovic, jkolek
Reviewed By: jkolek
Differential Revision: http://reviews.llvm.org/D3896
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210760 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-12 10:44:10 +00:00
|
|
|
II_DDIVU, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6;
|
2011-10-03 20:01:11 +00:00
|
|
|
|
2013-08-06 23:01:10 +00:00
|
|
|
let isCodeGenOnly = 1 in {
|
[mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64.
Summary:
The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have
been removed and replaced with GPR-based equivalents. For example:
div $1, $2
mflo $3
is now:
div $3, $1, $2
This patch disables the accumulator-based multiplies and divides for
MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead.
Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the
behaviour of the function.
MipsDelaySlotFiller now invalidates the liveness information when moving
instructions to the delay slot. Without this, divrem.ll will abort since
%GP ends up used before it is defined.
Reviewers: vmedic, zoran.jovanovic, jkolek
Reviewed By: jkolek
Differential Revision: http://reviews.llvm.org/D3896
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210760 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-12 10:44:10 +00:00
|
|
|
def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI0_64]>, MTLO_FM<0x11>,
|
|
|
|
|
ISA_MIPS3_NOT_32R6_64R6;
|
|
|
|
|
def MTLO64 : MoveToLOHI<"mtlo", GPR64Opnd, [LO0_64]>, MTLO_FM<0x13>,
|
|
|
|
|
ISA_MIPS3_NOT_32R6_64R6;
|
|
|
|
|
def MFHI64 : MoveFromLOHI<"mfhi", GPR64Opnd, AC0_64>, MFLO_FM<0x10>,
|
|
|
|
|
ISA_MIPS3_NOT_32R6_64R6;
|
|
|
|
|
def MFLO64 : MoveFromLOHI<"mflo", GPR64Opnd, AC0_64>, MFLO_FM<0x12>,
|
|
|
|
|
ISA_MIPS3_NOT_32R6_64R6;
|
|
|
|
|
def PseudoMFHI64 : PseudoMFLOHI<GPR64, ACC128, MipsMFHI>,
|
|
|
|
|
ISA_MIPS3_NOT_32R6_64R6;
|
|
|
|
|
def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>,
|
|
|
|
|
ISA_MIPS3_NOT_32R6_64R6;
|
|
|
|
|
def PseudoMTLOHI64 : PseudoMTLOHI<ACC128, GPR64>, ISA_MIPS3_NOT_32R6_64R6;
|
2011-10-03 19:28:44 +00:00
|
|
|
|
2012-01-24 21:41:09 +00:00
|
|
|
/// Sign Ext In Register Instructions.
|
2014-05-12 12:28:15 +00:00
|
|
|
def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>,
|
|
|
|
|
ISA_MIPS32R2;
|
|
|
|
|
def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>,
|
|
|
|
|
ISA_MIPS32R2;
|
2013-08-06 23:01:10 +00:00
|
|
|
}
|
2012-01-24 21:41:09 +00:00
|
|
|
|
2011-10-03 21:16:50 +00:00
|
|
|
/// Count Leading
|
2014-06-16 13:18:59 +00:00
|
|
|
def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>, ISA_MIPS64_NOT_64R6;
|
|
|
|
|
def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>, ISA_MIPS64_NOT_64R6;
|
2011-10-03 21:16:50 +00:00
|
|
|
|
2011-12-20 23:56:43 +00:00
|
|
|
/// Double Word Swap Bytes/HalfWords
|
2014-05-12 12:15:41 +00:00
|
|
|
def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>, ISA_MIPS64R2;
|
|
|
|
|
def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>, ISA_MIPS64R2;
|
2012-12-21 23:21:32 +00:00
|
|
|
|
2013-08-20 21:08:22 +00:00
|
|
|
def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>;
|
2011-12-20 23:56:43 +00:00
|
|
|
|
2013-08-06 23:01:10 +00:00
|
|
|
let isCodeGenOnly = 1 in
|
2013-08-08 21:37:32 +00:00
|
|
|
def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM;
|
2011-12-07 23:31:26 +00:00
|
|
|
|
2013-09-07 00:02:02 +00:00
|
|
|
def DEXT : ExtBase<"dext", GPR64Opnd, uimm6, MipsExt>, EXT_FM<3>;
|
|
|
|
|
def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm6>, EXT_FM<2>;
|
|
|
|
|
def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5>, EXT_FM<1>;
|
|
|
|
|
|
|
|
|
|
def DINS : InsBase<"dins", GPR64Opnd, uimm6, MipsIns>, EXT_FM<7>;
|
|
|
|
|
def DINSU : InsBase<"dinsu", GPR64Opnd, uimm6>, EXT_FM<6>;
|
|
|
|
|
def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5>, EXT_FM<5>;
|
2011-12-05 21:26:34 +00:00
|
|
|
|
2012-08-07 00:35:22 +00:00
|
|
|
let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
|
2013-08-06 23:08:38 +00:00
|
|
|
def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt),
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199391 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 14:27:20 +00:00
|
|
|
"dsll\t$rd, $rt, 32", [], II_DSLL>;
|
2013-08-06 23:08:38 +00:00
|
|
|
def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt),
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199391 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 14:27:20 +00:00
|
|
|
"sll\t$rd, $rt, 0", [], II_SLL>;
|
2013-08-06 23:08:38 +00:00
|
|
|
def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt),
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199391 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 14:27:20 +00:00
|
|
|
"sll\t$rd, $rt, 0", [], II_SLL>;
|
2012-08-07 00:35:22 +00:00
|
|
|
}
|
2014-03-20 11:51:58 +00:00
|
|
|
|
2014-05-27 18:53:06 +00:00
|
|
|
// We need the following pseudo instruction to avoid offset calculation for
|
2014-04-30 15:06:25 +00:00
|
|
|
// long branches. See the comment in file MipsLongBranch.cpp for detailed
|
|
|
|
|
// explanation.
|
|
|
|
|
|
|
|
|
|
// Expands to: daddiu $dst, $src, %PART($tgt - $baltgt)
|
2014-05-27 18:53:06 +00:00
|
|
|
// where %PART may be %hi or %lo, depending on the relocation kind
|
2014-04-30 15:06:25 +00:00
|
|
|
// that $tgt is annotated with.
|
|
|
|
|
def LONG_BRANCH_DADDiu : PseudoSE<(outs GPR64Opnd:$dst),
|
|
|
|
|
(ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
|
|
|
|
|
|
2014-03-20 11:51:58 +00:00
|
|
|
// Cavium Octeon cmMIPS instructions
|
2014-05-07 10:27:09 +00:00
|
|
|
let EncodingPredicates = []<Predicate>, // FIXME: The lack of HasStdEnc is probably a bug
|
|
|
|
|
AdditionalPredicates = [HasCnMips] in {
|
2014-03-20 11:51:58 +00:00
|
|
|
|
|
|
|
|
class Count1s<string opstr, RegisterOperand RO>:
|
|
|
|
|
InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
|
2014-04-02 18:40:43 +00:00
|
|
|
[(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> {
|
|
|
|
|
let TwoOperandAliasConstraint = "$rd = $rs";
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
class ExtsCins<string opstr, SDPatternOperator Op = null_frag>:
|
|
|
|
|
InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, uimm5:$pos, uimm5:$lenm1),
|
|
|
|
|
!strconcat(opstr, " $rt, $rs, $pos, $lenm1"),
|
|
|
|
|
[(set GPR64Opnd:$rt, (Op GPR64Opnd:$rs, imm:$pos, imm:$lenm1))],
|
|
|
|
|
NoItinerary, FrmR, opstr> {
|
|
|
|
|
let TwoOperandAliasConstraint = "$rt = $rs";
|
|
|
|
|
}
|
2014-03-20 11:51:58 +00:00
|
|
|
|
|
|
|
|
class SetCC64_R<string opstr, PatFrag cond_op> :
|
|
|
|
|
InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),
|
|
|
|
|
!strconcat(opstr, "\t$rd, $rs, $rt"),
|
2015-01-14 10:19:09 +00:00
|
|
|
[(set GPR64Opnd:$rd, (zext (cond_op GPR64Opnd:$rs,
|
|
|
|
|
GPR64Opnd:$rt)))],
|
2014-04-02 18:40:43 +00:00
|
|
|
II_SEQ_SNE, FrmR, opstr> {
|
|
|
|
|
let TwoOperandAliasConstraint = "$rd = $rs";
|
|
|
|
|
}
|
2014-03-20 11:51:58 +00:00
|
|
|
|
2014-04-04 16:21:59 +00:00
|
|
|
class SetCC64_I<string opstr, PatFrag cond_op>:
|
|
|
|
|
InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, simm10_64:$imm10),
|
|
|
|
|
!strconcat(opstr, "\t$rt, $rs, $imm10"),
|
2015-01-14 10:19:09 +00:00
|
|
|
[(set GPR64Opnd:$rt, (zext (cond_op GPR64Opnd:$rs,
|
|
|
|
|
immSExt10_64:$imm10)))],
|
2014-04-04 16:21:59 +00:00
|
|
|
II_SEQI_SNEI, FrmI, opstr> {
|
|
|
|
|
let TwoOperandAliasConstraint = "$rt = $rs";
|
|
|
|
|
}
|
|
|
|
|
|
2015-01-20 16:10:51 +00:00
|
|
|
class CBranchBitNum<string opstr, DAGOperand opnd, PatFrag cond_op,
|
|
|
|
|
RegisterOperand RO, bits<64> shift = 1> :
|
|
|
|
|
InstSE<(outs), (ins RO:$rs, uimm5_64:$p, opnd:$offset),
|
|
|
|
|
!strconcat(opstr, "\t$rs, $p, $offset"),
|
|
|
|
|
[(brcond (i32 (cond_op (and RO:$rs, (shl shift, immZExt5_64:$p)), 0)),
|
|
|
|
|
bb:$offset)], IIBranch, FrmI, opstr> {
|
|
|
|
|
let isBranch = 1;
|
|
|
|
|
let isTerminator = 1;
|
|
|
|
|
let hasDelaySlot = 1;
|
|
|
|
|
let Defs = [AT];
|
|
|
|
|
}
|
|
|
|
|
|
2014-03-20 11:51:58 +00:00
|
|
|
// Unsigned Byte Add
|
2014-04-02 18:40:43 +00:00
|
|
|
let Pattern = [(set GPR64Opnd:$rd,
|
|
|
|
|
(and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))] in
|
|
|
|
|
def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>,
|
|
|
|
|
ADD_FM<0x1c, 0x28>;
|
2014-03-20 11:51:58 +00:00
|
|
|
|
2015-01-20 16:10:51 +00:00
|
|
|
// Branch on Bit Clear /+32
|
|
|
|
|
def BBIT0 : CBranchBitNum<"bbit0", brtarget, seteq, GPR64Opnd>, BBIT_FM<0x32>;
|
|
|
|
|
def BBIT032: CBranchBitNum<"bbit032", brtarget, seteq, GPR64Opnd, 0x100000000>,
|
|
|
|
|
BBIT_FM<0x36>;
|
|
|
|
|
|
|
|
|
|
// Branch on Bit Set /+32
|
|
|
|
|
def BBIT1 : CBranchBitNum<"bbit1", brtarget, setne, GPR64Opnd>, BBIT_FM<0x3a>;
|
|
|
|
|
def BBIT132: CBranchBitNum<"bbit132", brtarget, setne, GPR64Opnd, 0x100000000>,
|
|
|
|
|
BBIT_FM<0x3e>;
|
|
|
|
|
|
2014-03-20 11:51:58 +00:00
|
|
|
// Multiply Doubleword to GPR
|
|
|
|
|
let Defs = [HI0, LO0, P0, P1, P2] in
|
|
|
|
|
def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>,
|
|
|
|
|
ADD_FM<0x1c, 0x03>;
|
|
|
|
|
|
2014-04-02 18:40:43 +00:00
|
|
|
// Extract a signed bit field /+32
|
|
|
|
|
def EXTS : ExtsCins<"exts">, EXTS_FM<0x3a>;
|
|
|
|
|
def EXTS32: ExtsCins<"exts32">, EXTS_FM<0x3b>;
|
|
|
|
|
|
|
|
|
|
// Clear and insert a bit field /+32
|
|
|
|
|
def CINS : ExtsCins<"cins">, EXTS_FM<0x32>;
|
|
|
|
|
def CINS32: ExtsCins<"cins32">, EXTS_FM<0x33>;
|
|
|
|
|
|
2014-04-01 18:35:26 +00:00
|
|
|
// Move to multiplier/product register
|
|
|
|
|
def MTM0 : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>;
|
|
|
|
|
def MTM1 : MoveToLOHI<"mtm1", GPR64Opnd, [MPL1, P0, P1, P2]>, MTMR_FM<0x0c>;
|
|
|
|
|
def MTM2 : MoveToLOHI<"mtm2", GPR64Opnd, [MPL2, P0, P1, P2]>, MTMR_FM<0x0d>;
|
|
|
|
|
def MTP0 : MoveToLOHI<"mtp0", GPR64Opnd, [P0]>, MTMR_FM<0x09>;
|
|
|
|
|
def MTP1 : MoveToLOHI<"mtp1", GPR64Opnd, [P1]>, MTMR_FM<0x0a>;
|
|
|
|
|
def MTP2 : MoveToLOHI<"mtp2", GPR64Opnd, [P2]>, MTMR_FM<0x0b>;
|
|
|
|
|
|
2014-03-20 11:51:58 +00:00
|
|
|
// Count Ones in a Word/Doubleword
|
|
|
|
|
def POP : Count1s<"pop", GPR32Opnd>, POP_FM<0x2c>;
|
|
|
|
|
def DPOP : Count1s<"dpop", GPR64Opnd>, POP_FM<0x2d>;
|
|
|
|
|
|
|
|
|
|
// Set on equal/not equal
|
|
|
|
|
def SEQ : SetCC64_R<"seq", seteq>, SEQ_FM<0x2a>;
|
2014-04-04 16:21:59 +00:00
|
|
|
def SEQi : SetCC64_I<"seqi", seteq>, SEQI_FM<0x2e>;
|
2014-03-20 11:51:58 +00:00
|
|
|
def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>;
|
2014-04-04 16:21:59 +00:00
|
|
|
def SNEi : SetCC64_I<"snei", setne>, SEQI_FM<0x2f>;
|
|
|
|
|
|
2014-04-24 16:31:10 +00:00
|
|
|
// 192-bit x 64-bit Unsigned Multiply and Add
|
2014-04-04 16:21:59 +00:00
|
|
|
let Defs = [P0, P1, P2] in
|
|
|
|
|
def V3MULU: ArithLogicR<"v3mulu", GPR64Opnd, 0, II_DMUL>,
|
|
|
|
|
ADD_FM<0x1c, 0x11>;
|
|
|
|
|
|
|
|
|
|
// 64-bit Unsigned Multiply and Add Move
|
|
|
|
|
let Defs = [MPL0, P0, P1, P2] in
|
|
|
|
|
def VMM0 : ArithLogicR<"vmm0", GPR64Opnd, 0, II_DMUL>,
|
|
|
|
|
ADD_FM<0x1c, 0x10>;
|
|
|
|
|
|
|
|
|
|
// 64-bit Unsigned Multiply and Add
|
|
|
|
|
let Defs = [MPL1, MPL2, P0, P1, P2] in
|
|
|
|
|
def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>,
|
|
|
|
|
ADD_FM<0x1c, 0x0f>;
|
|
|
|
|
|
2014-03-20 11:51:58 +00:00
|
|
|
}
|
|
|
|
|
|
2012-04-17 18:03:21 +00:00
|
|
|
}
|
2014-04-02 18:40:43 +00:00
|
|
|
|
2015-02-24 11:52:19 +00:00
|
|
|
/// Move between CPU and coprocessor registers
|
|
|
|
|
let DecoderNamespace = "Mips64", Predicates = [HasMips64] in {
|
|
|
|
|
def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd>, MFC3OP_FM<0x10, 1>;
|
|
|
|
|
def DMTC0 : MFC3OP<"dmtc0", GPR64Opnd>, MFC3OP_FM<0x10, 5>, ISA_MIPS3;
|
|
|
|
|
def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd>, MFC3OP_FM<0x12, 1>, ISA_MIPS3;
|
|
|
|
|
def DMTC2 : MFC3OP<"dmtc2", GPR64Opnd>, MFC3OP_FM<0x12, 5>, ISA_MIPS3;
|
|
|
|
|
}
|
|
|
|
|
|
2011-09-30 18:51:46 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// Arbitrary patterns that map to one or more instructions
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
2011-11-14 19:06:14 +00:00
|
|
|
// extended loads
|
2014-04-29 16:24:10 +00:00
|
|
|
def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
|
|
|
|
|
def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
|
|
|
|
|
def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
|
|
|
|
|
def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
|
2011-10-11 00:55:05 +00:00
|
|
|
|
|
|
|
|
// hi/lo relocs
|
2012-06-14 21:03:23 +00:00
|
|
|
def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
|
|
|
|
|
def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
|
|
|
|
|
def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
|
|
|
|
|
def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
|
|
|
|
|
def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
|
2012-11-21 20:40:38 +00:00
|
|
|
def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>;
|
2012-06-14 21:03:23 +00:00
|
|
|
|
|
|
|
|
def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
|
|
|
|
|
def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
|
|
|
|
|
def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
|
|
|
|
|
def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
|
|
|
|
|
def : MipsPat<(MipsLo tglobaltlsaddr:$in),
|
|
|
|
|
(DADDiu ZERO_64, tglobaltlsaddr:$in)>;
|
2012-11-21 20:40:38 +00:00
|
|
|
def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>;
|
2012-06-14 21:03:23 +00:00
|
|
|
|
2013-08-06 23:08:38 +00:00
|
|
|
def : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)),
|
|
|
|
|
(DADDiu GPR64:$hi, tglobaladdr:$lo)>;
|
|
|
|
|
def : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)),
|
|
|
|
|
(DADDiu GPR64:$hi, tblockaddress:$lo)>;
|
|
|
|
|
def : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)),
|
|
|
|
|
(DADDiu GPR64:$hi, tjumptable:$lo)>;
|
|
|
|
|
def : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)),
|
|
|
|
|
(DADDiu GPR64:$hi, tconstpool:$lo)>;
|
|
|
|
|
def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)),
|
|
|
|
|
(DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>;
|
|
|
|
|
|
|
|
|
|
def : WrapperPat<tglobaladdr, DADDiu, GPR64>;
|
|
|
|
|
def : WrapperPat<tconstpool, DADDiu, GPR64>;
|
|
|
|
|
def : WrapperPat<texternalsym, DADDiu, GPR64>;
|
|
|
|
|
def : WrapperPat<tblockaddress, DADDiu, GPR64>;
|
|
|
|
|
def : WrapperPat<tjumptable, DADDiu, GPR64>;
|
|
|
|
|
def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>;
|
|
|
|
|
|
|
|
|
|
defm : BrcondPats<GPR64, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
|
2011-10-11 19:09:09 +00:00
|
|
|
ZERO_64>;
|
|
|
|
|
|
2013-05-21 17:13:47 +00:00
|
|
|
def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
|
|
|
|
|
(BLEZ64 i64:$lhs, bb:$dst)>;
|
|
|
|
|
def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
|
|
|
|
|
(BGEZ64 i64:$lhs, bb:$dst)>;
|
|
|
|
|
|
2011-10-11 18:53:46 +00:00
|
|
|
// setcc patterns
|
2013-08-06 23:08:38 +00:00
|
|
|
defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>;
|
|
|
|
|
defm : SetlePats<GPR64, SLT64, SLTu64>;
|
|
|
|
|
defm : SetgtPats<GPR64, SLT64, SLTu64>;
|
|
|
|
|
defm : SetgePats<GPR64, SLT64, SLTu64>;
|
|
|
|
|
defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>;
|
2011-11-07 18:57:41 +00:00
|
|
|
|
|
|
|
|
// truncate
|
2014-11-07 16:54:21 +00:00
|
|
|
def : MipsPat<(trunc (assertsext GPR64:$src)),
|
|
|
|
|
(EXTRACT_SUBREG GPR64:$src, sub_32)>;
|
|
|
|
|
def : MipsPat<(trunc (assertzext GPR64:$src)),
|
|
|
|
|
(EXTRACT_SUBREG GPR64:$src, sub_32)>;
|
2013-08-06 23:08:38 +00:00
|
|
|
def : MipsPat<(i32 (trunc GPR64:$src)),
|
2014-05-07 10:27:09 +00:00
|
|
|
(SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>;
|
2012-02-28 07:46:26 +00:00
|
|
|
|
2015-02-18 14:57:05 +00:00
|
|
|
// Bypass trunc nodes for bitwise ops.
|
|
|
|
|
def : MipsPat<(i32 (trunc (and GPR64:$lhs, GPR64:$rhs))),
|
|
|
|
|
(EXTRACT_SUBREG (AND64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
|
|
|
|
|
def : MipsPat<(i32 (trunc (or GPR64:$lhs, GPR64:$rhs))),
|
|
|
|
|
(EXTRACT_SUBREG (OR64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
|
|
|
|
|
def : MipsPat<(i32 (trunc (xor GPR64:$lhs, GPR64:$rhs))),
|
|
|
|
|
(EXTRACT_SUBREG (XOR64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
|
|
|
|
|
|
2015-04-21 10:49:03 +00:00
|
|
|
// variable shift instructions patterns
|
|
|
|
|
def : MipsPat<(shl GPR64:$rt, (i32 (trunc GPR64:$rs))),
|
|
|
|
|
(DSLLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
|
|
|
|
|
def : MipsPat<(srl GPR64:$rt, (i32 (trunc GPR64:$rs))),
|
|
|
|
|
(DSRLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
|
|
|
|
|
def : MipsPat<(sra GPR64:$rt, (i32 (trunc GPR64:$rs))),
|
|
|
|
|
(DSRAV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
|
|
|
|
|
def : MipsPat<(rotr GPR64:$rt, (i32 (trunc GPR64:$rs))),
|
|
|
|
|
(DROTRV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
|
|
|
|
|
|
2011-12-07 23:14:41 +00:00
|
|
|
// 32-to-64-bit extension
|
2013-08-06 23:08:38 +00:00
|
|
|
def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
|
|
|
|
|
def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
|
|
|
|
|
def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>;
|
2011-12-20 22:06:20 +00:00
|
|
|
|
2011-12-20 22:40:40 +00:00
|
|
|
// Sign extend in register
|
2013-08-06 23:08:38 +00:00
|
|
|
def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
|
|
|
|
|
(SLL64_64 GPR64:$src)>;
|
2011-12-20 22:40:40 +00:00
|
|
|
|
2012-06-14 21:03:23 +00:00
|
|
|
// bswap MipsPattern
|
2013-08-06 23:08:38 +00:00
|
|
|
def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
|
2012-10-09 16:27:43 +00:00
|
|
|
|
2015-01-26 12:33:22 +00:00
|
|
|
// Carry pattern
|
|
|
|
|
def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
|
|
|
|
|
(DSUBu GPR64:$lhs, GPR64:$rhs)>;
|
|
|
|
|
let AdditionalPredicates = [NotDSP] in {
|
|
|
|
|
def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs),
|
|
|
|
|
(DADDu GPR64:$lhs, GPR64:$rhs)>;
|
|
|
|
|
def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm),
|
|
|
|
|
(DADDiu GPR64:$lhs, imm:$imm)>;
|
|
|
|
|
}
|
|
|
|
|
|
2015-01-20 16:10:51 +00:00
|
|
|
// Octeon bbit0/bbit1 MipsPattern
|
|
|
|
|
let Predicates = [HasMips64, HasCnMips] in {
|
|
|
|
|
def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst),
|
|
|
|
|
(BBIT0 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>;
|
|
|
|
|
def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst),
|
|
|
|
|
(BBIT032 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>;
|
|
|
|
|
def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst),
|
|
|
|
|
(BBIT1 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>;
|
|
|
|
|
def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst),
|
|
|
|
|
(BBIT132 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>;
|
|
|
|
|
}
|
|
|
|
|
|
2012-10-09 16:27:43 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// Instruction aliases
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
2014-05-08 16:12:31 +00:00
|
|
|
def : MipsInstAlias<"move $dst, $src",
|
|
|
|
|
(DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>,
|
2014-05-13 11:17:46 +00:00
|
|
|
GPR_64;
|
2014-05-08 16:12:31 +00:00
|
|
|
def : MipsInstAlias<"daddu $rs, $rt, $imm",
|
|
|
|
|
(DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
|
2014-09-15 14:47:46 +00:00
|
|
|
0>, ISA_MIPS3;
|
2014-05-08 16:12:31 +00:00
|
|
|
def : MipsInstAlias<"dadd $rs, $rt, $imm",
|
|
|
|
|
(DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
|
2014-06-13 12:49:06 +00:00
|
|
|
0>, ISA_MIPS3_NOT_32R6_64R6;
|
2014-05-08 16:12:31 +00:00
|
|
|
def : MipsInstAlias<"daddu $rs, $imm",
|
|
|
|
|
(DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
|
2014-09-15 14:47:46 +00:00
|
|
|
0>, ISA_MIPS3;
|
2014-05-08 16:12:31 +00:00
|
|
|
def : MipsInstAlias<"dadd $rs, $imm",
|
|
|
|
|
(DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
|
2014-06-13 12:49:06 +00:00
|
|
|
0>, ISA_MIPS3_NOT_32R6_64R6;
|
2014-05-08 16:12:31 +00:00
|
|
|
def : MipsInstAlias<"dsll $rd, $rt, $rs",
|
2014-05-09 13:02:27 +00:00
|
|
|
(DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
|
|
|
|
|
ISA_MIPS3;
|
2015-05-05 08:48:35 +00:00
|
|
|
def : MipsInstAlias<"dneg $rt, $rs",
|
|
|
|
|
(DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
|
|
|
|
|
ISA_MIPS3;
|
|
|
|
|
def : MipsInstAlias<"dneg $rt",
|
|
|
|
|
(DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 0>,
|
|
|
|
|
ISA_MIPS3;
|
|
|
|
|
def : MipsInstAlias<"dnegu $rt, $rs",
|
|
|
|
|
(DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
|
|
|
|
|
ISA_MIPS3;
|
2014-05-08 16:12:31 +00:00
|
|
|
def : MipsInstAlias<"dsubu $rt, $rs, $imm",
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(DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs,
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2014-09-15 14:47:46 +00:00
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InvertedImOperand64:$imm), 0>, ISA_MIPS3;
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2014-06-13 12:49:06 +00:00
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def : MipsInstAlias<"dsubi $rs, $rt, $imm",
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(DADDi GPR64Opnd:$rs, GPR64Opnd:$rt,
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InvertedImOperand64:$imm),
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0>, ISA_MIPS3_NOT_32R6_64R6;
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def : MipsInstAlias<"dsubi $rs, $imm",
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(DADDi GPR64Opnd:$rs, GPR64Opnd:$rs,
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InvertedImOperand64:$imm),
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0>, ISA_MIPS3_NOT_32R6_64R6;
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def : MipsInstAlias<"dsub $rs, $rt, $imm",
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(DADDi GPR64Opnd:$rs, GPR64Opnd:$rt,
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InvertedImOperand64:$imm),
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0>, ISA_MIPS3_NOT_32R6_64R6;
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2014-05-08 16:12:31 +00:00
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def : MipsInstAlias<"dsub $rs, $imm",
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(DADDi GPR64Opnd:$rs, GPR64Opnd:$rs,
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InvertedImOperand64:$imm),
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2014-06-13 12:49:06 +00:00
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0>, ISA_MIPS3_NOT_32R6_64R6;
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2014-05-08 16:12:31 +00:00
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def : MipsInstAlias<"dsubu $rs, $imm",
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(DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs,
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InvertedImOperand64:$imm),
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2014-09-15 14:47:46 +00:00
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0>, ISA_MIPS3;
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2014-05-09 09:24:49 +00:00
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def : MipsInstAlias<"dsra $rd, $rt, $rs",
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2014-05-09 13:02:27 +00:00
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(DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
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ISA_MIPS3;
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2014-05-08 16:12:31 +00:00
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def : MipsInstAlias<"dsrl $rd, $rt, $rs",
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2014-05-09 13:02:27 +00:00
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(DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
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ISA_MIPS3;
|
2013-01-18 20:15:06 +00:00
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|
2012-10-11 10:21:34 +00:00
|
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// Two operand (implicit 0 selector) versions:
|
2014-05-08 16:12:31 +00:00
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def : MipsInstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
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def : MipsInstAlias<"dmtc0 $rt, $rd", (DMTC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
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def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
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def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
|
2012-10-11 10:21:34 +00:00
|
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|
2014-09-10 06:10:24 +00:00
|
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let Predicates = [HasMips64, HasCnMips] in {
|
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|
def : MipsInstAlias<"synciobdma", (SYNC 0x2), 0>;
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def : MipsInstAlias<"syncs", (SYNC 0x6), 0>;
|
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def : MipsInstAlias<"syncw", (SYNC 0x4), 0>;
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def : MipsInstAlias<"syncws", (SYNC 0x5), 0>;
|
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}
|
2015-02-24 11:52:19 +00:00
|
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//===----------------------------------------------------------------------===//
|
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// Assembler Pseudo Instructions
|
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//===----------------------------------------------------------------------===//
|
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|
2015-03-04 13:01:14 +00:00
|
|
|
class LoadImmediate64<string instr_asm, Operand Od, RegisterOperand RO> :
|
2015-02-24 11:52:19 +00:00
|
|
|
MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm64),
|
|
|
|
|
!strconcat(instr_asm, "\t$rt, $imm64")> ;
|
2015-03-04 13:01:14 +00:00
|
|
|
def LoadImm64 : LoadImmediate64<"dli", imm64, GPR64Opnd>;
|
