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Author SHA1 Message Date
Owen Anderson
fd9085dca3 Tabs --> spaces. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137225 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 17:38:05 +00:00
Owen Anderson
10cbaab7b7 Cleanups based on Nick Lewycky's feedback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137224 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 17:36:48 +00:00
Owen Anderson
e66ef2d5f5 Rewrite some ARM InstrInfo functions to be most accepting of arbitrary register subclasses. Hopefully this fixes some buildbots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137223 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 17:21:20 +00:00
Rafael Espindola
f5ade5d39a Add support for the R and Q constraints. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137217 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 16:26:42 +00:00
Bruno Cardoso Lopes
155a92a491 Fix a bug in vpermilps mask checking. Fix PR10560 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137194 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 01:54:17 +00:00
Owen Anderson
33e57515b1 Push GPRnopc through a large number of instruction definitions to tighten operand decoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137189 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 00:03:03 +00:00
Jakob Stoklund Olesen
c70c2cafe1 Promote VMOVS to VMOVD when possible. 
On Cortex-A8, we use the NEON v2f32 instructions for f32 arithmetic. For
better latency, we also send D-register copies down the NEON pipeline by
translating them to vorr instructions.

This patch promotes even S-register copies to D-register copies when
possible so they can also go down the NEON pipeline.  Example:

        vldr.32 s0, LCPI0_0
    loop:
        vorr    d1, d0, d0
    loop2:
        ...
        vadd.f32        d1, d1, d16

The vorr instruction looked like this after regalloc:

    %S2<def> = COPY %S0, %D1<imp-def>

Copies involving odd S-registers, and copies that don't define the full
D-register are left alone.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137182 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 23:41:44 +00:00
Owen Anderson
de317f40f7 Tighten operand checking of register-shifted-register operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137180 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 23:33:27 +00:00
Bruno Cardoso Lopes
d40aa24ebf Add 256-bit support for v8i32, v4i64 and v4f64 ISD::SELECT. Fix PR10556 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137179 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 23:27:13 +00:00
Owen Anderson
c36481c474 Tighten operand checking on memory barrier instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137176 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 23:25:42 +00:00
Owen Anderson
35008c2f8d Tighten operand checking on CPS instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137172 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 23:05:39 +00:00
Owen Anderson
51c9805c4b Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137168 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 22:48:45 +00:00
Bruno Cardoso Lopes
18deb04e9c Add v16i16 and v32i8 store patterns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137166 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 22:39:53 +00:00
Bruno Cardoso Lopes
cde4a1abd5 Use fp unpack instructions to unpack int types. Until we have AVX2, this 
is the best we can do for these patterns. This fix PR10554.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137161 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 22:18:37 +00:00
Eli Friedman
fc430a662f Fix a couple ridiculous copy-paste errors. rdar://9914773 . 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137160 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 22:17:39 +00:00
Benjamin Kramer
793b811c50 ARM Disassembler: sign extend branch immediates. 
Not sure about BLXi, but this is what the old disassembler did.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137156 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 22:02:50 +00:00
Owen Anderson
51157d2234 Silence an false-positive warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137154 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 21:38:14 +00:00
Owen Anderson
65e95d950d Don't generate the old-style disassembler in CMake builds either. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137153 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 21:36:11 +00:00
Benjamin Kramer
9bd7c2836e The new ARM disassembler disassembles "bx lr" as a special BX_ret instruction so target specific analysis isn't needed anymore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137151 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 21:34:19 +00:00
Owen Anderson
ad0d36b79f Don't continue generating the old-style decoder file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137150 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 21:30:29 +00:00
Jim Grosbach
6cd5716f61 ARM fix typo in pre-indexed store lowering. 
rdar://9915869


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137148 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 21:22:41 +00:00
Owen Anderson
e6afbabb63 Attempt to fix CMake build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137147 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 21:09:59 +00:00
Owen Anderson
bd9091c18d Tighten Thumb1 branch predicate decoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137146 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 21:07:45 +00:00
Owen Anderson
8d7d2e1238 Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137144 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 20:55:18 +00:00
Bill Wendling
c6fbe5636d Revert r137134. It breaks some code as Eli pointed out. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137135 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 18:56:35 +00:00
Bill Wendling
a0f596c1fc Print out the variable declaration only if it is a declaration. Otherwise, a 
'static' variable will be emitted twice.
PR10081


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137134 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 18:31:50 +00:00
Bruno Cardoso Lopes
e2406dfd89 Reapply a more appropriate solution than in r137114. AVX supports 
v4f64 = sitofp v4i32. This fix PR10559.
Also add support for v4i32 = fptosi v4f64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137128 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 17:39:13 +00:00
Bruno Cardoso Lopes
a511b8e519 Revert r137114 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137127 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 17:39:01 +00:00
Justin Holewinski
4bdd4ed564 PTX: Add initial support for device function calls 
- Calls are supported on SM 2.0+ for function with no return values

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137125 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 17:36:31 +00:00
Renato Golin
719927a68f Emitting ARM build attributes and values as ULEB, rather than char. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137115 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 09:50:10 +00:00
Bruno Cardoso Lopes
e321d7ffc5 Handle sitofp between v4f64 <- v4i32. Fix PR10559 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137114 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 05:48:01 +00:00
Bruno Cardoso Lopes
2f613c5fff Add support for avx vector fextend 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137105 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 03:04:29 +00:00
Bruno Cardoso Lopes
a1dfb63b78 Add AVX versions of 128-bit sitofp and fptosi 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137104 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 03:04:25 +00:00
Bruno Cardoso Lopes
e5118ab7bb Add two patterns to match special vmovss and vmovsd cases. Also fix 
the patterns already there to be more strict regarding the predicate.
This fixes PR10558

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137100 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 01:43:09 +00:00
Bill Wendling
54f1536927 Add missing attributes to the C++ backend's output. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137091 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 00:47:30 +00:00
Bruno Cardoso Lopes
0f0e0a0e58 Make LowerVSETCC aware of AVX types and add patterns to match them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137090 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 00:46:57 +00:00
Jim Grosbach
3148a65490 ARM parsing and encoding for LDRBT instruction. 
Fix the instruction representation to correctly only allow post-indexed form.
Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137074 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-08 23:28:47 +00:00
Owen Anderson
648f9a75fd Thumb1 BL instructions encoding 22 bits of displacement, not 21. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137073 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-08 23:25:22 +00:00
Jakob Stoklund Olesen
36ee0e6405 Implement isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE for ARM. 
They improve the verbose assembly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137069 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-08 21:45:32 +00:00
Bruno Cardoso Lopes
328a9d4a0f Add support for several vector shifts operations while in AVX mode. Fix PR10581 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137067 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-08 21:31:08 +00:00
Jim Grosbach
09176e10db ARM load/store label parsing. 
Allow labels for load/store instructions when parsing. There's encoding
issues, still, so this doesn't work all the way through, yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137064 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-08 20:59:31 +00:00
Jakob Stoklund Olesen
2df3f58a0b Hoist hasLoadFromStackSlot and hasStoreToStackSlot. 
These the methods are target-independent since they simply scan the
memory operands.  They can live in TargetInstrInfoImpl.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137063 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-08 20:53:24 +00:00
Owen Anderson
6d74631062 Fix encodings for Thumb ASR and LSR immediate operands. They encode the range 1-32, with 32 encoded as 0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137062 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-08 20:42:17 +00:00
Eli Friedman
2cb1dfa446 Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are correctly active without HasT2ExtractPack. PR10611. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137061 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-08 19:49:37 +00:00
Benjamin Kramer
41ab14b725 Add MCInstrAnalysis class. This allows the targets to specify own versions of MCInstrDescs functions. 
- Add overrides for ARM.
- Teach llvm-objdump to use this instead of plain MCInstrDesc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137059 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-08 18:56:44 +00:00
Jakob Stoklund Olesen
66b0f515d5 Don't clobber pending ST regs when FP regs are killed. 
X86FloatingPoint keeps track of pending ST registers for an upcoming
inline asm instruction with fixed stack register constraints.  It does
this by remembering which FP register holds the value that should appear
at a fixed stack position for the inline asm.

When that FP register is killed before the inline asm, make sure to
duplicate it to a scratch register, so the ST register still has a live
FP reference.

This could happen when the same FP register was copied to two ST
registers, or when a spill instruction is inserted between the ST copy
and the inline asm.

This fixes PR10602.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137050 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-08 17:15:43 +00:00
Jim Grosbach
0d6fac36ed ARM load instruction shifted register index operands. 
Parsing and encoding for shifted index operands for load instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136986 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-05 22:03:36 +00:00
Jim Grosbach
f4fa3d6e46 ARM indexed load assembly parsing and encoding. 
More parsing support for indexed loads. Fix pre-indexed with writeback
parsing for register offsets and handle basic post-indexed offsets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136982 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-05 21:28:30 +00:00
Jim Grosbach
19dec207fc ARM refactor indexed store instructions. 
Refactor STR[B] pre and post indexed instructions to use addressing modes for
memory operands, which is necessary for assembly parsing and is more consistent
with the rest of the memory instruction definitions. Make some incremental
progress on refactoring away the mega-operand addrmode2 along the way, which
is nice.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136978 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-05 20:35:44 +00:00
Jim Grosbach
16578b5088 ARM simplify the postidx_reg operand encoding. 
The immediate portion of the operand is just a boolean (the 'U' bit indicating
add vs. subtract). Treat it as such.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136969 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-05 16:11:38 +00:00
Jim Grosbach
ca8c70b953 ARM use a dedicated printer for postidx_reg operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136968 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-05 15:48:21 +00:00
Bob Wilson
9a45008e91 Add missing register constraint for some VLD3/VLD4 pseudo instructions. 
<rdar://problem/9878189>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136962 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-05 07:24:09 +00:00
Chandler Carruth
8d8fa2506d Silence unused variable warnings in release builds. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136956 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-05 01:08:21 +00:00
Jason W Kim
4dd963b196 Fix http://llvm.org/bugs/show_bug.cgi?id=10583\n - test for 1 and 2 byte fixups to be added 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136954 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-05 00:53:03 +00:00
Owen Anderson
14c903a76b Fix broken encodings for the Thumb2 LDRD/STRD instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136942 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 23:18:05 +00:00
Jim Grosbach
039c2e19c4 ARM assembly parsing and encoding for LDR instructions. 
Enhance support for LDR instruction assembly parsing for post-indexed
addressing with immediate values. Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136940 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 23:01:30 +00:00
Evan Cheng
dd5663c8e4 Fix an obvious type. Patch by Ivan Krasin. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136899 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 18:38:15 +00:00
Owen Anderson
154c41dbbc LDCL_POST and STCL_POST need one's-complement offsets, rather than two's complement offsets. Add an appropriate immediate type for them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136896 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 18:24:14 +00:00
Duncan Sands
8036586229 Add obviously missing "break". Noticed by Andrey Karpov with 
the PVS-studio tool.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136878 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 15:45:59 +00:00
Jason W Kim
e651983e71 Fix http://llvm.org/bugs/show_bug.cgi?id=10568 
Move the reloc size assert into AsmBackend - where it is more apropos.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136855 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 00:38:45 +00:00
Bill Wendling
456a925c61 Only access both operands of an INSERT_SUBVECTOR if it is an INSERT_SUBVECTOR. 
Fixes PR10527.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136853 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 00:32:58 +00:00
Jim Grosbach
7ce057983e ARM refactoring assembly parsing of memory address operands. 
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.

The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.

This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.

Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136845 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-03 23:50:40 +00:00
Owen Anderson
0bc8bbb58d Fix broken encoding of tCBNZ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136837 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-03 23:21:48 +00:00
Eli Friedman
26689ac37e New approach to r136737: insert the necessary fences for atomic ops in platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing. 
I think this completes the basic CodeGen for atomicrmw and cmpxchg.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136813 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-03 21:06:02 +00:00
Benjamin Kramer
1488f76ed9 Remove unused variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136803 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-03 19:53:48 +00:00
Jakob Stoklund Olesen
56e3232d5a Handle IMPLICIT_DEF instructions in X86FloatingPoint. 
This fixes PR10575.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136787 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-03 16:33:19 +00:00
Eli Friedman
989f61e6c0 ARM backend support for atomicrmw and cmpxchg with non-monotonic ordering. Not especially pretty, but seems to work well enough. If this looks okay, I'll put together similar patches for Mips, PPC, and Alpha. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136737 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-02 22:44:16 +00:00
Eli Friedman
6cdc1f43e6 Don't create a ridiculous EXTRACT_ELEMENT. PR10563. 
The testcase looks extremely fragile, so I'm adding an assertion which should catch any cases like this.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136711 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-02 18:38:35 +00:00
Owen Anderson
96279d0eff Fix the broken encodings for the VFP vmov.f32 and vmov.f64 instructions, as well as the comments that explain them incorrectly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136707 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-02 18:30:00 +00:00
Jim Grosbach
b93509d382 Tidy up. 80 columns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136705 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-02 18:16:36 +00:00
Jim Grosbach
e39389a58d ARM: rename addrmode7 to addr_offset_none. 
Use a more descriptive name so the code is more self-documenting.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136704 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-02 18:07:32 +00:00
Bruno Cardoso Lopes
ac5f13fe3f Make this kind of lowering to be supported by 256-bit instructions: 
shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
To:
  shuffle (vload ptr)), undef, <1, 1, 1, 1>
Fix PR10494

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136691 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-02 16:06:18 +00:00
Roman Divacky
29630ff214 Remove trailing semicolon. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136690 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-02 15:54:03 +00:00
Roman Divacky
2c0d69fad0 Sketch out PowerPC ELF writer. This is enough to get clang -integrated-as 
to compile a working hello world on FreeBSD/PPC32.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136689 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-02 15:51:38 +00:00
Nick Lewycky
3207c9a440 Bail from FastISel when we encounter a volatile memset intrinsic. Patch by Ivan 
Krasin!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136663 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-02 00:40:16 +00:00
Jim Grosbach
02c8460a74 Move imm0_255 to ARMInstrInfo.td with the other immediate predicates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136656 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-01 22:02:20 +00:00
Jim Grosbach
b2756afa27 Fix comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136655 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-01 21:55:12 +00:00
Bruno Cardoso Lopes
55244ceac4 Add v4f64 -> v2f32 fp_round support. Also add a testcase to exercise 
the legalizer. This commit together with the two previous ones fixes
PR10495.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136654 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-01 21:54:09 +00:00
Bruno Cardoso Lopes
aed890bee0 Teach PreprocessISelDAG to be aware of vector types and to not process them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136653 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-01 21:54:05 +00:00
Bruno Cardoso Lopes
8af2451679 Lower CONCAT_VECTORS to use two VINSERTF128 instructions instead of 
using a stack store.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136652 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-01 21:54:02 +00:00
Chandler Carruth
81fd0ba8ab Actually finish switching to the new system for Target sublibrary 
TableGen deps introduced in r136023. This completes the fixing that
dgregor started in r136621. Sorry for missing these the first time
around.

This should fix some of the random race-condition failures people are
still seeing with CMake.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136643 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-01 19:55:11 +00:00
Bruno Cardoso Lopes
531f19f767 Since vectors with all ones can't be created with a 256-bit instruction, 
avoid returning early for v8i32 types, which would only be valid for
vector with all zeros. Also split the handling of zeros and ones into separate
checking logic since they are handled differently. This fixes PR10547

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136642 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-01 19:51:53 +00:00
Evan Cheng
8ead80db20 Set endianess and pointer size for PPC Linux. Bug noticed by Roman Divacky. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136639 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-01 19:43:05 +00:00
Richard Osborne
965b891762 Fix crash with varargs function with no named parameters. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136623 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-01 16:45:59 +00:00
Douglas Gregor
32ab312e3f Update CMake target names for tablegen-generated data in the X86 and ARM targets. This should fix the CMake build with MSVC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136621 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-01 16:29:27 +00:00
Bill Wendling
dccc03b242 Add the 'resume' instruction for the new EH rewrite. 
This adds the 'resume' instruction class, IR parsing, and bitcode reading and
writing. The 'resume' instruction resumes propagation of an existing (in-flight)
exception whose unwinding was interrupted with a 'landingpad' instruction (to be
added later).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136589 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-31 06:30:59 +00:00
Chandler Carruth
61377a1f3c Switch another of the old dependencies on implicitly produced synthetic 
rules to the new explicitly listed TableGen rules. Somehow I missed this
in my original sweep.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136567 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-30 10:10:23 +00:00
Bill Wendling
10c6d12a9f Revert r136253, r136263, r136269, r136313, r136325, r136326, r136329, r136338, 
r136339, r136341, r136369, r136387, r136392, r136396, r136429, r136430, r136444,
r136445, r136446, r136253 pending review.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136556 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-30 05:42:50 +00:00
Eric Christopher
ef7f1e71f7 Add support for the 'Q' constraint. 
Fixes rdar://9866494


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136523 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-29 21:18:58 +00:00
Jim Grosbach
e1cf5902ec ARM SRS instruction parsing, diassembly and encoding support. 
Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136509 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-29 20:26:09 +00:00
Jim Grosbach
33768dba54 ARM CPS mode immediate is 5 bits, not 4. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136505 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-29 20:02:39 +00:00
Jim Grosbach
2c6363a62d ARM assembly parsing and encoding for RFE instruction. 
Fill in the missing fixed bits and the register operand bits of the instruction
encoding. Refactor the definition to make the mode explicit, which is
consistent with how loads and stores are normally represented and makes
parsing much easier. Add parsing aliases for pseudo-instruction variants.
Update the disassembler for the new representations. Add tests for parsing and
encoding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136479 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-29 18:47:24 +00:00
Jim Grosbach
5a28748360 ARM SRS and RFE instructions are not code-gen only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136475 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-29 17:51:39 +00:00
Jim Grosbach
b48ce900f9 ARM range checking for mode on CPS instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136473 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-29 17:42:17 +00:00
Jim Grosbach
96e24fa892 Update FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136470 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-29 17:36:04 +00:00
Jim Grosbach
bd4562e163 Tweak comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136468 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-29 17:33:29 +00:00
Eli Friedman
55ba816883 Misc optimizer+codegen work for 'cmpxchg' and 'atomicrmw'. They appear to be 
working on x86 (at least for trivial testcases); other architectures will
need more work so that they actually emit the appropriate instructions for
orderings stricter than 'monotonic'. (As far as I can tell, the ARM, PPC,
Mips, and Alpha backends need such changes.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136457 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-29 03:05:32 +00:00
Bruno Cardoso Lopes
6126005259 Fix two tests that I crashed in the previous commits. The mask elts 
on the second half must be reindexed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136454 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-29 02:05:28 +00:00
Bruno Cardoso Lopes
dd6353073f Match VPERMIL masks more strictly and update the target specific mask 
generation to always catch the weird cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136453 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-29 01:31:15 +00:00
Bruno Cardoso Lopes
2eb4c2bcad Add DecodeShuffle shuffle support for VPERMIPD variantes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136452 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-29 01:31:11 +00:00