Commit Graph

554 Commits

Author SHA1 Message Date
Tom Stellard
3ef5383b35 DAGCombiner: Use correct value type for checking legality of BR_CC v3
LegalizeDAG.cpp uses the value of the comparison operands when checking
the legality of BR_CC, so DAGCombiner should do the same.

v2:
  - Expand more BR_CC value types for NVPTX

v3:
  - Expand correct BR_CC value types for Hexagon, Mips, and XCore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176694 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08 15:36:57 +00:00
Michael Liao
a6b20ced76 Fix PR10475
- ISD::SHL/SRL/SRA must have either both scalar or both vector operands
  but TLI.getShiftAmountTy() so far only return scalar type. As a
  result, backend logic assuming that breaks.
- Rename the original TLI.getShiftAmountTy() to
  TLI.getScalarShiftAmountTy() and re-define TLI.getShiftAmountTy() to
  return target-specificed scalar type or the same vector type as the
  1st operand.
- Fix most TICG logic assuming TLI.getShiftAmountTy() a simple scalar
  type.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176364 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01 18:40:30 +00:00
Eli Bendersky
700ed80d3d Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo
to TargetFrameLowering, where it belongs. Incidentally, this allows us
to delete some duplicated (and slightly different!) code in TRI.

There are potentially other layering problems that can be cleaned up
as a result, or in a similar manner.

The refactoring was OK'd by Anton Korobeynikov on llvmdev.

Note: this touches the target interfaces, so out-of-tree targets may
be affected.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175788 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-21 20:05:00 +00:00
Jim Grosbach
3450f800aa Update TargetLowering ivars for name policy.
http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly

ivars should be camel-case and start with an upper-case letter. A few in
TargetLowering were starting with a lower-case letter.

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175667 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-20 21:13:59 +00:00
Richard Osborne
8dc741e400 [XCore] Add missing 2r instructions.
These instructions are not targeted by the compiler but it is needed for
the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175407 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17 22:38:05 +00:00
Richard Osborne
763c858ede [XCore] Add TSETR instruction.
This instruction is not targeted by the compiler but it is needed for the
MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175406 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17 22:32:41 +00:00
Richard Osborne
a970dde906 [XCore] Add missing u10 / lu10 instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175404 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17 20:44:48 +00:00
Richard Osborne
cbe6c88b68 [XCore] Add missing u6 / lu6 instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175403 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17 20:43:17 +00:00
Jakob Stoklund Olesen
0873bc8419 Move MRI liveouts to XCore return instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174414 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05 18:21:46 +00:00
Chad Rosier
108fb3202a [PEI] Pass the frame index operand number to the eliminateFrameIndex function.
Each target implementation was needlessly recomputing the index.
Part of rdar://13076458

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174083 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-31 20:02:54 +00:00
Richard Osborne
970a479c02 [XCore] Add missing l2rus instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173634 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27 22:28:30 +00:00
Richard Osborne
b719d8b100 [XCore] Add missing l2r instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173629 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27 21:26:02 +00:00
Richard Osborne
9d2b1aef1b [XCore] Add missing 1r instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173624 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27 20:46:21 +00:00
Richard Osborne
f5e7e793f1 [XCore] Add missing 0r instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173623 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27 20:42:57 +00:00
Richard Osborne
c47bd9899b Add instruction encodings / disassembly support for l4r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173501 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25 21:55:32 +00:00
Richard Osborne
1f375e5bc7 Use the correct format in the STW / SETPSC instruction names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173494 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25 21:25:12 +00:00
Richard Osborne
0f1bcedf5a Fix order of operands for crc8_l4r
The order in which operands appear in the encoded instruction is different
to order in which they appear in assembly. This changes the XCore backend to
use the instruction encoding order.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173493 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25 21:20:28 +00:00
Richard Osborne
3b6a5eefe0 Add instruction encodings / disassembly support for l5r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173479 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25 20:20:07 +00:00
Richard Osborne
f5c3648921 Fix order of operands for l5r instructions.
With this change the operands order matches the order in which the operands
are encoded in the instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173477 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25 20:16:00 +00:00
Richard Osborne
907bfd740a Use correct mnemonic / instruction name for ldivu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173476 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25 20:11:26 +00:00
Richard Osborne
9e6a5a3746 Add instruction encodings / disassembly support for l6r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173288 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-23 20:08:11 +00:00
Richard Osborne
0ec35ac4fc Add instruction encodings / disassembly support for u10 / lu10 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173204 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22 22:55:04 +00:00
Richard Osborne
923cc3ebb0 Fix some incorrectly named u10 / lu10 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173090 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-21 21:12:30 +00:00
Richard Osborne
d5ab457c0e Remove unused multiclass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173087 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-21 20:50:54 +00:00
Richard Osborne
8da5434346 Add instruction encodings / disassembly support for u6 / lu6 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173086 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-21 20:44:17 +00:00
Richard Osborne
9b709f8b3f Add instruction encoding / disassembly support for ru6 / lru6 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173085 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-21 20:42:16 +00:00
Richard Osborne
a3458380b9 Use correct format for the LDAWCP instruction (u6).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173083 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-21 20:32:54 +00:00
Richard Osborne
b853c415c6 Add instruction encodings / disassembly support for l2rus instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172987 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 18:51:15 +00:00
Richard Osborne
c78ec6b6bc Add instruction encodings / disassembly support for l3r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172986 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 18:37:49 +00:00
Richard Osborne
a68c64fbb2 Add instruction encodings / disassembler support for 2rus instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172985 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 17:22:43 +00:00
Richard Osborne
62b8786d12 Add instruction encodings / disassembly support 3r instructions.
It is not possible to distinguish 3r instructions from 2r / rus instructions
using only the fixed bits. Therefore if an instruction doesn't match the
2r / rus format try to decode it as a 3r instruction before returning Fail.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 17:18:47 +00:00
Eric Christopher
1ced208be9 Last in the series of removing unnecessary '0' arguments for
address space. Reordered the EmitULEB128IntValue arguments to
make this easier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171949 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09 03:52:05 +00:00
Chandler Carruth
aeef83c6af Switch TargetTransformInfo from an immutable analysis pass that requires
a TargetMachine to construct (and thus isn't always available), to an
analysis group that supports layered implementations much like
AliasAnalysis does. This is a pretty massive change, with a few parts
that I was unable to easily separate (sorry), so I'll walk through it.

The first step of this conversion was to make TargetTransformInfo an
analysis group, and to sink the nonce implementations in
ScalarTargetTransformInfo and VectorTargetTranformInfo into
a NoTargetTransformInfo pass. This allows other passes to add a hard
requirement on TTI, and assume they will always get at least on
implementation.

The TargetTransformInfo analysis group leverages the delegation chaining
trick that AliasAnalysis uses, where the base class for the analysis
group delegates to the previous analysis *pass*, allowing all but tho
NoFoo analysis passes to only implement the parts of the interfaces they
support. It also introduces a new trick where each pass in the group
retains a pointer to the top-most pass that has been initialized. This
allows passes to implement one API in terms of another API and benefit
when some other pass above them in the stack has more precise results
for the second API.

The second step of this conversion is to create a pass that implements
the TargetTransformInfo analysis using the target-independent
abstractions in the code generator. This replaces the
ScalarTargetTransformImpl and VectorTargetTransformImpl classes in
lib/Target with a single pass in lib/CodeGen called
BasicTargetTransformInfo. This class actually provides most of the TTI
functionality, basing it upon the TargetLowering abstraction and other
information in the target independent code generator.

The third step of the conversion adds support to all TargetMachines to
register custom analysis passes. This allows building those passes with
access to TargetLowering or other target-specific classes, and it also
allows each target to customize the set of analysis passes desired in
the pass manager. The baseline LLVMTargetMachine implements this
interface to add the BasicTTI pass to the pass manager, and all of the
tools that want to support target-aware TTI passes call this routine on
whatever target machine they end up with to add the appropriate passes.

The fourth step of the conversion created target-specific TTI analysis
passes for the X86 and ARM backends. These passes contain the custom
logic that was previously in their extensions of the
ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces.
I separated them into their own file, as now all of the interface bits
are private and they just expose a function to create the pass itself.
Then I extended these target machines to set up a custom set of analysis
passes, first adding BasicTTI as a fallback, and then adding their
customized TTI implementations.

The fourth step required logic that was shared between the target
independent layer and the specific targets to move to a different
interface, as they no longer derive from each other. As a consequence,
a helper functions were added to TargetLowering representing the common
logic needed both in the target implementation and the codegen
implementation of the TTI pass. While technically this is the only
change that could have been committed separately, it would have been
a nightmare to extract.

The final step of the conversion was just to delete all the old
boilerplate. This got rid of the ScalarTargetTransformInfo and
VectorTargetTransformInfo classes, all of the support in all of the
targets for producing instances of them, and all of the support in the
tools for manually constructing a pass based around them.

Now that TTI is a relatively normal analysis group, two things become
straightforward. First, we can sink it into lib/Analysis which is a more
natural layer for it to live. Second, clients of this interface can
depend on it *always* being available which will simplify their code and
behavior. These (and other) simplifications will follow in subsequent
commits, this one is clearly big enough.

Finally, I'm very aware that much of the comments and documentation
needs to be updated. As soon as I had this working, and plausibly well
commented, I wanted to get it committed and in front of the build bots.
I'll be doing a few passes over documentation later if it sticks.

Commits to update DragonEgg and Clang will be made presently.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171681 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-07 01:37:14 +00:00
Chandler Carruth
0b8c9a80f2 Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.

There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.

The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.

I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).

I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-02 11:36:10 +00:00
Chandler Carruth
58a2cbef4a Resort the #include lines in include/... and lib/... with the
utils/sort_includes.py script.

Most of these are updating the new R600 target and fixing up a few
regressions that have creeped in since the last time I sorted the
includes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171362 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-02 10:22:59 +00:00
Bill Wendling
9d30e7208e Remove the getAttributesAtIndex and getNumAttrs methods in favor of using the getAttrSomewhere predicate. This prevents the uses of 'Attribute' as a collection of attributes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171271 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-31 00:49:59 +00:00
Bill Wendling
034b94b170 Rename the 'Attributes' class to 'Attribute'. It's going to represent a single attribute in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170502 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19 07:18:57 +00:00
Richard Osborne
c47793c62c Add instruction encodings / disassembly support for l2r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170345 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 16:28:02 +00:00
Richard Osborne
a839ffc323 Add instruction encodings for PEEK and ENDIN.
Previously these were marked with the wrong format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170334 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 14:23:54 +00:00
Richard Osborne
6e43b7f6b2 Fix parameter name in prototypes in XCoreDisassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170332 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 13:55:49 +00:00
Richard Osborne
35150cbf41 Add instruction encodings / disassembly support for rus instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170330 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 13:50:04 +00:00
Richard Osborne
ff6114e872 Add instruction encodings for ZEXT and SEXT.
Previously these were marked with the wrong format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170327 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 13:20:37 +00:00
Richard Osborne
1ffe48a84b Add instruction encodings / disassembly support for 2r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170323 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 12:29:31 +00:00
Richard Osborne
dd78daa199 Add instruction encodings / disassembly support for 0r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170322 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 12:26:29 +00:00
Richard Osborne
2694948966 Simplify assertion in XCoreInstPrinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170321 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 12:13:46 +00:00
Richard Osborne
b4d40a04f0 Update comments to match recommended doxygen style.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170320 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 12:13:41 +00:00
Richard Osborne
31061e68a2 Remove unnecessary include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170319 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 12:13:32 +00:00
Richard Osborne
54d6266e9b Add instruction encodings and disassembly for 1r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170293 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-16 17:37:34 +00:00
Richard Osborne
881e3cca66 Add XCore disassembler.
Currently there is no instruction encoding info and
XCoreDisassembler::getInstruction() always returns Fail. I intend to add
instruction encodings and tests in follow on commits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170292 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-16 17:29:14 +00:00
Richard Osborne
054169be24 Remove invalid instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170291 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-16 16:46:31 +00:00