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16449 Commits

Author SHA1 Message Date
Eric Christopher
c9a91fdaf9 Make sure offset is 0 for load/store register to the stack call. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116640 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 23:07:10 +00:00
Eric Christopher
00ed59a968 Formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116635 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 22:49:28 +00:00
Eric Christopher
315030ca74 Fix else if -> if in store machinery. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116628 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 22:32:37 +00:00
Bill Wendling
2695d8edd1 Reformatting. No functionalogicality changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116625 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 21:50:45 +00:00
Eric Christopher
a322425642 Refactor ARM fast-isel reg + offset to be a base + offset. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116622 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 21:32:12 +00:00
Jim Grosbach
5ad01c7728 Encoding information for the various ARM saturating add/sub instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116612 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 19:49:46 +00:00
Jim Grosbach
84760885e1 ARM binary encoding information for RSB and RSC instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116604 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 18:42:41 +00:00
Jim Grosbach
fd52906478 Don't mark argument value stores as immutable, as otherwise the post-RA 
scheduler may reorder loads from them before the stores and other such
badness. PR8347. Patch by David Meyer

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116602 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 18:34:47 +00:00
Bob Wilson
01b35c25de Use simple RegState::Define flag instead of getDefRegState(true). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116601 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 18:25:59 +00:00
Eric Christopher
2896df897c Expand GEP handling for constant offsets. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116594 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 18:02:07 +00:00
Jim Grosbach
6bdc8ae291 When expanding the MOVsr[la]_flag pseudos, the CPSR implicit def becomes 
an explicit def. Make sure to capture that properly. rdar://8556556

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116591 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 17:35:17 +00:00
Jim Grosbach
8abe32af38 ARM mode encoding information for UBFX and SBFX instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116588 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 17:15:16 +00:00
Bob Wilson
1dd5a2f4e1 Remove unused ARMISD::AND selection DAG node. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116566 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 04:34:40 +00:00
Bob Wilson
cfbece50f6 ARM instructions that are both predicated and set the condition codes 
have been printed with the "S" modifier after the predicate.  With ARM's
unified syntax, they are supposed to go in the other order.  We fixed this
for Thumb when we switched to unified syntax but missed changing it for
ARM.  Apparently we don't generate these instructions often because no one
noticed until now.  Thanks to Bill Wendling for the testcase!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116563 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 03:23:44 +00:00
Jim Grosbach
197a8df640 Encoding info for extension instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116560 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 02:29:58 +00:00
Jim Grosbach
58456c0b04 Add missing Rd encoding for MOVs instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116537 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 23:28:31 +00:00
Jim Grosbach
7032f922b1 Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos 
and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116534 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 22:57:13 +00:00
Jim Grosbach
792e9796b3 Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx' 
pseudonym.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116512 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 20:43:44 +00:00
Jim Grosbach
1de588df69 MOVi16 and MOVT ARM mode encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116498 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 18:54:27 +00:00
Jim Grosbach
2d294f564b Simplify encoding information and add 'dst' operand info for TAILJMP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116488 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 17:24:28 +00:00
Oscar Fuentes
7bd698153d Remove explicit dependency of LLVMARMCodeGen on LLVMARMAsmPrinter. It 
creates a cyclic dependency that breaks the build when
BUILD_SHARED_LIBS=ON

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116480 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 15:54:46 +00:00
Eric Christopher
eae8439771 Handle more complex GEP based loads and add a few TODOs to deal with 
GEP + alloca.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116474 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 09:29:41 +00:00
Bill Wendling
bbbdcd453d Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on 
here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116471 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 02:33:26 +00:00
Bill Wendling
946a2740a5 Add encoding for 'fmstat'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116466 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 01:19:34 +00:00
Bill Wendling
88cf038436 - Add encodings for multiply add/subtract instructions in all their glory. 
- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116464 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 01:02:08 +00:00
Jim Grosbach
bd38acfa6f Regenerate. No functional change, just cleanup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116459 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 00:15:18 +00:00
Jim Grosbach
55561d1882 Detabify and clean up 80 column violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116454 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 23:47:11 +00:00
Jim Grosbach
95369599c6 A few 80 column fixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116451 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 23:34:31 +00:00
Jim Grosbach
3a37866e53 trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116450 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 23:12:26 +00:00
Jim Grosbach
b4b07b93ea Add a FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116449 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 22:55:33 +00:00
Jim Grosbach
06ef444e5c Add operand encoding bits for SMC and SVC in ARM mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116447 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 22:38:23 +00:00
Jim Grosbach
832859d062 More encoding cleanup. Also add register Rd operands for indirect branches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116444 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 22:09:34 +00:00
Jim Grosbach
a7dbc1ead7 Simplify some ARM encoding information. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116440 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 21:48:54 +00:00
Eric Christopher
a9c575110f Update comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116438 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 21:41:51 +00:00
Jim Grosbach
6c354fd3f5 Add a FIXME. The ADR instruction is a bit odd. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116437 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 21:32:30 +00:00
Jim Grosbach
b3af5de2d9 Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern 
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116432 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 21:00:04 +00:00
Bill Wendling
67a704de03 Add MC encodings for VCVT* instrunctions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116431 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 20:58:46 +00:00
Jim Grosbach
596307e133 Add a FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116428 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 20:38:04 +00:00
Jim Grosbach
fa7d2cb680 Make a few more bits of some simple instructions explicit. nop, yield, wfe, 
wfi, sel, sev and bkpt. All would disassemble properly before, but more
explicitness is good, especially with the integrated assembler coming in
the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116427 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 20:30:55 +00:00
Jim Grosbach
b35ad41fef Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116421 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 19:56:10 +00:00
Jim Grosbach
e822f94509 Fix encoding for compares. No Rd register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116414 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 18:05:25 +00:00
Jim Grosbach
24989ecc70 Add ARM mode operand encoding information for ADDE/SUBE instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116412 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 18:00:52 +00:00
Rafael Espindola
6d8628061b Fix another case where we were preferring instructions with large 
immediates instead of 8 bits ones.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116410 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 17:14:25 +00:00
Rafael Espindola
dba81cf40e Fix PR8365 by adding a more specialized Pat that checks if an 'and' with 
8 bit constants can be used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116403 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 13:31:20 +00:00
Eric Christopher
ede42b0a22 Start handling more global variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116401 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 09:11:46 +00:00
Evan Cheng
14ce175216 Limit load / store issues (at least until we have a true multi-issue aware scheduler). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116389 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 01:54:21 +00:00
Bill Wendling
6932643a37 Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test 
just yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116386 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 01:17:33 +00:00
Bill Wendling
54908dd72b Add encodings for VCVT instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116385 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 00:56:35 +00:00
Jim Grosbach
89c898f8af Add ARM encoding information for comparisons, forced-cc-out arithmetics, and 
arithmetic-with-carry-in instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116384 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 00:50:27 +00:00
Bill Wendling
1fc6d8837f Add VCMPZ and VABS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116383 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 00:38:07 +00:00
Bill Wendling
cd77686254 Refactor VCMP instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116379 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 00:04:29 +00:00
Jim Grosbach
ef324d7044 Add the rest of the ARM so_reg encoding options (register shifted register) 
and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116377 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:53:58 +00:00
Bill Wendling
5a1fd8cf68 Add encodings for VNMUL[SD]. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116375 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:47:37 +00:00
Bill Wendling
caa3d467ab Add encodings for VDIV and VMUL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116370 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:22:27 +00:00
Evan Cheng
3f490f3469 Turn some fp stackifier assertion into errors to avoid silently generating bad code when assertions are off. rdar://8540457. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116368 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:19:28 +00:00
Jim Grosbach
2a6a93d542 Move the ARM so_imm encoding into a custom operand encoder and remove the 
explicit handling of the instructions referencing it from the MC code
emitter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116367 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:18:08 +00:00
Bill Wendling
52061f83e7 Refactor some of the encoding logic into a base class. This keeps us from having 
to add 10+ lines to every instruction.

It may turn out that we can move this base class into it's parent class.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116362 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:06:54 +00:00
Jim Grosbach
08bd54987f Add custom encoder for the 's' bit denoting whether an ARM arithmetic 
instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116360 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:00:24 +00:00
Bill Wendling
dd3bc112e6 Add encoding for VSUB and VCMP. 
Fear not! I'm going to try a refactoring right now. :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116359 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 22:55:35 +00:00
Bill Wendling
174777bb2b Encoding for VADDD. Plus a test for the VFP instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116348 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 22:08:41 +00:00
Bill Wendling
a0c14ef8f6 Split out the "size" field from the encoding. The newer documentation has it as 
a separate bit in the coding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116347 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 22:03:19 +00:00
Eric Christopher
558cf007b5 Fix thinko in arm fast isel alloca rewrite. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116339 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 21:23:43 +00:00
Jim Grosbach
499e886fe6 Encoding for ARM-mode VADD.F32 instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116338 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 21:22:40 +00:00
Eric Christopher
52b45056b2 Combine these together - should probably have some text associated 
that says what why what we just asserted is wrong.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116333 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 19:44:17 +00:00
Nick Lewycky
65b65d6ca4 Mark variable 'NoImplicitFloatOps' used only in an assert as used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116323 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 18:18:03 +00:00
Jim Grosbach
f59818b81a Add MOVi ARM encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116321 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 18:09:12 +00:00
Dan Gohman
320afb8c81 Initial va_arg support for x86-64. Patch by David Meyer! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116319 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 18:00:49 +00:00
Jim Grosbach
8e157302f4 Nuke unused wrapper function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116318 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 17:53:25 +00:00
Jakob Stoklund Olesen
d0eeeeb558 Remove the x86 MOV{32,64}{rr,rm,mr}_TC instructions. 
The reg-reg copies were no longer being generated since copyPhysReg copies
physical registers only.

The loads and stores are not necessary - The TC constraint is imposed by the
TAILJMP and TCRETURN instructions, there should be no need for constrained loads
and stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116314 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 17:15:00 +00:00
Jim Grosbach
0de6ab3c43 Add encoding information for the remainder of the generic arithmetic 
ARM instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116313 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 17:11:26 +00:00
Bob Wilson
77f42b5278 PR8359: The ARM backend may end up allocating registers D16 to D31 when 
"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers.  Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116310 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 16:22:47 +00:00
Eric Christopher
1541877941 Rework alloca handling so that we can load or store from casted 
address that we've looked through.

Fixes compilation problems in tramp3d from earlier patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116296 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 05:39:06 +00:00
Eric Christopher
5532433a57 Handle a wider arrangement of loads. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116284 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 00:43:21 +00:00
Evan Cheng
08cec1ef27 More ARM scheduling itinerary fixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116266 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 23:41:41 +00:00
Jim Grosbach
42fac8ee3b MC machine encoding for simple aritmetic instructions that use a shifted 
register operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116259 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 23:16:21 +00:00
Jason W Kim
17b443df43 Second set of ARM/MC/ELF changes. 
Added ARM specific ELF section types.
Added AttributesSection to ARMElfTargetObject
First step in unifying .cpu assembly tag with ELF/.o
llc now asserts on actual ELF emission on -filetype=obj :-)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116257 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 23:01:44 +00:00
Evan Cheng
60ff87914f Proper VST scheduling itineraries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116251 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 22:03:18 +00:00
Eric Christopher
5f9e8b971b Use a sane mechanism for that assert. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116249 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 22:01:22 +00:00
Eric Christopher
050d16c2a9 We're not going to handle dynamic allocas anywhere else. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116240 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 21:37:35 +00:00
Eric Christopher
fb0b892f7e Make sure that the call stack adjustments have default operands. Also 
leave custom lowerings for later.

Fixes some nightly tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116232 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 21:20:02 +00:00
Jakob Stoklund Olesen
4f9af2ef65 PowerPC varargs functions store live-in registers on the stack. Make sure we use 
virtual registers for those stores since RegAllocFast requires that each live
physreg only be used once.

This fixes PR8357.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116222 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 20:43:09 +00:00
Eric Christopher
8ff9a9da0a Found a bug turning this on by default. Disable again for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116220 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 20:26:21 +00:00
Eric Christopher
fa6b29dacd Fix help text. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116218 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 20:15:02 +00:00
Eric Christopher
feadddd6b6 Change flag from Enable to Disable since we're enabled by default. 
Also don't use fast-isel on non-darwin since it's untested.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116217 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 20:05:22 +00:00
Andrew Trick
1a2cf3b4d9 Fixes bug 8297: i386 cmpxchg8b, missing MachineMemOperand 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116214 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 19:02:04 +00:00
Jim Grosbach
62547267f0 More binary encoding stuff, taking advantage of the new "by name" operand 
matching in tblgen to do the predicate operand.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116213 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 18:51:51 +00:00
Eric Christopher
a2efc5ff6e Turn on arm fast isel by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116212 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 18:48:18 +00:00
Francois Pichet
1265776243 MSVC hangs on compilation of ARMDisassembler.cpp. PR6866 applied to ARM target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116201 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 11:36:19 +00:00
Eric Christopher
a1640d9ed9 Copy and pasteo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116198 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 08:40:05 +00:00
Eric Christopher
dccd2c3c43 Whitespace cleanup in ARM fast isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116197 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 08:38:55 +00:00
Eric Christopher
6a880d6ba8 Add srem libcall support to ARM fast isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116196 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 08:37:26 +00:00
Eric Christopher
7bdc4de4e7 Add i8 sdiv support for ARM fast isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116195 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 08:31:54 +00:00
Eric Christopher
3bbd396853 Implement select handling for ARM fast-isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116194 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 08:27:59 +00:00
Chris Lattner
60cb528246 Per discussion with Sanjiv, remove the PIC16 target from mainline. When/if 
it comes back, it will be largely a rewrite, so keeping the old codebase
in tree isn't helping anyone.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116190 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 05:44:40 +00:00
Michael J. Spencer
335b806c62 X86: Call ulldiv and ftol2 on Windows instead of their libgcc eqivilents. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116188 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 05:29:15 +00:00
Michael J. Spencer
92bf38c956 X86: MinGW should always use libgcc on Windows. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116177 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-10 23:11:06 +00:00
Michael J. Spencer
1802a9f8fe X86: Call _alldiv instead of __divdi3 on Windows (excluding cygwin). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116174 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-10 22:04:34 +00:00
Michael J. Spencer
ec38de2ca8 Fix Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116173 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-10 22:04:20 +00:00
Chris Lattner
749dc72bdc fix the expansion of va_arg instruction on PPC to know the arg 
alignment for PPC32/64, avoiding some masking operations.

llvm-gcc expands vaarg inline instead of using the instruction
so it has never hit this.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116168 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-10 18:34:00 +00:00
Michael J. Spencer
c0c8df3cea Fix Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116149 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-09 11:00:50 +00:00