Daniel Dunbar
77e2dd7bb2
X86: Mark JMP{32,64}[mr] as requires 32-bit/64-bit mode. They are the same
...
instruction, we only want to allow the one for the current subtarget.
- This also fixes suffix matching for jmp instructions, because it eliminates
the ambiguity between 'jmpl' and 'jmpq'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 20:44:16 +00:00
Daniel Dunbar
e4c52a2c41
X86: Mark some tail call pseduo instruction as code gen only.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108684 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 07:21:04 +00:00
Daniel Dunbar
df4c47be29
X86: Mark In32/64BitMode on LEAVE[64] and SYSEXIT[64].
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108683 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 07:21:01 +00:00
Daniel Dunbar
cf246b7f0b
X86: Mark MOV.*_{TC,NOREX} instruction as code gen only, they aren't real.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108680 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 06:14:49 +00:00
Daniel Dunbar
6c2c9a27c5
X86: MOV8o8a, MOV8ao8, etc. are only valid in 32-bit mode.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108679 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 06:14:44 +00:00
Bruno Cardoso Lopes
e86b01c153
Start the support for AVX instructions with 256-bit %ymm registers. A couple of
...
notes:
- The instructions are being added with dummy placeholder patterns using some 256
specifiers, this is not meant to work now, but since there are some multiclasses
generic enough to accept them, when we go for codegen, the stuff will be already
there.
- Add VEX encoding bits to support YMM
- Add MOVUPS and MOVAPS in the first round
- Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
- All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107996 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 18:27:43 +00:00
Chris Lattner
c5f5626a29
have the mc lowering process handle a few tail call forms, lowering them to
...
jumps where possible and turning the TAILCALL marker in the instruction
asm string into a proper comment.
This eliminates a FIXME and is on the path to finishing:
rdar://7639610 - eliminate encoding and asm info for TAILJMPd TAILJMPr TAILJMPn, etc.
However, I can't eliminate the encodings for these instructions because the JIT
still exists and has its own copy of the encoder, sigh.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107946 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 00:49:41 +00:00
Chris Lattner
599b531a96
Change LEA to have 5 operands for its memory operand, just
...
like all other instructions, even though a segment is not
allowed. This resolves a bunch of gross hacks in the
encoder and makes LEA more consistent with the rest of the
instruction set.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107934 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 23:46:44 +00:00
Chris Lattner
9fc05227a2
Implement the major chunk of PR7195: support for 'callw'
...
in the integrated assembler. Still some discussion to be
done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107825 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 22:27:31 +00:00
Eric Christopher
37106afe02
Add a couple more quick comments.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106717 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 02:07:57 +00:00
Eric Christopher
749bb7e2d9
Update according to feedback.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106677 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 20:49:35 +00:00
Nico Weber
50b9efc2a8
Add support for the x86 instructions "pusha" and "popa".
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106671 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 20:00:58 +00:00
Eric Christopher
18ebf74781
Update uses, defs, and comments for darwin tls patterns.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106621 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 08:01:49 +00:00
Eric Christopher
a938cfb13a
Finish ripping isTwoAddress out of X86. Some mindless formatting
...
and operand renaming to help.
The giant turn the constraints on and selectively turn it off
should probably be inverted at some point since it's just largely
50/50.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106367 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 00:37:40 +00:00
Eric Christopher
544153653b
Ensure that mov and not lea are used to stick the address into
...
the register. While we're at it, make sure it's in the right one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105645 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-08 22:04:25 +00:00
Eric Christopher
30ef0e5658
Add first pass at darwin tls compiler support.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105381 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-03 04:07:48 +00:00
Daniel Dunbar
dcbab9cf5a
AsmMatcher/X86: Mark _REV instructions as "code gen only", they aren't expected
...
to be matched.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104757 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 22:21:28 +00:00
Kevin Enderby
b106543592
Fix the x86 move to/from segment register instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104731 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 20:10:45 +00:00
Jakob Stoklund Olesen
3458e9e4df
Rename X86 subregister indices to something shorter.
...
Use the tablegen-produced enums.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104493 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 14:48:17 +00:00
Daniel Dunbar
62e4c671b6
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example:
...
addw $0xFFFF, %ax
should match the same as
addw $-1, %ax
but we used to match it to the longer encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104453 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 21:02:33 +00:00
Daniel Dunbar
54ddf3d9c7
tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104452 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 21:02:29 +00:00
Daniel Dunbar
1fe591da3e
X86: Model i64i32imm properly, as a subclass of all immediates.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104272 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:20:39 +00:00
Dan Gohman
e5e4ff974d
Fix assembly parsing and encoding of the pushf and popf family of
...
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104231 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 16:16:00 +00:00
Daniel Dunbar
52322e7b8b
MC/X86: Lower TAILCALLd[64] to JMP_1, to allow relaxation and to avoid same
...
prefix byte problem as in r104062.
- As a total hack to keep the TAILCALL markers in the output, which some tests depend on, this invents a new TAILJMP_1 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104120 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 15:26:43 +00:00
Kevin Enderby
c3ce05c594
Fix so "int3" is correctly accepted, added "into" and fixed "int" with an
...
argument, like "int $4", to not get an Assertion error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103791 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 19:16:02 +00:00
Dan Gohman
effc8c5269
Set isTerminator on TRAP instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103778 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 16:46:02 +00:00
Dan Gohman
7f357ec6d2
Add mayLoad and mayStore flags to instructions which missed them.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103776 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 16:34:55 +00:00
Chris Lattner
b5505d0ee3
reapply r103668 with a fix. Never make "minor syntax changes"
...
after testing before committing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103681 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 00:02:47 +00:00
Chris Lattner
3519f9d7d1
revert r103668 for now, it is apparently breaking things.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103677 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-12 23:40:59 +00:00
Chris Lattner
0de8e3f10a
moffset forms of moves are x86-32 only, make the parser
...
lower them to the correct x86-64 instructions since we
don't have a clean way to handle this in td files yet.
rdar://7947184
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103668 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-12 23:13:36 +00:00
Chris Lattner
2745f6e920
fix the encoding of the obscure "moffset" forms of moves, i386
...
part first. rdar://7947184
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103660 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-12 22:48:24 +00:00
Daniel Dunbar
c26ae5ab7e
MC/X86: X86AbsMemAsmOperand is subclass of X86NoSegMemAsmOperand.
...
- This fixes "leal 0, %eax", for example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103205 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 22:39:14 +00:00
Sean Callanan
1a8b789a4b
Eliminated the classification of control registers into %ecr_
...
and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103196 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 20:59:00 +00:00
Kevin Enderby
3c979b06c0
Fixed the encoding of the x86 push instructions. Using a 32-bit immediate value
...
caused the a pushl instruction to be incorrectly encoding using only two bytes
of immediate, causing the following 2 instruction bytes to be part of the 32-bit
immediate value. Also fixed the one byte form of push to be used when the
immediate would fit in a signed extended byte. Lastly changed the names to not
include the 32 of PUSH32 since they actually push the size of the stack pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102951 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-03 20:45:05 +00:00
Dan Gohman
71edb241a1
Remove the -disable-16bit command-line option, which is now obsolete.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102730 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-30 18:30:26 +00:00
Kevin Enderby
9ac7282117
Fixed the word sized Bit Scan Forward/Reverse instructions, they needed the
...
Operand size override prefix to be part of their records.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102556 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-28 23:20:40 +00:00
Evan Cheng
2bce5f4b56
Enable i16 to i32 promotion by default.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102493 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-28 08:30:49 +00:00
Evan Cheng
8b1190a540
Rather than having a ton of patterns for double shift instructions, e.g. SHLD16rrCL, just perform custom dag combine to form x86 specific dag so they match to the same pattern. This also makes sure later dag combine do not cause isel to miss them (e.g. promoting i16 to i32).
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102485 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-28 01:18:01 +00:00
Evan Cheng
1c45acf510
Fix obvious typos.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102467 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-27 21:46:03 +00:00
Evan Cheng
5528e7bcb1
isel (i32 anyext i16) as insert_subreg when 16-bit ops are being promoted.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101979 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21 01:47:12 +00:00
Evan Cheng
e5b51ac770
More work to allow dag combiner to promote 16-bit ops to 32-bit.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101621 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 06:13:15 +00:00
Evan Cheng
18ac410f4f
Fix ADD32rr_alt instruction encoding bug. Patch by Marius Wachtler.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100480 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-05 22:21:09 +00:00
Eric Christopher
6d1cd1cd04
Separate out the AES-NI instructions from the SSE4.2 instructions. Add
...
a new subtarget option for AES and check for the support. Add "westmere"
line of processors and add AES-NI support to the core i7.
Add a couple of TODOs for information I couldn't verify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100231 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 21:54:27 +00:00
Chris Lattner
ed52c8f5f4
revert r99743, this is saying that the repmovs instructinos have an
...
*input* of other type, which is the VT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99749 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-28 07:38:39 +00:00
Chris Lattner
0b5d4908dd
claiming to return other is pointless.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99743 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-28 05:57:36 +00:00
Chris Lattner
d486d77444
fix some modelling problems exposed by a patch I'm working on. bsr/bsf/ptest
...
nodes all have an EFLAGS result when made by isel lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99736 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-28 05:07:17 +00:00
Chris Lattner
baba4bb72f
eliminate the last of the parallel's!
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99700 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-27 02:47:14 +00:00
Chris Lattner
ec856800da
eliminate almost all the rest of the x86-32 parallels.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99686 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-27 00:45:04 +00:00
Jakob Stoklund Olesen
70feca409e
Teach TableGen to understand X.Y notation in the TSFlagsFields strings.
...
Remove much horribleness from X86InstrFormats as a result. Similar
simplifications are probably possible for other targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99539 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25 18:52:01 +00:00
Chris Lattner
589ad5d8c2
eliminate a bunch more parallels now that scheduling
...
handles dead implicit results more aggressively. More
to come, I think this is now just a data entry problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99486 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25 05:44:01 +00:00
Evan Cheng
cb0f06e05c
Disable folding loads into tail call in 32-bit PIC mode. It can introduce illegal code like this:
...
addl $12, %esp
popl %esi
popl %edi
popl %ebx
popl %ebp
jmpl *__Block_deallocator-L1$pb(%esi) # TAILCALL
The problem is the global base register is assigned GR32 register class. TCRETURNmi needs the registers making up the address mode to have the GR32_TC register class.
The *proper* fix is for X86DAGToDAGISel::getGlobalBaseReg() to return a copy from the global base register of the machine function rather than returning the register itself. But that has the potential of causing it to be coalesced to a more restrictive register class: GR32_TC. It can introduce additional copies and spills. For something as important the PIC base, it's not worth it especially since this is not an issue on 64-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99455 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25 00:10:31 +00:00
Chris Lattner
c54a2f150d
Switch INC8r to defining its pattern in terms of X86inc_flag
...
and defining the add pattern with Pat<>, eliminating a use of
parallel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99375 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 01:02:12 +00:00
Chris Lattner
1aec4d7596
switch SDTBinaryArithWithFlags to be a multiple-result node as well.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99370 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 00:49:29 +00:00
Chris Lattner
74c8d67af8
Switch SDTUnaryArithWithFlags to being modeled as a two-result
...
ISD node. The only change in the generated isel code are comments
like:
< // Src: (X86dec_flag:i16 GR16:i16:$src)
---
> // Src: (X86dec_flag:i16:i32 GR16:i16:$src)
because now it knows that X86dec_flag returns both an i16 (for the result)
and an i32 (for EFLAGS) in this case. Wewt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99369 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 00:47:47 +00:00
Chris Lattner
a0f7017752
remove useless or_is_add parallel's.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99359 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 00:15:23 +00:00
Chris Lattner
fdac0b66f0
reduce nesting.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99358 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 00:12:57 +00:00
Chris Lattner
99521af212
remove the patterns that I commented out in r98930, Dan verified
...
that they are dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99000 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 21:43:36 +00:00
Chris Lattner
e8cabf3c2e
add a new SDNPVariadic SDNP node flag, and use it in
...
dag isel gen instead of instruction properties. This
allows the oh-so-useful behavior of matching a variadic
non-root node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98934 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 05:07:09 +00:00
Chris Lattner
1d7dbd1716
comment out a bunch of parallel store patterns that apparently
...
can't match or just have no testcases. Will remove after
confirmation from dan that they really are dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98930 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 04:14:21 +00:00
Chris Lattner
e3486a4c9a
Now that tblgen can handle matching implicit defs of instructions
...
to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking
two inputs (which have to be the same type) and *returning an i32*.
This is how the SDNodes get made in the graph, but we weren't able
to model it this way due to deficiencies in the pattern language.
Now we can change things like this:
def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
- [(X86cmp RFP80:$lhs, RFP80:$rhs),
- (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
+ [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>;
and fix terrible crimes like this:
-def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
+def : Pat<(X86cmp GR8:$src1, 0),
(TEST8rr GR8:$src1, GR8:$src1)>;
This relies on matching the result of TEST8rr (which is EFLAGS, which is
an implicit def) to the result of X86cmp, an i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 00:01:11 +00:00
Chris Lattner
34b8a8857c
outs come before ins.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98864 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 20:50:06 +00:00
Chris Lattner
840e6371ea
fix the encoding of TAILJMPd. This fixes Benchmarks/Olden/bisort
...
with the integrated assembler!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98615 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-16 06:30:18 +00:00
Chris Lattner
da0688e08a
fix PR6605, X86ISD::CMP always returns i32 (EFLAGS), not
...
the operand type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98507 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14 18:44:35 +00:00
Chris Lattner
314a113184
add support for pentium class CPUs which do not have cmov,
...
PR4841. Patch by Craig Smith!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98496 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14 18:31:44 +00:00
Evan Cheng
f48ef03655
Do not force indirect tailcall through fixed registers: eax, r11. Add support to allow loads to be folded to tail call instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98465 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14 03:48:46 +00:00
Daniel Dunbar
f291be3159
MC/X86: Rename alternate spellings of ADD{8,16,32} and mark as "code gen only" so they don't get selected by the asm matcher.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98098 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-09 22:50:46 +00:00
Daniel Dunbar
1e8ee89c21
MC/X86: Rename alternate spellings of CMP{8,16,32} and mark as "code gen only" so they don't get selected by the asm matcher.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98097 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-09 22:50:40 +00:00
Kevin Enderby
0e822407b2
Fix the vmxon entry in the X86InstrInfo.td so it has the correct prefix bytes
...
for the encoding and is not the same as vmptrld.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97992 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-08 22:17:26 +00:00
Daniel Dunbar
b93c72cda4
X86: Fix encoding for TEST{8,16,32}rr.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97982 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-08 21:10:36 +00:00
Chris Lattner
341b27406d
Correct immediate sizes.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97957 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-08 18:55:15 +00:00
Anton Korobeynikov
e765f2b5e3
Describe what's going on with mingw alloca and why do we need separate instruction.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97888 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-06 20:07:32 +00:00
Anton Korobeynikov
043f3c2a0e
Lower dynamic stack allocation on mingw32 to separate instruction.
...
We cannot use a normal call here since it has extra unmodelled side
effects (it changes stack pointer). This should fix PR5292.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97884 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-06 19:32:29 +00:00
Jakob Stoklund Olesen
3cfe01072c
Fix the remaining MUL8 and DIV8 to define AX instead of AL,AH.
...
These instructions technically define AL,AH, but a trick in X86ISelDAGToDAG
reads AX in order to avoid reading AH with a REX instruction.
Fix PR6489.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97742 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-04 20:42:07 +00:00
Chris Lattner
99fe641325
remove nvload and two patterns that use it which are
...
better done by dag combine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97633 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-03 02:14:54 +00:00
Chris Lattner
f85eff76b2
factor the 'in the default address space' check out to a single
...
'dsload' pattern. tblgen doesn't check patterns to see if they're
textually identical. This allows better factoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97630 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-03 01:52:59 +00:00
Chris Lattner
1840991d54
factor the 'sign extended from 8 bit' patterns better so
...
that they are not destination type specific. This allows
tblgen to factor them and the type check is redundant with
what the isel does anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97629 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-03 01:45:01 +00:00
Dan Gohman
bc9d98b52d
The mayHaveSideEffects flag is no longer used.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97348 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-27 23:47:46 +00:00
Jakob Stoklund Olesen
c3027f769a
DIV8r must define %AX since X86DAGToDAGISel::Select() sometimes uses it
...
instead of %AL/%AH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97006 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-24 00:39:35 +00:00
Chris Lattner
6d9f86b773
remove a bunch of dead named arguments in input patterns,
...
though some look dubious afaict, these are all ok.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96899 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-23 06:54:29 +00:00
Sean Callanan
cebe955779
Added the rdtscp instruction to the x86 instruction
...
tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96073 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-13 02:06:11 +00:00
Sean Callanan
95a5a7d570
Fixed encodings for invlpg, invept, and invvpid.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96065 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-13 01:48:34 +00:00
Chris Lattner
a599de2410
remove special cases for vmlaunch, vmresume, vmxoff, and swapgs
...
fix swapgs to be spelled right.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96058 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-13 00:41:14 +00:00
Chris Lattner
a0331199fc
enhance the immediate field encoding to know whether the immediate
...
is pc relative or not, mark call and branches as pcrel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96026 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-12 22:27:07 +00:00
Chris Lattner
fdfeb6976f
Add support for a union type in LLVM IR. Patch by Talin!
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96011 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-12 20:49:41 +00:00
Daniel Dunbar
ccfa1db538
X86: Fix definition for RCL/RCR.*m? operations -- they were getting represented
...
with "tied memory operands", which is wrong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95950 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-12 01:22:03 +00:00
Chris Lattner
b8db331588
improve encoding information for branches. We now know they have
...
8 or 32-bit immediates, which allows the new encoder to handle
them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95927 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-11 21:45:31 +00:00
Chris Lattner
8b442a814e
unbreak the build.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95915 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-11 19:52:11 +00:00
Chris Lattner
bd13fb6254
refactor the conditional jump instructions in the .td file to
...
use a multipattern that generates both the 1-byte and 4-byte
versions from the same defm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95901 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-11 19:25:55 +00:00
Dan Gohman
f451cb870e
Fix "the the" and similar typos.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95781 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-10 16:03:48 +00:00
David Greene
51898d7a89
TableGen fragment refactoring.
...
Move some utility TableGen defs, classes, etc. into a common file so
they may be used my multiple pattern files. We will use this for
the AVX specification to help with the transition from the current
SSE specification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95727 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-09 23:52:19 +00:00
Chris Lattner
8f60e4d679
fix incorrect encoding of SBB8mi that Kevin noticed.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95448 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-05 22:56:11 +00:00
Chris Lattner
35e0e84f93
teach X86MCInstLower to lower the MOV32r0 and MOV8r0
...
pseudo instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95433 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-05 21:21:06 +00:00
Chris Lattner
c74e333ecc
factor code better in X86MCInstLower::Lower, teach it to
...
lower the SETB* instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95431 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-05 21:13:48 +00:00
Kevin Enderby
12ce0de462
Added support for X86 instruction prefixes so llvm-mc can assemble them. The
...
Lock prefix, Repeat string operation prefixes and the Segment override prefixes.
Also added versions of the move string and store string instructions without the
repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of
move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is
happy building the disassembler files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95252 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-03 21:04:42 +00:00
Evan Cheng
aa92bec010
Change TAILJMP's to be varargs and transfer implicit uses over from TCRETURN's. Otherwise the missing uses can make post-regalloc scheduling do bad things. This fixes 403.gcc.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94950 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-31 07:28:44 +00:00
Daniel Dunbar
b834f5d13d
MC/X86 AsmParser: Handle absolute memory operands correctly. We were doing
...
something totally broken and parsing them as immediates, but the .td file also
had the wrong match class so things sortof worked. Except, that is, that we
would parse
movl $0, %eax
as
movl 0, %eax
Feel free to guess how well that worked.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94869 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-30 01:02:48 +00:00
Daniel Dunbar
728e5eb927
X86.td: Refactor to bring operands that use print_pcrel_imm together.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94861 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-30 00:24:12 +00:00
Daniel Dunbar
ec2b1f1beb
AsmMatcher/X86: Separate out sublass for memory operands that have no segment
...
register, and use to cleanup a FIXME in X86AsmParser.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94859 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-30 00:24:00 +00:00
Evan Cheng
3bda20112e
Eliminate or_not_add and just use AddedComplexity so isel tries or_is_add patterns first.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93245 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-12 18:31:19 +00:00
Dan Gohman
f1b4d26e67
Reapply the MOV64r0 patch, with a fix: MOV64r0 clobbers EFLAGS.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93229 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-12 04:42:54 +00:00
Evan Cheng
199c4240fe
Extend r93152 to work on OR r, r. If the source set bits are known not to overlap, then select as an ADD instead.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93191 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-11 22:03:29 +00:00
Evan Cheng
05920b8146
Revert 93158. It's breaking quite a few x86_64 tests.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93185 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-11 21:13:41 +00:00
Evan Cheng
ac000fa0ed
Do not turn 8-bit OR to ADD since ADD8ri is not 3-addressfiable.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93182 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-11 20:18:04 +00:00
Dan Gohman
71c25b7d7b
Re-instate MOV64r0 and MOV16r0, with adjustments to work with the
...
new AsmPrinter. This is perhaps less elegant than describing them
in terms of MOV32r0 and subreg operations, but it allows the
current register to rematerialize them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93158 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-11 17:37:57 +00:00
Dan Gohman
7e0d64a49c
Pattern top-level operators don't need to be restricted to a
...
single user. The _su forms are intended for non-top-level nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93155 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-11 17:21:05 +00:00
Evan Cheng
4b0345be30
Select an OR with immediate as an ADD if the input bits are known zero. This allow the instruction to be 3address-fied if needed.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93152 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-11 17:03:47 +00:00
Evan Cheng
b093bd0565
Fix what looks to me obvious instruction definition bugs.
...
1. CMPXCHG8B and CMPXCHG16B did not specify implicit physical register defs and uses.
2. LCMPXCHG8B is loading 64 bit memory, not 32 bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92985 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-08 01:29:19 +00:00
Dan Gohman
4361bbfd0e
Remove the SDNPAssociative properties for the flags-producing
...
operators. Eli pointed out that it's not obvious what that
would mean.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92555 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-05 00:44:20 +00:00
Dan Gohman
43ffe6769a
Add SDNPCommutative and SDNPAssociative to several X86 target nodes.
...
This lets isel fold loads into them in more cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92506 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-04 20:51:05 +00:00
Eli Friedman
ba7b1c4db4
PR5886: Make sure IMUL32m is marked as setting EFLAGS, so scheduling doesn't
...
do illegal stuff around it. No testcase because the issue is very fragile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92167 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-26 20:08:30 +00:00
Chris Lattner
ac105c4dca
really remove the instruction, don't just comment it out
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91976 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-23 01:46:40 +00:00
Chris Lattner
9e3238303c
completely eliminate the MOV16r0 'instruction'. The only
...
interesting part of this is the divrem changes, which are
already tested by CodeGen/X86/divrem.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91975 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-23 01:45:04 +00:00
Chris Lattner
6a38182471
stop pattern matching 16-bit zero's of a register to MOV16r0,
...
instead use the appropriate subreggy thing. This generates identical
code on some large apps (thanks to Evan's cross class coalescing
stuff he did back in july). This means that MOV16r0 can go away
completely in the future soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91972 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-23 01:30:26 +00:00
Evan Cheng
b1f4981333
Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91910 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-22 17:47:23 +00:00
Evan Cheng
400073d546
On recent Intel u-arch's, folding loads into some unary SSE instructions can
...
be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.
movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0
instead of
cvtss2sd (%rdi), %xmm0
An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91672 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 07:40:29 +00:00
Sean Callanan
108934c65d
Instruction fixes, added instructions, and AsmString changes in the
...
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
Evan Cheng
2e489c4f9d
Re-enable 91381 with fixes.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91489 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-16 00:53:11 +00:00
Evan Cheng
ad9c0a3d8b
Use sbb x, x to materialize carry bit in a GPR. The result is all one's or all zero's.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91381 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-15 00:53:42 +00:00
Evan Cheng
15b0d97068
Fix an obvious bug. No test case since LEA16r is not being used.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91219 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-12 18:51:56 +00:00
Dan Gohman
39a1fab856
Minor whitespace fixes.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90166 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-30 23:33:53 +00:00
Dan Gohman
735afe14ee
Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.
...
Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89711 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-23 23:20:51 +00:00
Dan Gohman
e94975ee64
Use a tab in INT3's asm string, for consistency.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86850 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-11 18:07:16 +00:00
Anton Korobeynikov
3a639a07ea
Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364.
...
PS: It seems that blackfin usage of copy_to_regclass is completely bogus!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85766 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-02 00:11:39 +00:00
Dan Gohman
f705adbe5e
Initial x86 support for BlockAddresses.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85557 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-30 01:28:02 +00:00
Dan Gohman
533297b58d
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
...
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-29 18:10:34 +00:00
Dan Gohman
bab42bdd87
Following r84485, add Defs = [EFLAGS] to the 32-bit lock instructions too.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84652 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 18:14:49 +00:00
Chris Lattner
172862a2a7
remove strings from instructions who are never asmprinted.
...
All of these "subreg32" modifier instructions are handled
explicitly by the MCInst lowering phase. If they got to
the asmprinter, they would explode. They should eventually
be replace with correct use of subregs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84526 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 19:51:42 +00:00
Chris Lattner
71c7ace54f
remove the asmstring, it is now dead. Improve comment.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82390 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-20 07:32:00 +00:00
Chris Lattner
b3c8547cb8
kill off printPICLabel now, it's specialness is handled by
...
the MachineInstr ->MCInst lowering process, not in the
asmprinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82388 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-20 07:28:26 +00:00
Chris Lattner
e895c61515
Add an intel syntax MCInstPrinter implementation. You can now
...
transcode from AT&T to intel syntax with "llvm-mc foo.s -output-asm-variant=1"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82385 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-20 07:17:49 +00:00
Dan Gohman
e220c4b3d9
Add support for using the FLAGS result of or, xor, and and instructions
...
on x86, to avoid explicit test instructions. A few existing tests changed
due to arbitrary register allocation differences.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82263 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-18 19:59:53 +00:00
Sean Callanan
a2dc2825fc
Added RCL and RCR (rotate left and right with a
...
carry bit) instructions to the Intel instruction
tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82260 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-18 19:35:23 +00:00
Sean Callanan
9a86f10875
Added the LODS (load byte into register, usually
...
as part string parsing) instructions to the Intel
instruction tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82089 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-16 22:59:28 +00:00
Sean Callanan
358f1ef765
Added the LAR (load segment access rights)
...
instructions to the Intel instruction tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82084 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-16 21:55:34 +00:00
Sean Callanan
7e6d727c9b
Added the LOOP family of instructions to the Intel
...
instruction tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82083 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-16 21:50:07 +00:00
Sean Callanan
d2125a03af
Added an alternate form of register-register CMP
...
to the Intel instruction tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82081 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-16 21:11:23 +00:00
Sean Callanan
8d70854dd8
Added the ENTER instruction, which sets up a stack
...
frame, to the Intel instruction tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81995 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-16 02:57:13 +00:00
Sean Callanan
13cf8e9b82
Added the definitions for one-bit left shifts to
...
the Intel instruction tables.
The patterns will stay blank because ADD reg, reg
is faster, but having the encoding available is
useful for the disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81994 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-16 02:28:43 +00:00
Sean Callanan
356aed540c
Added far return instructions (that is, returns to
...
code in other segments) to the Intel instruction
tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81953 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-15 23:37:51 +00:00
Sean Callanan
62c28e3f91
Updated comments per Eli's suggestion.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81923 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-15 21:43:27 +00:00
Sean Callanan
37be5903a6
Added register-to-register ADD instructions to the
...
Intel tables, where the source operand is
specified by the R/M field and the destination
operand by the Reg field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81914 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-15 20:53:57 +00:00
Sean Callanan
38fee0edcf
Added a new register class for segment registers
...
to the Intel register table.
Added 16- and 64-bit MOVs to and from the segment
registers to the Intel instruction tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81895 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-15 18:47:29 +00:00
Sean Callanan
76f14be685
Modified the Intel instruction tables to include
...
versions of CALL and JMP with segmented addresses
provided in-line, as pairs of immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81818 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-15 00:35:17 +00:00
Sean Callanan
2a46f3678e
Added the WAIT instruction to the Intel tables,
...
for the purposes of the disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81603 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-12 02:52:41 +00:00
Sean Callanan
6f8f462ba5
Added CMPS (string comparison) instructions for all
...
operand widths to the Intel instruction tables, for
the purposes of the disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81601 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-12 02:25:20 +00:00
Sean Callanan
a82e4656b0
Added SCAS instructions in their 8, 16, 32, and
...
64-bit variants for the disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81591 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-12 00:37:19 +00:00
Sean Callanan
d00025a6c8
Added ADC, SUB, SBB, and OR instructions that operate
...
on rAX and an immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81551 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-11 19:01:56 +00:00
Sean Callanan
7893ec6494
Added XOR instructions for rAX and immediates of
...
various widths.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81458 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-10 19:52:26 +00:00
Sean Callanan
2f34a136b5
Added MOV instructions between rAX and memory offsets,
...
including segment offsets and (for 8-bit operands)
absolute offsets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81457 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-10 18:33:42 +00:00
Sean Callanan
1f24e01b87
Added a variety of PUSH and POP instructions, including
...
ones capable of accessing R/M operands instead of just
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81456 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-10 18:29:13 +00:00