Chris Lattner
b2c0650ad3
Fix encoding of rotates, such as rldicl
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29128 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-12 22:08:13 +00:00
Chris Lattner
e4172be920
Add a pattern for i64 sra. Print 8-byte units with a space between the .quad
...
and the data
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28934 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-27 20:07:26 +00:00
Chris Lattner
b410dc9977
Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit file
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28889 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-20 23:18:58 +00:00
Chris Lattner
96dc5e5f6d
remove unused flag
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28888 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-20 23:15:07 +00:00
Chris Lattner
001db453f5
Add PowerPC intrinsics to support dcbz[l]
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28696 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-06 21:29:23 +00:00
Chris Lattner
d8242b49b2
Add all of the data stream intrinsics and instructions. woo
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27442 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 22:27:14 +00:00
Chris Lattner
4d9100ddc9
Add m[tf]vscr instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27421 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 00:03:57 +00:00
Chris Lattner
fb143ce459
Fix the JIT encoding of VSEL
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27160 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-27 03:34:17 +00:00
Chris Lattner
eeaf72af39
Fix the JIT encoding of VSPLTI*
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27159 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-27 03:28:57 +00:00
Chris Lattner
b8a45c2798
Add all of the altivec comparison instructions. Add patterns for the
...
non-predicate altivec compare intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27143 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-26 04:57:17 +00:00
Chris Lattner
e7d959c069
implement the vsldoi intrinsic.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27139 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-26 00:41:48 +00:00
Chris Lattner
eb8b09f69f
Fix the JIT encoding of the VAForm_1 instructions, including vmaddfp
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26935 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 01:44:36 +00:00
Chris Lattner
fd97734f36
Mark instructions that are cracked by the PPC970 decoder as such.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26720 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-13 05:15:10 +00:00
Chris Lattner
88d211f823
Several big changes:
...
1. Use flags on the instructions in the .td file to indicate the PPC970 unit
type instead of a table in the .cpp file. Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
accurately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26719 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-12 09:13:49 +00:00
Chris Lattner
cedc6f4b30
PHI and INLINEASM are now built-in instructions provided by Target.td
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25674 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-27 01:46:15 +00:00
Nate Begeman
9e4dd9dfc9
Pattern-match return. Includes gross hack!
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24874 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-20 00:26:01 +00:00
Nate Begeman
3fb6877cb4
Add support for fmul node of type v4f32.
...
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = mul <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
Is selected to:
_foo:
li r2, 0
lvx v0, r2, r3
vxor v1, v1, v1
vmaddfp v0, v0, v0, v1
stvx v0, r2, r3
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24701 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-14 00:34:09 +00:00
Nate Begeman
0976122abc
Add support patterns to many load and store instructions which will
...
hopefully use patterns in the near future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24651 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-09 23:54:18 +00:00
Chris Lattner
1e48478557
Define BR in the .td file now that Evan made tblgen smarter.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24589 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-04 18:42:54 +00:00
Nate Begeman
7ac8e6b6a8
Represent the encoding of the SPR instructions as they actually are, so
...
that we can use the correct SPR numbers in the InstrInfo.td file. This is
necessary to support VRsave.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24521 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-29 22:42:50 +00:00
Nate Begeman
9b14f66320
Add the remainder of the AltiVec 4 x float instructions. Further
...
enhancements will be necessary to teach the code generator that since
there is no fmul, it will have to do vmaddfp, adding +0.0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24516 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-29 08:04:45 +00:00
Nate Begeman
01595c52b3
Small tweaks noticed while on the plane.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24492 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-26 22:39:34 +00:00
Nate Begeman
e4f17a5f9b
Some first bits of AltiVec stuff: Instruction Formats, Encodings, and
...
Registers. Apologies to Jim if the scheduling info so far isn't accurate.
There's a few more things like VRsave support that need to be finished up
in my local tree before I can commit code that Does The Right Thing for
turning 4 x float into the various altivec packed float instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24489 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-23 05:29:52 +00:00
Chris Lattner
3075a4e94d
Allow pseudos to have patterns, no functionality change
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23988 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-25 20:58:43 +00:00
Jim Laskey
538421411a
Added InstrSchedClass to each of the PowerPC Instructions.
...
Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23830 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-19 19:51:16 +00:00
Nate Begeman
2d5aff761d
Write patterns for the various shl and srl patterns that don't involve
...
doing something clever.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23824 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-19 18:42:01 +00:00
Chris Lattner
617742b1b8
Nuke PowerPCInstrFormats.h, its contents are dead. Remove the definitions
...
from the .td file that correspond to it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23736 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-14 22:44:13 +00:00
Chris Lattner
67ab118a6d
Add a bunch of patterns for F64 FP ops, add some more integer ops
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23533 91177308-0d34-0410-b5e6-96231b3b80d8
2005-09-29 23:34:24 +00:00
Chris Lattner
bfde080ce0
add patterns for x?oris?
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23268 91177308-0d34-0410-b5e6-96231b3b80d8
2005-09-08 17:40:49 +00:00
Chris Lattner
3e63ead49b
add patterns to the addi/addis/mulli etc instructions. Define predicates
...
for matching signed 16-bit and shifted 16-bit ppc immediates
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23267 91177308-0d34-0410-b5e6-96231b3b80d8
2005-09-08 17:33:10 +00:00
Chris Lattner
d1cdc7028c
Add patterns for some new instructions, allowing the use of the ineg fragment.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23266 91177308-0d34-0410-b5e6-96231b3b80d8
2005-09-08 17:01:54 +00:00
Chris Lattner
6159fb20c2
Add AND/OR/XOR
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23232 91177308-0d34-0410-b5e6-96231b3b80d8
2005-09-02 22:35:53 +00:00
Chris Lattner
218a15d02c
Add some initial patterns to simple binary instructions, though they
...
currently don't do anything. This elides patterns for binary operators
that ping on the carry flag, since we don't model it yet.
This patch also removes PPC::SUB, because it is dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23230 91177308-0d34-0410-b5e6-96231b3b80d8
2005-09-02 21:18:00 +00:00
Nate Begeman
6718f11feb
Fix JIT encoding of conditional branches
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23076 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-26 04:11:42 +00:00
Nate Begeman
394cd13ba3
Fix JIT encoding of ppc mfocrf instruction; the operands were reversed
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22707 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-08 20:04:52 +00:00
Chris Lattner
14522e31d9
switch over the rest of the formats that use RC to use isDOT
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21352 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-19 05:21:30 +00:00
Chris Lattner
883059fb58
Convert the XForm instrs and XSForm instruction over to use isDOT
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21351 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-19 05:15:18 +00:00
Chris Lattner
97a2d42999
Now that the ppc64 and vmx operands of I are always 0, forward substitute
...
them away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21350 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-19 05:05:22 +00:00
Chris Lattner
a611ab72ca
convert over bform and iform instructions
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21349 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-19 05:00:59 +00:00
Chris Lattner
57226fbc7b
Convert over DForm and DSForm instructions
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21348 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-19 04:59:28 +00:00
Chris Lattner
e19d0b1130
Convert XLForm and XForm instructions over to use PPC64 when appropriate.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21347 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-19 04:51:30 +00:00
Chris Lattner
5035cef732
Convert XO XS and XFX forms to use isPPC64
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21346 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-19 04:40:07 +00:00
Chris Lattner
0bdc6f1fd4
Turn PPC64 and VMX into classes that can be added to instructions instead of
...
bits that must be passed up the inheritance hierarchy. Convert MForm and AForm
instructions over
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21345 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-19 04:32:54 +00:00
Nate Begeman
16ac709c63
Change codegen for setcc to read the bit directly out of the condition
...
register. Added support in the .td file for the g5-specific variant
of cr -> gpr moves that executes faster, but we currently don't
generate it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21314 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-18 02:43:24 +00:00
Nate Begeman
ef7288c824
Add the necessary support to codegen condition register logical ops with
...
register allocated condition registers. Make sure that the printed
output is gas compatible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21295 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-14 03:20:38 +00:00
Nate Begeman
7af0248af4
Initial support for allocation condition registers
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21246 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-12 07:04:16 +00:00
Chris Lattner
6b4ea2cfa2
Revert the previous patch, which I didn't mean to check in.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21226 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-11 15:03:41 +00:00
Chris Lattner
26d4fdb968
Fix a minor bug (ORo didn't mark that it set CR0).
...
Refactor how . instructions are handled. In particular, instead of passing
the RC flag all the way up the inheritance hierarchy, just make a new tblgen
class 'DOT' which can be added to an instruction definition.
For example, instead of this:
-def AND : XForm_6<31, 28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-let Defs = [CR0] in
-def ANDo : XForm_6<31, 28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "and. $rA, $rS, $rB">;
We now have this:
+def AND : XForm_6<31, 28, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"and $rA, $rS, $rB">;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21225 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-11 15:01:39 +00:00
Chris Lattner
5cbf3bc202
Fix encoding of fsel, fixing olden/power, McCat/bisort and several others.
...
All of Olden passes now! :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18227 91177308-0d34-0410-b5e6-96231b3b80d8
2004-11-25 04:11:07 +00:00
Chris Lattner
cd61ec837f
Fix encoding of swari, fixing several programs, including Olden/mst
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18225 91177308-0d34-0410-b5e6-96231b3b80d8
2004-11-25 03:40:20 +00:00