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20528 Commits

Author SHA1 Message Date
Jim Grosbach
4c7edb3ad8 ARM assembly parsing and encoding for four-register VST1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145450 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 22:58:48 +00:00
Evan Cheng
a3438cf48b Add another missing pattern. llvm-gcc likes f64 but clang likes i64 so it was generating poor code for some SSE builtins. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145448 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 22:48:34 +00:00
Jim Grosbach
d5ca201891 ARM assembly parsing and encoding for three-register VST1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145442 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 22:38:04 +00:00
Jakob Stoklund Olesen
0edd83bfff Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions. 
Like V_SET0, these instructions are expanded by ExpandPostRA to xorps /
vxorps so they can participate in execution domain swizzling.

This also makes the AVX variants redundant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145440 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 22:27:25 +00:00
Andrew Trick
7d8867d453 comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145422 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 19:33:49 +00:00
Daniel Dunbar
d782bae970 build/CMake: Finish removal of add_llvm_library_dependencies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145420 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 19:25:30 +00:00
Michael J. Spencer
116bc795da MC/X86/COFF: Allow quotes in names when targeting MS/Windows, 
as MC is the only assembler we support.

This splits MS/Windows and GNU/Windows ASM infos into two seperate classes.
While there is currently only one difference, full MS C++ ABI support will
require many more.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145409 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 18:00:06 +00:00
Elena Demikhovsky
f68b214e2d Fixed vsqrt.ss intrinsic usage - order of input operands was wrong. 
Added a test.
Thanks Bruno for reviewing the patch.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145403 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 15:00:45 +00:00
Craig Topper
f267972d28 Fix shuffle decoding for memory forms for (V)SHUFPS/D. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145392 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 07:58:09 +00:00
Craig Topper
36e36ace77 Fix issues in shuffle decoding around VPERM* instructions. Fix shuffle decoding for VSHUFPS/D for 256-bit types. Add pattern matching for memory forms of VPERMILPS/VPERMILPD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145390 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 07:49:05 +00:00
Craig Topper
fe2a6c584a Fix VINSERTF128/VEXTRACTF128 to be marked as FP instructions. Allow execution dependency fix pass to convert them to their integer equivalents when AVX2 is enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145376 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 05:37:58 +00:00
Craig Topper
108126cfc6 Correctly mark VPERM2F128 as being an FP instruction and add execution domain fixing support to convert it to VPERM2I128 for AVX2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145370 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 03:57:34 +00:00
Jim Grosbach
6200611dff Better fix for ARM MOVT relocation encoding of thumb bit. 
Replaces r145318 with a more targetted fix for the relocation handling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145346 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 01:15:25 +00:00
Evan Cheng
678cda052c Add missing avx pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145272 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-28 20:27:23 +00:00
Duncan Sands
4c0c5451c7 Silence wrong warnings from GCC about variables possibly being used 
uninitialized: GCC doesn't understand that the variables are only used
if !UseImm, in which case they have been initialized.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145239 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-28 10:31:27 +00:00
Craig Topper
70b883b3a7 Add X86 instruction selection for VPERM2I128 when AVX2 is enabled. Merge VPERMILPS/VPERMILPD detection since they are pretty similar. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145238 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-28 10:14:51 +00:00
Craig Topper
71c4c12232 Make isCommutedVSHUFP more like the way isCommutedSHUFP is handled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145218 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-28 01:14:24 +00:00
Craig Topper
9d7025b56b Merge detecting and handling for VSHUFPSY and VSHUFPDY since a lot of the code was similar for both. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145199 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-27 21:41:12 +00:00
Wesley Peck
4c729f1152 Add several new instructions supported by the latest MicroBlaze. 
These instructions are not generated by the backend yet, this will come in a later commit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145161 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-27 05:16:58 +00:00
Wesley Peck
a0aa45c759 Optimize comparison against 0 in conditional instructions. 
Fix a couple of 80-column violations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145159 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-27 01:36:20 +00:00
Benjamin Kramer
0861f5793a Move code into anonymous namespaces. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145154 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-26 23:01:57 +00:00
Craig Topper
38034c568c Merge 128-bit and 256-bit X86ISD node types for VPERMILPS and VPERMILPD. Simplify some shuffle lowering code since V1 can never be UNDEF due to canonalizing that occurs when shuffle nodes are created. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145153 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-26 22:55:48 +00:00
Wesley Peck
a18f08318a Rename a couple of options and fix some simple typos. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145152 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-26 21:50:38 +00:00
Craig Topper
06cb680779 Collapse X86ISD node types for PUNPCKH*, PUNPCKL*, UNPCKLP*, and UNPCKHP* to not be type specific. Now we just have integer high and low and floating point high and low. Pattern matching will choose the correct instruction based on the vector type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145148 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-26 20:47:44 +00:00
Bruno Cardoso Lopes
1b9b377975 This patch contains support for encoding FMA4 instructions and 
tablegen patterns for scalar FMA4 operations and intrinsic. Also
add tests for vfmaddsd.

Patch by Jan Sjodin

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145133 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-25 19:33:42 +00:00
NAKAMURA Takumi
70aaf37c11 ARMLoadStoreOptimizer.cpp: Fix MSVC(Debug) build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145129 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-25 09:19:57 +00:00
Craig Topper
705f2431a0 Remove 256-bit specific node types for UNPCKHPS/D and instead use the 128-bit versions and let the operand type disinquish. Also fix the load form of the v8i32 patterns for these to realize that the load would be promoted to v4i64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145126 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-24 22:57:10 +00:00
Craig Topper
f475a55bd4 Remove AVX2 specific X86ISD node types for PUNPCKH/L and instead just reuse the 128-bit versions and let the vector type distinguish. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145125 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-24 22:20:08 +00:00
Benjamin Kramer
9d399b1fc2 X86: alias cqo to cqto. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145121 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-24 12:02:46 +00:00
Akira Hatanaka
421455f1ea This patch makes the following changes necessary for MIPS' direct code emission. 
- lower unaligned loads/stores.
- encode the size operand of instructions INS and EXT.
- emit relocation information needed for JAL (jump-and-link).  


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145113 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-23 22:19:28 +00:00
Akira Hatanaka
84bfc2f090 This patch addresses gp relative fixups/relocations for jump tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145112 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-23 22:18:04 +00:00
Benjamin Kramer
f238f50aaf X86: Use btq for bit tests if the immediate can't be encoded in 32 bits. 
Before:
	movabsq	$4294967296, %rax       ## encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00]
	testq	%rax, %rdi              ## encoding: [0x48,0x85,0xf8]
	jne	LBB0_2                  ## encoding: [0x75,A]

After:
	btq	$32, %rdi               ## encoding: [0x48,0x0f,0xba,0xe7,0x20]
	jb	LBB0_2                  ## encoding: [0x72,A]

btq is usually slower than testq because it doesn't fuse with the jump, but here we're better off
saving one register and a giant movabsq.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145103 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-23 13:54:17 +00:00
Elena Demikhovsky
52a35a89e6 I added several lines in X86 code generator that allow to choose 
VSHUFPS/VSHUFPD instructions while lowering VECTOR_SHUFFLE node. I check a commuted VSHUFP mask.

The patch was reviewed by Bruno.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145099 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-23 10:23:16 +00:00
Jakob Stoklund Olesen
7f5e43f61d Fix PR11422. 
This was a bug in keeping track of the available domains when merging
domain values.

The wrong domain mask caused ExecutionDepsFix to try to move VANDPSYrr
to the integer domain which is only available in AVX2.

Also add an assertion to catch future attempts at emitting AVX2
instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145096 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-23 04:03:08 +00:00
Hal Finkel
768c65f677 add basic PPC register-pressure feedback; adjust the vaarg test to match the new register-allocation pattern 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145065 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-22 16:21:04 +00:00
Craig Topper
796c193768 More fixes to the X86InstComments for shuffle instructions. In particular add AVX flavors of many instructions and fix the destination operand for some of the existing AVX entries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145063 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-22 14:27:57 +00:00
Craig Topper
f7de577a08 Fix shuffle decoding logic to handle UNPCKLPS/UNPCKLPD on 256-bit vectors correctly. Add support for decoding UNPCKHPS/UNPCKHPD for AVX 128-bit and 256-bit forms. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145055 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-22 01:57:35 +00:00
Craig Topper
c0d82857e0 Add methods for querying minimum SSE version along with AVX. Simplifies all the places that had to check a version of SSE and AVX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145053 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-22 00:44:41 +00:00
Craig Topper
6fa583d787 Lowering for v32i8 to VPUNPCKLBW/VPUNPCKHBW when AVX2 is enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145028 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-21 08:26:50 +00:00
Craig Topper
6347e8662c Add support for lowering 256-bit shuffles to VPUNPCKL/H for i16, i32, i64 if AVX2 is enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145026 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-21 06:57:39 +00:00
Craig Topper
a124f94952 Make LowerSIGN_EXTEND_INREG split 256-bit vectors when AVX1 is enabled and use AVX2 shifts when AVX2 is enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145022 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-21 01:12:36 +00:00
Craig Topper
0d86d462f8 Add code for lowering v32i8 shifts by a splat to AVX2 immediate shift instructions. Remove 256-bit splat handling from LowerShift as it was already handled by PerformShiftCombine. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145005 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-20 00:12:05 +00:00
Craig Topper
745a86bac9 Use 256-bit vcmpeqd for creating an all ones vector when AVX2 is enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145004 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-19 22:34:59 +00:00
Craig Topper
ba798c5e51 Remove some of the special classes that worked around an old tablegen limitation of not being able to remove redundant bitconverts from patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145003 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-19 21:01:54 +00:00
Craig Topper
98fc72940b Custom lower AVX2 variable shift intrinsics to shl/srl/sra nodes and remove the intrinsic patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144999 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-19 17:46:46 +00:00
Craig Topper
54f952afac Synthesize SSSE3/AVX 128-bit horizontal integer add/sub instructions from add/sub of appropriate shuffle vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144989 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-19 09:02:40 +00:00
Craig Topper
3113384a34 Collapse X86 PSIGNB/PSIGNW/PSIGND node types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144988 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-19 07:33:10 +00:00
Craig Topper
1666cb6d63 Extend VPBLENDVB and VPSIGN lowering to work for AVX2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144987 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-19 07:07:26 +00:00
Craig Topper
60d9a9206e Remove unused parameters from the AVX maskmov classes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144985 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-19 04:49:22 +00:00
Nadav Rotem
cbbe33fde4 Add AVX2 vpbroadcast support 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144967 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-18 02:49:55 +00:00