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20528 Commits

Author SHA1 Message Date
Nadav Rotem
c6c7e85a71 AVX2: Add patterns for variable shift operations 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144212 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 21:22:13 +00:00
Devang Patel
f4e0d5d83d Remove unnecessary include. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144211 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 21:11:02 +00:00
Nadav Rotem
bb539bf973 Add AVX2 support for vselect of v32i8 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144187 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 13:21:28 +00:00
Craig Topper
b80ada98c5 Enable execution dependency fix pass for YMM registers when AVX2 is enabled. Add AVX2 logical operations to list of replaceable instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144179 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 09:37:21 +00:00
Craig Topper
0a15035f52 Add instruction selection for AVX2 integer comparisons. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144176 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 08:06:13 +00:00
Craig Topper
aaa643c70e Add AVX2 instruction lowering for add, sub, and mul. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144174 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 07:28:55 +00:00
Chad Rosier
2f2fe417f9 Add support for encoding immediates in icmp and fcmp. Hopefully, this will 
remove a fair number of unnecessary materialized constants.
rdar://10412592


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144163 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 03:22:02 +00:00
Evan Cheng
44ee4714a8 Hide cpu name checking in ARMSubtarget. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144154 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 01:57:03 +00:00
Bruno Cardoso Lopes
ce1a538ab5 Properly handle Mips MC relocations and lower cpload and cprestore macros to MCInsts. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144139 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 22:26:47 +00:00
Evan Cheng
3568a1051e Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ldm or ldr pairs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144123 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 21:21:09 +00:00
Chad Rosier
66dc8ca04b ARMFastISel doesn't support thumb1. Rename isThumb to isThumb2 to reflect this. 
No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144122 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 21:12:00 +00:00
Lang Hames
5207bf2177 Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported. 
Add support for trimming constants to GetDemandedBits. This fixes some funky
constant generation that occurs when stores are expanded for targets that don't
support unaligned stores natively.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144102 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 18:56:23 +00:00
Pete Cooper
d752e0f7e6 Added invariant field to the DAG.getLoad method and changed all calls. 
When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144100 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 18:42:53 +00:00
Bruno Cardoso Lopes
ad6eef4a65 This patch handles unaligned loads and stores in Mips JIT. Mips backend 
implements unaligned loads and stores with assembler macro-instructions
ulw, usw, ulh, ulhu, ush, and this patch emits corresponding instructions
instead of these macros. Since each unaligned load/store is expanded
into two corresponding loads/stores where offset for second load/store is
modified by +3 (for words) or +1 (for halfwords).

Patch by Petar Jovanovic and Sasa Stankovic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144081 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 12:47:11 +00:00
NAKAMURA Takumi
0839033cbc PPCInstrInfo.cpp: Fix one "unused" warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144071 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 04:00:07 +00:00
Eli Friedman
9f1f26aefa Make sure to mark vector extload's as expand on ARM. Fixes PR11319. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144057 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 01:43:53 +00:00
Evan Cheng
7bc389b6b0 Add x86 isel logic and patterns to match movlps from clang generated IR for _mm_loadl_pi(). rdar://10134392, rdar://10050222 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144052 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 00:31:58 +00:00
Chad Rosier
0eff39f2e2 Enable support for returning i1, i8, and i16. Nothing special todo as it's the 
callee's responsibility to sign or zero-extend the return value.  The additional
test case just checks to make sure the calls are selected (i.e., -fast-isel-abort
doesn't assert).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144047 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 00:03:32 +00:00
Chad Rosier
62c8e8e3f6 Allow i1 to be promoted to i32 for ARM AAPCS and AAPCS-VFP calling convention as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144021 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 21:43:40 +00:00
Akira Hatanaka
4cae74bd74 Various Mips64 floating point instruction patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144019 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 21:38:58 +00:00
Akira Hatanaka
c370619bac Add definition of the base class for floating point comparison instructions 
and add Mips64's version too.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144018 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 21:37:33 +00:00
Akira Hatanaka
29d525a3ed Add code needed for copying between 64-bit integer and floating pointer 
registers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144017 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 21:35:45 +00:00
Akira Hatanaka
e7126ebd54 Add definitions of 64-bit instructions which move data between integer and 
floating pointer registers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144016 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 21:32:58 +00:00
Benjamin Kramer
70be28a5ad Simplify some uses of utohexstr. 
As a side effect hex is printed lowercase instead of uppercase now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144013 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 21:00:59 +00:00
Benjamin Kramer
055a647a9d Simplify code. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144012 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 21:00:43 +00:00
Jakob Stoklund Olesen
3e5d5c53a0 Expand V_SET0 to xorps by default. 
The xorps instruction is smaller than pxor, so prefer that encoding.

The ExecutionDepsFix pass will switch the encoding to pxor and xorpd
when appropriate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143996 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 19:15:58 +00:00
Akira Hatanaka
d83d98d4eb Add definition of 64-bit load upper immediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143994 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 19:10:49 +00:00
Akira Hatanaka
f83ba3293f Include RegSaveAreaSize in the computation of stack size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143993 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 19:07:35 +00:00
Akira Hatanaka
213b2a2188 Define functions that get or set the size of area on callee's stack frame which 
is used to save va_arg or byval arguments passed in registers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143992 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 19:06:10 +00:00
Akira Hatanaka
c4d6fd569d Use array_lengthof to compute the number of iterations of a loop. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143991 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 19:03:40 +00:00
Akira Hatanaka
7784046012 Fix patterns for unaligned 32-bit load. DSLL32 or DSRL32 should be emitted 
when shift amount is larger than 32.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143990 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 19:01:49 +00:00
Akira Hatanaka
68698cc20d Make the type of shift amount i32 in order to reduce the number of shift 
instruction definitions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143989 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 18:59:49 +00:00
Akira Hatanaka
bce22b48fe Add 64-bit to 32-bit trunc pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143988 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 18:57:41 +00:00
Craig Topper
4c763ee613 Add AVX2 variable shift instructions and intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143915 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 08:26:24 +00:00
Craig Topper
28692044db Add AVX2 VPMOVMASK instructions and intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143904 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 03:20:35 +00:00
Craig Topper
69f5df7778 Add AVX2 VEXTRACTI128 and VINSERTI128 instructions. Fix VPERM2I128 to be qualified with HasAVX2 instead of HasAVX. Mark VINSERTF128 and VEXTRACTF128 as never having side effects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143902 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 02:00:04 +00:00
Craig Topper
c8eb880a7f More AVX2 instructions and their intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143895 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-06 23:04:08 +00:00
Benjamin Kramer
5908536673 Replace (Lower|Upper)caseString in favor of StringRef's newest methods. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143891 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-06 20:37:06 +00:00
Craig Topper
27e5d0c72a Add more AVX2 instructions and intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143861 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-06 06:12:20 +00:00
Chad Rosier
42536af5ce Add support for passing i1, i8, and i16 call parameters. Also, be sure to 
zero-extend the constant integer encoding.  Test case provides testing for
both call parameters and materialization of i1, i8, and i16 types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143821 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-05 20:16:15 +00:00
Benjamin Kramer
41a964931a Add more PRI.64 macros for MSVC and use them throughout the codebase. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143799 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-05 08:57:40 +00:00
Chad Rosier
38f5c0da6d Allow i1 to be promoted to i32 for ARM APCS calling convention. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143755 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-05 00:02:56 +00:00
Eli Friedman
bd00a934c6 Enhanced vzeroupper insertion pass that avoids inserting vzeroupper where it is unnecessary through local analysis. Patch from Bruno Cardoso Lopes, with some additional changes. 
I'm going to wait for any review comments and perform some additional testing before turning this on by default.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143750 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-04 23:46:11 +00:00
Chad Rosier
451afbc6a2 Cannot create a result register for non-legal types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143749 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-04 23:45:39 +00:00
Chad Rosier
a4e07270bc When materializing an i32, SExt vs ZExt doesn't matter when we're trying to fit 
in a 16-bit immediate.  However, for the shorter non-legal types (i.e., i1, i8,
i16) we should not sign-extend.  This prevents us from materializing things
such as 'true' (i.e., i1 1).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143743 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-04 23:09:49 +00:00
Chad Rosier
44e895761f Enable support for materializing i1, i8, and i16 integers via move immediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143739 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-04 22:29:00 +00:00
Daniel Dunbar
7b1dd9aaf1 build/cmake: Coalesce the configuration time header include fragment generation 
for target definitions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143731 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-04 19:04:42 +00:00
Daniel Dunbar
b0d9ce567f build/cmake: Use tblgen macro directly instead of llvm_tablegen, which just 
added a layer of indirection with no value (not even conciseness).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143727 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-04 19:04:23 +00:00
Eli Friedman
5b7cc334c8 Add missing argument for atomic instructions in c++ backend. PR11268, part 2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143712 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-04 17:29:35 +00:00
Craig Topper
018262768f Add intrinsics for X86 vcvtps2ph and vcvtph2ps instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143683 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-04 06:59:49 +00:00
Evan Cheng
c39916b166 Fix some minor scheduling itinerary bug. It's not expected to actually affect codegen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143675 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-04 01:48:58 +00:00
Chad Rosier
8e4a2e4f73 Indentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143670 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-04 00:58:10 +00:00
Chad Rosier
f470cbbad2 Add fast-isel support for returning i1, i8, and i16. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143669 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-04 00:50:21 +00:00
Dan Gohman
65fd6564b8 Reapply r143206, with fixes. Disallow physical register lifetimes 
across calls, and only check for nested dependences on the special
call-sequence-resource register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143660 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-03 21:49:52 +00:00
Dan Bailey
e1f38f2ce1 fixed global array handling for ptx to use the correct bit widths 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143640 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-03 19:24:46 +00:00
Daniel Dunbar
a3a2dfd4a2 build: Add initial cut at LLVMBuild.txt files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143634 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-03 18:53:17 +00:00
Craig Topper
98e0b9c86d Add new X86 AVX2 VBROADCAST instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143612 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-03 07:35:53 +00:00
Chad Rosier
463fe24f1d Add support for sign-extending non-legal types in SelectSIToFP(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143603 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-03 02:04:59 +00:00
Lang Hames
a1e78888d9 Fixed parameter name. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143594 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-02 23:37:04 +00:00
Lang Hames
1a1d1fcc0b Try to lower memset/memcpy/memmove to vector instructions on ARM where the alignment permits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143582 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-02 22:52:45 +00:00
Chad Rosier
e07cd5e40a Add support for comparing integer non-legal types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143559 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-02 18:08:25 +00:00
Owen Anderson
81550dc0a8 Fix the issue that r143552 was trying to address the _right_ way. One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143557 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-02 18:03:14 +00:00
Owen Anderson
244006db5c The rules disallowing single-register reglist operands only apply to the POP alias, not to LDM/STM instructions. Revert r143552. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143553 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-02 17:46:18 +00:00
Owen Anderson
e31b42a6f5 Register list operands are not allowed to contain only a single register. Alternate encodings are used in that case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143552 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-02 17:41:23 +00:00
Chad Rosier
87633026d6 Factor out an EmitIntExt function. No functionality change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143547 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-02 17:20:24 +00:00
Craig Topper
205e3378fd More AVX2 instructions and intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143536 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-02 06:54:17 +00:00
Craig Topper
3f2b2c218f Add a bunch more X86 AVX2 instructions and their corresponding intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143529 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-02 04:42:13 +00:00
Chad Rosier
0d7b231c9b Factor out a SelectTrunc function. No functionality change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143523 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-02 00:18:48 +00:00
Jim Grosbach
6284afc293 ARM label operands can be quoted. 
For example, labels from Objective-C sources.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143511 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-01 22:38:31 +00:00
Jim Grosbach
ed6a0c5243 ARM label operands can have an optional '#' before them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143510 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-01 22:37:37 +00:00
Owen Anderson
60cb643f75 Fix disassembly of some VST1 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143507 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-01 22:18:13 +00:00
Sebastian Pop
0173864d8a rename getHostTriple into getDefaultTargetTriple 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143502 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-01 21:32:20 +00:00
Eli Friedman
f6aa6b12f1 Teach the x86 backend a couple tricks for dealing with v16i8 sra by a constant splat value. Fixes PR11289. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143498 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-01 21:18:39 +00:00
Richard Osborne
0e6c1c536b Don't fold negative offsets into cp / dp accesses to avoid relocation errors. 
This can happen if the address + addend is less than the start of the cp / dp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143459 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-01 11:31:53 +00:00
Jim Grosbach
681460f954 ARM VLD/VST assembly parsing for symbolic address operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143413 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-01 01:24:45 +00:00
Eli Friedman
a7dd4dfcca Add support for new atomics to cpp backend. Misc other fixes while I'm here. PR11268. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143406 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-31 23:59:22 +00:00
Jim Grosbach
4334e03252 ARM VST1 w/ writeback assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143369 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-31 21:50:31 +00:00
Jim Grosbach
f9f5a765ad ARM writeback vs. stride operands for VST/VLD. 
The _fixed variants have a writeback operand, but not a stride operand.
Split the conditional flag to distinguish the cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143356 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-31 19:11:23 +00:00
Owen Anderson
fb6ab2b30e More not-crashing NEON disassembly updates for the vld refactoring. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143351 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-31 17:17:32 +00:00
Craig Topper
6b1c5fc02a Begin adding AVX2 instructions. No selection support yet other than intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143331 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-31 02:15:10 +00:00
Nick Lewycky
4e478fed1b Switch new .file directive emission off by default, change llc's flag for it to 
-enable-dwarf-directory.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143326 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-31 01:06:02 +00:00
Craig Topper
e7b05504fa Add intrinsics and feature flag for read/write FS/GS base instructions. Also add AVX2 feature flag. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143319 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-30 19:57:21 +00:00
Benjamin Kramer
dade3c1448 X86: Emit logical shift by constant splat of <16 x i8> as a <8 x i16> shift and zero out the bits where zeros should've been shifted in. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143315 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-30 17:31:21 +00:00
Nadav Rotem
fb0dfbbff7 Fix pr11266. 
On x86: (shl V, 1) -> add V,V

Hardware support for vector-shift is sparse and in many cases we scalarize the
result. Additionally, on sandybridge padd is faster than shl.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143311 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-30 13:24:22 +00:00
Benjamin Kramer
95c885d65a PPC: Disable moves for all CR subregisters. 
Should fix assertion failures on ppc buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143290 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-29 19:43:38 +00:00
Dan Gohman
6f3ddef7c5 Revert r143206, as there are still some failing tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143262 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-29 00:41:52 +00:00
Jim Grosbach
e70ec84637 ARM mode 'mov' to 'mvn' assembler alias. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143237 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 22:50:54 +00:00
Jim Grosbach
89a6337085 Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm". 
When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example,
  mov r2, #-3
becomes
  mvn r2, #2

rdar://10349224


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143235 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 22:36:30 +00:00
Owen Anderson
b3727fe3ec Specify that the high bit of the alignment field is fixed to 0 on these instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143220 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 20:43:24 +00:00
Akira Hatanaka
feaa4c316f Make changes necessary in LowerFormalArguments to support Mips64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143218 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 19:55:48 +00:00
Akira Hatanaka
e42f33bd15 Make changes necessary in LowerCall to support Mips64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143217 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 19:49:00 +00:00
Akira Hatanaka
2ec69faf26 Add variable IsO32 to MipsTargetLowering. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143213 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 18:47:24 +00:00
Owen Anderson
cb9fed6655 Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143208 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 18:02:13 +00:00
Dan Gohman
bf923b815d Reapply r143177 and r143179 (reverting r143188), with scheduler 
fixes: Use a separate register, instead of SP, as the
calling-convention resource, to avoid spurious conflicts with
actual uses of SP. Also, fix unscheduling of calling sequences,
which can be triggered by pseudo-two-address dependencies.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143206 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 17:55:38 +00:00
Owen Anderson
82418ff4d1 Revert r143202. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143203 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 17:38:30 +00:00
Owen Anderson
7ccee5610a Specify fixed bits on CPS instructions to enable roundtripping. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143202 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 17:29:39 +00:00
Jim Grosbach
5d0492cfc4 Thumb2 ADD/SUB instructions encoding selection outside IT block. 
Outside an IT block, "add r3, #2" should select a 32-bit wide encoding
rather than generating an error indicating the 16-bit encoding is only
legal in an IT block (outside, the 'S' suffic is required for the 16-bit
encoding).

rdar://10348481


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143201 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 16:57:07 +00:00
Duncan Sands
62c1d00dfd Speculatively disable Dan's commits 143177 and 143179 to see if 
it fixes the dragonegg self-host (it looks like gcc is miscompiled).
Original commit messages:
Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.

Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.

Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.

Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.

This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.

Delete #if 0 code accidentally left in.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143188 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 09:55:57 +00:00
Dan Gohman
2ba60e5930 Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW 
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.

Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.

Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.

Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.

This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143177 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 01:29:32 +00:00
Jim Grosbach
c73d73eb88 ARM Allow 'q' registers in VLD/VST vector lists. 
Just treat it as if the constituent D registers where specified.

rdar://10348896

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143167 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 00:06:50 +00:00
Dan Gohman
33ba8b0e96 Remove the Alpha backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143164 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-27 22:56:32 +00:00
Owen Anderson
04b12a4cfb Add some NEON stores to the VLD decoding hook that were accidentally omitted previously. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143162 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-27 22:53:10 +00:00
Jakob Stoklund Olesen
b0117eed84 Also set addrmode6 alignment when align==size. 
Previously, we were only setting the alignment bits on over-aligned
loads and stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143160 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-27 22:39:16 +00:00
Jim Grosbach
55dabaa73a ARM isel for vld1, opcode selection for register stride post-index pseudos. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143158 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-27 22:25:42 +00:00
Evan Cheng
824a70a384 Avoid partial CPSR dependency from loop backedges. rdar://10357570 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143145 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-27 21:21:05 +00:00
Kevin Enderby
55c4127134 Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix and 
not depend on In32BitMode.  Use the sysexitq mnemonic for the version with the
REX.W prefix and only allow it only In64BitMode.  rdar://9738584


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143112 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-27 17:40:41 +00:00
Jim Grosbach
88484c0030 Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix. 
rdar://10348844

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143110 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-27 17:33:59 +00:00
Jim Grosbach
036a67d670 Thumb2 t2MVNi assembly parsing to recognize ".w" suffix. 
rdar://10348584


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143108 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-27 17:16:55 +00:00
Chad Rosier
6d64b3adab A branch predicated on a constant can just FastEmit an unconditional branch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143086 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-27 00:21:16 +00:00
Lang Hames
15701f8969 Rename NonScalarIntSafe to something more appropriate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143080 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-26 23:50:43 +00:00
Chad Rosier
8ff2664f2f Add a TODO comment. FastISel works by parsing each basic block from the bottom 
up.  Thus, improving the support for compares is goodness because it increases
the number of terminator instructions we can handle.  This creates many more 
opportunities for target specific fast-isel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143079 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-26 23:34:37 +00:00
Chad Rosier
ade620065d Factor a little more code into EmitCmp, which should have been done in the first 
place.  No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143078 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-26 23:25:44 +00:00
Chad Rosier
75698f346f Use EmitCmp in SelectBranch. No functional change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143076 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-26 23:17:28 +00:00
Chad Rosier
530f7cefd3 Factor out an EmitCmp function that can be used by both SelectCmp and 
SelectBranch.  No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143072 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-26 22:47:55 +00:00
Jim Grosbach
a581328ceb Thumb2 ldr pc-relative encoding fixes. 
We were parsing label references to the i12 encoding, which isn't right.
They need to go to the pci variant instead.

More of rdar://10348687

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143068 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-26 22:22:01 +00:00
Rafael Espindola
66bf7430f5 Fixes an issue reported by -verify-machineinstrs. 
Patch by Sanjoy Das.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143064 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-26 21:16:41 +00:00
Jim Grosbach
758a519a22 ARM parse parenthesized expressions for label references. 
Partial fix for rdar://10348687.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143063 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-26 21:14:08 +00:00
Rafael Espindola
e840e88239 This commit introduces two fake instructions MORESTACK_RET and 
MORESTACK_RET_RESTORE_R10; which are lowered to a RET and a RET
followed by a MOV respectively.  Having a fake instruction prevents
the verifier from seeing a MachineBasicBlock end with a
non-terminator (MOV).  It also prevents the rather eccentric case of a
MachineBasicBlock ending with RET but having successors nevertheless.

Patch by Sanjoy Das.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143062 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-26 21:12:27 +00:00
Lang Hames
75757f9fd1 Make sure short memsets on ARM lower to stores, even when optimizing for size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143055 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-26 20:56:52 +00:00
Jim Grosbach
9c5edc00c4 Thumb2 remove redundant ".w" suffix from t2MVNCCi pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143034 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-26 17:28:15 +00:00
James Molloy
015cca6c08 Revert r142530 at least temporarily while a discussion is had on llvm-commits regarding exactly how much optsize should optimize for size over performance. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143023 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-26 08:53:19 +00:00
Bill Wendling
de39d86f26 Use a worklist to prevent the iterator from becoming invalidated because of the 'removeSuccessor' call. Noticed in a Release+Asserts+Check buildbot. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143018 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-26 07:16:18 +00:00
Evan Cheng
f31151f34e Revert part of r142530. The patch potentially hurts performance especially 
on Darwin platforms where -Os means optimize for size without hurting
performance.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143002 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-26 01:17:44 +00:00
Bruno Cardoso Lopes
02dc51806e Corrects previously incorrect $sp change in MipsCompilationCallback. 
The address for $sp, and addresses for sdc1/ldc1 must be 8-byte aligned

Patch by Petar Jovanovic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142930 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-25 17:30:47 +00:00
Jim Grosbach
399cdca4d2 ARM assembly parsing and encoding for VLD1 with writeback. 
Four entry register lists.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142882 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-25 00:14:01 +00:00
Dan Gohman
3e6157de57 Remove the Blackfin backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142880 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-25 00:05:42 +00:00
Dan Gohman
29074ccf6c Remove the SystemZ backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142878 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-24 23:48:32 +00:00
Jim Grosbach
b36e03d987 Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142877 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-24 23:40:46 +00:00
Jim Grosbach
5921675ff5 ARM assembly parsing and encoding for VLD1 w/ writeback. 
Three entry register list variation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142876 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-24 23:26:05 +00:00
Eli Friedman
5c89cb8cd6 Don't crash on variable insertelement on ARM. PR10258. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142871 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-24 23:08:52 +00:00
Evan Cheng
aed4952753 ARMConstantPoolMBB::print should print BB number. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142867 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-24 23:01:03 +00:00
Jim Grosbach
12431329d6 ARM assembly parsing and encoding for VLD1 w/ writeback. 
One and two length register list variants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142861 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-24 22:16:58 +00:00
Jim Grosbach
10b90a9bbf ARM refactor am6offset usage for VLD1. 
Split am6offset into fixed and register offset variants so the instruction
encodings are explicit rather than relying an a magic reg0 marker.
Needed to being able to parse these.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142853 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-24 21:45:13 +00:00
Eli Friedman
3f3f6b067c Add support to the old JIT for acquire/release loads and stores on x86. PR11207. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142841 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-24 20:24:21 +00:00
Owen Anderson
a7c98f58ea Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142817 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-24 18:04:29 +00:00
Dan Gohman
692c1d8535 Change this overloaded use of Sched::Latency to be an overloaded 
use of Sched::ILP instead, as Sched::Latency is going away.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142813 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-24 17:55:11 +00:00
Dan Gohman
334190e47e Remove the explicit request for "Latency" scheduling from MSP430, 
as the Latency scheduler is going away.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142811 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-24 17:53:16 +00:00
Jim Grosbach
f8e74f816d Thumb2 LDM instructions can target PC. Make sure to encode it. 
PR11220


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142801 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-24 17:16:24 +00:00
Craig Topper
5679ec3b52 Add X86 SARX, SHRX, and SHLX instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142779 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-23 22:18:24 +00:00
Craig Topper
75485d6746 Add X86 RORX instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142741 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-23 07:34:00 +00:00
Craig Topper
4fea38f773 Add X86 MULX instruction for disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142738 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-23 00:33:32 +00:00
Craig Topper
272895f0ab Remove some duplicate specifying of neverHasSideEffects and mayLoad from X86 multiply instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142737 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-22 23:13:53 +00:00
Benjamin Kramer
1a2f9886a2 Move various generated tables into read-only memory, fixing up const correctness along the way. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142726 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-22 16:50:00 +00:00
Nadav Rotem
5b2bba6122 Fix pr11193. 
SHL inserts zeros from the right, thus even when the original
sign_extend_inreg value was of 1-bit, we need to sra.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142724 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-22 12:39:25 +00:00
Bill Wendling
b8dcb314f7 The different flavors of ARM have different valid subsets of registers. Check 
that the set of callee-saved registers is correct for the specific platform.
<rdar://problem/10313708> & ctor_dtor_count & ctor_dtor_count-2


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142706 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-22 00:29:28 +00:00
Jim Grosbach
224180e81b Assembly parsing for 4-register sequential variant of VLD2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142704 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 23:58:57 +00:00
Jim Grosbach
4661d4cac3 Assembly parsing for 2-register sequential variant of VLD2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142691 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 22:21:10 +00:00
Jim Grosbach
b6310316db Assembly parsing for 4-register variant of VLD1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142682 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 20:35:01 +00:00
Jim Grosbach
cdcfa28056 Assembly parsing for 3-register variant of VLD1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142675 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 20:02:19 +00:00
Jim Grosbach
280dfad489 ARM VLD parsing and encoding. 
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.

Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142670 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 18:54:25 +00:00
Owen Anderson
7784f1d2d8 Don't automatically set the "fc" bits on MSR instructions if the user didn't ask for them. This is a divergence from gas' behavior, but it is correct per the documentation and allows us to forge ahead with roundtrip testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142669 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 18:43:28 +00:00
Jim Grosbach
7926db8268 Nuke an #if0 that got accidentally left in. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142658 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 16:59:08 +00:00
Jim Grosbach
293a5f69fa whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142657 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 16:56:40 +00:00
Jim Grosbach
fe7b4998c6 Remove some outdated comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142653 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 16:14:12 +00:00
Craig Topper
b4c945716f Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with custom isel lowering code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142642 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 06:55:01 +00:00
Richard Smith
ed8db320af Fix unused variable warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142630 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 01:22:04 +00:00
Owen Anderson
cd20c58e98 Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142626 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 22:23:58 +00:00
Dan Gohman
5bdab4a63c Disable the PPC hazard recognizer. It currently only supports 
top-down scheduling and top-down scheduling is going away.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142621 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 21:45:36 +00:00
Owen Anderson
a3a6f215d0 Separate out ARM MSR instructions into M-class versions and AR-class versions. This fixes some roundtripping failures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142618 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 21:24:38 +00:00
Bill Wendling
767f8be9ee Add missing operand. <rdar://problem/10313323> 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142615 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 20:37:11 +00:00
Lang Hames
1dda3d511e Haven't yet found a nice way to handle TargetData verification in the 
AsmParser. This patch adds validation for target data layout strings upon
construction of TargetData objects. An attempt to construct a TargetData object
from a malformed string will trigger an assertion.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142605 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 19:24:44 +00:00
Jim Grosbach
01817c39a9 Tidy up. Trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142591 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 17:28:20 +00:00
Jim Grosbach
6b09c77b7a ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142583 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 15:04:25 +00:00
Jim Grosbach
d0b614754e ARM VTBX (one register) assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142581 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 14:48:50 +00:00
Chad Rosier
6690bca623 Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :( 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142557 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 00:07:12 +00:00
Evan Cheng
fd230df463 Fix TLS lowering bug. The CopyFromReg must be glued to the TLSCALL. rdar://10291355 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142550 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-19 22:22:54 +00:00
James Molloy
cdd8e46bec Use literal pool loads instead of MOVW/MOVT for materializing global addresses when optimizing for size. 
On spec/gcc, this caused a codesize improvement of ~1.9% for ARM mode and ~4.9% for Thumb(2) mode. This is
codesize including literal pools.

The pools themselves doubled in size for ARM mode and quintupled for Thumb mode, leaving suggestion that there
is still perhaps redundancy in LLVM's use of constant pools that could be decreased by sharing entries.

Fixes PR11087.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142530 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-19 14:11:07 +00:00
Bill Wendling
922ad78776 Make sure we emit the 'movw' and 'movt' only if it's supported. Otherwise, use a constant pool. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142485 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-19 09:24:02 +00:00
Bill Wendling
b677a135ac Remove some dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142484 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-19 09:04:11 +00:00
Craig Topper
717cdb0df8 Rename PEXTR to PEXT. Add intrinsics for BMI instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142480 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-19 07:48:35 +00:00
Bill Wendling
15a1a226be Emit the MOVT instruction only if the # LPads is > 64K. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142460 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 23:19:55 +00:00
Bill Wendling
a5871dc104 For Thumb mode, we need to use a constant pool if the value is too large to be 
used with the CMP instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142458 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 23:11:05 +00:00
Eric Christopher
857bf83414 Revert "Turn on the vzeroupper pass by default." 
This reverts commit 494f7ac3e8d2ab3d94e52317abf9c42a949fe1f3.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142455 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 23:10:11 +00:00
Jim Grosbach
862019c37f ARM VTBL (one register) assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142441 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 23:02:30 +00:00
Bill Wendling
85f3a0a4c4 Use the integer compare when the value is small enough. Use the "move into a 
register and then compare against that" method when it's too large. We have to
move the value into the register in the "movw, movt" pair of instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142440 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 22:52:20 +00:00
Eric Christopher
7e8ae57be9 Turn on the vzeroupper pass by default. 
I'll remove/rename the option in a few days.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142439 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 22:50:17 +00:00
Bill Wendling
952cb50fee Use the integer compare when the value is small enough. Use the "move into a 
register and then compare against that" method when it's too large. We have to
move the value into the register in the "movw, movt" pair of instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142437 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 22:49:07 +00:00
Lang Hames
e482471402 Teach fast isel about vector stores, and make DoSelectCall return false when it fails to emit a store. This fixes <rdar://problem/10215997>. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142432 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 22:11:33 +00:00
Bill Wendling
564392bd3f The value we're comparing against may be too large for the ARM CMP 
instruction. Move the value into a register and then use that for the CMP.
<rdar://problem/10305266>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142431 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 22:11:18 +00:00
Bill Wendling
b9fecf4e07 The immediate may be too large for the CMP instruction. Move it into a register 
and use that in the CMP.
<rdar://problem/10305266>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142429 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 21:55:58 +00:00
Jim Grosbach
a7d2e759ee Yet more ARM NEON assembly parsing for the lane index operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142416 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 20:21:17 +00:00
Jim Grosbach
aead579017 ARM vmla/vmls assembly parsing for the lane index operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142413 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 20:14:56 +00:00
Jim Grosbach
687656c630 ARM vmov assembly parsing for the lane index operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142412 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 20:10:47 +00:00
Andrew Trick
90b7b12f01 Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns. 
Clean up the patterns, fix comments, and avoid confusing both tools
and coders. Note that the special adds/subs SelectionDAG nodes no
longer have the dummy cc_out operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142397 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 19:18:52 +00:00
Bob Wilson
9d45de252c Use isIntN and isUIntN to check for valid signed/unsigned numbers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142395 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 18:46:49 +00:00
Andrew Trick
7f5f0dae33 whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142394 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 18:40:53 +00:00
Bill Wendling
f7b0207f1e A landing pad could have more than one predecessor. In that case, we want that 
predecessor to remove the jump to it as well. Delay clearing the 'landing pad'
flag until after the jumps have been removed. (There is an implicit assumption
in several modules that an MBB which jumps to a landing pad has only two
successors.)
<rdar://problem/10304224>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142390 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 18:30:49 +00:00
Jim Grosbach
9120088979 ARM vmla/vmls assembly parsing for the lane index operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142389 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 18:27:07 +00:00
Jim Grosbach
0a0374018f ARM vqdmulh assembly parsing for the lane index operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142386 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 18:12:09 +00:00
Jim Grosbach
970f787a7e ARM vmul assembly parsing for the lane index operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142381 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 18:01:52 +00:00
Bruno Cardoso Lopes
c3f16b316a Final patch that completes old JIT support for Mips: 
-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.

Patch by Sasa Stankovic

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142378 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 17:50:36 +00:00
Bob Wilson
ad952ad8f0 Fix incorrect check for sign-extended constant BUILD_VECTOR. 
<rdar://problem/10298332>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142371 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 17:34:51 +00:00
Jim Grosbach
e873d2a148 ARM vqdmlal assembly parsing for the lane index operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142365 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 17:16:30 +00:00
Jim Grosbach
9858a48afc Thumb2 parsing of 'mov.w' gets the cc_out operand wrong. Add an alias for it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142363 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 17:09:35 +00:00
Jim Grosbach
f2f5bc60f6 ARM assembly parsing and encoding for VMOV.i64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142356 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 16:18:11 +00:00
Justin Holewinski
c3cab3aec0 PTX: Fix disabling of MAD instruction selection 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142352 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 13:39:20 +00:00
Duncan Sands
17001ce25c Fix a bunch of unused variable warnings when doing a release 
build with gcc-4.6.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142350 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 12:44:00 +00:00
Bill Wendling
40825fbb40 Coding style cleanups. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142341 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 07:40:22 +00:00
David Meyer
928698b14e Remove NaClMode 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142338 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 05:29:23 +00:00
Chad Rosier
fe04757f5e Add support for dynamic stack realignment when in thumb1 mode. 
rdar://10288916


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142337 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 05:28:00 +00:00
Joe Abbey
895ede819f Commit test, capitalizing store... keep it simple. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142336 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 04:44:36 +00:00
Eli Friedman
0851a29b6d Fix misc warnings. Patch by Joe Abbey. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142332 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 03:17:34 +00:00
Lang Hames
d8ffe5bb16 Backing out patch. Will refactor to remove the AsmParser dependency on Target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142323 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 00:23:49 +00:00
Jim Grosbach
6248a546f2 ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142321 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 00:22:00 +00:00
Lang Hames
5fa792e65a Re-applying the target data layout verification patch from r142288, plus appropriate CMake dependencies. 
Thanks to Raphael Espindola for tracking down the CMake issues.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142306 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 23:24:48 +00:00
Jim Grosbach
ea46110f57 ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142303 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 23:09:09 +00:00
Nick Lewycky
44d798d976 Add support for a new extension to the .file directive: 
.file filenumber "directory" "filename"

This removes one join+split of the directory+filename in MC internals. Because
bitcode files have independent fields for directory and filenames in debug info,
this patch may change the .o files written by existing .bc files.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142300 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 23:05:28 +00:00
Chad Rosier
3a7572ff61 Add a few FIXME comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142299 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 22:54:23 +00:00
Jim Grosbach
fa1ee88052 Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142297 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 22:41:42 +00:00
Rafael Espindola
10820d9a97 142288 broke the build: 
Linking CXX executable ../../bin/llvm-as
../../lib/libLLVMAsmParser.a(LLParser.cpp.o):/home/espindola/llvm/llvm/lib/AsmParser/LLParser.cpp:function llvm::LLParser::ParseTargetDefinition(): error: undefined reference to 'llvm::TargetData::parseSpecifier(llvm::StringRef, llvm::TargetData*)'
clang-3: error: linker command failed with exit code 1 (use -v to see invocation)

Revert "Validate target data layout strings."

This reverts commit 599d2d4c25.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142296 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 22:37:51 +00:00
Bill Wendling
13a7121858 Now Igor, throw the switch...give my creation life! 
Use the custom inserter for the ARM setjmp intrinsics. Instead of creating the
SjLj dispatch table in IR, where it frequently violates serveral assumptions --
in particular assumptions made by the landingpad instruction about what can
branch to a landing pad and what cannot. Performing this in the back-end allows
us to violate these assumptions without the IR getting angry at us.

It also allows us to perform a small optimization. We can shove the address of
the dispatch's basic block into the function context and not have to add code
around the setjmp to check for the return value and jump to the dispatch.

Neat, huh?
<rdar://problem/10116753>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142294 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 22:26:23 +00:00
Jim Grosbach
0e387b2877 ARM NEON "vmov.i8" immediate assembly parsing and encoding. 
NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142293 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 22:26:03 +00:00
Lang Hames
599d2d4c25 Validate target data layout strings. 
Invalid strings in asm files will result in parse errors. Invalid string literals passed to TargetData constructors will result in an assertion.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142288 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 22:05:34 +00:00
Benjamin Kramer
d2c6ff1ac6 Use a SmallVector for intrinsic argument types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142259 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 21:33:26 +00:00
Bill Wendling
a48ed4fc8f Don't renumber the blocks here. This could cause problems later on if another 
pass renumbers the blocks again.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142258 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 21:32:56 +00:00
Cameron Zwarich
6f9c28060f Pseudoinstructions should not be less constrained than the instruction they are 
lowered to. This fixes a lot of verifier failures on the test suite.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142254 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 21:20:13 +00:00
Jim Grosbach
698f3b068f Tidy up organization. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142248 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 21:00:11 +00:00
Bill Wendling
5bc85286ff Add a call to EmitSjLjDispatchBlock. 
Once the intrinsics are marked as having a custom inserter, it will call this
method to emit the dispatch table into the machine function.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142245 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 20:37:20 +00:00
Jim Grosbach
32ab4aff69 Fix improperly formed assert() call. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142239 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 20:22:59 +00:00
Akira Hatanaka
8ae330ac90 Add definitions of conditional moves with 64-bit operands. Comment out code for 
expanding conditional moves, which is not needed since architectures that lack
support for conditional moves have been removed. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142226 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 18:53:29 +00:00
Hal Finkel
c61291609d Revert change to function alignment b/c existing logic was fine 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142224 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 18:53:03 +00:00
Chad Rosier
c378015d1c Removed set, but unused variables. 
Patch by Joe Abbey <jabbey@arxan.com>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142223 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 18:48:30 +00:00
Akira Hatanaka
8f3af87e99 Move class and instruction definitions for conditional moves to a seperate file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142220 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 18:43:19 +00:00
Akira Hatanaka
eea367ec97 Revert change made in r142205. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142217 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 18:33:24 +00:00
Akira Hatanaka
bdfd98a080 Redefine count-leading 0s and 1s instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142216 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 18:26:37 +00:00
Akira Hatanaka
89d306669e Redefine mfhi/lo and mthi/lo instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142214 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 18:24:15 +00:00
Akira Hatanaka
f1fddcd9e0 Redefine multiply and divide instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142211 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 18:21:24 +00:00
Akira Hatanaka
2d0a61da62 Add definition of a base class for logical shift/rotate instructions with two 
source registers and redefine 32-bit and 64-bit instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142210 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 18:17:58 +00:00
Hal Finkel
e9e5791556 Remove >80-col line and unicode 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142209 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 18:10:08 +00:00
Akira Hatanaka
363934665d Add definition of a base class for logical shift/rotate immediate instructions 
and have 32-bit and 64-bit instructions derive from it.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142207 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 18:06:56 +00:00
Akira Hatanaka
a01820a508 Add definition of immZExt5_64 and redefine immZExt5 as an ImmLeaf. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142205 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 18:01:00 +00:00
Michael J. Spencer
9904056a70 Fix CMake build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142204 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 17:50:39 +00:00
Devang Patel
827454e6e2 svn mv Target/ARM/ARMGlobalMerge.cpp Transforms/Scalar/GlobalMerge.cpp 
There is no reason to have simple IR level pass in lib/Target.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142200 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 17:17:43 +00:00
Hal Finkel
98daa9dcc8 Instructions for Book E PPC should be word aligned, set function alignment to reflect this 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142194 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 17:01:41 +00:00
Craig Topper
4b2dc74d3f Don't use inline assembly in 64-bit Visual Studio. Unfortunately, this means that cpuid leaf 7 can't be queried on versions of Visual Studio earlier than VS 2008 SP1. Fixes PR11147. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142177 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 05:33:10 +00:00
Bill Wendling
24bb925566 Add comment explaining that the order of processing doesn't matter here. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142176 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 05:25:09 +00:00
Hal Finkel
b31d3d271f Add PPC 440 scheduler and some associated tests (new files) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142171 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 04:03:55 +00:00
Hal Finkel
c6d08f10bf Add PPC 440 scheduler and some associated tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142170 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 04:03:49 +00:00
Craig Topper
ee62e4f6d1 Add X86 PEXTR and PDEP instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 16:50:08 +00:00
Benjamin Kramer
5efabcf01d Add AsmToken::getEndLoc and use it to add ranges to x86 asm register parsing. 
<stdin>:1:12: error: register %rax is only available in 64-bit mode
   incl    %rax
           ^~~~

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142137 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 12:10:27 +00:00
Benjamin Kramer
f82edaffb1 X86AsmParser: Synthesize EndLoc for tokens out of StartLoc + Length and print ranges for invalid operands. 
<stdin>:1:4: error: invalid instruction mnemonic 'abc'
   abc incl    %edi
   ^~~

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142135 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 11:28:29 +00:00
Nadav Rotem
c32a8c9073 Fix a bug in LowerV2I64Splat, which generated a BUILD_VECTOR for which there was 
no pattern.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142130 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 10:02:06 +00:00
Craig Topper
b53fa8bf19 Add X86 BZHI instruction as well as BMI2 feature detection. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 07:55:05 +00:00
Craig Topper
dc479c4a89 Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142117 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 07:05:40 +00:00
Cameron Zwarich
daada347b5 Add flags on Thumb2 indexed stores paralleling the flags on the indexed loads. 
These missing flags show up as errors when running -verify-coalescing on
test-suite.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142111 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 06:38:10 +00:00
Cameron Zwarich
d575137634 Fix an obvious typo found when looking at nearby code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142110 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 06:38:06 +00:00
Chris Lattner
d8b7aa2613 Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does. Enhance 
the X86 asmparser to produce ranges in the one case that was annoying me, for example:

test.s:10:15: error: invalid operand for instruction
movl 0(%rax), 0(%edx)
              ^~~~~~~

It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use 
ranges where appropriate if someone is interested.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142106 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 04:47:35 +00:00
Craig Topper
17730847d5 Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142105 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 03:51:13 +00:00
Craig Topper
4145c49aa0 Add X86 feature detection support for BMI instructions. Added new cpuid function for accessing leafs with sub leafs specified in ECX. Also added code to keep track of the max cpuid level supported in both basic and extended leaves and qualified the existing cpuid calls and the new call to leaf 7. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142089 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 00:21:51 +00:00
Craig Topper
566f233ba6 Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142082 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-15 20:46:47 +00:00