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15150 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
7144821c61 Add AVX SSE3 packed addsub instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107404 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 17:08:18 +00:00
Dan Gohman
20d4be151b Enable on-demand fast-isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107377 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 02:58:57 +00:00
Dan Gohman
abd1d859b3 Fix X86FastISel's add folding to actually work, and not fall back 
to SelectionDAG.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107376 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 02:58:21 +00:00
Bruno Cardoso Lopes
79b634c244 Add AVX SSE3 replicate and convert instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107375 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 02:33:39 +00:00
Dan Gohman
5c87bf64d6 Teach X86FastISel to fold constant offsets and scaled indices in 
the same address.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107373 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 02:27:15 +00:00
Bruno Cardoso Lopes
6596a62076 - Add AVX SSE2 Move doubleword and quadword instructions. 
- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
  in the .td file now have a AVX encoded form already working.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107365 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 01:20:06 +00:00
Bruno Cardoso Lopes
7ac7ed868a Move MOVD/MODQ code around, creating sections for each of them 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107308 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 18:49:10 +00:00
Bruno Cardoso Lopes
e26f14d150 Add AVX SSE2 mask creation and conditional store instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107306 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 18:38:10 +00:00
Bruno Cardoso Lopes
130acd15fc Fix a bug introduced in r107211 where instructions with memory operands are declared as commutable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107300 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 18:06:01 +00:00
Bruno Cardoso Lopes
1e4b723b20 Add AVX SSE2 packed integer extract/insert instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107293 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 17:03:03 +00:00
Gabor Greif
e1c2b9cc3d use ArgOperand API 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107280 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 13:03:37 +00:00
Bruno Cardoso Lopes
876085dcfa Add AVX SSE2 integer unpack instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107246 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 04:06:39 +00:00
Bruno Cardoso Lopes
d252fec7ae Add AVX SSE2 packed integer shuffle instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107245 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 03:47:56 +00:00
Bruno Cardoso Lopes
555bea62dd Small refactoring of SSE2 packed integer shuffle instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107243 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 03:29:36 +00:00
Bruno Cardoso Lopes
6d5d2b5de2 Add AVX SSE2 pack with saturation integer instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107241 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 02:30:25 +00:00
Bruno Cardoso Lopes
c0ea94a37c Add AVX SSE2 integer packed compare instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107240 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 02:21:09 +00:00
Bruno Cardoso Lopes
5a3a476750 - Add AVX form of all SSE2 logical instructions 
- Add VEX encoding bits to x86 MRM0r-MRM7r


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107238 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 01:58:37 +00:00
Bruno Cardoso Lopes
6c9fa43716 Add *several* AVX integer packed binop instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107225 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 23:47:49 +00:00
Bill Wendling
07d3177117 Revert r107205 and r107207. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107215 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 22:34:52 +00:00
Eric Christopher
33634d0672 Add another bswap idiom that isn't matched. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107213 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 22:22:22 +00:00
Bruno Cardoso Lopes
2c818072cc Move SSE2 Packed Integer instructions around, and create specific sections for each of them 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107211 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 22:12:16 +00:00
Bruno Cardoso Lopes
8d3cebca8e Add AVX Move Aligned/Unaligned packed integers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107206 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 21:25:12 +00:00
Bill Wendling
207855cff9 Introducing the "linker_weak" linkage type. This will be used for Objective-C 
metadata types which should be marked as "weak", but which the linker will
remove upon final linkage. For example, the "objc_msgSend_fixup_alloc" symbol is
defined like this:

       .globl l_objc_msgSend_fixup_alloc
       .weak_definition l_objc_msgSend_fixup_alloc
       .section __DATA, __objc_msgrefs, coalesced
       .align 3
l_objc_msgSend_fixup_alloc:
        .quad   _objc_msgSend_fixup
        .quad   L_OBJC_METH_VAR_NAME_1

This is different from the "linker_private" linkage type, because it can't have
the metadata defined with ".weak_definition".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107205 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 21:24:00 +00:00
Bruno Cardoso Lopes
147b7cad2f Add AVX ld/st XCSR register. 
Add VEX encoding bits for MRMXm x86 form



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107204 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 20:35:48 +00:00
Bob Wilson
21773e716f Add support for encoding VDUP (ARM core register) instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107201 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 20:13:29 +00:00
Bruno Cardoso Lopes
721ef73d88 Add AVX non-temporal stores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107178 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 18:22:01 +00:00
Bruno Cardoso Lopes
de173ca1fb Move non-temporal movs to their own section 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107168 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 17:42:37 +00:00
Bob Wilson
d5a563de07 Add support for encoding NEON VMOV (from core register to scalar) instructions. 
The encoding is the same as VMOV (from scalar to core register) except that
the operands are in different places.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107167 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 17:34:07 +00:00
Bruno Cardoso Lopes
ea86423cbd Add sqrt, rsqrt and rcp AVX instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107166 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 17:26:30 +00:00
Jim Grosbach
077f1bfa91 skip dbg_value instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107154 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 16:55:24 +00:00
Bob Wilson
1ab38469df The t2MOVi16 and t2MOVTi16 instructions do not set CPSR. Trying to add 
a CPSR operand to them causes an assertion failure, so apparently these
instructions haven't been getting a lot of use.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107147 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 16:25:11 +00:00
Rafael Espindola
d31f972bd3 Add a VT argument to getMinimalPhysRegClass and replace the copy related uses 
of getPhysicalRegisterRegClass with it.

If we want to make a copy (or estimate its cost), it is better to use the
smallest class as more efficient operations might be possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107140 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 14:02:34 +00:00
Duncan Sands
31a3a3ebaf Remove pointless variable LastDef. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107135 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 13:23:22 +00:00
Duncan Sands
58c86910b3 Remove unused variable Loc and pointless variables unified_syntax 
and thumb_mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107133 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 13:04:35 +00:00
Duncan Sands
978189e090 Remove an unused and a pointless variable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107131 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 13:00:29 +00:00
Duncan Sands
78337b4d4d Remove pointless and unused variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107130 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 12:48:49 +00:00
Duncan Sands
90c64f4aac Remove initialized but otherwise unused variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107127 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 11:22:26 +00:00
Evan Cheng
c36b5b9730 PR7503: uxtb16 is not available for ARMv7-M. Patch by Brian G. Lucas. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107122 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 05:38:36 +00:00
Evan Cheng
c170f66742 Change if-cvt options to something that actually as useable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107121 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 05:37:59 +00:00
Bruno Cardoso Lopes
b22dc70a5c Refactoring of arithmetic instruction classes with unary operator 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107116 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 01:33:09 +00:00
Jakob Stoklund Olesen
628a79771b When no memoperands are present, assume unaligned, volatile. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107114 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 01:13:07 +00:00
Bruno Cardoso Lopes
4548260ab5 Described the missing AVX forms of SSE2 convert instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107108 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 00:36:02 +00:00
Bob Wilson
5cdede43e9 Fix Thumb encoding of VMOV (scalar to ARM core register). The encoding is 
the same as ARM except that the condition code field is always set to ARMCC::AL.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107107 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 00:26:13 +00:00
Bob Wilson
62d24a4b92 Make the ARMCodeEmitter identify Thumb functions via ARMFunctionInfo instead 
of the Subtarget.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107086 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-28 22:23:17 +00:00
Jim Grosbach
e89c5e57cc tidy up style. no functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107073 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-28 21:29:17 +00:00
Bob Wilson
08baddbc07 Refactor encoding function for NEON 1-register with modified immediate format. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107070 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-28 21:16:30 +00:00
Bob Wilson
d896a97dc7 Support Thumb mode encoding of NEON instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107068 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-28 21:12:19 +00:00
Bill Wendling
c25ccf85e5 Reduce indentation via early exit. NFC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107067 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-28 21:08:32 +00:00
Jim Grosbach
e9e3f20ffb minor housekeeping cleanup: 80-column, trailing whitespace, spelling, etc.. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106988 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-28 04:27:01 +00:00
Gabor Greif
7a1d92a2cb use ArgOperand API 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106946 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-26 12:17:21 +00:00
Gabor Greif
6bec14fea0 use ArgOperand API 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106945 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-26 12:09:10 +00:00
Gabor Greif
1cfe44a460 use ArgOperand API 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106944 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-26 11:51:52 +00:00
Eli Friedman
a2c6f457a4 Followup to r106770: actually generate SXTB and SXTH for sign-extensions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106940 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-26 04:36:50 +00:00
Bob Wilson
52e4a0a074 Add support for encoding NEON VMOV (from scalar to core register) instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106938 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-26 04:07:15 +00:00
Evan Cheng
f6799394d5 It's now possible to run code placement pass for ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106935 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-26 01:52:05 +00:00
Jakob Stoklund Olesen
4f5d84e4ad When creating X86 MUL8 and DIV8 instructions, make sure we don't produce 
CopyFromReg nodes for aliasing registers (AX and AL). This confuses the fast
register allocator.

Instead of CopyFromReg(AL), use ExtractSubReg(CopyFromReg(AX), sub_8bit).

This fixes PR7312.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106934 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-26 00:39:23 +00:00
Bob Wilson
80d9bc0336 Renumber NEON instruction formats to be consecutive. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106927 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-26 00:05:09 +00:00
Bob Wilson
184723d9be Rename ARM instruction formats NEONGetLnFrm, NEONSetLnFrm and NEONDupFrm to 
"N..." instead of "NEON..." for consistency with the other NEON format names.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106921 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 23:56:05 +00:00
Bruno Cardoso Lopes
bdffc16d65 Add AVX convert CVTSS2SI{rr,rm} and CVTDQ2PS{rr,rm} instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106917 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 23:47:23 +00:00
Bob Wilson
2653263165 Remove unused NEONFrm and ThumbMiscFrm ARM instruction formats. 
Renumber MiscFrm to 25.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106916 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 23:45:37 +00:00
Bruno Cardoso Lopes
161476ec34 Reapply r106896: 
Add several AVX MOV flavors
Support VEX encoding for MRMDestReg



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106912 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 23:33:42 +00:00
Daniel Dunbar
e39e06af38 Thumb2ITBlockPass: Fix a possible dereference of an invalid iterator. This was 
introduced in r106343, but only showed up recently (with a particular compiler &
linker combination) because of the particular check, and because we have no
builtin checking for dereferencing the end of an array, which is truly
unfortunate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106908 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 23:14:54 +00:00
Bruno Cardoso Lopes
95325b08a3 revert this now, it's using avx instead of sse :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106906 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 23:04:29 +00:00
Evan Cheng
13151432ed Change if-conversion block size limit checks to add some flexibility. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106901 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 22:42:03 +00:00
Bob Wilson
5e7b607f72 Add support for encoding 3-register NEON instructions, and fix 
emitNEON2RegInstruction's handling of 2-address operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106900 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 22:40:46 +00:00
Bruno Cardoso Lopes
544a95d716 Add several AVX MOV flavors 
Support VEX encoding for MRMDestReg



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106896 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 22:27:51 +00:00
Dale Johannesen
1784d160e4 The hasMemory argument is irrelevant to how the argument 
for an "i" constraint should get lowered; PR 6309.  While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106893 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 21:55:36 +00:00
Bob Wilson
583a2a0615 Add support for encoding 2-register NEON instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106891 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 21:17:19 +00:00
Dan Gohman
ca5b8553ea pcmpeqd and friends are Commutable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106886 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 21:05:35 +00:00
Bob Wilson
8c605c601d Fix indentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106881 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 20:54:44 +00:00
Bill Wendling
730c07e50d - Reapply r106066 now that the bzip2 build regression has been fixed. 
- 2010-06-25-CoalescerSubRegDefDead.ll is the testcase for r106878.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106880 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 20:48:10 +00:00
Bruno Cardoso Lopes
39afa908de Move the last piece of SSE2 convert instructions to the Convert Instructions section 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106877 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 20:29:27 +00:00
Bruno Cardoso Lopes
6560ed35b4 More SSE refactoring, this time with different types of MOVs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106876 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 20:22:12 +00:00
Jim Grosbach
57bb394803 IT instructions are considered to be scheduling hazards, but are scheduled 
with the following instructions. This is done via trickery by considering the
instruction preceding the IT to be the hazard. Care must be taken to ensure
it's the first non-debug instruction, or the presence of debug info will
affect codegen.

Part of the continuing work for rdar://7797940, making ARM code-gen unaffected
by the presence of debug information.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106871 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 18:43:14 +00:00
Bruno Cardoso Lopes
0491e132fc Refactoring of more SSE conversion instructions. Also add some AVX instrinsics Int_V... placeholders 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106867 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 18:06:22 +00:00
Bob Wilson
ade57fa619 Add missing ARM and Thumb data layout info for vector types. 
Radar 8128745.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106820 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 04:41:08 +00:00
Bob Wilson
86fe66db3a Reduce indentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106819 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 04:12:31 +00:00
Bruno Cardoso Lopes
a0ae87fd5d Add some AVX convert instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106815 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 00:39:30 +00:00
Bruno Cardoso Lopes
8b94297727 Refactoring of SSE convert intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106808 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 23:37:07 +00:00
Bruno Cardoso Lopes
f241b26792 Refactoring of SSE conversion instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106804 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 22:22:21 +00:00
Bruno Cardoso Lopes
e0c437333e Refactor SSE cmp intrinsics and declare the same for AVX 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106796 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 22:04:40 +00:00
Bruno Cardoso Lopes
788184365a - Add AVX COMI{SS,SD}{rr,rm} and UCOMI{SS,SD}{rr,rm}. 
- Fix a small VEX encoding issue.
- Move compare instructions to their appropriate place.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106787 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 20:48:23 +00:00
Dale Johannesen
e5ff9ef195 Disallow matching "i" constraint to symbol addresses when 
address requires a register or secondary load to compute
(most PIC modes).  This improves "g" constraint handling.  8015842.

The test from 2007 is attempting to test the fix for PR1761,
but since -relocation-model=static doesn't work on Darwin
x86-64, it was not testing what it was supposed to be testing
and was passing erroneously.  Fixed to use Linux x86-64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106779 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 20:14:51 +00:00
Evan Cheng
8acf67672b Oops. IT block formation pass needs to be run at any optimization level. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106775 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 19:10:14 +00:00
Eli Friedman
761fa7af9e Always allow Thumb-2 SXTB, SXTH, UXTB, and UXTH. Fixes PR7324. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106770 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 18:20:04 +00:00
Bob Wilson
789fef987f PR7458: Try commuting Thumb2 instruction operands to put them into 2-address 
form so they can be narrowed to 16-bit instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106762 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 16:50:20 +00:00
Dan Gohman
4e39e9da0f Reapply r106634, now that the bug it exposed is fixed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106746 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 14:30:44 +00:00
Chris Lattner
645b209c4a Teach the x86 mc assembler that %dr6 = %db6, this implements 
rdar://8013734


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106725 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 07:29:18 +00:00
Chris Lattner
adabe1a92c more cleanups 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106724 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 07:18:14 +00:00
Chris Lattner
02758a44e4 reduce indentation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106723 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 07:16:25 +00:00
Chris Lattner
f8cbde46fb fix breakage from r98938 by correctly marking msp430 calls as variadic. 
Patch by Ben Ransford!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106722 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 06:46:50 +00:00
Dan Gohman
6b13cbca61 Fix a bug in the code which determines when it's safe to use the 
bt instruction, which was exposed by r106263.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106718 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 02:07:59 +00:00
Eric Christopher
37106afe02 Add a couple more quick comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106717 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 02:07:57 +00:00
Devang Patel
e9916a302f Use ValueMap instead of DenseMap. 
The ValueMapper used by various cloning utility maps MDNodes also.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106706 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 00:33:28 +00:00
Bruno Cardoso Lopes
6539dc6e6c Add AVX CMP{SS,SD}{rr,rm} instructions and encoding testcases 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106705 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 00:32:06 +00:00
Bruno Cardoso Lopes
34a491bd8e Move SSE and AVX shuffle, unpack and compare code to more appropriate places 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106702 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 00:15:50 +00:00
Bill Wendling
4b722108e2 We are missing opportunites to use ldm. Take code like this: 
void t(int *cp0, int *cp1, int *dp, int fmd) {
  int c0, c1, d0, d1, d2, d3;
  c0 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
  c1 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
  /* ... */
}

It code gens into something pretty bad. But with this change (analogous to the
X86 back-end), it will use ldm and generate few instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106693 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 23:00:16 +00:00
Bruno Cardoso Lopes
e93e300ad0 Add AVX MOVMSK{PS,PD}rr instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106683 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 21:30:27 +00:00
Bruno Cardoso Lopes
428256b818 Add tests for different AVX cmp opcodes, also teach the x86 asm parser to understand the vcmp instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106678 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 21:10:57 +00:00
Eric Christopher
749bb7e2d9 Update according to feedback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106677 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 20:49:35 +00:00