Commit Graph

5808 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
5ca0d14915 Vector shuffle mask <i32 4, i32 5, i32 2, i32 3> should yield "movsd", not "movss".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139686 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14 02:36:14 +00:00
Devang Patel
d2aaaf3a75 Remove ancient debug info constructs from test cases, they are not relevant to test case's main objective.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14 00:29:50 +00:00
Devang Patel
64789c582c Remove unnecessary old test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139674 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14 00:28:54 +00:00
Akira Hatanaka
8395c91d56 Delete test cases that generate code for allegrex/psp and cannot be repurposed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139652 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 22:29:13 +00:00
Eli Friedman
fe731214d2 Error out on CodeGen of unaligned load/store. Fix test so it isn't accidentally testing that case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139641 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 20:50:54 +00:00
Akira Hatanaka
a4b97f327d Add pattern used to match MipsLo, which is needed when the instruction selector
tries to match a dead MipsLo node (explanation in the link below).

http://article.gmane.org/gmane.comp.compilers.llvm.devel/42757/match=dagcombiner+dead



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139634 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 20:13:58 +00:00
Akira Hatanaka
302fdecf9d Disable tests which generate code for allegrex or psp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139632 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 20:00:35 +00:00
Nadav Rotem
e1490d1e43 update checked pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139631 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 19:59:18 +00:00
Nadav Rotem
aec5861bb6 Add vselect target support for targets that do not support blend but do support
xor/and/or (For example SSE2).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139623 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 19:17:42 +00:00
Andrew Trick
3c8015aa6c Generalize this test's CHECK statements to handle different indvars modes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139577 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 02:46:27 +00:00
Bruno Cardoso Lopes
8970060a4c Change testcase commandline to be more strict and silence buildbots
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139554 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 22:59:26 +00:00
Bruno Cardoso Lopes
5fc48100ee Fix PR10845. SUBREG_TO_REG shouldn't be used when the input and
destination types are equal!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139553 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 22:59:23 +00:00
Bruno Cardoso Lopes
457d53d9ce Revert the wrong part of r139528, and fix testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139541 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 21:24:07 +00:00
Bruno Cardoso Lopes
8e03a821f9 Not sure how CMPPS and CMPPD had already ever worked, I guess it didn't.
However with this fix it does now.

Basically the operand order for the x86 target specific node
is not the same as the instruction, but since the intrinsic need that
specific order at the instruction definition, just change the order
during legalization. Also, there were some wrong invertions of condition
codes, such as GE => LE, GT => LT, fix that too. Fix PR10907.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139528 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 19:30:40 +00:00
Eli Friedman
9f3b6a5a2a Fix mistake in test runline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139505 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 17:32:58 +00:00
Richard Osborne
a1d16b53e8 Associate a MemOperand with LDWCP nodes introduced during ISel.
This information is required if we want LDWCP to be hoisted out of loops.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139495 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 14:43:23 +00:00
Eli Friedman
cfeb55cdbc Really un-XFAIL the testcase, like I said I would in r139458.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139459 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10 02:02:27 +00:00
Richard Trieu
2db8628085 Fixed an assert from:
assert("not implemented for target shuffle node");

to:

  assert(0 && "not implemented for target shuffle node");

This causes a test failure in CodeGen/X86/palignr.ll which has
been marked as XFAIL for the time being.
Test failure filed at PR10901.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139454 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10 01:26:21 +00:00
Akira Hatanaka
33ff5aeaa8 Fix test cases.
Generate code for Mips32r1 unless a Mips32r2 feature is tested.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139433 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 23:14:58 +00:00
Eli Friedman
9db817fd0c Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the same type. Teach DAGCombiner::visitINSERT_VECTOR_ELT not to make invalid BUILD_VECTORs. Fixes PR10897.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139407 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 21:04:06 +00:00
Akira Hatanaka
8ddf6531b8 Drop support for Mips1 and Mips2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139405 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 20:45:50 +00:00
Nadav Rotem
8ffad56f8e Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139400 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 20:29:17 +00:00
Akira Hatanaka
d199d0c59c Drop support for Allegrex. Allegrex implements a variant of Mips2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139383 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 19:00:51 +00:00
Akira Hatanaka
ad5f0c9e73 Change default target architecture from Mips1 to Mips32r1 in preparation for
removing support for Mips1 and Mips2. 

This change and the ones that follow have been discussed with and approved by
Bruno.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139344 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 01:13:27 +00:00
Devang Patel
9aee335c23 Directly point debug info to the stack slot of the arugment, instead of trying to keep track of vreg in which it the arugment is copied. The LiveDebugVariable can keep track of variable's ranges.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139330 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 22:59:09 +00:00
Bruno Cardoso Lopes
7ec8fb8830 Add a AVX version of a simple i64 -> f64 bitcast. This could be
triggered using llc with -O0, which wouldn't let it be folded and
expose the lack of this pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139320 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 21:52:33 +00:00
Bruno Cardoso Lopes
7cf79a88c8 Reapply testcase from r139309!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139318 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 21:05:43 +00:00
Bruno Cardoso Lopes
caa60f15e4 Remove this crashing test, until I figure out what's going wrong here
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139309 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 18:32:36 +00:00
Bruno Cardoso Lopes
814c6ced85 Add AVX versions of blend vector operations and fix some issues noticed
in Nadav's r139285 and r139287 commits.

1) Rename vsel.ll to a more descriptive name
2) Change the order of BLEND operands to "Op1, Op2, Cond", this is
necessary because PBLENDVB is already used in different places with
this order, and it was being emitted in the wrong way for vselect
3) Add AVX patterns and tests for the same SSE41 instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139305 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 18:05:08 +00:00
Bruno Cardoso Lopes
7db2d3a504 Fix PR10844: Add patterns to cover non foldable versions of X86vzmovl.
Triggered using llc -O0. Also fix some SET0PS patterns to their AVX
forms and test it on the testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139304 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 18:05:02 +00:00
Nadav Rotem
4b36e07487 This test is already covered by llvm/trunk/test/CodeGen/X86/vsel.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139288 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 08:43:23 +00:00
Nadav Rotem
cbdd2d10ba add a testcase for the previous patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139287 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 08:31:31 +00:00
Nadav Rotem
ffe3e7da84 Add X86-SSE4 codegen support for vector-select.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139285 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 08:11:19 +00:00
Eli Friedman
d5ccb0558f Fix atomic load and store on x86 to pass -verify-machineinstrs (and possibly fix some subtle bugs involving passes which check mayStore()).
This isn't exactly ideal, but it is good enough for the moment.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139245 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 18:48:32 +00:00
Duncan Sands
68b859f757 Another forgotten trampoline testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139230 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 10:05:14 +00:00
Eli Friedman
981a010c09 Relax the MemOperands on atomics a bit. Fixes -verify-machineinstrs failures for atomic laod/store on ARM.
(The fix for the related failures on x86 is going to be nastier because we actually need Acquire memoperands attached to the atomic load instrs, etc.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139221 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 02:23:42 +00:00
Devang Patel
541a81cc2b While sinking machine instructions, sink matching DBG_VALUEs also otherwise live debug variable pass will drop DBG_VALUEs on the floor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139208 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 00:07:58 +00:00
Nick Lewycky
756a0a1f39 Disable these tests harder. They're XFAIL'd, but that means they still run, and
these tests all infinitely recurse, bringing my system down into swapping hell.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139192 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 22:08:18 +00:00
Evan Cheng
4a51708448 Fix fall outs from my recent change on how carry bit is modeled during isel.
Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well.
Also fix isel hook to correctly set the optional operand.
rdar://10073745


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139157 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 18:52:20 +00:00
Jakob Stoklund Olesen
9b0e1e7a5b Atomic pseudos don't use (as in read) CPSR. They clobber it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139148 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 17:40:35 +00:00
Duncan Sands
4a544a79bd Split the init.trampoline intrinsic, which currently combines GCC's
init.trampoline and adjust.trampoline intrinsics, into two intrinsics
like in GCC.  While having one combined intrinsic is tempting, it is
not natural because typically the trampoline initialization needs to
be done in one function, and the result of adjust trampoline is needed
in a different (nested) function.  To get around this llvm-gcc hacks the
nested function lowering code to insert an additional parent variable
holding the adjust.trampoline result that can be accessed from the child
function.  Dragonegg doesn't have the luxury of tweaking GCC code, so it
stored the result of adjust.trampoline in the memory GCC set aside for
the trampoline itself (this is always available in the child function),
and set up some new memory (using an alloca) to hold the trampoline.
Unfortunately this breaks Go which allocates trampoline memory on the
heap and wants to use it even after the parent has exited (!).  Rather
than doing even more hacks to get Go working, it seemed best to just use
two intrinsics like in GCC.  Patch mostly by Sanjoy Das.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139140 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 13:37:06 +00:00
Dan Gohman
b116142d3b Revert r129875, XFAILing this test for arm, since the fix was reverted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139058 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 00:14:24 +00:00
Jakob Stoklund Olesen
5047d76575 Pseudo CMOV instructions don't clobber EFLAGS.
The explanation about a 0 argument being materialized as xor is no
longer valid.  Rematerialization will check if EFLAGS is live before
clobbering it.

The code produced by X86TargetLowering::EmitLoweredSelect does not
clobber EFLAGS.

This causes one less testb instruction to be generated in the cmov.ll
test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139057 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 23:52:55 +00:00
Bill Wendling
47e208bbea Try to eliminate the use of the 'unwind' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139046 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 22:41:11 +00:00
Eli Friedman
4136d23c48 Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139044 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 22:33:24 +00:00
Bill Wendling
d5941195e2 Better fix for this testcase. Update it to the new EH scheme entirely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139039 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 21:27:08 +00:00
Bill Wendling
cc6927b9e1 Update for new EH stuff. (I'm not sure if this is 100% correct.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139038 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 21:24:17 +00:00
Duncan Sands
147272b8a7 Darwin wants ctors/dtors to be ordered the other way round to linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139015 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 18:07:19 +00:00
Kalle Raiskila
989621f1f8 Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139004 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 10:05:01 +00:00
Dan Gohman
6b13cd4154 Revert r131152, r129796, r129761. This code is currently considered
to be unreliable on platforms which require memcpy calls, and it is
complicating broader legalize cleanups. It is hoped that these cleanups
will make memcpy byval easier to implement in the future.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138977 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01 23:07:08 +00:00