6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-30 19:29:20 +00:00
Code Issues Projects Releases Wiki Activity
82,237 Commits 39 Branches 0 Tags 277 MiB
6643d9c180
Commit Graph

1098 Commits

Author SHA1 Message Date
Craig Topper
c5eaae4e9b Convert more static tables of registers used by calling convention to uint16_t to reduce space. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152538 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-11 07:57:25 +00:00
Craig Topper
b78ca42384 Use uint16_t to store registers and opcode in static tables in the target specific backends. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152537 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-11 07:16:55 +00:00
Akira Hatanaka
d229b7b8f4 Do not custom lower i64 nodes if i64 is not a legal type. Move lines that set 
operation action of nodes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152452 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-10 00:03:50 +00:00
Akira Hatanaka
0a40c2353c Lower SETCC nodes during legalization. Previously, it was lowered in DAG combine pass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152450 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-09 23:46:03 +00:00
Akira Hatanaka
6e1beea6bf Remove unused header files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152447 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-09 23:28:30 +00:00
Ahmed Charles
e38ec24758 Fix undefined behavior in the Mips backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152390 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-09 06:36:45 +00:00
Akira Hatanaka
ee8c3b03fb Invoke setTargetDAGCombine for SELECT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152290 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-08 03:26:37 +00:00
Akira Hatanaka
e2bdf7fc93 Swap the operands of a select node if the false (the second) operand is 0. 
For example, this pattern 
(select (setcc lhs, rhs, cc), true, 0)
is transformed to this one:
(select (setcc lhs, rhs, inverse(cc)), 0, true)

This enables MipsDAGToDAGISel::ReplaceUsesWithZeroReg (added in r152280) to
replace 0 with $zero.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152285 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-08 02:14:24 +00:00
Akira Hatanaka
5fdf50065d Set minimum function alignment to 3 if target is Mips64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152282 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-08 01:59:33 +00:00
Akira Hatanaka
7065b7b203 This patch eliminates redundant instructions that produce 0. 
For example, the first instruction in the code below can be eliminated if the
use of $vr0 is replaced with $zero: 

addiu $vr0, $zero, 0
add $vr2, $vr1, $vr0

add $vr2, $vr1, $zero



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152280 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-08 01:51:59 +00:00
Jim Grosbach
c6449b636f Make MCRegisterInfo available to the the MCInstPrinter. 
Used to allow context sensitive printing of super-register or sub-register
references.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152043 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-05 19:33:20 +00:00
Craig Topper
9ebfbf8b9f Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce static data size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152016 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-05 05:37:41 +00:00
Craig Topper
e4fd907e72 Use uint16_t to store register overlaps to reduce static data. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152001 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-04 10:43:23 +00:00
Craig Topper
015f228861 Use uint16_t to store registers in callee saved register tables to reduce size of static data. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151996 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-04 03:33:22 +00:00
Akira Hatanaka
b2930b92d3 Changes for migrating to using register mask operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151847 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-01 22:27:29 +00:00
Akira Hatanaka
dfa27aea12 Fix bugs which were introduced when support for base+index floating point loads 
and stores was added.

- SelectAddr should return false if Parent is an unaligned f32 load or store.
- Only aligned load and store nodes should be matched to select reg+imm
  floating point instructions.
- MIPS does not have support for f64 unaligned load or store instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151843 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-01 22:12:30 +00:00
Akira Hatanaka
e9e520f23e Pass endian information to constructors. Define separate functions to create 
objects for big endian and little endian targets.

Patch by Jack Carter.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151788 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-01 01:53:15 +00:00
Evan Cheng
4bfcd4acbc Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151645 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-28 18:51:51 +00:00
Daniel Dunbar
20bd5296ce Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151630 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-28 15:36:07 +00:00
Jia Liu
bb481f8820 remove blanks, and some code format 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151625 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-28 07:46:26 +00:00
Evan Cheng
ec52aaa12f Some ARM implementaions, e.g. A-series, does return stack prediction. That is, 
the processor keeps a return addresses stack (RAS) which stores the address
and the instruction execution state of the instruction after a function-call
type branch instruction.

Calling a "noreturn" function with normal call instructions (e.g. bl) can
corrupt RAS and causes 100% return misprediction so LLVM should use a
unconditional branch instead. i.e.
mov lr, pc
b _foo
The "mov lr, pc" is issued in order to get proper backtrace.

rdar://8979299


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151623 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-28 06:42:03 +00:00
Akira Hatanaka
980a999238 Add comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151615 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-28 03:18:43 +00:00
Akira Hatanaka
b75673b6e1 Do not reserve $gp as a dedicated global base register if the target ABI is not O32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151614 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-28 03:17:38 +00:00
Akira Hatanaka
44b6c715ac Add support for floating point base register + offset register addressing mode 
load and store instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151611 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-28 02:55:02 +00:00
Akira Hatanaka
3d14b9e28d Remove unnecessary template parameters. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151540 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-27 19:17:53 +00:00
Akira Hatanaka
b90113a23e Fix instruction predicates that were not set correctly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151538 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-27 19:09:08 +00:00
Jia Liu
c4a238c20f delete useless comment&blank 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151512 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-27 02:21:34 +00:00
Akira Hatanaka
e4ea241853 Add definitions of floating point multiply add/sub and negative multiply 
add/sub instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151415 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-25 00:21:52 +00:00
Akira Hatanaka
648f00c2f0 Add an option to use a virtual register as the global base register instead of 
reserving a physical register ($gp or $28) for that purpose.

This will completely eliminate loads that restore the value of $gp after every
function call, if the register allocator assigns a callee-saved register, or
eliminate unnecessary loads if it assigns a temporary register. 

example:

.cpload $25       // set $gp.
...
.cprestore 16     // store $gp to stack slot 16($sp).
...
jalr $25          // function call. clobbers $gp.
lw $gp, 16($sp)   // not emitted if callee-saved reg is chosen.
...
lw $2, 4($gp)
...
jalr $25          // function call.
lw $gp, 16($sp)   // not emitted if $gp is not live after this instruction.
...



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151402 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-24 22:34:47 +00:00
Jia Liu
8060356377 comment fix 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151341 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-24 02:17:26 +00:00
Jia Liu
c2e2dcd56f some comment fix 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151340 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-24 02:15:57 +00:00
Jia Liu
fc77014f24 replace a balnk with - 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151337 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-24 02:05:28 +00:00
Jia Liu
1711cdf7f4 80 columns of Mips InstPrinter Makefile 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151332 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-24 01:47:01 +00:00
Craig Topper
44d23825d6 Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151134 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-22 05:59:10 +00:00
Akira Hatanaka
5990bd7ba6 Use a function in MathExtras to do sign extension. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151107 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-22 00:16:54 +00:00
Ahmed Charles
b0934ab7d8 Remove dead code. Improve llvm_unreachable text. Simplify some control flow. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150918 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-19 11:37:01 +00:00
Jia Liu
c5707112e7 remove Emacs-tag form .cpp files in Mips Backend, and fix some typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150805 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-17 08:55:11 +00:00
Akira Hatanaka
38bdc5762f Do not promote i32 arguments to i64. This was causing unnecessary sign extension 
instructions to be emitted.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150782 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-17 02:20:26 +00:00
Jia Liu
8f5e8c1cd6 add Emacs tag and fix some comment error in file headers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150775 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-17 01:23:50 +00:00
Akira Hatanaka
178d870795 Remove comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150739 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-16 22:52:29 +00:00
Akira Hatanaka
e3186774f3 Remove trailing whitespace. Add newline. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150706 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-16 17:48:20 +00:00
Craig Topper
bc2198133a Convert assert(0) to llvm_unreachable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149961 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-07 02:50:20 +00:00
Craig Topper
655b8de7b2 Convert assert(0) to llvm_unreachable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149814 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-05 07:21:30 +00:00
Andrew Trick
061efcfb3e TargetPassConfig: confine the MC configuration to TargetMachine. 
Passes prior to instructon selection are now split into separate configurable stages.
Header dependencies are simplified.
The bulk of this diff is simply removal of the silly DisableVerify flags.

Sorry for the target header churn. Attempting to stabilize them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149754 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-04 02:56:59 +00:00
Andrew Trick
843ee2e6a4 Added TargetPassConfig. The first little step toward configuring codegen passes. 
Allows command line overrides to be centralized in LLVMTargetMachine.cpp.
LLVMTargetMachine can intercept common passes and give precedence to command line overrides.
Allows adding "internal" target configuration options without touching TargetOptions.
Encapsulates the PassManager.
Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs.
Allows modifying the target configuration hooks without rebuilding the world.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149672 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-03 05:12:41 +00:00
Akira Hatanaka
6c2cf8b1fb Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which is 
needed to emit a 64-bit gp-relative relocation entry. Make changes necessary
for emitting jump tables which have entries with directive .gpdword. This patch
does not implement the parts needed for direct object emission or JIT.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149668 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-03 04:33:00 +00:00
Akira Hatanaka
3f5b107a4b Set the correct stack pointer register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149585 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-02 03:17:04 +00:00
Akira Hatanaka
590baca06c Expand EHSELECTION and EHSELECTION nodes. Set the correct exception pointer and 
selector registers.
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149584 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-02 03:13:40 +00:00
Akira Hatanaka
1ad175e7e0 Add DWARF numbers of 64-bit registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149583 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-02 02:56:14 +00:00
James Molloy
2d8955a77c Ensure .AliasedSymbol() is called on all uses of getSymbol(). Affects ARM and MIPS ELF backends. 
Fixes PR11877



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149180 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-28 15:58:32 +00:00
Akira Hatanaka
4bd73cac6a Mark 64-bit register RA_64 unused too. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148918 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-25 04:19:22 +00:00
Akira Hatanaka
de5a0b65c2 Modify MipsFrameLowering::emitPrologue and emitEpilogue. 
- Use MipsAnalyzeImmediate to expand immediates that do not fit in 16-bit.
- Change the types of variables so that they are sufficiently large to handle
  64-bit pointers.
- Emit instructions to set register $28 in a function prologue after
  instructions which store callee-saved registers have been emitted. 
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148917 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-25 04:12:04 +00:00
Akira Hatanaka
36e91e9599 Modify MipsRegisterInfo::eliminateFrameIndex to use MipsAnalyzeImmediate to 
expand offsets that do not fit in the 16-bit immediate field of load and store
instructions. Also change the types of variables so that they are sufficiently
large to handle 64-bit pointers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148916 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-25 03:55:10 +00:00
NAKAMURA Takumi
50da3cb0f8 MipsAnalyzeImmediate.h: Fix to add DataTypes.h for msvc. 
inttypes.h is not supplied in msvc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148912 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-25 03:34:41 +00:00
NAKAMURA Takumi
e0794d331a Target/Mips: Unbreak CMake build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148909 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-25 03:15:46 +00:00
Akira Hatanaka
57fa38225c Lower 64-bit immediates using MipsAnalyzeImmediate that has just been added. 
Add a test case to show fewer instructions are needed to load an immediate
with the new way of loading immediates.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148908 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-25 03:01:35 +00:00
Akira Hatanaka
dc81eae9d2 Add class MipsAnalyzeImmediate which comes up with an instruction sequence to 
load an immediate. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148900 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-25 01:43:36 +00:00
Akira Hatanaka
25dae8f4a3 Sign-extend 32-bit integer arguments when they are passed in 64-bit registers, 
which is what N32/64 does.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148875 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-24 23:18:43 +00:00
Akira Hatanaka
08067b26f7 Pass CCState by reference. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148871 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-24 22:07:36 +00:00
Akira Hatanaka
e6e4b3a002 Pattern for f32 to i64 conversion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148869 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-24 22:05:25 +00:00
Akira Hatanaka
5387f2e4f3 64-bit sign extension in register instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148862 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-24 21:41:09 +00:00
Owen Anderson
4f8dc7b17a Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148833 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-24 18:37:29 +00:00
David Blaikie
4d6ccb5f68 More dead code removal (using -Wunreachable-code) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 21:51:11 +00:00
Jakob Stoklund Olesen
71f0fc1ca8 Ignore register mask operands when lowering instructions to MC. 
This is similar to implicit register operands.  MC doesn't understand
register liveness and call clobbers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148437 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-18 23:52:19 +00:00
Jim Grosbach
ec3433852d Tidy up. MCAsmBackend naming conventions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148400 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-18 18:52:16 +00:00
Jakob Stoklund Olesen
31867660cb Add a CoveredBySubRegs property to Register descriptions. 
When set, this bit indicates that a register is completely defined by
the value of its sub-registers.

Use the CoveredBySubRegs property to infer which super-registers are
call-preserved given a list of callee-saved registers.  For example, the
ARM registers D8-D15 are callee-saved.  This now automatically implies
that Q4-Q7 are call-preserved.

Conversely, Win64 callees save XMM6-XMM15, but the corresponding
YMM6-YMM15 registers are not call-preserved because they are not fully
defined by their sub-registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148363 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-18 00:16:39 +00:00
David Blaikie
2dd674fdce Removing unused default switch cases in switches over enums that already account for all enumeration values explicitly. 
(This time I believe I've checked all the -Wreturn-type warnings from GCC & added the couple of llvm_unreachables necessary to silence them. If I've missed any, I'll happily fix them as soon as I know about them)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148262 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-16 23:24:27 +00:00
Rafael Espindola
29a17145ad Add big endian mips support. Based on a patch by Jack Carter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147924 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-11 04:04:14 +00:00
Rafael Espindola
fddf804597 Add the skeleton of an asm parser for mips. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147923 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-11 03:56:41 +00:00
Benjamin Kramer
f321e1075e Remove VectorExtras. This unused helper was written for a type of API that is discouraged now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147738 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-07 19:42:13 +00:00
Chad Rosier
a32a08c8e2 Fix uninitialized variable warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147676 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-06 20:02:49 +00:00
Akira Hatanaka
b0e7af7797 Enable -soft-float for MIPS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147541 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-04 19:29:11 +00:00
Akira Hatanaka
2010325a11 Rename immLUiOpnd. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147519 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-04 03:09:26 +00:00
Akira Hatanaka
f12e702a8c - Define base classes for Jump-and-link instructions and make 32-bit and 64-bit 
versions derive from them.
- JALR64 is not needed since N64 does not emit jal. 
- Add template parameter to BranchLink that sets the rt field. 
- Fix the set of temporary registers for O32 and N64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147518 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-04 03:02:47 +00:00
Akira Hatanaka
cb9dd72fdc Have getRegForInlineAsmConstraint return the correct register class when target 
is Mips64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147516 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-04 02:45:01 +00:00
Bruno Cardoso Lopes
ce8524c016 Cleanup Mips code and rename some variables. Patch by Jack Carter 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147383 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 21:09:41 +00:00
Bruno Cardoso Lopes
3aa035fa0c Improve Mips JIT. 
Implement encoder methods getJumpTargetOpValue and getBranchTargetOpValue
for jmptarget and brtarget Mips tablegen operand types in the code emitter
for old-style JIT. Rename the pc relative relocation for branches - new
name is Mips::reloc_mips_pc16.

Patch by Sasa Stankovic

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147382 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 21:04:30 +00:00
Akira Hatanaka
fd1d9250b2 Add MachineMemOperands to instructions generated in storeRegToStackSlot or 
loadRegFromStackSlot. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147235 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-24 03:11:18 +00:00
Akira Hatanaka
9dfd4399a9 Detect unaligned loads/stores that have been added for Mips64 support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147234 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-24 03:07:37 +00:00
Akira Hatanaka
9dbeb0284d If target ABI is N64, LEA should be daddiu. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147232 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-24 02:59:27 +00:00
Rafael Espindola
090445967f Move the Mips only bits of the ELF writer to lib/Target/Mips. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147133 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 03:03:17 +00:00
Akira Hatanaka
bc24985c5f Local dynamic TLS model for direct object output. Create the correct TLS MIPS 
ELF relocations.

Patch by Jack Carter.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147118 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 01:05:17 +00:00
Rafael Espindola
dc9a8a378d Reduce the exposure of Triple::OSType in the ELF object writer. This will 
avoid including ADT/Triple.h in many places when the target specific bits are
moved.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147059 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 17:00:36 +00:00
Akira Hatanaka
c7541c49a9 Fix bug in zero-store peephole pattern reported in pr11615. 
The patch and test case were originally written by Mans Rullgard.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147024 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 00:31:10 +00:00
Akira Hatanaka
c79507a4dd Expand 64-bit CTLZ nodes if target architecture does not support it. Add test 
case for DCLO and DCLZ.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147022 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 00:20:27 +00:00
Akira Hatanaka
7f162743fc Expand 64-bit CTPOP and CTTZ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147021 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 00:14:05 +00:00
Akira Hatanaka
9aed504c82 Expand 64-bit atomic load and store. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147019 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 00:02:58 +00:00
Akira Hatanaka
c0ea04389c Add definition of DSBH (Double Swap Bytes within Halfwords) and 
DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147017 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:56:43 +00:00
Akira Hatanaka
4d2b0f3ce7 Add definition of WSBH (Word Swap Bytes within Halfwords), which is an 
instruction supported by mips32r2, and add a pattern which replaces bswap with
a ROTR and WSBH pair.
 
WSBW is removed since it is not an instruction the current architectures
support.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147015 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:47:44 +00:00
Akira Hatanaka
e1bcd6b5c6 64-bit uint-fp conversion nodes are expanded. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147014 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:40:56 +00:00
Akira Hatanaka
9388383b34 Enable custom lowering DYNAMIC_STACKALLOC nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147013 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:35:46 +00:00
Akira Hatanaka
056a1bc40f Set the correct stack pointer register that should be saved or restored. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147012 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:28:36 +00:00
Akira Hatanaka
2fd0475cdb Add function MipsDAGToDAGISel::SelectMULT and factor out code that generates 
nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU
nodes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147008 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:10:57 +00:00
Akira Hatanaka
49d534bb3d Fix indentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147007 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:58:01 +00:00
Akira Hatanaka
8dc684d2a2 64-bit data directive. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147005 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:52:19 +00:00
Akira Hatanaka
ef43c2de86 32-to-64-bit sext_inreg pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147004 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:40:40 +00:00
Akira Hatanaka
acb5a06f7a Add 64-bit extload patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147003 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:36:08 +00:00
Akira Hatanaka
ab05b6c227 Add patterns for matching extloads with 64-bit address. The patterns are enabled 
only when the target ABI is N64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147001 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:33:53 +00:00
Akira Hatanaka
990d639f55 Add code in MipsDAGToDAGISel for selecting constant +0.0. 
MIPS64 can generate constant +0.0 with a single DMTC1 instruction. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146999 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:25:50 +00:00
Akira Hatanaka
05c585319b Revert part of r146995 that was accidentally commmitted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146996 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:09:36 +00:00