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Author SHA1 Message Date
Benjamin Kramer
b22da2a72c X86: smulo -> add is now done target-independently in DAGCombiner, remove the patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131801 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-21 18:32:01 +00:00
Cameron Zwarich
37fed38ec1 Fix PR9978 by adding RIP to GR64_TC so it can be used as an address in PIC code. It 
is already in GR64 for the same reasons. Since it isn't allocatable it can't cause
any problems.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131787 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-21 04:13:49 +00:00
Akira Hatanaka
52106e1e25 Use the correct register to access stack frame objects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131785 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-21 03:01:03 +00:00
Akira Hatanaka
f346c69530 Insert instructions that copy $sp to or from $fp at the right locations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131784 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-21 02:29:26 +00:00
Akira Hatanaka
43299776d7 Change the order fixed objects are created in MipsTargetLowering::LowerCall in 
preparation for reversing StackDirection.

Fixed objects are created in the following order:  
 1. Incoming arguments passed on stack.
 2. va_arg objects (include both arguments that are passed in registers and
    pointer to the location of the first va_arg argument).
 3. $gp restore slot.
 4. Outgoing arguments passed on stack.
 5. Pointer to alloca'd space.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131767 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-20 23:22:14 +00:00
Eli Friedman
c088345f13 Add fast-isel support for byval calls on x86. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131764 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-20 22:21:04 +00:00
Akira Hatanaka
d37776d1c1 In CC_MipsO32, allocate a stack space regardless of whether the argument is 
passed in register or on the stack.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131758 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-20 21:39:54 +00:00
Akira Hatanaka
6ffbf82e22 Define functions that get/set maximum call frame size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131752 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-20 20:11:17 +00:00
Rafael Espindola
b8adb8af0f adds some attributes to attribute section when cpu is "xscale" 
(this is what used in Android NDK, when architecture is ARMv5)

patch by Koan-Sin Tan

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131751 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-20 20:10:34 +00:00
Rafael Espindola
298c8e12ea fixes target address tBL and tBLX and sets relocation type 
of tBL/tBLX to R_ARM_THM_CALL (ARM ELF 4.7.1.6)

Patch by koan-sin tan.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131748 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-20 20:01:01 +00:00
Stuart Hastings
0e29ed081b Re-commit 131641 with fixes; de-pseudoize MOVSX16rr8 and friends. 
rdar://problem/8614450


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131746 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-20 19:04:40 +00:00
Akira Hatanaka
17a1e87751 Make $fp and $ra callee-saved registers and let PrologEpilogInserter handle 
saving and restoring them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131745 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-20 18:39:33 +00:00
Evan Cheng
0b65599015 Revert accidental commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131739 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-20 17:38:48 +00:00
Benjamin Kramer
eb274e6bdd Rename the "sandybridge" subtarget to "corei7-avx", for GCC compatibility. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131730 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-20 15:11:26 +00:00
Benjamin Kramer
6e35e4c8c1 Remove noisy semicolons. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131724 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-20 09:20:25 +00:00
Akira Hatanaka
cd0f90f831 Fix bug in which nodes that write to argument registers do not get glued with the JALR node. Patch by Sasa Stankovic 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131714 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-20 02:30:51 +00:00
Akira Hatanaka
d992f6c666 Remove code that creates unnecessary frame objects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131711 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-20 01:45:06 +00:00
Akira Hatanaka
da0a3571d6 Define variables and functions in MipsFunctionInfo. 
This is the first of a series of patches that attempt to simplify handling of 
stack frame objects. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131710 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-20 01:17:58 +00:00
Chad Rosier
a166089f36 Don't attempt to tail call optimize for Win64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131709 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-20 00:59:28 +00:00
Evan Cheng
2e6496026f Revert r131664 and fix it in instcombine instead. rdar://9467055 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131708 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-20 00:54:37 +00:00
Eli Friedman
dc51575a5f Add fast-isel support for zeroext and signext ret instructions on x86. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131689 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 22:16:13 +00:00
Eric Christopher
2bbecd8f6d Oddly people want to use the 'r' constraint for fp constants on x86. 
Fixes rdar://9218925
Fixes PR9601


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131682 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 21:33:47 +00:00
Jason W Kim
861b9c6a39 This fixes one divergence between LLVM and binutils for ARM in the 
text section.

Assume the following bit of annotated assembly:

.section	.data.rel.ro,"aw",%progbits
.align	2
.LAlpha:
.long	startval(GOTOFF)

.text
.align	2
.type	main,%function
.align	4

main: ;;; assume "main" starts at offset 0x20
0x0	push	{r11, lr}
0x4	movw	r0, :lower16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-4) + 8) = -20
0x8	movt	r0, :upper16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-8) + 8) = -16
0xc	... blah

.LBeta:
0x10	add	r0, pc, r0
0x14	... blah

.LGamma:
0x18	add	r1, pc, r1

Above snippet results in the following relocs in the .o file for the
first pair of movw/movt instructions

00000024 R_ARM_MOVW_PREL_NC .LAlpha
00000028 R_ARM_MOVT_PREL .LAlpha

And the encoded instructions in the .o file for main: must be

00000020 <main>:
20:	e92d4800 push	{fp, lr}
24:	e30f0fec movw	r0, #65516	; 0xffec i.e. -20
28:	e34f0ff0 movt	r0, #65520	; 0xfff0 i.e. -16

However, llc (prior to this commit) generates the following sequence

00000020 <main>:
20:	e92d4800 push	{fp, lr}
24:	e30f0fec movw	r0, #65516	; 0xffec - i.e. -20
28:	e34f0fff movt	r0, #65535	; 0xffff - i.e. -1

What has to happen in the ArmAsmBackend is that if the relocation is PC
relative, the 16 bits encoded as part of movw and movt must be both addends,
not addresses. It makes sense to encode addresses by right shifting the value
by 16, but the result is incorrect for PIC.
i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case.

This change agrees with what GNU as does, and makes the PIC code run.

MC/ARM/elf-movt.s covers this case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131674 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 20:55:25 +00:00
Rafael Espindola
a3bff99f0a ADD64ri32 sign extends its argument, so we need to use a R_X86_64_32S. 
Fixes PR9934.

We really need to start tblgening the relocation info :-(

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131669 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 20:32:34 +00:00
Akira Hatanaka
a1a7ba8382 Align i64 arguments to 64 bit boundaries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131668 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 20:29:48 +00:00
Evan Cheng
0efaa5e6a1 crc32 with 64-bit output zeros upper 32-bits. rdar://9467055 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131664 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 18:57:12 +00:00
Akira Hatanaka
59d266029c Increase number of available registers when target is MIPS32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131660 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 18:25:03 +00:00
Akira Hatanaka
95b8ae190e Simplify CC_MipsO32 and merge it with CC_MipsO32_VarArgs. Patch by Sasa Stankovic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131657 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 18:06:05 +00:00
Stuart Hastings
d22f036c2a Reverting 131641 to investigate 'bot complaint. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131654 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 17:54:42 +00:00
Jim Grosbach
6635b04a43 80 columns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131649 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 17:34:53 +00:00
Akira Hatanaka
d48cfaec35 Fix data layout string. i64 is aligned to 64 bit boundaries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131642 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 17:21:09 +00:00
Stuart Hastings
b6dcf3c514 Revise MOVSX16rr8/MOVZX16rr8 (and rm variants) to no longer be 
pseudos.  rdar://problem/8614450


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131641 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 16:59:50 +00:00
Cameron Zwarich
055cdfc541 Use the correct register class for Cell varargs spilling. This fixes all of the 
verifier failures in the CodeGen/CellSPU tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131631 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 04:44:19 +00:00
Mon P Wang
28e2b1d29a Fixed sdiv and udiv for <4 x i16>. The test from r125402 still applies for this change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131630 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 04:15:07 +00:00
Cameron Zwarich
d76773a221 Make CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll pass with the verifier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131627 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 03:11:06 +00:00
Cameron Zwarich
0113e4e3f2 Fix PR8828 by removing the explicit def in MovePCToLR as well as the pointless 
piclabel operand. The operand in the tablegen definition doesn't actually turn
into an MI operand, so it just confuses anything checking the TargetInstrDesc
for the number of operands. It suffices to just have an implicit def of LR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131626 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 02:56:28 +00:00
Cameron Zwarich
462b6dc6bf Reuse the TargetInstrDesc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131625 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 02:56:23 +00:00
Cameron Zwarich
21803721d5 Correctly constrain a register class when computing frame offsets, as the Thumb2 
add instruction takes an rGPR. This fixes the last of PR8825.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131619 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 02:18:27 +00:00
Eli Friedman
22486c9aba Revert unintentional commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131597 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 23:13:10 +00:00
Eli Friedman
107ffd58f7 More instcombine simplifications towards better debug locations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131596 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 23:11:30 +00:00
Cameron Zwarich
631fcbf810 Add missing mayLoad / mayStore flags to instruction definitions without patterns, 
which fixes all of the CodeGen/MBlaze verifier failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131595 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 23:03:10 +00:00
Cameron Zwarich
e4c6445405 Reserve the segment registers on x86 to fix verifier failures in any code that 
uses them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131591 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 22:24:48 +00:00
Cameron Zwarich
20a41cb2b2 Reserve r29 on Alpha. This fixes all verifier failures in CodeGen/Alpha. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131587 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 21:54:32 +00:00
Tanya Lattner
db28247522 Handle perfect shuffle case that generates a vrev for vectors of floats. 
Add test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131582 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 21:44:54 +00:00
Cameron Zwarich
955db42568 Fix more of PR8825. Now all of CodeGen/ARM passes with VerifyCoalescing turned on. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131578 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 21:25:14 +00:00
Johnny Chen
a96581f4f7 Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immediate operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131565 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 20:32:41 +00:00
Chad Rosier
871f664093 Enables vararg functions that pass all arguments via registers to be optimized into tail-calls when possible. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131560 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 19:59:50 +00:00
Evan Cheng
b936e3006f Revise r131553. Just use the type of the input node and forgo the bitcast. rdar://9449159. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131555 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 18:59:17 +00:00
Evan Cheng
d48fda46f5 Fix an ARMTargetLowering::LowerSELECT bug: legalized result must have same type as input. Sorry test cases only trigger when dag combine is disabled. rdar://9449178 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131553 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 18:47:27 +00:00
Justin Holewinski
657d1bed23 PTX: add flag to disable mad/fma selection 
Patch by Dan Bailey

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131537 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 15:42:23 +00:00
Tanya Lattner
2a8eb722c7 In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32. 
Updated test case and reverted change to the PerfectShuffle Table.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131529 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 06:42:21 +00:00
Cameron Zwarich
141ec63962 Fix typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131519 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 02:29:50 +00:00
Cameron Zwarich
7d336c0c68 Fix more of PR8825 by correctly using rGPR registers when lowering atomic 
compare-and-swap intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131518 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 02:20:07 +00:00
Cameron Zwarich
d6ffcd88ba Actually, the address operand of the Thumb2 LDREX / STREX instructions *can* 
take r13, so we can just make it a GPR. This fixes PR8825.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131507 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 23:26:20 +00:00
Cameron Zwarich
3c60ff4f3d Correct a minor problem with the Thumb2 LDREX and STREX instruction encodings. They 
were marked as taking a tGPR when in reality they take an rGPR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131506 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 23:11:12 +00:00
Tanya Lattner
c81c9709ef vrev is incorrectly defined in the perfect shuffle table. The ordering is backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131488 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 20:48:40 +00:00
Mon P Wang
fee22869ca Enable autodetect of popcnt 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131476 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 18:33:37 +00:00
Eli Friedman
19515b4e52 Add x86 fast-isel for calls returning first-class aggregates. rdar://9435872. 
This is r131438 with a couple small fixes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131474 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 18:29:03 +00:00
Eli Friedman
b8e0d3412c Clean up the mess created by r131467+r131469. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131471 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 18:02:22 +00:00
Stuart Hastings
6db2c2fe21 Revert 131467 due to buildbot complaint. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131469 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 16:59:46 +00:00
Stuart Hastings
504421e327 Fix an obscure issue in X86_64 parameter passing: if a tiny byval is 
passed as the fifth parameter, insure it's passed correctly (in R9).
rdar://problem/6920088


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131467 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 16:45:55 +00:00
Nadav Rotem
86694297ff Fix a bug in PerformEXTRACT_VECTOR_ELTCombine. The code created an ADD SDNode 
with two different types, in cases where the index and the ptr had different
types.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131461 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 08:31:57 +00:00
Eric Christopher
6abb7bae10 Update comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131459 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 08:16:14 +00:00
Eric Christopher
c324f72ab7 Support XOR and AND optimization with no return value. 
Finishes off rdar://8470697


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131458 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 08:10:18 +00:00
Eric Christopher
811c2b7110 Couple less magic numbers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131457 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 07:50:41 +00:00
Eric Christopher
8102bf003e Make this code a little less magic number laden. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131456 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 07:47:55 +00:00
Chris Lattner
5d4718b1c7 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131455 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 07:22:33 +00:00
Eli Friedman
c93943b6fe Back out r131444 and r131438; they're breaking nightly tests. I'll look into 
it more tomorrow.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131451 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 02:36:59 +00:00
Eli Friedman
cdc9a20561 Add x86 fast-isel for calls returning first-class aggregates. rdar://9435872. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131438 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 00:13:47 +00:00
Jim Grosbach
0c72076190 Kill some dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131431 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-16 22:24:07 +00:00
Eli Friedman
57f4b03621 Remove dead code. Fix associated test to use FileCheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131424 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-16 21:28:22 +00:00
Eli Friedman
482feb33b2 Make fast-isel work correctly s/uadd.with.overflow intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131420 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-16 21:06:17 +00:00
Rafael Espindola
6469540adf sets bit 0 of the function address of thumb function in .symtab 
("T is 1 if the target symbol S has type STT_FUNC and the
symbol addresses a Thumb instruction ;it is 0 otherwise."
from "ELF for the ARM Architecture" 4.7.1.2)

Patch by Koan-Sin Tan!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131406 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-16 16:17:21 +00:00
Eli Friedman
d0118a2371 Fix a FIXME by moving the fast-isel implementation of the objectsize intrinsic from the x86 code to the generic code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131332 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-14 00:47:51 +00:00
Rafael Espindola
a3f88148e6 Don't produce a vmovntdq if we don't have AVX support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131330 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-14 00:30:01 +00:00
Eli Friedman
d25d16c901 Zap useless code; this hasn't done anything useful since fast-isel switched to being bottom-up (a very long time ago). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131329 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-14 00:19:32 +00:00
Julien Lerouge
eea6c95d5d Fix a source of non determinism in FindUsedTypes, use a SetVector instead of a 
set.

rdar://9423996


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131283 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-13 05:20:42 +00:00
Akira Hatanaka
01765eb0a1 Fix setting of isCommutable flag. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131233 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-12 17:42:08 +00:00
Eric Christopher
c493a1f317 Turn this into a table, this will make more sense shortly. 
Part of rdar://8470697


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131200 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-11 21:44:58 +00:00
Owen Anderson
18901d63bf Fix encoding of Thumb BLX register instructions. Patch by Koan-Sin Tan. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131189 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-11 17:00:48 +00:00
Nadav Rotem
4301222525 Add custom lowering of X86 vector SRA/SRL/SHL when the shift amount is a splat vector. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131179 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-11 08:12:09 +00:00
Bill Wendling
61512ba251 Give the 'eh.sjlj.dispatchsetup' intrinsic call the value coming from the setjmp 
intrinsic call. This prevents it from being reordered so that it appears
*before* the setjmp intrinsic (thus making it completely useless).
<rdar://problem/9409683>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131174 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-11 01:11:55 +00:00
Eric Christopher
b38fe4b52d Optimize atomic lock or that doesn't use the result value. 
Next up: xor and and.

Part of rdar://8470697


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131171 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-10 23:57:45 +00:00
Eric Christopher
988397dcbc Refactor lock versions of binary operators to be a little less 
cut and paste.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131139 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-10 18:36:16 +00:00
Jason W Kim
f4351ceb93 First cut at getting debugging support for ARM/MC/ELF/.o 
DWARF stuff also gets fixed up by ELFARMAsmBackend::ApplyFixup(),
but the offset is not guaranteed to be mod 4 == 0 as in text/data. 




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131137 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-10 18:07:25 +00:00
Justin Holewinski
0d10970789 PTX: add PTX 2.3 setting in PTX sub-target. 
Patch by Wei-Ren Chen

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131123 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-10 12:32:11 +00:00
Eric Christopher
49ac3d7da9 Fix td file comments for Mips. 
Patch by Liu <proljc@gmail.com>!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131086 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-09 18:16:46 +00:00
Mon P Wang
183c627d89 Fixed MC encoding for index_align for VLD1/VST1 (single element from one lane) for size 32 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131085 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-09 17:47:27 +00:00
Benjamin Kramer
f51190b697 X86: Add a bunch of peeps for add and sub of SETB. 
"b + ((a < b) ? 1 : 0)" compiles into
	cmpl	%esi, %edi
	adcl	$0, %esi
instead of
	cmpl	%esi, %edi
	sbbl	%eax, %eax
	andl	$1, %eax
	addl	%esi, %eax

This saves a register, a false dependency on %eax
(Intel's CPUs still don't ignore it) and it's shorter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131070 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-08 18:36:07 +00:00
Jakob Stoklund Olesen
ca66226e7e Eliminate the ARM sub-register indexes that are not needed by the sources. 
Tablegen will invent its own names for these indexes, and the register file is a
bit simpler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131059 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-07 21:22:42 +00:00
Eric Christopher
33c110e602 Fix the non-MC encoding of pkhbt and pkhtb. 
Patch by Stephen Hines.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131045 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-07 04:37:27 +00:00
Akira Hatanaka
325e66d81a 1. Keep lines in 80 columns. 
2. Remove unused function.
3. Correct indentation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131028 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-06 22:11:29 +00:00
Eli Friedman
fc5d305597 Make the logic for determining function alignment more explicit. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131012 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-06 20:34:06 +00:00
Rafael Espindola
f2b0423200 Dead code elimination. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130984 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-06 14:56:22 +00:00
Justin Holewinski
ab0145d2a9 PTX: add PTX 2.3 language target 
Patch by Wei-Ren Chen

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130980 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-06 11:40:36 +00:00
Rafael Espindola
108709d4d1 Move PPC Linux to CFI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130951 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-05 21:34:33 +00:00
Eli Friedman
297015913a PR9848: pandn is not commutative. 
No test because I can't think of any way to write one that won't break quickly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130932 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-05 17:45:31 +00:00
Bill Wendling
087aad44cb Remove a flag that would set the ".eh" symbol as .globl. MachO was the only one 
who used this flag, and it now emits CFI and doesn't emit this anymore. All
other targets left this flag "false".
<rdar://problem/8486371>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130918 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-05 06:49:15 +00:00
Jakob Stoklund Olesen
4f5de9bb40 Fix X86RegisterInfo::getMatchingSuperRegClass for sub_8bit_hi. 
It is OK for B to be any GR8_ABCD_H superclass, the returned register class
doesn't have to map surjectively onto B.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130892 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-04 23:54:54 +00:00
Jakob Stoklund Olesen
21f7902a89 Implement SystemZRegisterInfo::getMatchingSuperRegClass to enable cross-class joins. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130857 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-04 19:02:04 +00:00
Devang Patel
64915dec28 Do not emit location expression size twice. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130854 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-04 19:00:57 +00:00
Rafael Espindola
6af0b762db Fix cmake build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130850 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-04 18:46:56 +00:00
Akira Hatanaka
6b7588e6c4 Prevent instructions using $gp from being placed between a jalr and the instruction that restores the clobbered $gp. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130847 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-04 17:54:27 +00:00
Jakob Stoklund Olesen
b89383aeff Implement MSP430RegisterInfo::getMatchingSuperRegClass to enable cross-class 
coalescing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130814 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-04 01:01:36 +00:00
Jakob Stoklund Olesen
2944b4fe05 Mark ultra-super-registers QQQQ as call-clobbered instead of the D sub-registers. 
LiveVariables doesn't understand that clobbering D0 and D1 completely overwrites
Q0, so if Q0 is live-in to a function, its live range will extend beyond a
function call that only clobbers D0 and D1. This shows up in the
ARM/2009-11-01-NeonMoves test case.

LiveVariables should probably implement the much stricter rules for physreg
liveness that RAFast imposes - a physreg is killed by the first use of any
alias.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130801 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-03 22:31:24 +00:00
Bill Wendling
9493a285d1 Replace the "movnt" intrinsics with a native store + nontemporal metadata bit. 
<rdar://problem/8460511>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130791 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-03 21:11:17 +00:00
Akira Hatanaka
9ff1b9b259 Fix function MipsRegisterInfo::getRegisterNumbering. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130774 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-03 18:41:54 +00:00
Bob Wilson
e1a56ae747 Temporarily disable use of divmod compiler-rt functions for iOS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130766 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-03 17:33:22 +00:00
Bruno Cardoso Lopes
0a69ba309f Fold ARM coprocessor intrinsics patterns into the instructions defs whenever 
it's possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130764 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-03 17:29:29 +00:00
Bruno Cardoso Lopes
54ad87ab78 Add a few ARM coprocessor intrinsics. Testcases included 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130763 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-03 17:29:22 +00:00
Benjamin Kramer
d2189bf12a Remove unused variables caught by GCC's -Wunused-but-set-variable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130755 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-03 16:00:27 +00:00
Michael J. Spencer
34868ee4de Add pentium{3,4}m cpus. Patch by Alexander Best! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130749 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-03 03:42:50 +00:00
Eric Christopher
2fc496fcf5 xmm0 is an implicit parameter in this and so shouldn't be in the 
string template.

Fixes rdar://8493866


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130747 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-03 01:28:32 +00:00
Dan Gohman
cca82149ad Add an unfolded offset field to LSR's Formula record. This is used to 
model constants which can be added to base registers via add-immediate
instructions which don't require an additional register to materialize
the immediate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130743 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-03 00:46:49 +00:00
Eric Christopher
52f6c03a45 Apparently the check for direct calls is unnecessary. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130716 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-02 20:16:33 +00:00
Rafael Espindola
2866edf120 Add 130690 back. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130693 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-02 15:58:16 +00:00
Rafael Espindola
b2d7336fde Revert while I debug the tests that use march but not mtriple. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130691 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-02 15:42:31 +00:00
Rafael Espindola
433771c514 Move ppc OS X to cfi too. I am building it on an old ppc mini, but it will take some time. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130690 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-02 15:00:52 +00:00
Rafael Espindola
450a5a1207 Add r130623 back now that ELF has been fixed to work with -fno-dwarf2-cfi-asm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130658 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-01 15:44:13 +00:00
Chandler Carruth
9bc1537488 Remove an unused variable from this function introduced in r130637, 
likely a result of copy/paste.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130640 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-01 06:14:10 +00:00
Rafael Espindola
5426a9ee37 GCC uses a different encoding of pointers in the FDE when using 
-fno-dwarf2-cfi-asm. Implement the same behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130637 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-01 04:49:54 +00:00
Rafael Espindola
c35280647b I forgot these files in the previous commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130635 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-01 04:19:24 +00:00
Rafael Espindola
debd7e4e8b Simplify the handling of pcrel relocations on ELF. Now we do the right thing 
for all symbol differences and can drop the old EmitPCRelSymbolValue
method.

This also make getExprForFDESymbol on ELF equal to the one on MachO, and it
can be made non-virtual.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130634 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-01 03:50:49 +00:00
Rafael Espindola
2b3e12d0cb Revert the previous patch while I figure out how to make llvm-gcc 
less agressive about disabling cfi on linux :-(

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130626 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-30 23:03:44 +00:00
Jakob Stoklund Olesen
60045c233a X86AsmPrinter doesn't know how to handle the X86II::MO_GOT_ABSOLUTE_ADDRESS flag 
after folding ADD32ri to ADD32mi, so don't do that.

This only happens when the greedy register allocator gets itself in trouble and
spills %vreg9 here:

16L             %vreg9<def> = MOVPC32r 0, %ESP<imp-use>; GR32:%vreg9
48L             %vreg9<def> = ADD32ri %vreg9, <es:_GLOBAL_OFFSET_TABLE_>[TF=1], %EFLAGS<imp-def,dead>; GR32:%vreg9

That should never happen, the live range should be split instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130625 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-30 23:00:05 +00:00
Rafael Espindola
89fc9e8f5e Enable CFI on OS X. 
Currently the output should be almost identical to the one produced by CodeGen
to make the transition easier.

The only two differences I know of are:

* Some files get an extra advance loc of size 0. This will be fixed when
relaxations are enabled.
* The optimization of declaring an EH symbol as an external variable is not
implemented. This is a subset of adding the nounwind attribute, so we if really
this at -O0 we should probably do it at the IL level.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130623 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-30 22:29:54 +00:00
Rafael Espindola
f1a5c7ec04 Add all the plumbing needed for MC to expand cfi to the old tables in 
the final assembly. It is the same technique used when targeting
assemblers that don't support .loc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130587 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-30 03:44:37 +00:00
Eric Christopher
5ac179ccd2 80-col. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130558 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 23:12:01 +00:00
Eli Friedman
b451770b26 Zap a couple now-unused functions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130557 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 22:56:48 +00:00
Eli Friedman
c573e2c7ea Switch to ImmLeaf (which can be used by FastISel) for a few more common ARM/Thumb2 patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130552 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 22:48:03 +00:00
Eric Christopher
d94bc549fc Add FastEmitInst_ii for the arm fast isel generator. It doesn't use it, but 
if it ever did it needs the def machinery.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130549 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 22:07:50 +00:00
Eric Christopher
632ae892e6 Some cleanup and optimize fallthrough more. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130546 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 21:56:31 +00:00
Eli Friedman
9ebf57ae13 Re-committing r130454, which does not in fact break anything. 
Fix a rather obscure crash caused by ARM fast-isel generating code which redefines a register.
rdar://problem/9338332 .



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130539 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 21:22:56 +00:00
Eric Christopher
bcf26aee86 Add trunc->branch support, this won't help with clang's i8->i1 truncations 
for bools, but is a start.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130534 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 20:02:39 +00:00
Daniel Dunbar
0eab5c4d85 MCExpr: Add FindAssociatedSection, which attempts to mirror the 'as' semantics 
that associate sections with expressions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130517 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 18:00:03 +00:00
Andrew Trick
d49ffe8284 Teach Thumb2 isel to fold and->rotr ==> ROR. 
Generalization of Nate Begeman's patch!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130502 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 14:18:15 +00:00
Benjamin Kramer
ce3a022b8c This is done. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130499 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 14:09:57 +00:00
Chris Lattner
bb0fff0cb4 clean up after Sean's r127646 patch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130475 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 05:40:18 +00:00
Chris Lattner
d7d030a447 use the MachineInstrBuilder operator-> to simplify some code. 
There are probably more instances of this floating around.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130474 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 05:24:29 +00:00
Eric Christopher
6344a5f146 Update comments and checks to match reality. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130464 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 00:07:20 +00:00
Eric Christopher
299bbb23a4 Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130463 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 00:03:10 +00:00
Eli Friedman
6e6014cfb3 Revert r130454; apparently this doesn't actually work. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130462 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-28 23:55:14 +00:00
Eli Friedman
2f7fcd7198 Fix a rather obscure crash caused by ARM fast-isel generating code which redefines a register. 
rdar://problem/9338332 .



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130454 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-28 23:03:25 +00:00
Daniel Dunbar
f86500bc4f Target/X86/MC: Add an option for disabling arith relaxation, for my own testing 
purposes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130438 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-28 21:23:31 +00:00
Eli Friedman
d227eedf82 fast-isel sret calls, try 2. We actually do need to do something on x86-32. rdar://problem/9303592 . 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130429 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-28 20:19:12 +00:00
Eli Friedman
6cf31b0a1a Revert r130348; causing buildbot issues on x86-32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130412 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-28 18:06:10 +00:00
Eric Christopher
7a20a37bac Be more layout aware here and swap the successor and branch condition 
if it means we get a fallthrough.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130404 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-28 16:52:09 +00:00
Rafael Espindola
bfa27cc5d7 Add a getExprForPersonalitySymbol method to MCAsmInfo. Use it when 
converting the symbol passed to .cfi_personality into bytes is the file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130400 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-28 16:09:09 +00:00
Eric Christopher
8f232d307a Let the immediate leaf pattern take transforms and switch the signed 
immediate patterns in arm to using the pattern.

Handles rdar://9299434


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130386 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-28 05:49:04 +00:00
Chris Lattner
4c19b17a17 move PR9803 to this readme. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130385 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-28 05:33:16 +00:00
Devang Patel
c26f5447e3 Teach dwarf writer to handle complex address expression for .debug_loc entries. 
This fixes clang generated blocks' variables' debug info.
Radar 9279956.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130373 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-28 02:22:40 +00:00
Justin Holewinski
2d525c5532 PTX: support for select_cc and fixes for setcc 
- expansion of SELECT_CC into SETCC
- force SETCC result type to i1
- custom selection for handling i1 using SETCC

Patch by Dan Bailey

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130358 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-28 00:19:56 +00:00
Justin Holewinski
9c86533347 PTX: support for select 
- selection of SELP instruction
- new selp.ll test

Patch by Dan Bailey

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130357 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-28 00:19:55 +00:00
Justin Holewinski
ef342fc751 PTX: mov fix and rounding correction for cvt 
- fix typo in MOV
- correct fp rounding on CVT
- new cvt.ll test

Patch by Dan Bailey

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130356 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-28 00:19:54 +00:00
Justin Holewinski
8ff9cd203f PTX: support for fneg 
- selection of FNEG instruction
- new fneg.ll test

Patch by Dan Bailey

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130355 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-28 00:19:53 +00:00
Justin Holewinski
4fea05acfa PTX: support for zext loads and trunc stores 
- expansion of EXTLOAD and TRUNCSTORE instructions

Patch by Dan Bailey

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130354 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-28 00:19:52 +00:00
Justin Holewinski
5a3cb924c6 PTX: support for bitwise operations on predicates 
- selection of bitwise preds (AND, OR, XOR)
- new bitwise.ll test

Patch by Dan Bailey

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130353 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-28 00:19:51 +00:00
Justin Holewinski
9583a86ba8 PTX: patch to AsmPrinter 
- immediate value cast as long not int
- handles initializer for constant array

Patch by Dan Bailey

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130352 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-28 00:19:50 +00:00
Eli Friedman
8211a6a61d fast-isel sret. We actually don't need to do anything special on x86. :) rdar://problem/9303592 . 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130348 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-27 23:58:52 +00:00
Rafael Espindola
60246a9622 Remove unnecessary argument. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130343 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-27 23:17:57 +00:00
Rafael Espindola
7afec9cc0f Rename getPersonalityPICSymbol to getCFIPersonalitySymbol, document it, and 
give it a bit more responsibility. Also implement it for MachO.

If hacked to use cfi, 32 bit MachO will produce

.cfi_personality 155, L___gxx_personality_v0$non_lazy_ptr

and 64 bit will produce

.cfi_presonality ___gxx_personality_v0

The general idea is that .cfi_personality gets passed the final symbol. It is
up to codegen to produce it if using indirect representation (like 32 bit
MachO), but it is up to MC to decide which relocations to create.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130341 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-27 23:08:15 +00:00
Eli Friedman
2790ba8e5a Make the fast-isel code for literal 0.0 a bit shorter/faster, since 0.0 is common. rdar://problem/9303592 . 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130338 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-27 22:41:55 +00:00
Kevin Enderby
e23aea28f9 Fix a bug in the case that there is no add or subtract symbol and the offset 
value is zero so it does not add a NULL expr operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130330 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-27 21:02:27 +00:00
Devang Patel
0be77dff11 Revert r130178. It turned out to be not the optimal path to emit complex location expressions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130326 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-27 20:29:27 +00:00
Eli Friedman
d5089a9794 Refactor out code to fast-isel a memcpy operation with a small constant 
length.  (I'm planning to use this to implement byval.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130274 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-27 01:45:07 +00:00
Eli Friedman
547eb4fd56 Fix an edge case involving branches in fast-isel on x86. 
rdar://problem/9303306 .



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130272 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-27 01:34:27 +00:00
Chris Lattner
325eeb1cd7 Transform: "icmp eq (trunc (lshr(X, cst1)), cst" to "icmp (and X, mask), cst" 
when X has multiple uses.  This is useful for exposing secondary optimizations,
but the X86 backend isn't ready for this when X has a single use.  For example,
this can disable load folding.

This is inching towards resolving PR6627.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130238 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-26 20:18:20 +00:00
Jim Grosbach
f7da8821b4 ARM and Thumb2 support for atomic MIN/MAX/UMIN/UMAX loads. 
rdar://9326019


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130234 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-26 19:44:18 +00:00
Jakob Stoklund Olesen
c9e5015dec Add a TRI::getLargestLegalSuperClass hook to provide an upper limit on register class inflation. 
The hook will be used by the register allocator when recomputing register
classes after removing constraints.

Thumb1 code doesn't allow anything larger than tGPR, and x86 needs to ensure
that the spill size doesn't change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130228 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-26 18:52:33 +00:00
Rafael Espindola
b28d4f152e Print all the moves at a given label instead of just the first one. 
Remove previous DwarfCFI hack.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130187 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-26 03:58:56 +00:00
Devang Patel
0c99861836 Let dwarf writer allocate extra space in the debug location expression. This space, if requested, will be used for complex addresses of the Blocks' variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130178 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-26 00:12:46 +00:00
Chris Lattner
ed0318eab8 add a missed bitfield instcombine. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130137 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-25 18:44:26 +00:00
Akira Hatanaka
f48eb533d5 Lower BlockAddress node when relocation-model is static. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130131 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-25 17:10:45 +00:00
Chandler Carruth
a4a2a03c31 Remove some hard coded CR-LFs. Some of these were the entire files, one of 
these was just one line of a file. Explicitly set the eol-style property on the
files to try and ensure this fix stays.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130125 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-25 07:11:23 +00:00
Duncan Sands
d03bcc1364 Fix comment typo. Noticed by Liu. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130120 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-25 06:21:43 +00:00
Sebastian Redl
dac4b9267b Fix Target/ARM/Thumb1FrameLowering.h header guard. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130097 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-24 15:47:01 +00:00
Jay Foad
ddcdcc8863 Remove unused STL header includes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130068 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-23 19:53:52 +00:00
Benjamin Kramer
20115617d4 Silence an overzealous uninitialized variable warning from GCC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130053 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-23 08:21:06 +00:00
Andrew Trick
1c3af779fc Thumb2 and ARM add/subtract with carry fixes. 
Fixes Thumb2 ADCS and SBCS lowering: <rdar://problem/9275821>.
t2ADCS/t2SBCS are now pseudo instructions, consistent with ARM, so the
assembly printer correctly prints the 's' suffix.

Fixes Thumb2 adde -> SBC matching to check for live/dead carry flags.

Fixes the internal ARM machine opcode mnemonic for ADCS/SBCS.
Fixes ARM SBC lowering to check for live carry (potential bug).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130048 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-23 03:55:32 +00:00
Andrew Trick
5adfba283d whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130046 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-23 03:24:11 +00:00
Johnny Chen
597fa65373 Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should 
print out ldr, not ldr.n.

rdar://problem/9267772


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130008 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-22 19:12:43 +00:00
Benjamin Kramer
e7cf062537 DAGCombine: fold "(zext x) == C" into "x == (trunc C)" if the trunc is lossless. 
On x86 this allows to fold a load into the cmp, greatly reducing register pressure.
  movzbl	(%rdi), %eax
  cmpl	$47, %eax
->
  cmpb	$47, (%rdi)

This shaves 8k off gcc.o on i386. I'll leave applying the patch in README.txt to Chris :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130005 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-22 18:47:44 +00:00
Devang Patel
0a6ea83f39 Add asserts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129995 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-22 16:44:29 +00:00
Benjamin Kramer
b20a8fc8a6 X86: Try to use a smaller encoding by transforming (X << C1) & C2 into (X & (C2 >> C1)) & C1. (Part of PR5039) 
This tends to happen a lot with bitfield code generated by clang. A simple example for x86_64 is
uint64_t foo(uint64_t x) { return (x&1) << 42; }
which used to compile into bloated code:
	shlq	$42, %rdi               ## encoding: [0x48,0xc1,0xe7,0x2a]
	movabsq	$4398046511104, %rax    ## encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00]
	andq	%rdi, %rax              ## encoding: [0x48,0x21,0xf8]
	ret                             ## encoding: [0xc3]

with this patch we can fold the immediate into the and:
	andq	$1, %rdi                ## encoding: [0x48,0x83,0xe7,0x01]
	movq	%rdi, %rax              ## encoding: [0x48,0x89,0xf8]
	shlq	$42, %rax               ## encoding: [0x48,0xc1,0xe0,0x2a]
	ret                             ## encoding: [0xc3]

It's possible to save another byte by using 'andl' instead of 'andq' but I currently see no way of doing
that without making this code even more complicated. See the TODOs in the code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129990 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-22 15:30:40 +00:00
Evan Cheng
db6cbe1ff1 In Thumb2 mode, lower frame indix references to: 
add <rd>, sp, #<imm8>
ldr <rd>, [sp, #<imm8>]
When the offset from sp is multiple of 4 and in range of 0-1020.
This saves code size by utilizing 16-bit instructions.

rdar://9321541


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129971 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-22 01:42:52 +00:00
Rafael Espindola
abf9af60ad Compute the size of the FDE encoding instead of hard coding it. Update 
X8664_ELFTargetObjectFile::getFDEEncoding to match reality.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129959 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-22 00:08:43 +00:00
Rafael Espindola
e8cfbd843d Remove unused argument. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129955 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-21 23:39:26 +00:00
Devang Patel
71f3f1146f Fix DWARF description of Q registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129952 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-21 23:22:35 +00:00
Devang Patel
27f5acb7d4 Fix DWARF description of S registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129947 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-21 22:48:26 +00:00
Devang Patel
64d3d12f37 As per ARM docs, register Dx is described as DW_OP_regx(256+x) in DWARF. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129922 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-21 17:51:06 +00:00
Justin Holewinski
326fb9d1fb PTX: Expand useable register space 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129913 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-21 16:08:02 +00:00
Che-Liang Chiou
5efde18dd2 ptx: fix parameter ordering 
This patch depends on the prior fix r129908 that changes to use std::find,
rather than std::binary_search, on unordered array.

Patch by Dan Bailey


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129909 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-21 10:56:58 +00:00
Che-Liang Chiou
4a17cad900 ptx: PTXMachineFunctionInfo no longer sort registers and so should not use std::binary_search 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129908 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-21 10:16:20 +00:00
Evan Cheng
c8578948c9 Remove -use-divmod-libcall. Let targets opt in when they are available. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129884 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-20 22:20:12 +00:00
Eli Friedman
e5ff344fc0 Revert r129846; it's breaking a buildbot. See 
http://google1.osuosl.org:8011/builders/llvm-x86_64-linux-checks/builds/825/steps/test.llvm.stage2/logs/st.ll



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129869 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-20 19:00:08 +00:00
Jakob Stoklund Olesen
6bfba2e5af Prefer cheap registers for busy live ranges. 
On the x86-64 and thumb2 targets, some registers are more expensive to encode
than others in the same register class.

Add a CostPerUse field to the TableGen register description, and make it
available from TRI->getCostPerUse. This represents the cost of a REX prefix or a
32-bit instruction encoding required by choosing a high register.

Teach the greedy register allocator to prefer cheap registers for busy live
ranges (as indicated by spill weight).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129864 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-20 18:19:48 +00:00
Stuart Hastings
e341e8ce1a Excise unintended hunk in 129858. <rdar://problem/7662569> 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129862 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-20 18:09:26 +00:00
Stuart Hastings
c73158730d ARM byval support. Will be enabled by another patch to the FE. <rdar://problem/7662569> 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129858 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-20 16:47:52 +00:00
Justin Holewinski
e1fee48cd0 PTX: Add intrinsics to list of built-in intrinsics, which allows them to be 
used by Clang.  To help Clang integration, the PTX target has been split
     into two targets: ptx32 and ptx64, depending on the desired pointer size.

- Add GCCBuiltin class to all intrinsics
- Split PTX target into ptx32 and ptx64

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129851 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-20 15:37:17 +00:00
Che-Liang Chiou
b32204cd16 ptx: add integer div and rem instruction 
Patched by Dan Bailey


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129848 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-20 09:28:55 +00:00