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6618 Commits

Author SHA1 Message Date
Chris Lattner
2544f42692 add support for instruction prefixes on the same line as the instruction, 
implementing rdar://8033482 and PR7254.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113348 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-08 05:17:37 +00:00
Chris Lattner
34e53140c2 change the MC "ParseInstruction" interface to make it the 
implementation's job to check for and lex the EndOfStatement
marker.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113347 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-08 05:10:46 +00:00
Chris Lattner
9607c40601 gas accepts xchg <mem>, <reg> as a synonym for xchg <reg>, <mem>. 
Add this to the mc assembler, fixing PR8061


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113346 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-08 04:53:27 +00:00
Chris Lattner
a247685b30 fix the encoding of the "jump on *cx" family of instructions, 
rdar://8061602


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113343 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-08 04:30:51 +00:00
Bruno Cardoso Lopes
90462b4ae1 Factor out some x86 vector shuffle rewriting and add comments about the direction the shuffle lowering is heading to 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113286 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-07 21:03:14 +00:00
Bruno Cardoso Lopes
0d1340b181 Move code around to prepare for moving some of the logic together to another function 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113267 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-07 20:20:27 +00:00
Bill Wendling
d8dd5757e0 Add an MVT::x86mmx type. It will take the place of all current MMX vector types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113261 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-07 20:03:56 +00:00
Evan Cheng
dc0b06c815 Remove a dead comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113259 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-07 20:01:10 +00:00
Bruno Cardoso Lopes
58277b17c3 decouple MMX check from regular splat checks. Some refactoring is coming, and MMX should be left alone to be easily removed after moving to intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113247 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-07 18:41:45 +00:00
Bruno Cardoso Lopes
673bf78bb5 Remove now useless check, because the code can be matched below, no need to leave it for isel 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113242 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-07 18:29:03 +00:00
Bruno Cardoso Lopes
67fc1e76d4 Minor change. Since the checks are equivalent, use isMMX 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113239 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-07 18:24:00 +00:00
Dale Johannesen
86097c384f Add patterns for MMX that use the new intrinsics. 
Enable palignr intrinsic.
These may need adjustment for a new VT in due course.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113233 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-07 18:10:56 +00:00
Bruno Cardoso Lopes
70e81f1517 Remove unused target specific node 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113224 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-07 17:38:55 +00:00
Benjamin Kramer
aceeb3a4e2 Don't leak the old operand when transforming "sldt" into "sldtw". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113200 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-07 14:40:58 +00:00
Chris Lattner
e9e0fc5eed add missing cmov aliases, this resolves rdar://8208499 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113189 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-07 00:05:45 +00:00
Chris Lattner
7d284de955 remove duplicated entry 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113188 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-06 23:57:24 +00:00
Chris Lattner
c5cebeb3cb "sldt <mem>" is ambiguous in 64-bit mode, but should 
always be disambiguated as sldtw.  sldtw and sldtq with
a mem operands have the same effect, but sldtw is more
compact.  Force it to sldtw, resolving rdar://8017530


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113186 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-06 23:51:44 +00:00
Chris Lattner
d68c474ec5 fix rdar://8017621 - llvm-mc can't guess encoding for "push $(1000)" 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113184 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-06 23:40:56 +00:00
Chris Lattner
9389b60a03 fix the operand constraints of the immediate form of in/out, 
allowing unsigned 8-bit operands.  This fixes rdar://8208481



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113182 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-06 23:29:05 +00:00
Chris Lattner
ce4a3355d9 in the case where an instruction only has one implementation 
of a mneumonic, report operand errors with better location
info.  For example, we now report:

t.s:6:14: error: invalid operand for instruction
        cwtl $1
             ^

but we fail for common cases like:

t.s:11:4: error: invalid operand for instruction
   addl $1, $1
   ^

because we don't know if this is supposed to be the reg/imm or imm/reg
form.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113178 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-06 22:11:18 +00:00
Chris Lattner
a008e8ac73 Now that we know if we had a total fail on the instruction mnemonic, 
give a more detailed error.  Before:

t.s:11:4: error: unrecognized instruction
   addl $1, $1
   ^
t.s:12:4: error: unrecognized instruction
   f2efqefa $1
   ^

After:

t.s:11:4: error: invalid operand for instruction
   addl $1, $1
   ^
t.s:12:4: error: invalid instruction mnemonic 'f2efqefa'
   f2efqefa $1
   ^

This fixes rdar://8017912 - llvm-mc says "unrecognized instruction" when it means "invalid operands"


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113176 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-06 21:54:15 +00:00
Chris Lattner
69c7249a6f simplify the hacks around jrcxz. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113167 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-06 20:10:12 +00:00
Chris Lattner
ec6789f4f9 have tblgen detect when an instruction would have matched, but 
failed because a subtarget feature was not enabled.  Use this to
remove a bunch of hacks from the X86AsmParser for rejecting things
like popfl in 64-bit mode.  Previously these hacks weren't needed,
but were important to get a message better than "invalid instruction"
when used in the wrong mode.

This also fixes bugs where pushal would not be rejected correctly in
32-bit mode (just pusha).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113166 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-06 20:08:02 +00:00
Chris Lattner
79ed3f77e8 change MatchInstructionImpl to return an enum instead of bool. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113165 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-06 19:22:17 +00:00
Chris Lattner
0692ee676f have AsmMatcherEmitter.cpp produce the hunk of code that gets included 
into the middle of the class, and rework how the different sections of
the generated file are conditionally included for simplicity.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113163 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-06 19:11:01 +00:00
Roman Divacky
436c54a186 Redefine LOOP* instructions from I to Ii8PCRel as they take an i8 argument. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113158 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-06 18:43:14 +00:00
Chris Lattner
47ab90bfa8 random cleanups 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113157 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-06 18:32:06 +00:00
Chris Lattner
f0f5780b39 update this. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113116 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-05 20:22:09 +00:00
Chris Lattner
beac75da37 implement rdar://6653118 - fastisel should fold loads where possible. 
Since mem2reg isn't run at -O0, we get a ton of reloads from the stack,
for example, before, this code:

int foo(int x, int y, int z) {
  return x+y+z;
}

used to compile into:

_foo:                                   ## @foo
	subq	$12, %rsp
	movl	%edi, 8(%rsp)
	movl	%esi, 4(%rsp)
	movl	%edx, (%rsp)
	movl	8(%rsp), %edx
	movl	4(%rsp), %esi
	addl	%edx, %esi
	movl	(%rsp), %edx
	addl	%esi, %edx
	movl	%edx, %eax
	addq	$12, %rsp
	ret

Now we produce:

_foo:                                   ## @foo
	subq	$12, %rsp
	movl	%edi, 8(%rsp)
	movl	%esi, 4(%rsp)
	movl	%edx, (%rsp)
	movl	8(%rsp), %edx
	addl	4(%rsp), %edx    ## Folded load
	addl	(%rsp), %edx     ## Folded load
	movl	%edx, %eax
	addq	$12, %rsp
	ret

Fewer instructions and less register use = faster compiles.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113102 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-05 02:18:34 +00:00
Chris Lattner
17aa68055b zap dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113073 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-04 18:12:00 +00:00
Bruno Cardoso Lopes
2eb63dfa0a Remove the last bit of isShuffleMaskLegal checks and improve the comment regarding mmx shuffles 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113059 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-04 02:58:56 +00:00
Bruno Cardoso Lopes
828f6ae03c make explicit that we not handle several mmx shuffles 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113058 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-04 02:50:13 +00:00
Bruno Cardoso Lopes
aace0f295b Emit target specific nodes to handle palignr. Do not touch it for MMX versions yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113056 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-04 02:36:07 +00:00
Bruno Cardoso Lopes
c800c0d25f Emit target specific nodes to handle splats starting at zero indicies 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113055 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-04 02:02:14 +00:00
Bruno Cardoso Lopes
bbfc31012b Emit target specific nodes for isPSHUFHWMask and isPSHUFLWMask 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113050 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-04 01:36:45 +00:00
Bruno Cardoso Lopes
4c827f5ae1 Emit target specific nodes for isSHUFPMask 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113048 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-04 01:22:57 +00:00
Bruno Cardoso Lopes
d344f28b9d Previous isMOVLMask matching already emits targets nodes, remove check 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113047 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-04 00:50:08 +00:00
Bruno Cardoso Lopes
e09abcd3c4 One more check from the original isShuffleMaskLegal goes away 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113045 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-04 00:46:16 +00:00
Bruno Cardoso Lopes
b733996110 Remove a duplicated but useless check that i've inserted in the previous commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113044 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-04 00:43:12 +00:00
Bruno Cardoso Lopes
a22c84571a Refactor some code and remove the extra checks for unpckl_undef and unpckh_undef 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113043 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-04 00:39:43 +00:00
Bruno Cardoso Lopes
43c05744b5 Remove check for unpckh mask 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113035 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 23:32:47 +00:00
Bruno Cardoso Lopes
ef3adb3243 Remove check for unpckl mask 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113034 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 23:31:50 +00:00
Bruno Cardoso Lopes
7256e22f77 Inline isShuffleMaskLegal into LowerVECTOR_SHUFFLE, so we can start 
checking each standalone condition and decide whether emit target
specific nodes or remove the condition if it's already matched before.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113031 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 23:24:06 +00:00
Bruno Cardoso Lopes
e8f279cbd4 Reapply considered harmfull part of rr112934 and r112942. 
"Use target specific nodes instead of relying in unpckl and
unpckh pattern fragments during isel time. Also place a
depth limit in getShuffleScalarElt.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113020 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 22:09:41 +00:00
Dale Johannesen
caa9ba228d Remove the rest of the nonexistent 64-bit AVX instructions. 
Bruno, please review.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113014 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 21:23:00 +00:00
Bruno Cardoso Lopes
190d0a54c1 Reapply last harmless part of r112934, the pattern fragment to match X86Unpcklpd 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113009 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 20:44:26 +00:00
Bruno Cardoso Lopes
2a4460606e Reintroduce a simple function refactoring done in r112934, also without any functionality changes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113008 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 20:20:02 +00:00
Bruno Cardoso Lopes
be8b084d8a Reapply piecies of r112942 and r112934 which don't do 
functional changes


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113007 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 20:10:35 +00:00
Bruno Cardoso Lopes
b3e0669b8e Reapply Fix comment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113006 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 19:55:05 +00:00
Daniel Dunbar
3139422058 Revert r112934, "- Use specific nodes to match unpckl masks.", which introduced 
some infinite loop and select failures.
 - Apologies for eager reverting, but its branch day.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113000 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 19:38:11 +00:00
Daniel Dunbar
78541f258c Revert r112938 "Fix comment", which depends on r112934, which introduced some 
infinite loop and select failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112999 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 19:38:08 +00:00
Daniel Dunbar
a87ccce95b Revert r112942, "Use punpckh and unpckh family of nodes instead of using unpckh 
mask pattern fragment", which depends on r112934, which introduced some infinite
loop and select failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112998 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 19:38:05 +00:00
Bruno Cardoso Lopes
95f1e2d6b5 AVX doesn't support mm operations neither its instrinsics. 
The AVX versions of PALIGN and PABS* should only exist for
128-bit. Remove the unnecessary stuff.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112944 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 02:08:45 +00:00
Bruno Cardoso Lopes
4b0c9f3e73 Use punpckh and unpckh family of nodes instead of using unpckh mask pattern fragment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112942 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 01:39:08 +00:00
Bruno Cardoso Lopes
01f0847ce8 Fix comment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112938 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 01:28:51 +00:00
Bruno Cardoso Lopes
5e5342b0a8 - Use specific nodes to match unpckl masks. 
- Teach getShuffleScalarElt how to handle more target
specific nodes, so the DAGCombine can make use of it.
- Add another hack to avoid the node update problem
during legalization. More description on the comments



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112934 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 01:24:00 +00:00
Jakob Stoklund Olesen
3061c4442e Don't call Predicate_* from X86 target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112921 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 00:35:18 +00:00
Anton Korobeynikov
ace53f2fbc Properly emit __chkstk call instead of __alloca on non-mingw windows targets. 
Patch by Cameron Esfahani!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112902 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 23:03:46 +00:00
Bruno Cardoso Lopes
ed5c711a6e Move insertps mask decoding to header file 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112896 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 22:43:39 +00:00
Anton Korobeynikov
c7c62bb3ca Revert win64 changes. They seem to be incomplete 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112885 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 22:31:32 +00:00
Anton Korobeynikov
2f4fad99ea Properly allocate win64 shadow reg area. 
Patch by Jan Sjodin!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112875 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 22:16:28 +00:00
Bruno Cardoso Lopes
5594560766 Move decoding of insertps back to avoid unused warnings in x86 isel lowering, and fix movlhps/movhlps to decode 4 elements shuffles 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112869 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 21:51:11 +00:00
Dan Gohman
24bde5bce1 Don't narrow the load and store in a load+twiddle+store sequence unless 
there are clearly no stores between the load and the store. This fixes
this miscompile reported as PR7833.

This breaks the test/CodeGen/X86/narrow_op-2.ll optimization, which is
safe, but awkward to prove safe. Move it to X86's README.txt.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112861 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 21:18:42 +00:00
Bruno Cardoso Lopes
6b1d0a3b36 Move x86 specific shuffle mask decoding to its own header, it's also going to be used elsewhere. Also trim trailing whitespaces 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112846 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 18:40:13 +00:00
Bruno Cardoso Lopes
3722f007b6 Replace unpckl_undef and unpckh_undef matching with target specific opcodes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112806 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 05:23:12 +00:00
Bruno Cardoso Lopes
dd69db858c Move condition out to prepare for more matching 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112805 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 04:20:26 +00:00
Bruno Cardoso Lopes
ad10fb2b56 Remove checking for isUNPCKL_v_undef_Mask, the specific node is already emitted for it 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112804 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 03:57:58 +00:00
Bruno Cardoso Lopes
d00bfe1f8d become more strict about when it's safe to use X86ISD::MOVLPS 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112799 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 02:35:51 +00:00
Bruno Cardoso Lopes
4783a3ee13 Revert r112689, avoid those kind of checks cause they mess up with mmx 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112760 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-01 22:59:03 +00:00
Bruno Cardoso Lopes
29c353b9c3 Using target specific nodes for shuffle nodes makes the mask 
check more strict, breaking some cases not checked in the
testsuite, but also exposes some foldings not done before,
as this example:

  movaps  (%rdi), %xmm0
  movaps  (%rax), %xmm1
  movaps  %xmm0, %xmm2
  movss %xmm1, %xmm2
  shufps  $36, %xmm2, %xmm0

now is generated as:

  movaps  (%rdi), %xmm0
  movaps  %xmm0, %xmm1
  movlps  (%rax), %xmm1
  shufps  $36, %xmm1, %xmm0



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112753 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-01 22:33:20 +00:00
Bruno Cardoso Lopes
56098f5d26 Use movlps, movlpd, movss and movsd specific nodes instead of pattern matching with movlp pattern fragment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112694 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-01 05:08:25 +00:00
Bruno Cardoso Lopes
9cfad89a68 minor change, simplify some logic 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112689 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-01 00:57:08 +00:00
Bruno Cardoso Lopes
e654b56eb1 Move some functions around so they can be used for some other to come function 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112687 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-01 00:51:36 +00:00
Bruno Cardoso Lopes
013bb3dee9 Use x86 specific MOVSLDUP node, add more patterns to match it and remove useless load nodes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112661 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-31 22:35:05 +00:00
Bruno Cardoso Lopes
5023ef281c Use x86 specific MOVSHDUP node and add more patterns to match it 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112657 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-31 22:22:11 +00:00
Jakob Stoklund Olesen
63b1dbaadd Make %EFLAGS unallocatable. 
No CCR virtual registers should exist, and %EFLAGS is used in ways that can
surprise RegAllocFast.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112650 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-31 21:51:07 +00:00
Bruno Cardoso Lopes
7ff30bb1a5 Use MOVHLPS node instead of matching using movhlps and movhlps_undef pattern fragments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112644 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-31 21:38:49 +00:00
Bruno Cardoso Lopes
f2db5b48d0 Use MOVLHPS and MOVHLPS x86 nodes whenever possible. Also remove some useless nodes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112642 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-31 21:15:21 +00:00
Bruno Cardoso Lopes
20a07f422d Use X86ISD::MOVSS and MOVSD to represent the movl mask pattern, also fix the handling of those nodes when seeking for scalars inside vector shuffles 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112570 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-31 02:26:40 +00:00
Eli Friedman
5033f64694 A couple of small missed optimizations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112411 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-29 05:07:40 +00:00
Chris Lattner
4644a936dc add a bunch more common shuffles to the instprinter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112397 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-29 03:08:08 +00:00
Chris Lattner
6aa928d57a I have manually decoded the imm field of an insertps one too many 
times.  This patch causes llc and llvm-mc (which both default to
verbose-asm) to print out comments after a few common shuffle 
instructions which indicates the shuffle mask, e.g.:

	insertps	$113, %xmm3, %xmm0     ## xmm0 = zero,xmm0[1,2],xmm3[1]
	unpcklps	%xmm1, %xmm0    ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
	pshufd	$1, %xmm1, %xmm1        ## xmm1 = xmm1[1,0,0,0]

This is carefully factored to keep the information extraction (of the
shuffle mask) separate from the printing logic.  I plan to move the
extraction part out somewhere else at some point for other parts of
the x86 backend that want to introspect on the behavior of shuffles.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112387 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-28 20:42:31 +00:00
Chris Lattner
24faf611a3 fix the buildvector->insertp[sd] logic to not always create a redundant 
insertp[sd] $0, which is a noop.  Before:

_f32:                                   ## @f32
	pshufd	$1, %xmm1, %xmm2
	pshufd	$1, %xmm0, %xmm3
	addss	%xmm2, %xmm3
	addss	%xmm1, %xmm0
                                        ## kill: XMM0<def> XMM0<kill> XMM0<def>
	insertps	$0, %xmm0, %xmm0
	insertps	$16, %xmm3, %xmm0
	ret

after:

_f32:                                   ## @f32
	movdqa	%xmm0, %xmm2
	addss	%xmm1, %xmm2
	pshufd	$1, %xmm1, %xmm1
	pshufd	$1, %xmm0, %xmm3
	addss	%xmm1, %xmm3
	movdqa	%xmm2, %xmm0
	insertps	$16, %xmm3, %xmm0
	ret

The extra movs are due to a random (poor) scheduling decision.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112379 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-28 17:59:08 +00:00
Chris Lattner
3ddcc43040 fix the BuildVector -> unpcklps logic to not do pointless shuffles 
when the top elements of a vector are undefined.  This happens all
the time for X86-64 ABI stuff because only the low 2 elements of
a 4 element vector are defined.  For example, on:

_Complex float f32(_Complex float A, _Complex float B) {
  return A+B;
}

We used to produce (with SSE2, SSE4.1+ uses insertps):

_f32:                                   ## @f32
	movdqa	%xmm0, %xmm2
	addss	%xmm1, %xmm2
	pshufd	$16, %xmm2, %xmm2
	pshufd	$1, %xmm1, %xmm1
	pshufd	$1, %xmm0, %xmm0
	addss	%xmm1, %xmm0
	pshufd	$16, %xmm0, %xmm1
	movdqa	%xmm2, %xmm0
	unpcklps	%xmm1, %xmm0
	ret

We now produce:

_f32:                                   ## @f32
	movdqa	%xmm0, %xmm2
	addss	%xmm1, %xmm2
	pshufd	$1, %xmm1, %xmm1
	pshufd	$1, %xmm0, %xmm3
	addss	%xmm1, %xmm3
	movaps	%xmm2, %xmm0
	unpcklps	%xmm3, %xmm0
	ret

This implements rdar://8368414


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112378 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-28 17:28:30 +00:00
Chris Lattner
6e80e44926 improve comments in the unpcklps generating logic, introduce 
a new EltStride variable instead of reusing NumElems variable
for a non-obvious purpose.  No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112377 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-28 17:15:43 +00:00
Bruno Cardoso Lopes
27f1279411 Clean up the logic of vector shuffles -> vector shifts. 
Also teach this logic how to handle target specific shuffles if
needed, this is necessary while searching recursively for zeroed
scalar elements in vector shuffle operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112348 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-28 02:46:39 +00:00
Anton Korobeynikov
c52bedba54 Properly handle passing of FP stuff to varargs function on Win64: 
value should be copied to the corresponding shadow reg as well.
Patch by Cameron Esfahani!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112262 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-27 14:43:06 +00:00
Daniel Dunbar
d8d36e61fd X86: Fix an encoding issue with LOCK_ADD64mr, which could lead to very hard to find miscompiles with the integrated assembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112250 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-27 01:30:14 +00:00
Jim Grosbach
fcb4a8ead3 Simplify eliminateFrameIndex() interface back down now that PEI doesn't need 
to try to re-use scavenged frame index reference registers. rdar://8277890

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112241 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-26 23:32:16 +00:00
Bruno Cardoso Lopes
af57738f00 zap the now unused MVT::getIntVectorWithNumElements 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112218 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-26 20:53:12 +00:00
Bob Wilson
3b7bbfd36c Fix comment typos. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112202 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-26 18:08:11 +00:00
Chris Lattner
8306968c14 implement SplitVecOp_CONCAT_VECTORS, fixing the included testcase with SSE1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112171 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-26 05:51:22 +00:00
Chris Lattner
97a2a56f43 fix sse1 only codegen in x86-64 mode, which is something we 
apparently try to support.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112168 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-26 05:24:29 +00:00
Bruno Cardoso Lopes
e943c15621 Fix PR7748 without using microsoft extensions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112128 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-26 01:02:53 +00:00
Chris Lattner
1a68958d3d we should pattern match the SSE complex arithmetic ops. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112109 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-25 23:31:42 +00:00
Bruno Cardoso Lopes
3e60a232c1 Revert this for now, PUNPCKLDQ dont operate on v4f32 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112090 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-25 21:26:37 +00:00
Daniel Dunbar
3d6e4c3111 X86: Fix misencode of RI64mi8. This fixes OpenSSL / x86_64-apple-darwin10 / clang -O3. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112089 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-25 21:11:02 +00:00
Benjamin Kramer
fc19695c9a Remove dead recursive function. Yay for clang -Wunused-function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112060 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-25 17:27:58 +00:00
Anton Korobeynikov
9f7f83b861 Fix nasty mingw32 bug, which e.g. prevented llvm-gcc bootstrap there. 
Mark _alloca call as clobberring EFLAGS, otherwise some DCE might remove
other flags-clobberring stuff (e.g. cmp instructions) occuring after
_alloca call.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112034 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-25 07:50:11 +00:00
Bruno Cardoso Lopes
f76c55aa40 PUNPCKLDQ should also be used for v4f32 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112020 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-25 02:55:40 +00:00
Bruno Cardoso Lopes
7338bbd32a teach lowering to get target specific nodes for pshufd, emulating the same isel behavior for now, so we can pass all vector shuffle tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112017 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-25 02:35:37 +00:00
Daniel Dunbar
fba88d49e3 MC/X86: Tweak imul recognition, previous hack only applies for the imul form 
taking immediates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111950 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 19:37:56 +00:00
Daniel Dunbar
ae528f65ba MC/X86: Add custom hack for recognizing "imul $12, %eax" and friends. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111947 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 19:24:18 +00:00
Daniel Dunbar
ee9102587e MC/X86: Warn on scale factors > 1 without index register, instead of erroring, 
for 'as' compatibility.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111945 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 19:13:38 +00:00
Dan Gohman
92b651fb19 Fix X86's isLegalAddressingMode to recognize that static addresses 
need not be RIP-relative in small mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111917 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 15:55:12 +00:00
Bruno Cardoso Lopes
8878e21fe6 Use pshufhw and pshuflw in more cases and fix getTargetShuffleNode number of arguments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111890 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 01:16:15 +00:00
Bruno Cardoso Lopes
3efc0778c9 Start using target speficic nodes for shuffles: pshufhw and pshuflw 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111837 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 20:41:02 +00:00
Gabor Greif
11bc1652c9 tyops 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111835 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 20:30:51 +00:00
Chris Lattner
d80c7e1232 Add a new llvm.x86.int intrinsic, allowing access to the 
x86 int and int3 instructions.  Patch by Peter Housel!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111831 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 19:39:25 +00:00
Chris Lattner
b7f243a638 random improvement for variable shift codegen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111813 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 17:30:29 +00:00
Anton Korobeynikov
4654a07e25 Revert invalid r111792. Jump tables are not broken on x86-64 / coff, 
it's COFF emitter which does not support differences of two symbols
(and needs to be fixed). GAS is pretty fine with code produced.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111801 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 07:38:51 +00:00
Michael J. Spencer
3464cec4d8 Workaround broken jump tables on x86-64 COFF. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111792 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 04:45:37 +00:00
Anton Korobeynikov
699647cabc Use rip-rel addressing on win64 by default. For this we just 
defaults to small pic code model.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111741 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-21 17:21:11 +00:00
Michael J. Spencer
da0bfcdaf9 MC: Add partial x86-64 support to COFF. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111728 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-21 05:58:13 +00:00
Dan Gohman
8bef744518 Fix x86 fast-isel's cmp+branch folding to avoid folding when the 
comparison is in a different basic block from the branch. In such
cases, the comparison's operands may not have initialized virtual
registers available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111709 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-21 02:32:36 +00:00
Bruno Cardoso Lopes
bf8154a439 Prepare LowerVECTOR_SHUFFLEv8i16 to use x86 target specific nodes directly 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111704 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-21 01:32:18 +00:00
Bruno Cardoso Lopes
3157ef1c13 This is the first step towards refactoring the x86 vector shuffle code. The 
general idea here is to have a group of x86 target specific nodes which are
going to be selected during lowering and then directly matched in isel.

The commit includes the addition of those specific nodes and a *bunch* of
patterns, and incrementally we're going to switch between them and what we
have right now. Both the patterns and target specific nodes can change as
we move forward with this work.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111691 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-20 22:55:05 +00:00
Chris Lattner
59f8a6a666 fix PR7465, mishandling of lcall and ljmp: intersegment long 
call and jumps.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111496 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-19 01:18:43 +00:00
Chris Lattner
efbdc8e236 minor progress towards fixing PR7465 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111494 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-19 01:00:34 +00:00
Bill Wendling
86b98b5874 Marked with ATTRIBUTE_USED so that clang doesn't complain. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111383 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-18 18:40:57 +00:00
Chris Lattner
0d857cf8d1 remove some code that is dead now that lea's are modeled with segment registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111343 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-18 02:40:44 +00:00
Anton Korobeynikov
5dad73cec8 Revert part of one of the prev. patches - tailjmp will follow later. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111291 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 21:08:28 +00:00
Anton Korobeynikov
3a1e54a6b9 More fixes for win64: 
- Do not clobber al during variadic calls, this is AMD64 ABI-only feature
  - Emit wincall64, where necessary
Patch by Cameron Esfahani!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111289 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 21:06:07 +00:00
Anton Korobeynikov
e9df15e65c Enable more win64 calls folding opportunities. 
Patch by Cameron Esfahani!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111288 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 21:06:01 +00:00
Eli Friedman
bc1fb2b6fa Comment out some broken/unused/useless instructions which mess up disassembly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111185 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-16 21:18:51 +00:00
Eli Friedman
321473d51d Don't attempt to SimplifyShortMoveForm in 64-bit mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111182 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-16 21:03:32 +00:00
Matt Fleming
453db50333 Hookup ELF support for X86. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111173 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-16 18:36:14 +00:00
Jakob Stoklund Olesen
de78f05cf7 Partially revert r111155. It looks like MSVC is calling an operator<() that 
clang says is unused.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111167 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-16 18:24:54 +00:00
Jakob Stoklund Olesen
a649ab542d Remove unused functions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111155 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-16 17:18:18 +00:00
Argyrios Kyrtzidis
8c8b9ee8c8 Revert r111082. No warnings for this common pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111102 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-15 10:27:23 +00:00
Eric Christopher
c0b2a2018a Rework how the non-sse2 memory barrier is lowered so that the 
encoding is correct for the built-in assembler.

Based on a patch from Chris.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111083 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-14 21:51:50 +00:00
Argyrios Kyrtzidis
7268d97ae6 Add ATTRIBUTE_UNUSED to methods that are not supposed to be used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111082 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-14 21:35:10 +00:00
Chris Lattner
132929aa9e improve indentation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111073 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-14 17:26:09 +00:00
Bruno Cardoso Lopes
30baa63474 Add comments to some pattern fragments in x86 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111041 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-13 20:39:01 +00:00
Dale Johannesen
1b4051095d Revert 110491. While not wrong, it was based on a 
misanalysis and is undesirable.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111028 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-13 18:43:45 +00:00
Bruno Cardoso Lopes
bb0a9489e0 Fix comment to reflect code, and remove an unused argument 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111022 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-13 17:50:47 +00:00
Bruno Cardoso Lopes
bbadd39bbb Improve comment to make explicit why not to touch this could before JIT goes MC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111021 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-13 17:44:10 +00:00
Eric Christopher
63f02ac349 Revert last patch and r110954 as I meant to. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111001 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-13 02:37:50 +00:00
Eric Christopher
4404c00db6 Revert r110954 for now, pseudo instructions can't make it through to the JIT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111000 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-13 02:30:00 +00:00
Bruno Cardoso Lopes
64baddc0f2 Some small clean-up: use of pseudo instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110954 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-12 20:55:18 +00:00
Bruno Cardoso Lopes
642eb02045 - Teach SSEDomainFix to switch between different levels of AVX instructions. Here we guess that AVX will have domain issues, so just implement them for consistency and in the future we remove if it's unnecessary. 
- Make foldMemoryOperandImpl aware of 256-bit zero vectors folding and support the 128-bit counterparts of AVX too.
- Make sure MOV[AU]PS instructions are only selected when SSE1 is enabled, and duplicate the patterns to match AVX.
- Add a testcase for a simple 128-bit zero vector creation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110946 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-12 20:20:53 +00:00
Bruno Cardoso Lopes
6da9cee0f1 Define AVX 128-bit pattern versions of SET0PS/PD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110937 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-12 18:20:59 +00:00
Bruno Cardoso Lopes
4d04362813 Fix comment order 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110898 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-12 02:08:52 +00:00
Bruno Cardoso Lopes
8c05a850f4 Begin to support some vector operations for AVX 256-bit intructions. The long 
term goal here is to be able to match enough of vector_shuffle and build_vector
so all avx intrinsics which aren't mapped to their own built-ins but to
shufflevector calls can be codegen'd. This is the first (baby) step, support
building zeroed vectors.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110897 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-12 02:06:36 +00:00
Daniel Dunbar
09062b1672 MC/X86/AsmParser: Give an explicit error message when we reject an instruction 
because it could have an ambiguous suffix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110890 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-12 00:55:42 +00:00
Daniel Dunbar
f1e29d4c21 MC/AsmParser: Push the burdon of emitting diagnostics about unmatched 
instructions onto the target specific parser, which can do a better job.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110889 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-12 00:55:38 +00:00
Daniel Dunbar
4f98f83459 tblgen/AsmMatcher: Always emit the match function as 'MatchInstructionImpl', 
target specific parsers can adapt the TargetAsmParser to this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110888 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-12 00:55:32 +00:00
Jakob Stoklund Olesen
d29583bd32 Fix <rdar://problem/8282498> even if it doesn't reproduce on trunk. 
When a register is defined by a partial load:

  %reg1234:sub_32 = MOV32mr <fi#-1>; GR64:%reg1234

That load cannot be folded into an instruction using the full 64-bit register.
It would become a 64-bit load.

This is related to the recent change to have isLoadFromStackSlot return false on
a sub-register load.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110874 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 23:08:22 +00:00
Dan Gohman
d881627d33 Use ISD::ADD instead of ISD::SUB with a negated constant. This 
avoids trouble if the return type of TD->getPointerSize() is
changed to something which doesn't promote to a signed type,
and is simpler anyway.

Also, use getCopyFromReg instead of getRegister to read a
physical register's value.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110835 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 18:14:00 +00:00
Daniel Dunbar
b3cb696794 MCAsmParser: Add dump() hook to MCParsedAsmOperand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110790 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:37:04 +00:00
Bruno Cardoso Lopes
045573ce21 Add AVX matching patterns to Packed Bit Test intrinsics. 
Apply the same approach of SSE4.1 ptest intrinsics but
create a new x86 node "testp" since AVX introduces
vtest{ps}{pd} instructions which set ZF and CF depending
on sign bit AND and ANDN of packed floating-point sources.

This is slightly different from what the "ptest" does.
Tests comming with the other 256 intrinsics tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110744 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 23:25:42 +00:00
Bruno Cardoso Lopes
9f798e9a9e Add AVX movnt{pd,ps,dq} 256-bit intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110650 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 02:49:24 +00:00
Bruno Cardoso Lopes
fcfcca1d9b Add AVX movmsk 256-bit intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110648 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 02:34:56 +00:00
Bruno Cardoso Lopes
405f11b300 Support AVX 256-bit load and store intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110645 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 01:43:16 +00:00
Bruno Cardoso Lopes
6719784148 Patterns to match AVX cmp instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110633 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 00:13:20 +00:00
Bruno Cardoso Lopes
533a7df02d Add matching patterns for vblend AVX intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110630 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 00:02:05 +00:00
Eric Christopher
5cb33a384f Wording. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110618 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-09 22:52:47 +00:00
Bruno Cardoso Lopes
93f6c1ec6e Add VCVTPD2PS, VCVTPS2DQ, VCVTPS2PDY, VCVTTPD2DQY, VCVTTPS2DQ and VCVTPD2DQ 256-bit conversion intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110608 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-09 21:51:56 +00:00
Bruno Cardoso Lopes
8468157278 Add patterns to AVX conversions instructions. Do that instead of declaring more intructions whenever is possible, more coming 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110605 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-09 21:24:59 +00:00
Oscar Fuentes
4951870e04 CMake: eliminated unnecessary target_link_libraries. 
Next time the build is broken due to wrong library dependencies, just
try building again (if you are on some Unix and are building all LLVM
targets) or ask someone to commit the regenerated LLVMLibDeps.cmake.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110593 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-09 20:33:08 +00:00
Bruno Cardoso Lopes
ad4910429c Memory version of vcvtdq2pd intrinsic 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110582 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-09 18:20:14 +00:00
Bruno Cardoso Lopes
251871ca66 Patterns to match vinsert, vbroadcast, vmovmask and vcvtdq2pd AVX intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110580 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-09 18:03:43 +00:00
Dale Johannesen
7f6eb639bd Use sdmem and sse_load_f64 (etc.) for the vector 
form of CMPSD (etc.)  Matching a 128-bit memory
operand is wrong, the instruction uses only 64 bits
(same as ADDSD etc.)  8193553.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110491 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-07 00:33:42 +00:00
Bruno Cardoso Lopes
4945dd8314 Patterns to match AVX 256-bit vzero intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110480 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-06 22:10:01 +00:00
Bruno Cardoso Lopes
bd2d90f5a5 Patterns to match AVX 256-bit permutation intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110468 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-06 20:03:27 +00:00
Owen Anderson
90c579de5a Reapply r110396, with fixes to appease the Linux buildbot gods. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110460 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-06 18:33:48 +00:00
Bruno Cardoso Lopes
9c3806461c Patterns to match AVX 256-bit horizontal arithmetic intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110427 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-06 02:10:30 +00:00
Bruno Cardoso Lopes
9c09f16a53 Patterns to match AVX 256-bit arithmetic intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110425 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-06 01:52:29 +00:00
Owen Anderson
1f74590e9d Revert r110396 to fix buildbots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110410 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-06 00:23:35 +00:00
Eric Christopher
e74a088d92 Add an option to always emit realignment code for a particular module. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110404 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-05 23:57:43 +00:00
Owen Anderson
9ccaf53ada Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static 
ID member as the sole unique type identifier.  Clean up APIs related to this change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110396 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-05 23:42:04 +00:00
Bruno Cardoso Lopes
ac09835a22 Support very basic (doesn't include ABI support in the front-end, varags, ...) 256-bit argument passing and return for AVX 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110394 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-05 23:35:51 +00:00
Eric Christopher
505656c6a2 Handle the memory barrier pseudo that goes to nothing for the JIT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110371 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-05 20:04:36 +00:00
Eric Christopher
da93b2cb8f Set hasSideEffects on the 64-bit no-sse memory barrier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110369 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-05 19:54:59 +00:00
Eric Christopher
280f96c508 Be a little bit more specific about target for the memory barrier 
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110360 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-05 18:36:20 +00:00
Eric Christopher
c34ea3770e Handle the pseudo in MCInstLower. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110359 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-05 18:34:30 +00:00
Eric Christopher
b6729dc0ef Make x86-64 membarriers work without sse and clean up some of the 
uses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110274 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-04 23:03:04 +00:00
Eli Friedman
7752442bfa PR7814: Truncates cannot be ignored for signed comparisons. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110268 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-04 22:40:58 +00:00
Devang Patel
5c1d941f00 Add DEBUG message. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110224 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-04 18:06:05 +00:00
Benjamin Kramer
56d23947ca Enable COFF writer on mingw32 and cygwin. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110200 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-04 15:32:40 +00:00
Benjamin Kramer
c575283675 Print an error message when someone tries -integrated-as on an unsupported target. 
- The COFF backend doesn't support MingW/Cygwin at the moment, it'll report an
  error, but it's still much better than random assertions from the MachO backend.
- We want to make ELF the default eventually, it's what the majority of targets use.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110197 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-04 13:16:30 +00:00
Chris Lattner
656f6800b2 fix a win64 encoding problem, patch by Cameron Esfahani! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110164 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-03 22:49:22 +00:00
Michael J. Spencer
0cd1ee2308 MC: Remove HasAbsolutizedSet from WindowsX86AsmBackend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109949 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-31 07:21:44 +00:00
Michael J. Spencer
e2195d8b35 Add relax all support to the COFF object streamer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109947 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-31 06:22:29 +00:00
Bruno Cardoso Lopes
98f985607b Support all 128-bit AVX vector intrinsics. Most part of them I already 
declared during the addition of the assembler support, the additional
changes are:
- Add missing intrinsics
- Move all SSE conversion instructions in X86InstInfo64.td to the SSE.td file.
- Duplicate some patterns to AVX mode.
- Step into PCMPEST/PCMPIST custom inserter and add AVX versions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109878 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-30 19:54:33 +00:00
Bruno Cardoso Lopes
5b7dab83e9 Fix typo! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109877 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-30 19:41:24 +00:00
Jakob Stoklund Olesen
b2eeed7464 Revert r109652, and remove the offending assert in loadRegFromStackSlot instead. 
We do sometimes load from a too small stack slot when dealing with x86 arguments
(varargs and smaller-than-32-bit args). It looks like we know what we are doing
in those cases, so I am going to remove the assert instead of artifically
enlarging stack slot sizes.

The assert in storeRegToStackSlot stays in. We don't want to write beyond the
bounds of a stack slot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109764 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-29 17:42:27 +00:00
Jakob Stoklund Olesen
4c010ec851 Create a fixed stack object for varargs that is as large as any register. 
The size of this object isn't used for anything - technically it is of variable
size.

This avoids a false positive from the assert in
X86InstrInfo::loadRegFromStackSlot, and fixes PR7735.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109652 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-28 20:55:38 +00:00
Nate Begeman
51409214d7 Implement a vectorized algorithm for <16 x i8> << <16 x i8> 
This is about 4x faster and smaller than the existing scalarization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109566 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-28 00:21:48 +00:00
Nate Begeman
bdcb5afb77 ~40% faster vector shl <4 x i32> on SSE 4.1 Larger improvements for smaller types coming in future patches. 
For:

define <2 x i64> @shl(<4 x i32> %r, <4 x i32> %a) nounwind readnone ssp {
entry:
  %shl = shl <4 x i32> %r, %a                     ; <<4 x i32>> [#uses=1]
  %tmp2 = bitcast <4 x i32> %shl to <2 x i64>     ; <<2 x i64>> [#uses=1]
  ret <2 x i64> %tmp2
}

We get:

_shl:                                   ## @shl
	pslld	$23, %xmm1
	paddd	LCPI0_0, %xmm1
	cvttps2dq	%xmm1, %xmm1
	pmulld	%xmm1, %xmm0
	ret

Instead of:

_shl:                                   ## @shl
	pshufd	$3, %xmm0, %xmm2
	movd	%xmm2, %eax
	pshufd	$3, %xmm1, %xmm2
	movd	%xmm2, %ecx
	shll	%cl, %eax
	movd	%eax, %xmm2
	pshufd	$1, %xmm0, %xmm3
	movd	%xmm3, %eax
	pshufd	$1, %xmm1, %xmm3
	movd	%xmm3, %ecx
	shll	%cl, %eax
	movd	%eax, %xmm3
	punpckldq	%xmm2, %xmm3
	movd	%xmm0, %eax
	movd	%xmm1, %ecx
	shll	%cl, %eax
	movd	%eax, %xmm2
	movhlps	%xmm0, %xmm0
	movd	%xmm0, %eax
	movhlps	%xmm1, %xmm1
	movd	%xmm1, %ecx
	shll	%cl, %eax
	movd	%eax, %xmm0
	punpckldq	%xmm0, %xmm2
	movdqa	%xmm2, %xmm0
	punpckldq	%xmm3, %xmm0
	ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109549 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-27 22:37:06 +00:00
Michael J. Spencer
dfd30187c6 Make MC use Windows COFF on Windows and add tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109494 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-27 06:46:15 +00:00
Jakob Stoklund Olesen
81c7b19f04 The isLoadFromStackSlot and isStoreToStackSlot have no way of reporting 
subregister operands like this:

%reg1040:sub_32bit<def> = MOV32rm <fi#-2>, 1, %reg0, 0, %reg0, %reg1040<imp-def>; mem:LD4[FixedStack-2](align=8)

Make them return false when subreg operands are present. VirtRegRewriter is
making bad assumptions otherwise.

This fixes PR7713.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109489 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-27 04:17:01 +00:00
Jakob Stoklund Olesen
516cd4575e Add assertions that expose the PR7713 miscompilation: Accessing a stack slot 
with a too-big register class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109488 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-27 04:16:58 +00:00
Evan Cheng
dee81010eb On x86, f32 / f64 nodes share the same registers as 128-bit vector values. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109450 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-26 21:50:05 +00:00
Bruno Cardoso Lopes
3c45734274 Temporary hack to let codegen assert or generate poor code in case 
we are using AVX and no AVX version of the desired intruction is present,
this is better for incremental dev (without fallbacks it's easier to spot
what's missing). Not sure this is the best hack thought (we can also disable
all HasSSE* predicates by dinamically marking them 'false' if AVX is present)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109434 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-26 21:01:18 +00:00
Evan Cheng
70017e44cd Add an ILP scheduler. This is a register pressure aware scheduler that's 
appropriate for targets without detailed instruction iterineries.
The scheduler schedules for increased instruction level parallelism in
low register pressure situation; it schedules to reduce register pressure
when the register pressure becomes high.

On x86_64, this is a win for all tests in CFP2000. It also sped up 256.bzip2
by 16%.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109300 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-24 00:39:05 +00:00
Bruno Cardoso Lopes
3c8e1bee63 Support x86 "eiz" and "riz" pseudo index registers in the assembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109295 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-24 00:06:39 +00:00
Bruno Cardoso Lopes
f64a7d49a0 Remove trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109276 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-23 22:15:26 +00:00
Bruno Cardoso Lopes
f528d2b438 Add AVX version of CLMUL instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109248 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-23 18:41:12 +00:00
Bruno Cardoso Lopes
26a9142bd6 Declare CLMUL as a subtarget feature 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109207 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-23 01:22:45 +00:00
Bruno Cardoso Lopes
cdae7e8244 Add x86 CLMUL (Carry-less multiplication) cpu feature 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109206 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-23 01:17:51 +00:00
Bruno Cardoso Lopes
6b7e9168a4 Add complete assembler support for FMA3 instructions, with descriptions and encodings taken from the AVX manual 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109204 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-23 00:54:35 +00:00
Dale Johannesen
c76d23f2e2 The only supported calling convention for X86-64 uses 
SSE, so we can't return floating point values if this
is disabled.  Detect this error for clang.

With SSE1 only, f64 is a problem; it can be done, but
neither llvm-gcc nor clang has ever generated correct
code for it.  Since nobody noticed this I think it's
OK to treat it as an error for now.

This also handles SSE-sized vectors of floating point.
8207686, 8204109.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109201 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-23 00:30:35 +00:00
Bruno Cardoso Lopes
06e6e101a0 Fix some AVX instructions which didnt had HasAVX prefix. And also a problem with PINSRW, which was totally wrong because of a typo I introduced previously 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109198 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-23 00:14:54 +00:00
Bruno Cardoso Lopes
fb583a9842 Add remaining AVX instructions (most of them dealing with GR64 destinations. This complete the assembler support for the general AVX ISA. But we still miss instructions from FMA3 and CLMUL specific feature flags, which are now the next step 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109168 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-22 21:18:49 +00:00
Chris Lattner
134d8eec87 remove the JIT "NeedsExactSize" feature and supporting logic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109167 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-22 21:17:55 +00:00
Chris Lattner
0123c1da35 X86MCInstLower now depends on AsmPrinter being around. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109154 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-22 21:10:04 +00:00
Chris Lattner
456fdaf0ce instead of migrating it to the MC instruction encoder, just 
rip out the implementation of X86InstrInfo::GetInstSizeInBytes.
The code being ripped out just implemented a copy and hacked up
version of the (old) instruction encoder, and is buggy and 
terrible in other ways.  Since "GetInstSizeInBytes" is really 
only there to support the JIT's "NeedsExactSize" hook (which
noone is using), just rip out the code.  I will rip out the
NeedsExactSize hook next.

This resolves rdar://7617809 - switch X86InstrInfo::GetInstSizeInBytes to use X86MCCodeEmitter



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109149 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-22 21:05:13 +00:00
Chandler Carruth
8a89a6ae9c Attempt to fix linking issues with CMake. Please review other CMake users, 
especially on other platforms. Is there a better way to fix this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109084 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-22 06:27:45 +00:00
Eric Christopher
9a9d275dc7 Custom lower the memory barrier instructions and add support 
for lowering without sse2.  Add a couple of new testcases.

Fixes a few libgomp tests and latent bugs.  Remove a few todos.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109078 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-22 02:48:34 +00:00
Eric Christopher
90eb4024ba 80-columns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109070 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-22 00:26:08 +00:00
Nate Begeman
0c07b64fec Make fast isel win64-aware w.r.t. call-clobbered regs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109069 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-22 00:09:39 +00:00
Bruno Cardoso Lopes
2b69143083 Add more 256-bit forms for a bunch of regular AVX instructions 
Add 64-bit (GR64) versions of some instructions (which are not
described in their SSE forms, but are described in AVX)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109063 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 23:53:50 +00:00
Rafael Espindola
fcbd1a749f Fixes win64. It was broken by a previous patch where I missed the !isWin64 
and then forced every register to be a vr128 on win64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109060 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 23:19:57 +00:00
Chris Lattner
908bafe6fa add some rough support for making mcinst lowering work without an 
asmprinter or mangler around.  This is option #B for killing off 
X86InstrInfo::GetInstSizeInBytes.  Option #A (killing 
"needsexactsize") was sent for consideration to llvmdev.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109056 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 23:03:35 +00:00
Bruno Cardoso Lopes
e29f37f6a1 Add missing AVX convert instructions. Those instructions are not described in their SSE forms (although they exist), but add the AVX forms anyway, so the assembler can benefit from it 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109039 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 21:37:59 +00:00
Nate Begeman
c8ea673bc0 Fix a couple issues with Win64 ABI 
1) all registers were spilled as xmm, regardless of actual size
2) win64 abi doesn't do the varargs-size-in-%al thing

Still to look into:

xmm6-15 are marked as clobbered by call instructions on win64 even though they aren't.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109035 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 20:49:52 +00:00
Bruno Cardoso Lopes
928fc3b4a0 Avoid AVX instructions to be selected instead of its SSE form 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109032 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 20:38:42 +00:00
Eric Christopher
dab4dac2a0 Pulling out previous patch, must've run the tests in 
the wrong directory.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109005 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 09:23:56 +00:00
Eric Christopher
87f41370a8 Lower MEMBARRIER on x86 and support processors without SSE2. 
Fixes a pile of libgomp failures in the llvm-gcc testsuite due
to the libcall not existing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109004 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 09:05:23 +00:00
Bruno Cardoso Lopes
cf6ca03128 Add AVX only vzeroall and vzeroupper instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109002 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 08:56:24 +00:00
Bruno Cardoso Lopes
7d7d15a159 Add new AVX vpermilps, vpermilpd and vperm2f128 instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108984 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 03:07:42 +00:00
Bruno Cardoso Lopes
4b13f3cf3d Add new AVX vmaskmov instructions, and also fix the VEX encoding bits to support it 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108983 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 02:46:58 +00:00
Bruno Cardoso Lopes
1154f426d7 Add new AVX vextractf128 instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108964 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 23:19:02 +00:00
Chris Lattner
6e8154354f make asmprinter optional, even though passing in null will cause things to explode right now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108955 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 22:45:33 +00:00
Chris Lattner
cb63ecba31 continue pushing dependencies around. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108952 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 22:35:40 +00:00
Chris Lattner
c0115b5ca1 reduce X86MCInstLower dependencies on asmprinter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108950 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 22:30:53 +00:00
Chris Lattner
0c13cf36ad pass around MF, not MMI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108949 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 22:26:07 +00:00
Chris Lattner
7648bd428b cleanups. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108947 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 22:23:57 +00:00
Chris Lattner
1a34c83caf move two asmprinter methods into the asmprinter .cpp file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108945 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 22:18:19 +00:00
Bruno Cardoso Lopes
e1c29be6f0 Add new AVX instruction vinsertf128 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108892 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 19:44:51 +00:00
Eric Christopher
72852a8cfb Constify some arguments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108812 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 06:52:21 +00:00
Bruno Cardoso Lopes
43945d99de Add AVX vbroadcast new instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108788 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 00:11:13 +00:00
Daniel Dunbar
7b81a0ef17 Update CMake files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108787 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 00:08:13 +00:00
Chris Lattner
aef40351f6 fix a layering problem by moving the x86 implementation 
of AsmPrinter and InstLowering into libx86 and out of the
asmprinter subdirectory.  Now X86/AsmPrinter just depends on
MC stuff, not all of codegen and LLVM IR.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108782 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-19 23:41:57 +00:00
Bruno Cardoso Lopes
94143ee625 Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108769 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-19 23:32:44 +00:00
Daniel Dunbar
77e2dd7bb2 X86: Mark JMP{32,64}[mr] as requires 32-bit/64-bit mode. They are the same 
instruction, we only want to allow the one for the current subtarget.
 - This also fixes suffix matching for jmp instructions, because it eliminates
   the ambiguity between 'jmpl' and 'jmpq'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108746 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-19 20:44:16 +00:00
Daniel Dunbar
926f2bb3d8 X86-64: Mark WINCALL and more tail call instructions as code gen only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108685 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-19 07:21:07 +00:00
Daniel Dunbar
e4c52a2c41 X86: Mark some tail call pseduo instruction as code gen only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108684 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-19 07:21:04 +00:00
Daniel Dunbar
df4c47be29 X86: Mark In32/64BitMode on LEAVE[64] and SYSEXIT[64]. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108683 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-19 07:21:01 +00:00
Daniel Dunbar
90b374cded MC/X86: We now match instructions like "incl %eax" correctly for the arch we are 
assembling; remove crufty custom cleanup code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108681 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-19 06:14:54 +00:00
Daniel Dunbar
cf246b7f0b X86: Mark MOV.*_{TC,NOREX} instruction as code gen only, they aren't real. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108680 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-19 06:14:49 +00:00
Daniel Dunbar
6c2c9a27c5 X86: MOV8o8a, MOV8ao8, etc. are only valid in 32-bit mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108679 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-19 06:14:44 +00:00
Daniel Dunbar
54074b5f04 TblGen/AsmMatcher: Add support for honoring instruction Requires<[]> attributes as part of the matcher. 
- Currently includes a hack to limit ourselves to "In32BitMode" and "In64BitMode", because we don't have the other infrastructure to properly deal with setting SSE, etc. features on X86.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108677 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-19 05:44:09 +00:00
Daniel Dunbar
d73ada7d24 Target: Give the TargetAsmParser access to the TargetMachine. 
- Unfortunate, but necessary for now to handle subtarget instruction matching. Eventually we should factor out the lower level target machine information so we don't need to do this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108664 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-19 00:33:49 +00:00
Chris Lattner
89a902e1c2 the stackifier is global! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108626 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-17 17:42:04 +00:00
Chris Lattner
a40ce7e394 doxygenify some comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108625 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-17 17:40:51 +00:00
Eric Christopher
697cba8ec2 Remove unnecessary check that was subsumed into canRealignStack. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108588 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-17 00:33:04 +00:00
Eric Christopher
acdb4b9203 Make comment a bit more clear as well as return statement since 
needsStackRealignment is currently checking the can conditions as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108581 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-17 00:25:41 +00:00
Jakob Stoklund Olesen
78e6e00922 Remove the isMoveInstr() hook. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108567 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-16 22:35:46 +00:00