Commit Graph

1224 Commits

Author SHA1 Message Date
Tom Stellard
d7858afe79 R600/SI: Initailize encoding fields of unused VOP3 modifiers to 0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213564 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 17:12:40 +00:00
Tom Stellard
0794af86a1 R600/SI: Initialize unused VOP3 sources to 0 instead of SIOperand.ZERO
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213563 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 17:12:37 +00:00
Tom Stellard
9787e8c76b R600/SI: Add instruction shrinking pass
This pass converts 64-bit instructions to 32-bit when possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213561 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 16:55:33 +00:00
Tom Stellard
df99a7f5dc R600/SI: VOPC instructions explicitly define VCC
Therefore we don't need to add it to the implict defs list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213558 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 16:27:24 +00:00
Tom Stellard
05388f25d7 R600/SI: Clean up some of the unused REGISTER_{LOAD,STORE} code
There are a few more cleanups to do, but I ran into some problems
with ext loads and trunc stores, when I tried to change some of the
vector loads and stores from custom to legal, so I wasn't able to
get rid of everything.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213552 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 15:45:06 +00:00
Tom Stellard
3280804237 R600/SI: Use scratch memory for large private arrays
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213551 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 15:45:01 +00:00
Tom Stellard
c912b101d2 R600/SI: Specify wavefront size for SI and CI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213550 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 15:44:58 +00:00
Tom Stellard
59b8363f8a R600/SI: Remove vaddr operand from BUFFER_LOAD_*_OFFSET instructions
This operand is never used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213549 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 15:44:55 +00:00
Tom Stellard
b664d47cb0 R600/SI: Store constant initializer data in constant memory
This implements a solution for constant initializers suggested
by Vadim Girlin, where we store the data after the shader code
and then use the S_GETPC instruction to compute its address.

This saves use the trouble of creating a new buffer for constant data
and then having to pass the pointer to the kernel via user SGPRs or the
input buffer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213530 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 14:01:14 +00:00
Tom Stellard
b97240dba8 R600/SI: Add isCFDepth0 Predicate to SALU addc pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213529 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 14:01:12 +00:00
Tom Stellard
54a2540fee R600/SI: Use VALU for i1 XOR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213528 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 14:01:10 +00:00
Tom Stellard
ad9769a118 R600/SI: Use a custom encoding method for simm16 in SOPP branch instructions
This allows us to explicitly define the type of fixup that is needed,
so we can distinguish this from future fixup types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213527 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 14:01:08 +00:00
Tom Stellard
efb733cbba R600/SI: Rename SOPP operands to match the encoding fields
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213526 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 14:01:05 +00:00
NAKAMURA Takumi
7a3c3e9a15 SIISelLowering.cpp: Define _USE_MATH_DEFINES to let M_PI provided on MS <cmath>.
FIXME: Would it be better to move it into configure?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213477 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-20 11:15:07 +00:00
Matt Arsenault
af1797fd03 R600: Remove unused function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213472 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-20 06:31:06 +00:00
Matt Arsenault
eb957bfe32 R600/SI: Remove dead code and add missing tests.
This probably was killed by some generic DAGCombiner
improvements in checking the TargetBooleanContents instead
of just 1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213471 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-20 06:11:02 +00:00
Matt Arsenault
f7a4b7a676 Revert accidentally committed r213459
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213461 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-19 19:17:33 +00:00
Matt Arsenault
7f36bf5f3d XXX - Increase unroll threshold
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213459 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-19 19:16:34 +00:00
Matt Arsenault
18ecf3fff3 R600/SI: implement range reduction for sin/cos
These instructions can only take a limited input range, and return
the constant value 1 out of range. We should do range reduction to
be able to process arbitrary values. Use a FRACT instruction after
normalization to achieve this. Also add a test for constant folding
with the lowered code with unsafe-fp-math enabled.

v2: use DAG lowering instead of intrinsic, adapt test
v3: calculate constant, fold pattern into instruction definition
v4: misc style fixes, add sin-fold testcase, cosmetics

Patch by Grigori Goronzy

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213458 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-19 18:44:39 +00:00
Matt Arsenault
fd22980d6b R600: Implement a few simple TTI queries.
I'm not sure if these have any effect right now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213455 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-19 18:15:16 +00:00
Tim Northover
7714a60ed1 R600: support fpext/fptrunc operations to and from f16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213376 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-18 13:01:37 +00:00
Tim Northover
cc03227446 R600: support f16 -> f64 conversion intrinsic.
Unfortunately, we don't seem to have a direct truncation, but the
extension can be legally split into two operations so we should
support that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213357 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-18 08:43:24 +00:00
Matt Arsenault
a32c319741 R600: Implement TTI:getPopcntSupport
The test is just copied from X86, and I don't know of a better
way to test it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213351 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-18 06:07:13 +00:00
Matt Arsenault
15865afcf7 Fix typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213285 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 17:50:22 +00:00
Tim Northover
3e61ccdded CodeGen: extend f16 conversions to permit types > float.
This makes the two intrinsics @llvm.convert.from.f16 and
@llvm.convert.to.f16 accept types other than simple "float". This is
only strictly needed for the truncate operation, since otherwise
double rounding occurs and there's no way to represent the strict IEEE
conversion. However, for symmetry we allow larger types in the extend
too.

During legalization, we can expand an "fp16_to_double" operation into
two extends for convenience, but abort when the truncate isn't legal. A new
libcall is probably needed here.

Even after this commit, various target tweaks are needed to actually use the
extended intrinsics. I've put these into separate commits for clarity, so there
are no actual tests of f64 conversion here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213248 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 10:51:23 +00:00
Matt Arsenault
21a9a6658e Use range for
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213230 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 06:19:06 +00:00
Matt Arsenault
df4663be6a R600: Short circuit alloca check if address space isn't private.
Skip calling GetUnderlyingObject in cases where it obviously
isn't from an alloca. This should only be a compile time improvement.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213229 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 06:13:41 +00:00
Matt Arsenault
a27bf373d9 R600/SI: Allow using f32 rcp / rsq when denormals not handled.
These are precise enough to use for OpenCL unless denormals
are handled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213107 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-15 23:50:10 +00:00
Matt Arsenault
7929c13df0 R600/SI: Fix select on i1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213096 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-15 21:44:37 +00:00
Matt Arsenault
4b0a7f3946 R600/SI: Implement less wrong f32 fdiv
Assuming single precision denormals and accurate sqrt/div are not
reported, this passes the OpenCL conformance test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213089 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-15 20:18:31 +00:00
Matt Arsenault
e4c6241505 R600: Add predicate for UnsafeFPMath
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213088 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-15 20:18:24 +00:00
Matt Arsenault
fc7ff2ac50 R600: Remove intrinsics that appear to be unused
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213087 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-15 20:10:27 +00:00
Jan Vesely
7b5f8a525a R600: Implement zero undef variants of ctlz/cttz
v2: use ffbh/l if available
v3: Rebase on top of Matt's SI patches

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <tom@stellard.net>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213072 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-15 15:51:09 +00:00
NAKAMURA Takumi
3ee5fc8618 Prune Redundant libdeps in CMake's target_link_libraries and LLVMBuild.txt.
I checked this with Release+Asserts on x86_64-mingw32. Please restore partially if this were overkill.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213064 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-15 11:37:03 +00:00
Matt Arsenault
5fbf09a69f R600: Add dag combine for copy of an illegal type.
This helps avoid redundant instructions to unpack, and repack
the vectors. Ideally we could recognize that pattern and eliminate
it. Currently v4i8 and other small element type vectors are scalarized,
so this has the added bonus of avoiding that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213031 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-15 02:06:31 +00:00
Matt Arsenault
b7df516d1f R600: Add denormal handling subtarget features.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213018 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-14 23:40:49 +00:00
Matt Arsenault
5b70c8ac7e R600/SI: Default to no single precision denormals.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213017 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-14 23:40:43 +00:00
Matt Arsenault
0ed20177c2 Remove unused include
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212898 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-13 03:08:59 +00:00
Matt Arsenault
74c9fe26e6 R600: Use range for and fix missing consts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212897 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-13 03:06:43 +00:00
Matt Arsenault
bb098a4d87 R600: Make ShaderType private
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212896 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-13 03:06:39 +00:00
Matt Arsenault
8e53751320 R600: Add option to disable promote alloca
This can make writing some tests harder, so add a flag
to disable it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212893 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-13 02:08:26 +00:00
Marek Olsak
438e1f2ad8 R600/SI: Use i32 vectors for resources and samplers
This affects new intrinsics only.

What surprises me is that v32i8 still works.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212831 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-11 17:11:52 +00:00
Marek Olsak
5a35fdcafb R600/SI: add sample and image intrinsics exposing all instruction fields
We need the intrinsics with offsets, so why not just add them all.
The R128 parameter will also be useful for reducing SGPR usage.
GL_ARB_image_load_store also adds some image GLSL modifiers like "coherent",
so Mesa will probably translate those to slc, glc, etc.

When LLVM 3.5 is released, I'll switch Mesa to these new intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212830 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-11 17:11:46 +00:00
Marek Olsak
4071d6f58b R600/SI: fix shadow mapping for 1D and 2D array textures
It was conflicting with def TEX_SHADOW_ARRAY, which also handles them.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212829 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-11 17:11:39 +00:00
Jan Vesely
865527a09b R600: Implement float to long/ulong
Use alg. from LegalizeDAG.cpp
Move Expand setting to SIISellowering

v2: Extend existing tests instead of creating new ones
v3: use separate LowerFPTOSINT function
v4: use TargetLowering::expandFP_TO_SINT
    add comment about using FP_TO_SINT for uints

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <tom@stellard.net>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212773 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 22:40:21 +00:00
Matt Arsenault
425ef825a6 R600/SI: Add support for llvm.convert.{to|from}.fp16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212676 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 03:22:20 +00:00
Matt Arsenault
0e1619e77c R600: Fix mishandling of load / store chains.
Fixes various bugs with reordering loads and stores.
Scalarized vector loads weren't collecting the chains
at all.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212473 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-07 18:34:45 +00:00
Matt Arsenault
7b1c5f52b0 Fix typo, weird indentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212472 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-07 18:34:42 +00:00
Matt Arsenault
f92e09efd3 Use cast<> instead of dyn_cast + assert
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212380 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-05 21:16:43 +00:00
Matt Arsenault
9363b585ce Fix grammar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212379 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-05 21:16:40 +00:00
Chandler Carruth
70968365db [codegen,aarch64] Add a target hook to the code generator to control
vector type legalization strategies in a more fine grained manner, and
change the legalization of several v1iN types and v1f32 to be widening
rather than scalarization on AArch64.

This fixes an assertion failure caused by scalarizing nodes like "v1i32
trunc v1i64". As v1i64 is legal it will fail to scalarize v1i32.

This also provides a foundation for other targets to have more granular
control over how vector types are legalized.

Patch by Hao Liu, reviewed by Tim Northover. I'm committing it to allow
some work to start taking place on top of this patch as it adds some
really important hooks to the backend that I'd like to immediately start
using. =]

http://reviews.llvm.org/D4322

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212242 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-03 00:23:43 +00:00
Tom Stellard
fad0de390b R600: Add a comment that llvm.AMDGPU.trunc is a legacy intrinsic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212218 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-02 20:53:57 +00:00
Tom Stellard
4a70647269 R600/SI: Use a ComplexPattern for ADDR64 addressing of MUBUF loads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212217 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-02 20:53:56 +00:00
Tom Stellard
1378871b1a R600: Promote i64 loads to v2i32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212216 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-02 20:53:54 +00:00
Tom Stellard
b48c8c49d5 R600/SI: Adjsut SGPR live ranges before register allocation
SGPRs are written by instructions that sometimes will ignore control flow,
which means if you have code like:

if (VGPR0) {
  SGPR0 = S_MOV_B32 0
} else {
  SGPR0 = S_MOV_B32 1
}

The value of SGPR0 will 1 no matter what the condition is.

In order to deal with this situation correctly, we need to view the
program as if it were a single basic block when we calculate the
live ranges for the SGPRs.  They way we actually update the live
range is by iterating over all of the segments in each LiveRange
object and setting the end of each segment equal to the start of
the next segment.  So a live range like:

[3888r,9312r:0)[10032B,10384B:0)  0@3888r

will become:

[3888r,10032B:0)[10032B,10384B:0)  0@3888r

This change will allow us to use SALU instructions within branches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212215 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-02 20:53:48 +00:00
Tom Stellard
a75d388f18 R600/SI: Add verifier check for immediates in register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212214 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-02 20:53:44 +00:00
Matt Arsenault
b1fb2ba24d R600: Fix crashes when an illegal type load or store is not handled.
I don't think anything hits this now, but will be exposed in future
patches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212197 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-02 17:44:53 +00:00
Matt Arsenault
97fb702886 R600: Move mul combine to separate function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212052 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-30 17:55:48 +00:00
Matt Arsenault
d36aada6fd R600: Remove unused declarations leftover from AMDIL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212051 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-30 17:37:17 +00:00
Craig Topper
521a69f182 Add ops() method to SDNode that returns an ArrayRef<SDUse>. Use it to simplify some code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211993 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-29 00:40:57 +00:00
Matt Arsenault
896cde882f R600: Move trivial getters into header, use initializer list
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211917 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-27 17:57:00 +00:00
Matt Arsenault
ee5d4a7b73 R600: Don't crash on unhandled instruction in promote alloca
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211906 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-27 16:52:49 +00:00
Matt Arsenault
20e4c0d24e Fix missing newline and simplify debug printing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211850 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-27 02:36:59 +00:00
Matt Arsenault
556a7c0f08 R600: Move load/store ReplaceNodeResults to common code.
Future patches will want to custom lower loads on SI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211848 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-27 02:33:47 +00:00
Matt Arsenault
3cd8cf6bbd R600/SI: Add FP mode bits to binary.
The default rounding mode to initialize the mode register needs
to be reported to the runtime. Fill in other bits a kernel
may be interested in setting for future use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211791 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-26 17:22:30 +00:00
Aaron Ballman
2711c0a68b Silencing a warning about isZExtFree hiding an inherited virtual function. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211783 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-26 13:45:47 +00:00
Matt Arsenault
b0f5a0e7e7 R600: Fix vector FMA
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211757 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-26 01:28:05 +00:00
Tom Stellard
11580ee62d R600/SI: Use a ComplexPattern for MUBUF stores
Now that non-leaf ComplexPatterns are allowed we can fold all the MUBUF
store patterns into the instruction definition.  We will also be able to
reuse this new ComplexPattern for MUBUF loads and atomic operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211644 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-24 23:33:07 +00:00
Tom Stellard
78d1e95201 R600: Promote i64 stores to v2i32
Now we need only one 64-bit pattern for stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211643 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-24 23:33:04 +00:00
Matt Arsenault
95eb45c5d9 R600: Fix inconsistency in rsq instructions.
R600 was using a clamped version of rsq, but SI was not. Add a
new rsq_clamped intrinsic and use them consistently.

It's unclear to me from the documentation what behavior
the R600 instructions have, so I assume they have the legacy behavior
described by the SI documents. For R600, use RECIPSQRT_IEEE
for both llvm.AMDGPU.rsq.legacy and llvm.AMDGPU.rsq. R600 also
has RECIPSQRT_FF, which I'm not sure how it fits in here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211637 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-24 22:13:39 +00:00
Matt Arsenault
a91ff54e43 R600: Remove DIV_INF
This corresponded to an amdil instruction which there is
a 2 instruction equivalent for.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211616 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-24 17:42:16 +00:00
Matt Arsenault
26da337208 R600/SI: Move pattern to instruction definition
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211614 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-24 17:17:06 +00:00
Matt Arsenault
140c6ae970 R600/SI: Verify restrictions on div_scale operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211524 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-23 18:28:31 +00:00
Matt Arsenault
ed143b7c0c R600/SI: Fix div_scale intrinsic.
The operand that must match one of the others does matter,
and implement selecting for it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211523 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-23 18:28:28 +00:00
Matt Arsenault
791c054391 R600: Remove AMDILISelLowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211519 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-23 18:00:55 +00:00
Matt Arsenault
6272302394 R600: Select is not expensive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211518 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-23 18:00:52 +00:00
Matt Arsenault
9ad2c7ef92 R600: Move add/sub with overflow out of AMDILISelLowering
Add more tests for these.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211517 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-23 18:00:49 +00:00
Matt Arsenault
5f607c0b39 R600: Move more out of AMDILISelLowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211516 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-23 18:00:44 +00:00
Matt Arsenault
a12b356464 R600: Don't set fp_round_inreg action.
There's no point in setting this since it seems to only
by created in 1 place for ppcf128

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211515 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-23 18:00:41 +00:00
Matt Arsenault
c4471e9248 R600/SI: Handle i64 sub.
We can handle it the same way as add

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211514 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-23 18:00:38 +00:00
Matt Arsenault
e564b6ed79 R600/SI: Move selection of i64 add to separate function.
Also don't use a SmallVector for fixed size array.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211513 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-23 18:00:34 +00:00
Matt Arsenault
b170a8042a R600: Rename AMDIL file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211512 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-23 18:00:31 +00:00
Matt Arsenault
cf88d40c8a Fix missing words in sentence
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211511 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-23 18:00:26 +00:00
Matt Arsenault
261698fbd5 Use helper function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211510 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-23 18:00:24 +00:00
Matt Arsenault
1f93cf49fc Alphabetize forward declarations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211509 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-23 18:00:20 +00:00
Jan Vesely
ddf2a7902a R600: Use LowerSDIVREM for i64 node replace
v2: move div/rem node replacement to R600ISelLowering
    make lowerSDIVREM protected

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211478 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-22 21:43:01 +00:00
Jan Vesely
cd88535ab9 R600: Implement custom SDIVREM.
Instead of separate SDIV/SREM. SDIV used UDIV which in turn used UDIVREM anyway.
SREM used SDIV(UDIV->UDIVREM)+MUL+SUB, using UDIVREM directly is more efficient.

v2: Don't use all caps names

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211477 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-22 21:43:00 +00:00
Tom Stellard
c0bf939e80 R600/SI: Add patterns for ctpop inside a branch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211378 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-20 17:06:11 +00:00
Tom Stellard
61d64acd0c R600/SI: Add a pattern for f32 ftrunc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211377 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-20 17:06:09 +00:00
Tom Stellard
2cda6e8ca6 R600: Expand vector flog2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211376 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-20 17:06:07 +00:00
Tom Stellard
2d245e2da4 R600: Expand vector fexp2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211375 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-20 17:06:05 +00:00
Tom Stellard
98b0736565 R600/SI: SI Control Flow Annotation bug fixed
Mixing of AddAvailableValue and GetValueAtEndOfBlock methods of SSAUpdater
leaded to the endless loop generation when the nested loops annotated.

This fixes a bug in the OCL_ML/KNN OpenCV test.  The test case is too
complex for FileCheck and would be very fragile.

Patch by: Elena Denisova

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211374 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-20 17:06:02 +00:00
Tom Stellard
538c95179c R600/SI: Add a VALU pattern for i64 xor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211373 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-20 17:05:57 +00:00
Matt Arsenault
7d1f7798db R600: Trivial subtarget feature cleanups.
Remove an unused AMDIL leftover, correct extra periods
appearing in the help menu.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211341 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-20 06:50:05 +00:00
Alp Toker
d06976aba7 Fix typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211304 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-19 19:41:26 +00:00
Craig Topper
bd01df2487 Convert some assert(0) to llvm_unreachable or fold an 'if' condition into the assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211254 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-19 06:10:58 +00:00
Matt Arsenault
d9b35435b8 R600/SI: Add intrinsics for various math instructions.
These will be used for custom lowering and for library
implementations of various math functions, so it's useful
to expose these as builtins.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211247 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-19 01:19:19 +00:00
Matt Arsenault
2ea6d93c5e Use stdint macros for specifying size of constants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211231 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-18 22:11:03 +00:00
Matt Arsenault
ce09bda96e R600: Handle fnearbyint
The difference from rint isn't really relevant here,
so treat them as equivalent. OpenCL doesn't have nearbyint,
so this is sort of pointless other than for completeness.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211229 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-18 22:03:45 +00:00
Marek Olsak
f286d63757 R600/SI: add gather4 and getlod intrinsics (v3)
This contains all the previous patches + getlod support on top of it.
It doesn't use SDNodes anymore, so it's quite small.
It also adds v16i8 to SReg_128, which is used for the sampler descriptor.

Reviewed-by: Tom Stellard

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211228 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-18 22:00:29 +00:00
Matt Arsenault
311ea12506 Use LL suffix for literal that should be 64-bits.
This hopefully fixes Windows

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211225 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-18 21:40:43 +00:00
Jan Vesely
52b6c2d6ef R600: Expand vector fceil
Move fp64 fceil tests to fceil64.ll

v2: rebase

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211194 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-18 17:57:29 +00:00
Matt Arsenault
4380c61415 Work around ridiculous warning.
Apparently C++ doesn't really have hex floating point constants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211192 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-18 17:45:58 +00:00
Matt Arsenault
2b6e6fc1a8 R600/SI: Add intrinsics for brev instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211187 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-18 17:13:57 +00:00
Matt Arsenault
795ae8615f R600/SI: Prettier operand printing for 64-bit ops.
Copy what is done for 32-bit already so the order is about the same.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211186 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-18 17:13:51 +00:00
Matt Arsenault
debd831223 R600: Implement f64 ftrunc, ffloor and fceil.
CI has instructions for these, so this fixes them for older hardware.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211183 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-18 17:05:30 +00:00
Matt Arsenault
a5395c03f0 R600: Custom lower f64 frint for pre-CI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211182 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-18 17:05:26 +00:00
Matt Arsenault
f7aa5f9379 R600/SI: Temporary fix for f64 fneg
This should be a source modifier, but this unblocks
most of my math patches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211181 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-18 17:05:22 +00:00
Matt Arsenault
3de1bed8f4 R600/SI: Comparisons set vcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211178 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-18 16:53:48 +00:00
Jan Vesely
c32d52df24 R600: Implement 64bit SRA
v2: Use capitalized variable name

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211159 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-18 12:27:17 +00:00
Jan Vesely
2d06e73d88 R600: Implement 64bit SRL
v2: use C++ style comment

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211158 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-18 12:27:15 +00:00
Jan Vesely
a64058f3eb R600: Implement 64bit SHL
v2: Use c++ style comment

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211157 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-18 12:27:13 +00:00
Tom Stellard
540fe7f20e R600/SI: Make sure target flags are set on pseudo VOP3 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211120 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-17 19:34:46 +00:00
Matt Arsenault
3f1f259c22 R600/SI: Match cttz_zero_undef
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211116 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-17 17:36:27 +00:00
Matt Arsenault
62e378b057 R600/SI: Match ctlz_zero_undef
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211115 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-17 17:36:24 +00:00
Tom Stellard
f56e7678d1 R600: Use LDS and vectors for private memory
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211110 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-17 16:53:14 +00:00
Tom Stellard
ff8dc48da3 R600/SI: Add a pattern for llvm.AMDGPU.barrier.global
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211109 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-17 16:53:09 +00:00
Tom Stellard
bae98b1b45 SelectionDAG: Expand i64 = FP_TO_SINT i32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211108 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-17 16:53:07 +00:00
Tom Stellard
41bfd7846b R600/SI: Re-initialize the m0 register after using it for indirect addressing
We need to store a value greater than or equal to the number of LDS
bytes allocated by the shader in the m0 register in order for LDS
instructions to work correctly.

We always initialize m0 at the beginning of a shader, but this register
is also used for indirect addressing offsets, so we need to
re-initialize it any time we use indirect addressing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211107 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-17 16:53:04 +00:00
Matt Arsenault
f9ef37a986 Fix copy paste error
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211003 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-15 21:22:52 +00:00
Matt Arsenault
fa848ccd09 R600: Remove a few more things from AMDILISelLowering
Try to keep all the setOperationActions for integer ops
together.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211001 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-15 21:08:58 +00:00
Matt Arsenault
e2480a202f R600: Fix assert on vector sdiv
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211000 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-15 21:08:54 +00:00
Matt Arsenault
62f6ab7a6d R600: Move / cleanup more leftover AMDIL stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210998 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-15 20:23:38 +00:00
Matt Arsenault
57177e3361 R600: Move division custom lowering out of AMDILISelLowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210997 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-15 20:08:02 +00:00
Matt Arsenault
61bfbc4d96 R600: Report that integer division is expensive.
Divides by weird constants now emit much better code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210995 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-15 19:48:16 +00:00
Matt Arsenault
36b9c7c872 R600: Remove dead code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210994 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-15 19:48:13 +00:00
Matt Arsenault
212514f179 Fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210968 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-14 04:26:07 +00:00
Matt Arsenault
aac455af99 R600: Fix asserts related to constant initializers
This would assert if a constant address space was extern
and therefore didn't have an initializer. If the initializer
was undef, it would hit the unreachable unhandled initializer case.

An extern global should never really occur since we don't have
machine linking, but bugpoint likes to remove initializers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210967 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-14 04:26:05 +00:00
Matt Arsenault
15f474c925 R600: Use address space enum instead of value
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210966 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-14 04:26:01 +00:00
Matt Arsenault
f317d86f8f R600: Cleanup some old AMDIL stuff.
Move / delete some of the more obviously wrong
setOperationAction calls. Most of these are setting Expand
for types that aren't legal which is the default anyway.
Leave stuff that might require more thought on whether it's
junk or not as it is.

No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210922 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 17:20:53 +00:00
Tom Stellard
61bc72e9ae R600: Remove AMDIL instruction and register definitions
Most of these are no longer used any more.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210915 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 16:38:59 +00:00
Matt Arsenault
efa4805b58 R600: Don't call setOperationAction with things that aren't opcodes.
CondCode actions are set with setCondCodeAction.
This should have been a harmless bug since the values seem to only
collide only with nodes that don't need to be handled, and these are
already correctly setup elsewhere.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210888 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 07:44:38 +00:00
Matt Arsenault
d344c6bcf9 R600/SI: Fix selection error on i64 rotl / rotr.
Evergreen is still broken due to missing shl_parts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210885 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 04:00:30 +00:00
Tom Stellard
6b0a08b15b R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtarget
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210869 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 01:32:00 +00:00
Tom Stellard
ee0f3892f9 R600: Drop use of cached TargetMachine in R600InstrInfo.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210868 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 01:31:56 +00:00
Tom Stellard
aa48b83e80 R600: Drop use of cached TargetMachine in AMDGPUInstrInfo.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210865 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 01:02:57 +00:00
Matt Arsenault
00c3986254 R600: Mostly remove remaining AMDIL intrinsics.
Delete all unused ones, and add new AMDGPU named intrinsics for
the ones that are. Handle the old AMDIL names for comptability (although
remove their GCCBuiltin names) and add tests since there weren't any
for these before.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210827 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-12 21:15:44 +00:00
Matt Arsenault
0b87955888 R600/SI: Use a register set to -1 for data0 on ds_inc*/ds_dec*
There is not such thing as a 0-data ds instruction, and the data
operand needs to be a vgpr set to something meaningful.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210756 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-12 08:21:54 +00:00
Tom Stellard
beef5c58d7 R600: Set correct InstrItinClass for instructions using *Helper classes
We weren't doing this before, so all instruction using the *Helper
classes were considered for any ALU slot.

This fixes a hang in the builtin-char-clz-1.0.generated.cl piglit test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210703 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-11 20:51:42 +00:00
Tom Stellard
7ae77a1b1e R600: BCNT_INT is a vector only instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210702 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-11 20:51:39 +00:00
Matt Arsenault
7fa80b45eb R600/SI: Fix bitcast between v2i32 and f64
This is the same problem fixed in r210664 for more types.

The test passes without this fix. For some reason
I'm only hitting this when creating selects lowered
to v2i32 selects.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210692 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-11 19:31:13 +00:00
Matt Arsenault
4600175c7f R600/SI: Update place using old subtarget predicate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210683 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-11 18:11:34 +00:00
Matt Arsenault
c9dbd0da7a R600/SI: Add common 64-bit LDS atomics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210680 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-11 18:08:54 +00:00
Matt Arsenault
481a071a8b R600/SI: Add instruction definitions for 64-bit LDS atomics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210679 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-11 18:08:50 +00:00
Matt Arsenault
6b19a3a474 R600/SI: Add 32-bit LDS atomic cmpxchg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210678 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-11 18:08:48 +00:00
Matt Arsenault
a396a70c1d R600/SI: Use LDS atomic inc / dec
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210677 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-11 18:08:45 +00:00
Matt Arsenault
2da1a85cbb R600/SI: Add other LDS atomic operations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210676 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-11 18:08:42 +00:00
Matt Arsenault
507d8cad7b R600/SI: Add instruction definitions for more LDS ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210675 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-11 18:08:39 +00:00
Matt Arsenault
4a19dd468d R600/SI: Fix backwards names for local atomic instructions.
The manual lists them as *_RTN_U32, not *_U32_RTN, which is more
consistent with how every other sized instruction is named.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210674 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-11 18:08:37 +00:00
Matt Arsenault
b97095b94f R600/SI: Refactor local atomics.
Use patterns that will also match the immediate offset to
match the normal read / writes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210673 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-11 18:08:34 +00:00
Matt Arsenault
8a9df8f92c R600/SI: Use v_cvt_f32_ubyte* instructions
This eliminates extra extract instructions when loading an i8 vector to
a float vector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210666 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-11 17:50:44 +00:00
Matt Arsenault
a2dca4cc04 R600/SI: Fix selection failure on scalar_to_vector
There seem to be only 2 places that produce these,
and it's kind of tricky to hit them.

Also fixes failure to bitcast between i64 and v2f32,
although this for some reason wasn't actually broken in the
simple bitcast testcase, but did in the scalar_to_vector one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210664 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-11 17:40:32 +00:00
Rafael Espindola
e12b0bbc02 Try to fix the msvc build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210636 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-11 04:41:37 +00:00
Matt Arsenault
3692045d8e Use cast instead of assert + dyn_cast
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210628 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-11 03:30:06 +00:00
Matt Arsenault
e0162b9648 R600: Add helper functions.
Extract these from some of my other patches, since this
is the only thing really making them dependent on each other.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210627 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-11 03:29:54 +00:00
Tom Stellard
cd0b8d6cbf R600/SI: Emit an error when attempting to spill VGPRs v4
I can't get VGPR spilling to work reliable, so for now just emit
an error when the register allocator tries to spill VGPRs.

v2:
  - Fix build
v3:
  - Added crash fix when spilling SPGRs
v4:
  - Use V_MOV_B32 as a dummy instruction instead of S_NOP

Patch by: Darren Powell

https://bugs.freedesktop.org/show_bug.cgi?id=75276

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210588 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 21:20:41 +00:00
Tom Stellard
48d11b0228 R600/SI: Fix a crash when spilling SGPRs
We need to make sure only one new instruction is added when spilling
otherwise the register allocator may crash.

This fixes a crash in the game Antichamber.

https://bugs.freedesktop.org/show_bug.cgi?id=75276

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210587 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 21:20:38 +00:00
Matt Arsenault
1f4772305a R600: Use BCNT_INT for evergreen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210569 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 19:18:28 +00:00
Matt Arsenault
69891c0115 R600/SI: Implement i64 ctpop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210568 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 19:18:24 +00:00
Matt Arsenault
ee9772d9dd R600/SI: Use bcnt instruction for ctpop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210567 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 19:18:21 +00:00
Matt Arsenault
bfd00e21b7 R600: Handle fcopysign
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210564 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 19:00:20 +00:00
Matt Arsenault
0ba78a9121 R600/SI: Handle sign_extend and zero_extend to i64 with patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210563 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 18:54:59 +00:00
Tom Stellard
f586a260ca SelectionDAG: Expand SELECT_CC to SELECT + SETCC
This consolidates code from the Hexagon, R600, and XCore targets.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210539 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 16:01:22 +00:00
Matt Arsenault
405ed284b7 R600/SI: Rename VOP3 helper class to be more general
It has other uses besides shift instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210478 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 17:00:46 +00:00
Matt Arsenault
1968da36ed R600/SI: Keep 64-bit not on SALU
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210476 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 16:36:31 +00:00
Matt Arsenault
cf7a113d2f R600: Fix selection failure for vector bswap
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210475 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 16:20:25 +00:00
Matt Arsenault
798a829eca R600/SI: Match rsq instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210226 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-05 00:15:55 +00:00
Matt Arsenault
6db82d3819 Use nullptr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210222 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-05 00:01:12 +00:00
Matt Arsenault
1b68686365 Fix typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210135 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-03 23:06:13 +00:00
Matt Arsenault
3871a03035 R600: Set all float vector expands in the same place
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209988 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-01 07:38:21 +00:00
Matt Arsenault
606b80c8c4 R600/SI: Remove redundant patterns
These patterns are already handled in the instruction definition.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209979 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-31 19:25:17 +00:00
Matt Arsenault
da5824d073 R600/SI: Fix [s|u]int_to_fp for i1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209971 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-31 06:47:42 +00:00
Matt Arsenault
bf933548ba R600/SI: Fix pattern variable names.
These are confusing enough since the order swaps,
so give them more useful names.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209787 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-29 01:18:01 +00:00
Matt Arsenault
fed4bab148 R600: Add definition for flat address space ID.
Use 4 since that's probably what it will be for spir.
Move ADDRESS_NONE to the end to keep the constant_buffer_* values
unchanged, since apparently a bunch of r600 tests use those directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209463 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 18:27:07 +00:00
Matt Arsenault
3c698f35e0 R600: Try to convert BFE back to standard bit ops when possible.
This allows existing DAG combines to work on them, and then
we can re-match to BFE if necessary during instruction selection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209462 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 18:09:12 +00:00
Matt Arsenault
e3ed404672 R600: Add dag combine for BFE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209461 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 18:09:07 +00:00
Matt Arsenault
7e12b82625 R600: Implement ComputeNumSignBitsForTargetNode for BFE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209460 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 18:09:03 +00:00
Matt Arsenault
9859540b06 R600: Implement computeMaskedBitsForTargetNode for BFE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209459 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 18:09:00 +00:00
Matt Arsenault
cb0402e9a4 R600: Expand mul24 for GPUs without it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209458 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 18:00:24 +00:00
Matt Arsenault
21851f9adb R600: Expand mad24 for GPUs without it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209457 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 18:00:20 +00:00
Matt Arsenault
f49da4338a R600: Add intrinsics for mad24
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209456 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 18:00:15 +00:00
Matt Arsenault
351c658fc2 R600/SI: Move instruction pattern to instruction definition
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209454 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 17:45:20 +00:00
Matt Arsenault
bce7d05ba9 R600/SI: Match fp_to_uint / uint_to_fp for f64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209388 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 03:20:30 +00:00
Matt Arsenault
afd1747bbc R600: Add comment describing problems with LowerConstantInitializer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209333 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 22:59:17 +00:00
Matt Arsenault
bd124c85ef R600: Partially fix constant initializers for structs and vectors.
This should extend the current workaround to work with structs
that only contain legal, scalar types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209331 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 22:42:42 +00:00
Matt Arsenault
49323774b4 Use cast<> instead of unchecked dyn_cast
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209310 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 18:03:59 +00:00
Matt Arsenault
f5d9170e67 Remove unused method declaration
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209174 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-19 22:55:35 +00:00
Aaron Ballman
50d09f1212 Resolving MSVC warnings about switch statements with a default label, but no case labels. No functional changes intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209126 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-19 14:29:04 +00:00
Tom Stellard
17200e3bb3 R600/SI: Refactor the VOP3_32 tablegen class
This will allow us to use a single MachineInstr to represent
instructions which behave the same but have different encodings
on some subtargets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209028 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-16 20:56:47 +00:00
Tom Stellard
9d99d7a185 R600/SI: Add a PredicateControl class for managing TableGen predicates
This was inspired by the PredicateControl class in the MIPS backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209027 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-16 20:56:45 +00:00
Tom Stellard
9b24e0c6f2 R600/SI: Move tablegen patterns away from instruction defs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209026 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-16 20:56:44 +00:00
Tom Stellard
1c073c3954 R600/SI: Remove unused instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209025 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-16 20:56:43 +00:00
Tom Stellard
3bd63cd655 R600/SI: Promote f32 SELECT to i32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209024 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-16 20:56:41 +00:00
Tom Stellard
03b96200c6 R600/SI: Remove duplicate pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209023 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-16 20:56:37 +00:00
Matt Arsenault
a8f7afaeb4 Use range for
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208922 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 21:44:05 +00:00
Tom Stellard
29d4ed329e R600/SI: Stop using VSrc_* as the default register class for types.
We now use SReg_* for integer types and VReg_* for floating-point types.
This should help simplify the SIFixSGPRCopies pass and no longer causes
ISel to insert a COPY after termiator instuctions that output a value.

This change is covered by exisitng tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208888 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 14:41:57 +00:00
Tom Stellard
704fe35d88 R600/SI: Fix a bug with handling of INSERT_SUBREG in SIFixSGPRCopies
This prevents a future commit from regressing the load-i1.ll test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208887 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 14:41:55 +00:00
Tom Stellard
c1de569ce8 R600/SI: Only use SALU instructions for 64-bit add in a block of CF depth 0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208886 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 14:41:54 +00:00
Tom Stellard
bfffad69b2 R600/SI: Use VALU instructions for i1 ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208885 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 14:41:50 +00:00
Jay Foad
6b543713a2 Rename ComputeMaskedBits to computeKnownBits. "Masked" has been
inappropriate since it lost its Mask parameter in r154011.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208811 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-14 21:14:37 +00:00