Commit Graph

50 Commits

Author SHA1 Message Date
Ulrich Weigand
5e220753ff [PowerPC] Add assembler parser
This adds assembler parser support to the PowerPC back end.

The parser will run for any powerpc-*-* and powerpc64-*-* triples,
but was tested only on 64-bit Linux.  The supported syntax is
intended to be compatible with the GNU assembler.

The parser does not yet support all PowerPC instructions, but
it does support anything that is generated by LLVM itself.
There is no support for testing restricted instruction sets yet,
i.e. the parser will always accept any instructions it knows,
no matter what feature flags are given.

Instruction operands will be checked for validity and errors
generated.  (Error handling in general could still be improved.)

The patch adds a number of test cases to verify instruction
and operand encodings.  The tests currently cover all instructions
from the following PowerPC ISA v2.06 Book I facilities:
Branch, Fixed-point, Floating-Point, and Vector. 
Note that a number of these instructions are not yet supported
by the back end; they are marked with FIXME.

A number of follow-on check-ins will add extra features.  When
they are all included, LLVM passes all tests (including bootstrap)
when using clang -cc1as as the system assembler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181050 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 19:49:39 +00:00
Hal Finkel
171a8adf31 Add PPC instruction record forms and associated query functions
This is prep. work for the implementation of optimizeCompare. Many PPC
instructions have 'record' forms (in almost all cases, this means that the RC
bit is set) that cause the result of the instruction to be compared with zero,
and the result of that comparison saved in a predefined condition register. In
order to add the record forms of the instructions without too much
copy-and-paste, the relevant functions have been refactored into multiclasses
which define both the record and normal forms.

Also, two TableGen-generated mapping functions have been added which allow
querying the instruction code for the record form given the normal form (and
vice versa).

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179356 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12 02:18:09 +00:00
Hal Finkel
1abaf907b6 Add a SchedMachineModel for the PPC G5
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178850 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05 05:49:18 +00:00
Hal Finkel
575e9229bd Add a SchedMachineModel for the PPC A2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178848 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05 05:34:08 +00:00
Hal Finkel
110e323b61 PPC: Enable FRES and FRSQRTE on the default PPC64 description
I discussed this with Bill Schmidt on IRC, and it was decided that this is a
safe and reasonable default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178659 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03 14:40:18 +00:00
Hal Finkel
2d8f62017d Remove some unsupported-feature comments from PPC.td
These refer to the reciprocal estimate support recently committed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178618 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03 04:03:58 +00:00
Hal Finkel
827307b95f Use PPC reciprocal estimates with Newton iteration in fast-math mode
When unsafe FP math operations are enabled, we can use the fre[s] and
frsqrte[s] instructions, which generate reciprocal (sqrt) estimates, together
with some Newton iteration, in order to quickly generate floating-point
division and sqrt results. All of these instructions are separately optional,
and so each has its own feature flag (except for the Altivec instructions,
which are covered under the existing Altivec flag). Doing this is not only
faster than using the IEEE-compliant fdiv/fsqrt instructions, but allows these
computations to be pipelined with other computations in order to hide their
overall latency.

I've also added a couple of missing fnmsub patterns which turned out to be
missing (but are necessary for good code generation of the Newton iterations).
Altivec needs a similar fix, but that will probably be more complicated because
fneg is expanded for Altivec's v4f32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178617 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03 04:01:11 +00:00
Hal Finkel
4647919784 Add more PPC floating-point conversion instructions
The P7 and A2 have additional floating-point conversion instructions which
allow a direct two-instruction sequence (plus load/store) to convert from all
combinations (signed/unsigned i32/i64) <--> (float/double) (on previous cores,
only some combinations were directly available).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178480 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-01 17:52:07 +00:00
Hal Finkel
8049ab15e4 Add the PPC lfiwax instruction
This instruction is available on modern PPC64 CPUs, and is now used
to improve the SINT_TO_FP lowering (by eliminating the need for the
separate sign extension instruction and decreasing the amount of
needed stack space).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178446 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-31 10:12:51 +00:00
Hal Finkel
f5d5c43460 Add PPC FP rounding instructions fri[mnpz]
These instructions are available on the P5x (and later) and on the A2. They
implement the standard floating-point rounding operations (floor, trunc, etc.).
One caveat: frin (round to nearest) does not implement "ties to even", and so
is only enabled in fast-math mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178337 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 08:57:48 +00:00
Hal Finkel
efdd4673d6 Add the PPC64 ldbrx/stdbrx instructions
These are 64-bit load/store with byte-swap, and available on the P7 and the A2.
Like the similar instructions for 16- and 32-bit words, these are matched in the
target DAG-combine phase against load/store-bswap pairs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178276 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 19:25:55 +00:00
Hal Finkel
c53ab4d77f Add the PPC64 popcntd instruction
PPC ISA 2.06 (P7, A2, etc.) has a popcntd instruction. Add this instruction and
tell TTI about it so that popcount-loop recognition will know about it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178233 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 13:29:47 +00:00
Bill Schmidt
dbc86b98f2 Add notes about future PowerPC features
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174232 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-01 23:10:09 +00:00
Bill Schmidt
cdc3b74cfb LLVM enablement for some older PowerPC CPUs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174230 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-01 22:59:51 +00:00
Hal Finkel
5bb16fdbb3 Add definitions for the PPC a2q core marked as having QPX available
This is the first commit of a large series which will add support for the
QPX vector instruction set to the PowerPC backend. This instruction set is
used on the IBM Blue Gene/Q supercomputers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173973 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-30 21:17:42 +00:00
Hal Finkel
621b77ade2 Add PPC Freescale e500mc and e5500 subtargets.
Add subtargets for Freescale e500mc (32-bit) and e5500 (64-bit) to
the PowerPC backend.

Patch by Tobias von Koch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162764 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 16:12:39 +00:00
Hal Finkel
009f7afbeb Add support for the PPC isel instruction.
The isel (integer select) instruction is supported on the 440 and A2
embedded cores and on the POWER7.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159045 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22 23:10:08 +00:00
Hal Finkel
6670c82df5 Fixes for PPC host detection and features.
POWER4 is a 64-bit CPU (better matched to the 970).
The g3 is really the 750 (no altivec), the g4+ is the 74xx (not the 750).

Patch by Andreas Tobler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158363 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-12 16:39:23 +00:00
Hal Finkel
5a53c6e345 Enable MFOCRF generation on the PPC A2 core.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158324 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-11 19:57:04 +00:00
Hal Finkel
bd5cafd9bb Rename the PPC target feature gpul to mfocrf.
The PPC target feature gpul (IsGigaProcessor) was only used for one thing:
To enable the generation of the MFOCRF instruction. Furthermore, this
instruction is available on other PPC cores outside of the G5 line. This
feature now corresponds to the HasMFOCRF flag.

No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158323 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-11 19:57:01 +00:00
Hal Finkel
622382fc5e Add POWER6 and POWER7 CPU types to the PPC backend.
No functional change; these will be used by upcoming scheduler enhancements.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158313 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-11 15:43:08 +00:00
Hal Finkel
b66e943d4c Fix some 80-col. violations I introduced with the A2 PPC64 core.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153852 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-01 21:20:14 +00:00
Hal Finkel
4d989ac93c Add instruction itinerary for the PPC64 A2 core.
This adds a full itinerary for IBM's PPC64 A2 embedded core. These
cores form the basis for the CPUs in the new IBM BG/Q supercomputer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153842 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-01 19:22:40 +00:00
Jia Liu
31d157ae1a Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-18 12:03:15 +00:00
Hal Finkel
c6d08f10bf Add PPC 440 scheduler and some associated tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142170 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 04:03:49 +00:00
Hal Finkel
8ee53e2eb6 initial test commit (remove whitespace)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141972 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 18:54:13 +00:00
Chris Lattner
84a04adf3a dissolve some more hacks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119115 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 03:53:53 +00:00
Jakob Stoklund Olesen
fddb7667ca Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.

This works well because TableGen resolves member references late:

class I : Instruction {
  AddrMode AM = AddrModeNone;
  let TSFlags{3-0} = AM.Value;
}

let AM = AddrMode4 in
def ADD : I;

TSFlags gets the expected bits from AddrMode4 in this example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100384 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-05 03:10:20 +00:00
Evan Cheng
027fdbe3ba Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59953 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-24 07:34:46 +00:00
Chris Lattner
4ee451de36 Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-29 20:36:04 +00:00
Chris Lattner
b9a7bea99c Switch PPC return lower to use an autogenerated CC description.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34940 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-06 00:59:59 +00:00
Jim Laskey
c35010d3a4 Honor cpu directive, take two.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32492 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-12 20:57:08 +00:00
Chris Lattner
a7a5854f1c Rename some subtarget features. A CPU now can *have* 64-bit instructions,
can in 32-bit mode we can choose to optionally *use* 64-bit registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28824 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-16 17:34:12 +00:00
Evan Cheng
0f3ac8d8d4 getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28378 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-18 00:12:58 +00:00
Evan Cheng
c01d497255 Remove PointerType from class Target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28368 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-17 21:20:27 +00:00
Chris Lattner
419ed53006 add callee saved vector regs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26805 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-16 22:07:06 +00:00
Chris Lattner
fd97734f36 Mark instructions that are cracked by the PPC970 decoder as such.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26720 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-13 05:15:10 +00:00
Chris Lattner
88d211f823 Several big changes:
1. Use flags on the instructions in the .td file to indicate the PPC970 unit
   type instead of a table in the .cpp file.  Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
   algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
   accurately.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26719 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-12 09:13:49 +00:00
Chris Lattner
bf751e2d6f Add a subtarget feature for the stfiwx instruction. I know the G5 has it,
but I don't know what other PPC impls do.  If someone could update the proc
table, I would appreciate it :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26421 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-28 07:08:22 +00:00
Evan Cheng
19c9550744 Subtarget feature can now set any variable to any value
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25678 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-27 08:09:42 +00:00
Jim Laskey
f0c2be4d2b Add attribute name and type to SubtargetFeatures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24012 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-26 17:28:23 +00:00
Chris Lattner
aa38be17c8 mark this as beta
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23906 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-23 22:23:45 +00:00
Chris Lattner
c8d28890f6 rearrange things a bit so that instructions can use subtarget features in the
future.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23902 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-23 22:08:13 +00:00
Chris Lattner
2e1f823aed improve -help output
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23892 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-23 05:28:51 +00:00
Jim Laskey
5476b9bfce Add g3 back to the mix and reorder to irritate them anal folk. Actually, it's
to group appropriately and provide cues to maintainers that the lists don't
need to be ordered.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23880 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-22 08:04:24 +00:00
Chris Lattner
4245f1d790 64-bit reg support should not be enabled by default, as support isn't complete.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23878 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-21 22:15:43 +00:00
Jim Laskey
f5fc2cbd6b Plugin new subtarget backend into the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23870 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-21 19:05:19 +00:00
Jim Laskey
538421411a Added InstrSchedClass to each of the PowerPC Instructions.
Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23830 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-19 19:51:16 +00:00
Chris Lattner
f379997adc Rename PowerPC*.td -> PPC*.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23740 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-14 23:40:39 +00:00
Chris Lattner
4c7b43b43f Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23738 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-14 23:37:35 +00:00