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19412 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
3bde6fe0df Introduce a pass to insert vzeroupper instructions to avoid AVX to 
SSE transition penalty. The pass is enabled through the "x86-use-vzeroupper"
llc command line option. This is only the first step (very naive and
conservative one) to sketch out the idea, but proper DFA is coming next
to allow smarter decisions. Comments and ideas now and in further commits
will be very appreciated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138317 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-23 01:14:17 +00:00
Jim Grosbach
04d55f1905 Thumb parsing and encoding for SBC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138311 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:55:58 +00:00
Jim Grosbach
934755ac04 Thumb parsing and encoding for RSB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138308 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:47:13 +00:00
Owen Anderson
8e1e60b5f8 Reject invalid imod values in t2CPS instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138306 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:44:04 +00:00
Owen Anderson
c6788c83b4 t2SMLAD is a four-register instruction, not a three-register one. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138301 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:31:45 +00:00
Owen Anderson
22d35086fe Correct operand naming of t2USAT16 to allow proper decoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138300 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:27:47 +00:00
Jim Grosbach
86b5d2b02d Revert r138278 now that r138289 has fixed the root issue. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138299 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:25:48 +00:00
Owen Anderson
2379fc235f Match operand naming to allow correct decoding of t2LDRSH_POST. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138298 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:22:05 +00:00
Jim Grosbach
6dcafc0d0b Improve error checking for tPUSH and tPOP register lists. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138295 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:17:34 +00:00
Owen Anderson
796c3659c9 Match operand names to provide correct decoding for Thumb2 SMULL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138294 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:16:48 +00:00
Owen Anderson
2c9f83533b Provide a correct decoder hook for Thumb2 shifted registers. Found by randomized testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138292 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:10:16 +00:00
Jim Grosbach
7260c6a4ea Thumb assemmbly parsing diagnostic improvements for LDM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138287 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:01:07 +00:00
Benjamin Kramer
3c1fece071 X86: Add some operand types required to identify calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138285 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 22:55:32 +00:00
Jim Grosbach
5e8701002b Temporarilly mark tMUL as not commutable. 
It's not playing nicely in the coalescer with the tied operand. Disable
commutability for now while we figure out the deeper fix.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138278 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 22:00:18 +00:00
Owen Anderson
838130e3b9 Provide operand encoding information for half-precision VCVT instructions. Found by randomized testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138273 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 21:34:00 +00:00
Bruno Cardoso Lopes
2ac8111159 Add support for breaking 256-bit int VETCC into two 128-bit ones, 
avoding scalarization of the compare. Reduces code from 59 to 6
instructions. Fix PR10712.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138271 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 20:31:04 +00:00
Bruno Cardoso Lopes
bde9f1b302 Add 128-bit AVX codegen for PCMP* family of integer instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138270 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 20:31:00 +00:00
Owen Anderson
357ec6850b Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138269 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 20:27:12 +00:00
Jim Grosbach
11e03e7c2d Tighten up ARM reglist validation a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138258 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 18:50:36 +00:00
Owen Anderson
2cbf210450 Fix another batch of VLD/VST decoding crashes discovered by randomized testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138255 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 18:42:13 +00:00
Owen Anderson
f1c8e3e70e Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138251 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 18:22:06 +00:00
Jim Grosbach
a33b31be45 Clean up predicates on ARM target instruction aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138249 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 18:04:24 +00:00
Owen Anderson
b113ec55e8 Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138246 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 17:56:58 +00:00
Benjamin Kramer
0dac82d92e Cast through intptr_t, ISO C++ requires it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138186 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-20 02:22:42 +00:00
Chad Rosier
fea95c6bad Remove the VMOVQQ pseudo instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138177 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-20 00:52:40 +00:00
Chad Rosier
bdc18572be Remove VMOVQQQQ pseudo instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138174 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-20 00:40:14 +00:00
Jakob Stoklund Olesen
ac3656ed7a Add <imp-def> operands to QQ and QQQQ stack loads. 
This pleases the register scavenger and brings
test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll a little closer to
working with -verify-machineinstrs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138164 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-20 00:17:45 +00:00
Chad Rosier
e5038e191d VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg. 
Therefore, rather then generate a pseudo instruction, which is later expanded,
generate the necessary instructions in place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138163 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-20 00:17:25 +00:00
Jim Grosbach
0780b6303b Thumb parsing and encoding support for NOP. 
The irony is not lost that this is not a completely trivial patchset.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138143 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 23:24:36 +00:00
Akira Hatanaka
854a7db117 Fix bug in function IsShiftedMask. Remove parameter SizeInBits, which is not 
needed for Mips32.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138132 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 22:59:00 +00:00
Jim Grosbach
2c3f70e5d4 Thumb assembly parsing and encoding for NEG. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138131 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 22:51:03 +00:00
Jim Grosbach
3a244bd8b3 Fix NEG alias 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138125 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 22:30:58 +00:00
Jim Grosbach
7a01069420 Be more lenient on tied operand matching for MUL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138124 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 22:30:46 +00:00
Bruno Cardoso Lopes
0c9acfcb50 Re-write part of VEX encoding logic, to be more easy to read! Also fix 
a bug and add a testcase!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138123 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 22:27:29 +00:00
Jim Grosbach
7a32fa1c78 Update tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138116 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 22:19:48 +00:00
Jim Grosbach
88ae2bc6d5 Thumb assembly parsing and encoding for MUL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138108 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 22:07:46 +00:00
Jim Grosbach
4ec6e888ec Thumb assembly parsing and encoding for MOV. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138076 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 20:46:54 +00:00
Jim Grosbach
73a1c2cea1 Tidy up. Tab character. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138072 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 20:30:19 +00:00
Jim Grosbach
b86e2dbf61 Tab characters. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138066 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 19:41:46 +00:00
Jim Grosbach
1b7b68f087 Thumb assembly parsing and encoding for LSL(immediate). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138063 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 19:29:25 +00:00
Jim Grosbach
05b0156734 Thumb assembly parsing and encoding for LDRSB and LDRSH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138061 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 19:17:58 +00:00
Jim Grosbach
38466309d5 Thumb assembly parsing and encoding for LDRH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138060 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 18:55:51 +00:00
Jim Grosbach
48ff5ffe9e Thumb assembly parsing and encoding for LDRB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138059 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 18:49:59 +00:00
Jim Grosbach
67b95f902a Thumb assembly parsing and encoding for LDR(literal). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138052 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 18:20:48 +00:00
Jim Grosbach
ecd8589683 Thumb assembly parsing and encoding for LDR(immediate) form T2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138050 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 18:13:48 +00:00
Jim Grosbach
2f7232efd5 Use helper function to check for low registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138048 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 17:57:22 +00:00
Jim Grosbach
60f91a3d95 Thumb assembly parsing and encoding for LDR(immediate) form T1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138047 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 17:55:24 +00:00
Jim Grosbach
c6d7c653c9 Add explanatory comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138042 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 16:52:32 +00:00
Kalle Raiskila
67a9b1fcc7 Have SPU backend use the external TCE scheduler, if the library is loaded as a 
module.

Patch by Pekka Jääskeläinen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138037 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 10:50:24 +00:00
Craig Topper
e004d941ec Add TB encoding to VEX versions of SSE fp logical operations to fix disassembler 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138034 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 05:28:50 +00:00
Bruno Cardoso Lopes
863e0f25b7 Fix PR10677. Initial patch and idea by Peter Cooper but I've changed the 
implementation!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138029 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 02:23:56 +00:00
Benjamin Kramer
a67f14bf53 Make a bunch of symbols private. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138025 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 01:42:18 +00:00
Bruno Cardoso Lopes
df01610d6f Re-encoded 128-bit AVX versions of SQRT, RSQRT, RCP have 3 operands 
instead of 2. They were already defined this way in their regular
version, but not for the intrinsics versions (*_Int), and that would work
for assembly emission but not for object code, since a MachineOperand
would be missing. This commit fix PR10697.

Also removed the {VSQRT,VRSQRT,VRCP}r_Int forms and match the intrinsic
via INSERT_SUBREG+EXTRACT_SUBREG patterns. The same couldn't be done for
memory versions because sse_load_f32/sse_load_f64 operand need special
handling and don't work like regular "addr" operands.

There are right now 114 "*_Int" and 98 "Int_*" forms! I'm slowly
removing them as I step through, but hope we can get rid of these
someday, they are really annoying :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138012 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 23:59:21 +00:00
Akira Hatanaka
5ac8547a41 Use subword loads instead of a 4-byte load when the size of a structure (or a 
piece of it) that is being passed by value is smaller than a word.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138007 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 23:39:37 +00:00
Owen Anderson
78affc9ea1 STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate. 
Found by randomized testing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138003 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 22:47:44 +00:00
Owen Anderson
846dd95f87 Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138000 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 22:31:17 +00:00
Owen Anderson
1dd56f05e1 Remember to fill in some operands so we can print _something_ coherent even when decoding the CPS instruction soft-fails. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137997 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 22:15:25 +00:00
Owen Anderson
14090bf263 Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions. 
Fixes a large class of disassembler crashes found by randomized testing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137995 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 22:11:02 +00:00
Jim Grosbach
93b3eff623 Thumb assembly parsing and encoding for LDM instruction. 
Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137986 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 21:50:53 +00:00
Akira Hatanaka
dbe9a31683 Make IsShiftedMask a static function rather than defining it in an 
anonymous namespace.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137975 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 20:07:42 +00:00
Jim Grosbach
0d1511c022 Thumb assembly parsing and encoding for CMP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137963 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 18:08:29 +00:00
Jim Grosbach
11cca7a2ea Thumb instructions CBZ and CBNZ are Thumb2, not THumb1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137956 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 17:51:36 +00:00
Jim Grosbach
90b5a08e1f ARM Thumb blx instruction fixup has same data range as bl. 
These fixups are handled poorly in general, and should have a single
contiguous range of bits per fixup type, but that's not how they're
currently organized, so for now in complex ones like for blx, we just tell the
emitter it's OK for the fixup to munge any bit it wants.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137947 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 16:57:50 +00:00
Jim Grosbach
5f687decc8 80 columns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137946 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 16:50:45 +00:00
Bruno Cardoso Lopes
44d12eb998 Clenup and fix encoding for Mips ins and ext instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137943 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 16:30:49 +00:00
Jim Grosbach
3ce23d3d87 Add missing 'break'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137941 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 16:08:39 +00:00
Richard Osborne
c4dcf323cc Add intrinsics for SETEV, GETED, GETET. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137938 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 13:00:48 +00:00
Bruno Cardoso Lopes
24b90e2287 Cleanup vector logical ops in AVX and add use int versions for simple 
v2i64

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137919 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 02:11:34 +00:00
Jim Grosbach
2f815c0b50 Remove extraneous newline from operand print method. PR10569. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137900 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 23:23:07 +00:00
Jim Grosbach
421993f428 Clean up patterns for Thumb1 system instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137897 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 23:08:57 +00:00
Akira Hatanaka
667645f814 Changed definition of EXT and INS per Bruno's comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137892 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 22:59:46 +00:00
Jim Grosbach
395b453bed Thumb assembly parsing and encoding for B. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137891 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 22:57:40 +00:00
Jim Grosbach
00f5d98205 Thumb assembly parsing and encoding for ASR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137889 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 22:49:09 +00:00
Bruno Cardoso Lopes
0dd80b0d69 Fix PR10688. Add support for spliting 256-bit vector shifts when the 
shift amount is variable

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137885 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 22:12:20 +00:00
Jim Grosbach
c40578250d Tidy up. 80 columns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137881 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 21:58:18 +00:00
Jim Grosbach
70939ee141 ARM clean up the imm_sr operand class representation. 
Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137879 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 21:51:27 +00:00
Jim Grosbach
ef3bf64bf8 Fix predicate for imm1_32 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137865 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 21:01:11 +00:00
Jim Grosbach
5a1cd045cd Thumb assembly parsing and encoding for ADR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137864 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 20:37:40 +00:00
Jim Grosbach
4372ca6fe4 80 columns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137857 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 19:55:51 +00:00
Jim Grosbach
8884148b8e Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137856 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 19:53:53 +00:00
Akira Hatanaka
511961a44c Add support for half-word unaligned loads and stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137848 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 18:49:18 +00:00
Owen Anderson
0aa38ab1fb Be more careful in the Thumb decoder hooks to avoid walking off the end of the OpInfo array. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137838 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 18:14:48 +00:00
Akira Hatanaka
77b85b6474 Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137831 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 17:45:08 +00:00
Owen Anderson
83e3f67fb6 Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment. 
Patch by James Molloy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137830 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 17:44:15 +00:00
Bruno Cardoso Lopes
0e6d230abd Introduce matching patterns for vbroadcast AVX instruction. The idea is to 
match splats in the form (splat (scalar_to_vector (load ...))) whenever
the load can be folded. All the logic and instruction emission is
working but because of PR8156, there are no ways to match loads, cause
they can never be folded for splats. Thus, the tests are XFAILed, but
I've tested and exercised all the logic using a relaxed version for
checking the foldable loads, as if the bug was already fixed. This
should work out of the box once PR8156 gets fixed since MayFoldLoad will
work as expected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137810 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 02:29:19 +00:00
Bruno Cardoso Lopes
8a5b262e80 Update comments about vector splat handling in x86 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137808 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 02:29:13 +00:00
Bruno Cardoso Lopes
fc0a702128 Now that we have a canonical way to handle 256-bit splats: 
vinsertf128 $1 + vpermilps $0, remove the old code that used to first
do the splat in a 128-bit vector and then insert it into a larger one.
This is better because the handling code gets simpler and also makes a
better room for the upcoming vbroadcast!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137807 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 02:29:10 +00:00
Akira Hatanaka
bb15e117d3 Add support for ext and ins. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137804 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 02:05:42 +00:00
Jim Grosbach
89e2aa6afd Thumb ADD(immediate) parsing support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137788 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 23:57:34 +00:00
Owen Anderson
16280308ac Separate out Thumb1 instructions that need an S bit operand from those that do not, for the purposes of decoding them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137787 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 23:45:44 +00:00
Jim Grosbach
194bd89829 Thumb parsing diagnostics for low-reg requirements on ADD and MOV. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137779 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 22:20:01 +00:00
Jim Grosbach
00c9a51888 Add missing exit for 'case'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137774 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 21:42:31 +00:00
Jim Grosbach
3912b73c74 Thumb assembly parsing and encoding for ADD(register) instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137759 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 21:34:08 +00:00
Jim Grosbach
d54b4e612a Move some logic into a helper function and expand the commentary. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137756 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 21:12:37 +00:00
Jim Grosbach
47a0d52b69 ARM thumb assembly parsing for arithmetic flag setting instructions. 
Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137746 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 20:45:50 +00:00
Bruno Cardoso Lopes
3b86598cfa Instead of always leaving the work to the generic legalizer when 
there is no support for native 256-bit shuffles, be more smart in some
cases, for example, when you can extract specific 128-bit parts and use
regular 128-bit shuffles for them. Example:

For this shuffle:
  shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32>
                <i32 1, i32 0, i32 7, i32 6>

This was expanded to:
  vextractf128  $1, %ymm1, %xmm2
  vpextrq $0, %xmm2, %rax
  vmovd %rax, %xmm1
  vpextrq $1, %xmm2, %rax
  vmovd %rax, %xmm2
  vpunpcklqdq %xmm1, %xmm2, %xmm1
  vpextrq $0, %xmm0, %rax
  vmovd %rax, %xmm2
  vpextrq $1, %xmm0, %rax
  vmovd %rax, %xmm0
  vpunpcklqdq %xmm2, %xmm0, %xmm0
  vinsertf128 $1, %xmm1, %ymm0, %ymm0
  ret

Now we get:
  vshufpd $1, %xmm0, %xmm0, %xmm0
  vextractf128  $1, %ymm1, %xmm1
  vshufpd $1, %xmm1, %xmm1, %xmm1
  vinsertf128 $1, %xmm1, %ymm0, %ymm0

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137733 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 18:21:54 +00:00
Jim Grosbach
d0d3f7e01f ARM .align NOP padding uses different encoding pre-ARMv6. 
Patch by Kristof Beyls and James Malloy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137723 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 17:06:20 +00:00
Akira Hatanaka
614051a1c5 Fix handling of double precision loads and stores when Mips1 is targeted. 
Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This 
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.

Without the changes made in this patch, llc produces code that has the same 
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137711 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 03:51:51 +00:00
Akira Hatanaka
8957481e6a Define function MipsMCInstLower::LowerOperand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137707 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 02:21:03 +00:00
Akira Hatanaka
78d1b11aa5 Add parameter Offset to MipsMCInstLower::LowerSymbolOperand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137706 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 02:15:03 +00:00