Michael J. Spencer
c0c8df3cea
Fix Whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116149 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-09 11:00:50 +00:00
Chris Lattner
0d9a0865c6
add jit support for the new psuedo instructions I added for
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the add/or xform. The JIT isn't mcized yet, boo.
This fixes Olden/voronoi, bh and a ton of other stuff that
uses the jit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116125 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 23:59:27 +00:00
Chris Lattner
8dae787db4
machine a mutable machineinstr down into emitInstruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116124 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 23:54:01 +00:00
Cameron Esfahani
ec37b00b17
Recommit 116056, now with the missing file...
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116083 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 19:24:18 +00:00
Andrew Trick
5900201aa7
reverting 116056: win64_params.ll may need to be conditionalized?
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116063 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 17:22:42 +00:00
Cameron Esfahani
d7b8d91d4a
Small patch to restore home register stack space allocation for the Win64 case. Add test case. This code eventually needs to be tighter, since it's always allocating it, even in leaf routines.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116056 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 10:31:30 +00:00
Chris Lattner
d043529b34
fix a subtle bug I introduced in my refactoring, where we stopped preferring
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the i8 versions of instructions in some cases. In test6, we started
generating:
cmpq $0, -8(%rsp) ## encoding: [0x48,0x81,0x7c,0x24,0xf8,0x00,0x00,0x00,0x00]
## <MCInst #478 CMP64mi32
## <MCOperand Reg:114>
## <MCOperand Imm:1>
## <MCOperand Reg:0>
## <MCOperand Imm:-8>
## <MCOperand Reg:0>
## <MCOperand Imm:0>>
instead of:
cmpq $0, -8(%rsp) ## encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
## <MCInst #479 CMP64mi8
## <MCOperand Reg:114>
## <MCOperand Imm:1>
## <MCOperand Reg:0>
## <MCOperand Imm:-8>
## <MCOperand Reg:0>
## <MCOperand Imm:0>>
Fix this and add some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116053 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 05:12:14 +00:00
Chris Lattner
15df55d8c2
reapply: Use the new TB_NOT_REVERSABLE flag instead of special
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reapply: reimplement the second half of the or/add optimization. We should now
with no changes. Turns out that one missing "Defs = [EFLAGS]" can upset things
a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116040 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 03:57:25 +00:00
Chris Lattner
99ae6659da
reapply the patch reverted in r116033:
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"Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'"
With a critical fix: the add pseudos clobber EFLAGS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116039 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 03:54:52 +00:00
Daniel Dunbar
b88b00ba2b
Revert "Reimplement (part of) the or -> add optimization. Matching 'or' into
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'add'", which seems to have broken just about everything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116033 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 02:07:32 +00:00
Daniel Dunbar
b38109fc2d
Revert "Use the new TB_NOT_REVERSABLE flag instead of special ", which depends
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on r116007, which I am about to revert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116032 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 02:07:29 +00:00
Daniel Dunbar
32f0cdba30
Revert "reimplement the second half of the or/add optimization. We should now",
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which depends on r116007, which I am about to revert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116031 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 02:07:26 +00:00
Chris Lattner
cd3167b281
reimplement the second half of the or/add optimization. We should now
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only end up emitting LEA instead of OR. If we aren't able to promote
something into an LEA, we should never be emitting it as an ADD.
Add some testcases that we emit "or" in cases where we used to produce
an "add".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116026 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 01:05:10 +00:00
Chris Lattner
05e27c5786
Use the new TB_NOT_REVERSABLE flag instead of special
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casing FsMOVAPDrr/FsMOVAPSrr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116016 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 00:03:02 +00:00
Chris Lattner
a228376185
simplify some map operations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116014 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 23:57:02 +00:00
Chris Lattner
122e2ea043
Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'
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is general goodness because it allows ORs to be converted to LEA to avoid
inserting copies. However, this is bad because it makes the generated .s
file less obvious and gives valgrind heartburn (tons of false positives in
bitfield code).
While the general fix should be in valgrind, we can at least try to avoid
emitting ADD instructions that *don't* get promoted to LEA. This is more
work because it requires introducing pseudo instructions to represents
"add that knows the bits are disjoint", but hey, people really love valgrind.
This fixes this testcase:
https://bugs.kde.org/show_bug.cgi?id=242137#c20
the add r/i cases are coming next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116007 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 23:36:18 +00:00
Chris Lattner
45a1cb26a3
Reduce casting in various tables by defining the table
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with the right types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116001 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 23:08:41 +00:00
Chris Lattner
afcd543a55
simplify code: don't build up vector only to assert it is empty.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115997 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 22:26:19 +00:00
Chris Lattner
9649e9acdd
convert test to use the existing classes that the multipatterns
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use. Since TEST is completely different than all other binops,
don't define a multipattern for it.
This completes factorization of binops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115982 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 21:31:03 +00:00
Chris Lattner
00e94baf4e
convert cmp to use a multipattern
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115978 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 20:56:25 +00:00
Evan Cheng
835580fc3a
Canonicalize X86ISD::MOVDDUP nodes to v2f64 to make sure all cases match. Also eliminate unneeded isel patterns. rdar://8520311
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115977 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 20:50:20 +00:00
Chris Lattner
9e94000c16
reduce redundancy between pattern copies.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115968 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 20:14:23 +00:00
Chris Lattner
a2b8b16c7e
the opcode for BinOpMI/BinOpMI8 is always the same, remove the argument.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115967 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 20:06:24 +00:00
Chris Lattner
a3208e122c
convert adc/sbb to a multipattern. Because the adde/sube nodes
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are not defined as returning EFLAGS (like add_flag and friends),
the entire multipattern and several of the subclasses need to be
cloned.
This could be handled through better instantiation support in tblgen,
but it isn't meta enough.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115964 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 20:01:55 +00:00
Jakob Stoklund Olesen
8456c4f957
Fix obvious mistake pointed out by Michael Spencer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115952 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 18:47:10 +00:00
Chris Lattner
b046810fe4
add support for isConvertibleToThreeAddress to ArithBinOpEFLAGS,
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allowing us to convert ADD over. deletes 160 lines of .td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115897 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 01:37:01 +00:00
Chris Lattner
521ff704a1
Fix a few issues in ArithBinOpEFLAGS that made it specific to and.
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Start using ArithBinOpEFLAGS for OR, XOR, and SUB.
This removes 500 lines from the .td file. Now AND/OR/XOR/SUB are all
defined exactly the same way instead of being close relatives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115896 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 01:26:27 +00:00
Chris Lattner
4b181c87de
Convert 'and' to single instance of a multipattern
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which instantiates the 34 versions of and all in one
swoop. The BaseOpc/BaseOpc2/BaseOpc4 stuff should not
be required, but tblgen's feeble brain explodes when I
use Or4<BaseOpc>.V in the multipattern.
No change in the generated .inc files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115893 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 01:10:20 +00:00
Chris Lattner
511c686f76
add a new BinOpAI class to represent the immediate form that directly acts on EAX.
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This does change the generated .inc files to include the implicit use/def of eax.
Since these instructions are only generated by the assembler and disassembler it
doesn't actually matter though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115885 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 00:43:39 +00:00
Chris Lattner
1bb9adae4c
add a bunch of classes for other common patterns.
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As usual, no change in generated .inc files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115882 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 00:35:28 +00:00
Chris Lattner
2b8d30d080
Define a new BinOpRI8 class and use it to define the imm8 versions of and.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115880 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 00:12:45 +00:00
Jakob Stoklund Olesen
635127a8c6
Constrain the offset register to a *_NOSP register class when inserting LEA
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instructions.
This unbreaks the machine code verifier and fixes PR8317.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 00:07:26 +00:00
Chris Lattner
78266110bf
add the pattern operator to match to X86TypeInfo, use this to
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convert AND64ri32 to use BinOpRI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115878 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 00:01:39 +00:00
Jakob Stoklund Olesen
8f42a19fb0
Properly handle GR32_NOSP in X86RegisterInfo::getMatchingSuperRegClass.
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This function looks like it is about ready to be generated by TebleGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115876 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 23:56:46 +00:00
Chris Lattner
b2fc409827
enhance X86TypeInfo to include information about the encoding and
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operand kind for immediates. Use these to define a new BinOpRI
class and switch AND8/16/32ri over to it. AND64ri32 needs some
more refactoring before it can make the switcheroo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115752 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 05:55:42 +00:00
Chris Lattner
3ab0b59aad
add a class for _REV nodes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115748 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 05:35:22 +00:00
Chris Lattner
08808f9733
sink more intelligence into the ITy base class. Now it knows
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that i8 operations are even and i16,i32,i64 operations have a
low opcode bit set (they are odd).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 05:28:38 +00:00
Chris Lattner
44402c0701
refactor things a bit, now the REX_W and OpSize prefix bytes are inferred from the type info.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115745 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 05:20:57 +00:00
Chris Lattner
da4b361726
with tblgen suitably extended, we can now get the load node from typeinfo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115744 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 04:58:43 +00:00
Chris Lattner
417b54354b
lets go all meta and define new X86 type wrappers that declare the associated
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gunk that goes along with an MVT (e.g. reg class, preferred load operation,
memory operand)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115727 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 00:45:24 +00:00
Chris Lattner
ff27af206e
introduce a new BinOpRM class and use it to factor AND*rm. This points out
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that I need a heavier handed approach to get ultimate factorization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115726 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 00:30:49 +00:00
Chris Lattner
c7252ce743
remove the !nameconcat tblgen feature. It "shorthand" and only used in 4 places
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where !cast is just as short.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115722 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 00:19:21 +00:00
Chris Lattner
8d978a75b4
allow !strconcat to take more than two operands to eliminate
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!strconcat(!strconcat(!strconcat(!strconcat
Simplify some x86 td files to use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115719 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 23:58:18 +00:00
Chris Lattner
20b2499a7c
associate the instruction suffix letter with the integer gpr
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register class, and use this to simplify use of BinOpRR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115716 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 23:43:04 +00:00
Chris Lattner
e00047c906
introduce a new BinOpRR class, and convert 4 and instructions to use it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115715 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 23:32:05 +00:00
Chris Lattner
6dbbff9172
Move cmov pseudo instructions to InstrCompiler,
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convert all the rest of the cmovs to the multiclass,
with good results:
X86InstrCMovSetCC.td | 598 +--------------------------------------------------
X86InstrCompiler.td | 61 +++++
2 files changed, 77 insertions(+), 582 deletions(-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115707 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 23:09:10 +00:00
Chris Lattner
25cbf504fe
Use #NAME# to have the CMOV multiclass define things with the same names as before
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(e.g. CMOVBE16rr instead of CMOVBErr16).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115705 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 23:00:14 +00:00
Chris Lattner
df72eaef3d
enhance tblgen to support anonymous defm's, use this to
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simplify the X86 CMOVmr's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115702 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 22:51:56 +00:00
Chris Lattner
286997c745
convert cmov mr patterns to use a multipattern. Death to redundancy
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and verbosity
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115701 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 22:42:54 +00:00
Chris Lattner
d350e4757e
switch CMOVBE to the multipattern:
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21 insertions(+), 53 deletions(-)
Moar change coming before I switch the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115697 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 22:23:58 +00:00
Chris Lattner
e583c892d8
fix a bug I introduced in r115669, which ended up with MOV64mr_TC
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not getting marked as mayStore. This fixes llvm-gcc bootstrap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115693 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 22:16:48 +00:00
Chris Lattner
b484213d1b
add a multiclass for cmov's, but don't start using it yet.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115692 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 22:01:02 +00:00
Chris Lattner
d244699067
use a multipattern to define setcc instructions:
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X86InstrCMovSetCC.td | 200 ++++++---------------------------------------------
1 file changed, 27 insertions(+), 173 deletions(-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115689 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 21:34:29 +00:00
Chris Lattner
2c383d8c4d
move SETB pseudos into the same place in InstrCompiler.td
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115686 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 21:18:04 +00:00
Chris Lattner
508fc4708b
Replace a gross hack (the MOV64ri_alt instruction) with a slightly less
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gross hack (having the asmmatcher handle the alias).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 21:09:45 +00:00
Chris Lattner
748a2fe917
distribute the rest of the contents of X86Instr64bit.td out to
...
the right places. X86Instr64bit.td now dies, long live x86-64!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115669 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 20:49:15 +00:00
Chris Lattner
10701928ff
move the rest of the simple 64-bit arithmetic into InstrArithmetic.td
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115663 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 20:35:37 +00:00
Chris Lattner
5bbbcdb1d8
continue moving 64-bit stuff into X86InstrArithmetic.td
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115660 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 20:23:31 +00:00
Chris Lattner
64227940e7
move 64-bit add and adc to InstrArithmetic.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115632 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 16:59:08 +00:00
Chris Lattner
c7d4655b57
rewrote two addr constraints so that they are only set, not set and then nestedly cleared.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115631 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 16:52:25 +00:00
Chris Lattner
6367cfc470
split the 32-bit integer arithmetic instructions out to their own file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115627 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 16:39:12 +00:00
Chris Lattner
5249ff34fb
integrate the 64-bit shifts into X86InstrShiftRotate.td. Enough for tonight.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115608 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 07:13:35 +00:00
Chris Lattner
5f58e84af8
move 32-bit shift and rotates out to their own file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115607 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 07:00:12 +00:00
Chris Lattner
2c065e1c86
add new file
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115606 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 06:52:35 +00:00
Chris Lattner
8917cd3d67
move sign and zero extensions out to their own file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115605 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 06:52:26 +00:00
Chris Lattner
d8cc2722a4
move some instructions from Instr64Bit -> InstrInfo.
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bswap32 doesn't read eflags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115604 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 06:47:35 +00:00
Chris Lattner
5673e1d314
move CMOV_FR32 and friends to InstrCompiler, since they are
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pseudo instructions.
Move POPCNT to InstrSSE since they are SSE4 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115603 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 06:41:40 +00:00
Chris Lattner
41efbfaa66
move various pattern matching support goop out of X86Instr64Bit, to live
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with the 32-bit stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115602 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 06:37:31 +00:00
Chris Lattner
35649fc3dd
split conditional moves and setcc's out to their own file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115601 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 06:33:16 +00:00
Chris Lattner
d3f033d969
move string pseudo instructions to InstrCompiler consolidate 64-bit and 32-bit together.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115600 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 06:27:48 +00:00
Chris Lattner
010496c6a7
move the atomic pseudo instructions out to X86InstrCompiler.td
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115599 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 06:22:35 +00:00
Chris Lattner
8af88ef157
move more pseudo instructions out to X86InstrCompiler.td
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115598 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 06:10:16 +00:00
Chris Lattner
d071b83b5d
move VMX instructions out to their own file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115597 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 06:06:53 +00:00
Chris Lattner
87be16a9e1
continue moving stuff out to X86InstrSystem.td. Move
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control flow stuff out to X86InstrControl.td. Move
some compiler pseudo instructions and Pat<> patterns
out to X86InstrCompiler.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115596 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 06:04:14 +00:00
Chris Lattner
434c7cb8a1
refactor .td files a bit, moving system instructions out to X86InstrSystem.td
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115591 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 05:32:15 +00:00
Bill Wendling
6cf6c79e82
The pshufw instruction came about in MMX2 when SSE was introduced. Don't place
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it in with the SSSE3 instructions.
Steward! Could you place this chair by the aft sun deck? I'm trying to get away
from the Astors. They are such boors!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115552 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-04 20:24:01 +00:00
Anton Korobeynikov
e7beda183d
va_args support for Win64.
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Patch by Cameron!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115480 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-03 22:52:07 +00:00
Anton Korobeynikov
6af61ca789
Properly emit stack probe on win64 (for non-mingw targets).
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Based on the patch by Cameron Esfahani!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115479 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-03 22:02:38 +00:00
Eli Friedman
d32d85e5ba
Add 3DNowA instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115477 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-03 20:23:13 +00:00
Chris Lattner
591d76ea5a
the immediate field of pshufw is actually an 8-bit field, not a 8-bit field that is sign extended. This fixes PR8288
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115473 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-03 19:09:13 +00:00
Rafael Espindola
0febc4657b
Jim Asked us to move DataLayout on ARM back to the most specialized classes. Do
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so and also change X86 for consistency.
Investigating if this can be improved a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115469 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-03 18:59:45 +00:00
Chris Lattner
cc07d7116a
add support for the prefetch/prefetchw instructions, move femms into
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the right file. The assembler supports all the 3dnow instructions now,
but not the "3dnowa" ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115468 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-03 18:42:30 +00:00
Chris Lattner
f132fa0e74
what the heck, add support for the rest of the 3dNow! binary operations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115467 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-03 18:24:18 +00:00
Chris Lattner
548abfcbd6
Implement support for the bizarre 3DNow! encoding (which is unlike anything
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else in X86), and add support for pavgusb. This is apparently the
only instruction (other than movsx) that is preventing ffmpeg from building
with clang.
If someone else is interested in banging out the rest of the 3DNow!
instructions, it should be quite easy now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115466 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-03 18:08:05 +00:00
Chris Lattner
7330d97069
stub out a header to put 3dNow! instructions into.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115429 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-02 23:06:23 +00:00
Chris Lattner
d476914607
fix a regression introduced in r115243, in which the instruction
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backing int_x86_ssse3_pshuf_w got removed. This caused PR8280.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115422 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-02 21:32:15 +00:00
Jim Grosbach
7ac1609a3b
Rename the AsmPrinter directory to InstPrinter for those targets that have
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been MC-ized for assembly printing. MSP430 is mostly so, but still has the
asm printer and lowering code in the printer subdir for the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 22:39:28 +00:00
Benjamin Kramer
b0f96facd6
Delete token *after* reading from it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115311 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 12:25:27 +00:00
Dale Johannesen
0488fb649a
Massive rewrite of MMX:
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The x86_mmx type is used for MMX intrinsics, parameters and
return values where these use MMX registers, and is also
supported in load, store, and bitcast.
Only the above operations generate MMX instructions, and optimizations
do not operate on or produce MMX intrinsics.
MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into
smaller pieces. Optimizations may occur on these forms and the
result casted back to x86_mmx, provided the result feeds into a
previous existing x86_mmx operation.
The point of all this is prevent optimizations from introducing
MMX operations, which is unsafe due to the EMMS problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Jim Grosbach
ddcf859851
Clean up asm writer usage for x86 and msp430 to flag that the writer should
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use MC instructions in the printInstruction() method via the tablegen flag
for it rather than a #define prior to including the autogenerated bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115238 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:40:25 +00:00
Chris Lattner
905f2e0669
preemptively add the rest of the non-n fpstack instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115168 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 17:11:29 +00:00
Chris Lattner
9ee4aed3b6
implement support for finit, PR8258
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115156 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 16:42:53 +00:00
Chris Lattner
0bb83a84d4
add support for fstcw, PR8259
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115154 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 16:39:29 +00:00
Kevin Enderby
8ebf66236e
Adds getPointerSize() to the AsmBackend which will be needed by the final patch
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for the dwarf .loc support to emit dwarf line number tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115153 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 16:38:07 +00:00
Rafael Espindola
a8c02c3bdd
Correctly produce R_X86_64_32 or R_X86_64_32S.
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With this patch in
movq $foo, foo(%rip)
foo:
.long foo
We produce a R_X86_64_32S for the first relocation and R_X86_64_32 for the
second one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115134 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 03:11:42 +00:00
Eric Christopher
e487b017e9
Noticed by inspection when looking for other cmov bits.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115100 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 23:00:29 +00:00
Nick Lewycky
8892b033e4
Add parens to fix GCC warning:
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lib/Target/X86/X86MCCodeEmitter.cpp: 190: error: suggest parentheses around '&&' within '||'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 18:56:57 +00:00
Chris Lattner
a25f933396
implement rdar://8491845 - Gas supports commuted forms of non-commutable instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115061 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 18:39:16 +00:00
Chris Lattner
6f42027263
fix rdar://8490728 - llvm-mc rejects gpr64 form of 'movmskpd'
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115029 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 05:05:03 +00:00
Chris Lattner
f3654db458
add assembler support for the cvtsd2sil/cvtsd2siq mnemonics, rdar://8456382
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115027 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 04:55:40 +00:00
Chris Lattner
78a194693b
make the x86 mccode emitter emit the 0x67 and 0x66 prefix bytes in the same
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order as cctools for diffability.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115022 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 03:43:43 +00:00
Chris Lattner
8a5072903e
implement support for 32-bit address operands in 64-bit mode, which
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are defined to emit the 0x67 prefix byte. rdar://8482675
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115021 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 03:33:25 +00:00
Chris Lattner
b2ef4c1235
add basic avx support to the disassembler, also teach it about ssmem/sdmem
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operands.
With this done, we can remove the _Int suffixes from the round instructions
without the disassembler blowing up. This allows the assembler to support
them, implementing rdar://8456376 - llvm-mc rejects 'roundss'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115019 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 02:57:56 +00:00
Chris Lattner
bf6018ac5a
add asmparser support for cvttpd2dq by removing some Int_ prefixes.
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Clean up cvttps2dq by removing some redundant implementations of the
same instruction. rdar://8456382
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115018 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 02:36:32 +00:00
Chris Lattner
0c04e4f58f
implement rdar://8456382 - cvtsd2si support, by removing some Int_ prefixes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115017 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 02:24:57 +00:00
Chris Lattner
7c51a3172c
implement rdar://8456378 and PR7557 - support for the fstsw,
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an instruction that requires a WHOLE NEW wonderful kind of alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115015 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 01:50:45 +00:00
Chris Lattner
7036f8be4d
change the protocol TargetAsmPArser::MatchInstruction method to take an
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MCStreamer to emit into instead of an MCInst to fill in. This allows the
matcher extra flexibility and is more convenient.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115014 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 01:42:58 +00:00
Dale Johannesen
a8bd1ff8c5
MMX parameters aren't handled here yet.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114844 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 17:29:47 +00:00
Chris Lattner
2956462742
yet more aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114822 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 07:24:57 +00:00
Chris Lattner
b1162fc05e
add a couple more aliases, rdar://8456378
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114821 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 07:21:41 +00:00
Chris Lattner
df967d6137
fix rdar://8470918 - llvm-mc can't assemble smovl
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114819 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 07:11:53 +00:00
Chris Lattner
cb296ec0b6
Fix rdar://8468087 - llvm-mc commutes fmul (and friend) operands.
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My previous fix for rdar://8456371 should only apply to fmulp/faddp,
not to fmul/fadd. Instruction set orthogonality is overrated or
something.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114818 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 07:08:21 +00:00
Chris Lattner
80945784f9
improve indentation
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114815 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 06:34:01 +00:00
Eric Christopher
722d315ac9
This code should never fire on non-darwin subtargets.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114811 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 06:01:51 +00:00
Chris Lattner
fd8fddd830
implement support for 'clr' alias. This is part of rdar://8416805,
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but balrog was wanting it on irc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114809 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 04:23:03 +00:00
Rafael Espindola
73ffea47d2
Move ELF to HasReliableSymbolDifference=true. Also take the opportunity to put
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symbols defined in merge sections in independent atoms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114786 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-25 05:42:19 +00:00
Dale Johannesen
c451051157
We can't return SSE/MMX vectors if SSE is disabled.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114745 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-24 19:05:48 +00:00
Owen Anderson
f523e476c2
Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further
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reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114710 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 23:45:25 +00:00
Owen Anderson
71e416ac3a
Add isConditionalMove bits to X86 and ARM instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114703 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 22:57:01 +00:00
Cameron Esfahani
4af1eaee70
Fix PR8201: Update the code to call via X86::CALL64pcrel32 in the 64-bit case.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114597 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 22:35:21 +00:00
Eric Christopher
56a8b817b1
Temporarily work around new address lowering while I figure out what
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needs to happen for darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114577 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 20:42:08 +00:00
Bob Wilson
eafca4e2b2
Attempt to fix llvm-gcc build. It was crashing when building gcov.o for an
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ARM cross-compiler on x86, because the MMO size did not match the type size.
This fixes the MMO size and also the size of the stack object to match the
type size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114554 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 17:35:14 +00:00
Chris Lattner
2c5291b563
fix rdar://8456371 - Handle commutable instructions written backward.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114536 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 06:26:39 +00:00
Chris Lattner
1eb1b68e3a
Fix an inconsistency in the x86 backend that led it to reject "calll foo" on
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x86-32: 32-bit calls were named "call" not "calll". 64-bit calls were correctly
named "callq", so this only impacted x86-32.
This fixes rdar://8456370 - llvm-mc rejects 'calll'
This also exposes that mingw/64 is generating a 32-bit call instead of a 64-bit call,
I will file a bugzilla.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114534 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 05:49:14 +00:00
Chris Lattner
bc57c6db4a
fix rdar://8456412 - llvm-mc crash in encoder on "mov %rdx, %cr8"
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Teaching the code generator about CR8-15, how to rex them up, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114533 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 05:29:50 +00:00
Chris Lattner
c2b942acf6
add the missing aliases for fp stack cmovs, rdar://8456391
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114531 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 04:56:20 +00:00
Chris Lattner
f93b90c5df
reimplement elf TLS support in terms of addressing modes, eliminating SegmentBaseAddress.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114529 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 04:39:11 +00:00
Chris Lattner
33d60d5e56
Fix rdar://8456364 - llvm-mc rejects '%CS'
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114528 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 04:11:10 +00:00
Chris Lattner
0c289c140e
fix rdar://8456389 - llvm-mc mismatch with 'as' on 'fstp'
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-This line, and those below, will be ignored--
M test/MC/AsmParser/X86/x86_instructions.s
M lib/Target/X86/AsmParser/X86AsmParser.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114527 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 04:04:03 +00:00
Chris Lattner
61129252e4
fix rdar://8456361 - llvm-mc rejects 'rep movsd'
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114526 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 03:50:32 +00:00
Chris Lattner
492a43e6f6
convert the last 4 X86ISD nodes that should have memoperands to have them.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114523 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 01:28:21 +00:00
Chris Lattner
2156b79c49
give X86ISD::FNSTCW16m a memoperand, since it touches memory. It only
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can access the stack due to how it is generated though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114522 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 01:11:26 +00:00
Chris Lattner
0729093cd7
give FP_TO_INT16_IN_MEM and friends a memoperand. They are only
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used with stack slots, but hey, lets be safe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114521 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 01:05:16 +00:00
Chris Lattner
8864155a35
give VZEXT_LOAD a memory operand, it now works with segment registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114515 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 00:34:38 +00:00
Chris Lattner
0b79cfee15
revert r114386 now that address modes work correctly, we get a nice
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call through gs-relative memory now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114510 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 00:11:31 +00:00
Chris Lattner
93c4a5bef7
give LCMPXCHG_DAG[8] a memory operand, allowing it to work with addrspace 256/257
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114508 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 23:59:42 +00:00
Chris Lattner
b86faa17a4
reimplement support for GS and FS relative address space matching
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by having X86DAGToDAGISel::SelectAddr get passed in the parent node
of the operand match (the load/store/atomic op) and having it get
the address space from that, instead of having special FS/GS addr
mode operations that require duplicating the entire instruction set
to support.
This makes FS and GS relative accesses *far* more predictable and
work much better. It also simplifies the X86 backend a bit, more
to come.
There is still a pending issue with nodes like ISD::PREFETCH and
X86ISD::FLD, which really should be MemSDNode's but aren't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114491 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 22:07:31 +00:00
Owen Anderson
bc146b0a4d
Reimplement r114460 in target-independent DAGCombine rather than target-dependent, by using
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the predicate to discover the number of sign bits. Enhance X86's target lowering to provide
a useful response to this query.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114473 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 20:42:50 +00:00
Chris Lattner
52a261b3c1
fix a long standing wart: all the ComplexPattern's were being
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passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel
like detangling). Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114471 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 20:31:19 +00:00
Chris Lattner
701cd62297
even though I'm about to rip it out, simplify the address mode stuff
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114468 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 19:41:58 +00:00
Chris Lattner
fc448ff89b
convert a couple more places to use the new getStore()
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114463 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 18:51:21 +00:00
Owen Anderson
c004eec71b
When adding the carry bit to another value on X86, exploit the fact that the carry-materialization
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(sbbl x, x) sets the registers to 0 or ~0. Combined with two's complement arithmetic, we can fold
the intermediate AND and the ADD into a single SUB.
This fixes <rdar://problem/8449754>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114460 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 18:41:19 +00:00
Chris Lattner
8026a9d3ee
eliminate some uses of the getStore overload.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114453 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 17:50:43 +00:00
Chris Lattner
3d6ccfba31
propagate MachinePointerInfo through various uses of the old
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SelectionDAG::getExtLoad overload, and eliminate it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114446 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 17:04:51 +00:00
Chris Lattner
d1c24ed81c
convert the targets off the non-MachinePointerInfo of getLoad.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114410 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 06:44:06 +00:00
Chris Lattner
e8639036b1
it's more elegant to put the "getConstantPool" and
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"getFixedStack" on the MachinePointerInfo class. While
this isn't the problem I'm setting out to solve, it is the
right way to eliminate PseudoSourceValue, so lets go with it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114406 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 06:22:23 +00:00
Chris Lattner
51abfe490b
update the X86 backend to use the MachinePointerInfo version of one
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of the getLoad methods. This fixes at least one bug where an incorrect
svoffset is passed in (a potential combiner-aa miscompile).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114404 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 06:02:19 +00:00
Chris Lattner
e54b482d1c
Fix a bug where the x86 backend would lower memcpy/memset of segment relative operations
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into non-segment-relative copies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114402 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 05:43:34 +00:00
Chris Lattner
e72f2027e9
reimplement memcpy/memmove/memset lowering to use MachinePointerInfo
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instead of srcvalue/offset pairs. This corrects SV info for mem
operations whose size is > 32-bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114401 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 05:40:29 +00:00
Chris Lattner
59db5496f4
convert targets to the new MF.getMachineMemOperand interface.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114391 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 04:39:43 +00:00