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51785 Commits

Author SHA1 Message Date
Jim Grosbach
9e7b42a40e ARM VQADD implied destination operand form aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146179 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 20:49:43 +00:00
Jim Grosbach
1c2c8a9389 ARM a few more VMUL implied destination operand form aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146177 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 20:42:35 +00:00
Akira Hatanaka
ca0747917d Implement 64-bit support for thread local storage handling. 
- Modify lowering of global TLS address nodes.
- Modify isel of ThreadPointer.
- Wrap target global TLS address nodes that are operands of loads with WrapperPIC. 
- Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be
  substituted with other existing nodes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146175 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 20:34:32 +00:00
Owen Anderson
4a4fdf3476 Teach SelectionDAG to match more calls to libm functions onto existing SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146171 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 19:32:14 +00:00
Jim Grosbach
40e2855547 ARM assembler support for register name aliases. 
rdar://10550084

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146170 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 19:27:38 +00:00
Evan Cheng
43d5d4ca1c Make MachineInstr instruction property queries more flexible. This change all 
clients to decide whether to look inside bundled instructions and whether
the query should return true if any / all bundled instructions have the
queried property.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146168 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 19:23:10 +00:00
Evan Cheng
2f435511e9 Many of the SSE patterns should not be selected when AVX is available. This led to the following code in X86Subtarget.cpp 
if (HasAVX)
    X86SSELevel = NoMMXSSE;

This is so patterns that are predicated on hasSSE3, etc. would not be selected when avx is available. Instead, the AVX variant is selected.
However, this breaks instructions which do not have AVX variants.

The right way to fix this is for the SSE but not-AVX patterns to predicate on something like hasSSE3() && !hasAVX().
Then we can take out the hack in X86Subtarget.cpp. Patterns which do not have AVX variants do not need to change.

However, we need to audit all the patterns before we make the change. This patch is workaround that fixes one specific case,
the prefetch instructions. rdar://10538297


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146163 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 19:00:42 +00:00
Daniel Dunbar
3b0887e291 Revert r146143, "Fix bug 9905: Failure in code selection for llvm intrinsics 
sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP,
FEXP2).", it is failing tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146157 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 17:32:18 +00:00
Jan Sjödin
703420f50e Src2 and src3 were accidentally swapped for the FMA4 rr patterns. Undo this and fix the encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146151 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 14:43:19 +00:00
Nadav Rotem
44bac7cd65 Fix a bug in the integer-promotion of bitcast operations on vector types. 
We must not issue a bitcast operation for integer-promotion of vector types, because the
location of the values in the vector may be different.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146150 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 13:10:01 +00:00
Stepan Dyatkovskiy
72590c9738 Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146143 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 07:55:03 +00:00
Hal Finkel
6772452644 MTCTR needs to be glued to BCTR so that CTR is not marked dead in MTCTR (another find by -verify-machineinstrs) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146137 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 04:36:44 +00:00
Pete Cooper
8f391d9330 Reverting r145899 as it breaks clang self-hosting 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146136 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 03:24:10 +00:00
Jim Grosbach
730fe6c1b6 ARM NEON two-operand aliases for VSHL(immediate). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146125 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 01:30:04 +00:00
Jakob Stoklund Olesen
e6f9e9d836 Drop the HasInlineAsm flag. 
It is not used any more. We are tracking inline assembly misalignments
directly through the BBInfo.Unalign and KnownBits fields.

A simple conservative size estimate is not good enough since it can
cause alignment padding to be underestimated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146124 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 01:22:39 +00:00
Jim Grosbach
ff4cbb4c9a ARM NEON two-operand aliases for VSHL(register). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146123 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 01:12:35 +00:00
Jakob Stoklund Olesen
99486be8ba Simplify offset verification. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146121 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 01:10:05 +00:00
Jim Grosbach
517a013a4f Fix copy/past-o. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146120 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 01:02:26 +00:00
Jim Grosbach
2b8810c500 ARM NEON two-operand aliases for VMUL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146119 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:59:47 +00:00
Jakob Stoklund Olesen
540c6d9d26 Don't include alignment padding in BBInfo.Size. 
Compute alignment padding before and after basic blocks dynamically.

Heed basic block alignment.

This simplifies bookkeeping because we don't have to constantly add and
remove padding from BBInfo.Size.  It also makes it possible to track the
extra known alignment bits we get after a tBR_JTr terminator and when
entering an aligned basic block.

This makes the ARMConstantIslandPass aware of aligned basic blocks.

It is tricky to model block alignment correctly when dealing with inline
assembly and tBR_JTr instructions that have variable size.  If inline
assembly turns out to be smaller than expected, that may cause following
alignment padding to be larger than expected.  This could cause constant
pool entries to move out of range.

To avoid that problem, we use the worst case alignment padding following
inline assembly. This may cause slightly suboptimal constant island
placement in aligned basic blocks following inline assembly.  Normal
functions should be unaffected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146118 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:55:02 +00:00
Jim Grosbach
8254f02231 ARM VFP support 'fmrs/fmsr' aliases for 'vldr' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146116 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:52:55 +00:00
Jim Grosbach
67ca1adf82 ARM VFP support 'flds/fldd' aliases for 'vldr' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146115 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:49:29 +00:00
Jim Grosbach
a44f2c4a28 ARM optional destination operand variants for VEXT instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146114 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:43:47 +00:00
Chad Rosier
667f826622 Fix 80-column. 
Simplify code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146112 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:38:45 +00:00
Jim Grosbach
3bc8a3d3af ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146111 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:31:07 +00:00
Chad Rosier
14d622dce6 Fix comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146109 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:11:31 +00:00
Peter Collingbourne
d40e103ea5 EngineBuilder: support for custom TargetOptions. Fixes the 
ExceptionDemo example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146108 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 23:58:57 +00:00
Chad Rosier
0c89f7fda2 Fix comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146107 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 23:57:55 +00:00
Jim Grosbach
af4edea67b ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands. 
For 'gas' compatibility.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146106 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 23:40:58 +00:00
Akira Hatanaka
08a7d92da6 Modify class ReadHardware and add definition of 64-bit version of instruction 
RDHWR. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146101 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 23:31:26 +00:00
Akira Hatanaka
f99c1e5a19 Add newline. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146100 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 23:26:03 +00:00
Akira Hatanaka
be7b67368c Add 64-bit HWR29 register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146099 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 23:23:52 +00:00
Akira Hatanaka
da86fa14f0 32 to 64-bit anyext pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146097 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 23:21:19 +00:00
Akira Hatanaka
0a18cdc372 32 to 64-bit zext pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146096 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 23:14:41 +00:00
Jim Grosbach
9fa0a743e6 ARM two-operand aliases for VAND/VEOR/VORR instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146095 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 23:08:12 +00:00
Jim Grosbach
30a264eb7f ARM two-operand aliases for VADDW instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146093 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 23:01:10 +00:00
Jim Grosbach
d900441e13 ARM two-operand aliases for VADD instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146091 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 22:52:54 +00:00
Chad Rosier
32c5981005 Flesh out a bit more of the bitcode use-list ordering preservation code. 
Nothing too interesting at this point, but comments are welcome.
Part of rdar://9860654 and PR5680.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146090 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 22:49:05 +00:00
Bruno Cardoso Lopes
d1bcf0dbc1 Variable cleanup. Based on past patch submittals variable names have 
been normalized and more descriptive comments added. Patch by Reed
Kotler and Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146088 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 22:35:30 +00:00
Eli Friedman
0e6307f642 Make sure we correctly set LiveRegGens when a call is unscheduled. <rdar://problem/10460321>. No testcase because this is very sensitive to scheduling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146087 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 22:24:28 +00:00
Akira Hatanaka
2c78be01f6 64-bit WrapperPICPat patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146086 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 22:11:43 +00:00
Eli Friedman
30c44e18bf Fix an assertion in the scheduler. PR11386. No testcase included because it's rather delicate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146083 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 22:06:02 +00:00
Akira Hatanaka
20aa12ae5c Define base class for WrapperPICPat. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146081 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 21:54:54 +00:00
Akira Hatanaka
7398bf01c2 Modify LowerFCOPYSIGN to handle Mips64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146080 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 21:48:50 +00:00
Chad Rosier
cbbb09687f Begin adding experimental support for preserving use-list ordering of bitcode 
files.  First, add a new block USELIST_BLOCK to the bitcode format.  This is 
where USELIST_CODE_ENTRYs will be stored.  The format of the USELIST_CODE_ENTRYs
have not yet been defined.  Add support in the BitcodeReader for parsing the
USELIST_BLOCK.
Part of rdar://9860654 and PR5680.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146078 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 21:44:12 +00:00
Nick Lewycky
e77ae2d692 These global variables aren't thread-safe, STATISTIC is. Andy Trick tells me 
that he isn't using these any more, so just delete them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146076 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 21:35:59 +00:00
Chad Rosier
4e6c03fc3d ValueEnumerator - debug dump(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146070 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 20:44:46 +00:00
Akira Hatanaka
bd15090aa2 Fix comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146063 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 20:15:01 +00:00
Akira Hatanaka
3bdc03a592 Fix comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146062 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 20:13:53 +00:00
Akira Hatanaka
4d0eb637f0 Fix 64-bit immediate patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146059 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 20:10:24 +00:00
Jim Grosbach
4f66a050a2 Nuke inadvertant debugging commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146057 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 19:56:16 +00:00
Jim Grosbach
577b09155f Darwin assembler improved relocs when w/o subsections_via_symbols. 
When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146054 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 19:46:59 +00:00
Jakub Staszak
feb468ab24 Remove unneeded semicolon. 
Skip two looking up at BlockChain.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146053 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 19:46:10 +00:00
Jim Grosbach
8524bca750 Thumb2 alias for long-form pop and friends. 
rdar://10542474

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146046 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 18:32:28 +00:00
Jim Grosbach
9a70df99ca ARM support the .arm and .thumb directives for assembly mode switching. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146042 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 18:04:19 +00:00
Jim Grosbach
470855b24f ARM NEON VCLT(register) is a pseudo aliasing VCGT(register). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146039 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 17:51:15 +00:00
Duncan Sands
0ea3a0c236 Remove unused include. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146037 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 17:18:31 +00:00
Craig Topper
d802326335 Fix a bunch of SSE/AVX patterns to use proper memop types. In particular, not using integer loads other than v2i64/v4i64 since the others are all promoted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146031 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 08:30:53 +00:00
Bill Wendling
b3ec329c14 Adjust the stack by one pointer size for all frameless stacks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146030 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 07:58:55 +00:00
Bill Wendling
c61751373a Fix off-by-one error when encoding the stack size for a frameless stack. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146029 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 07:49:49 +00:00
Evan Cheng
5a96b3dad2 Add bundle aware API for querying instruction properties and switch the code 
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 07:15:52 +00:00
David Blaikie
5729c5848c Adding missing anchor to DATDeltaAlgorithm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146025 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 06:44:23 +00:00
Hal Finkel
234bb38d6c make CR spill and restore 64-bit clean (no functional change), and fix some other problems found with -verify-machineinstrs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146024 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 06:34:06 +00:00
Hal Finkel
6d0e014b1f make base register selection used in eliminateFrameIndex 64-bit clean 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146023 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 06:34:02 +00:00
Hal Finkel
ae37cd0a37 set mayStore and mayLoad on CR pseudos 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146022 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 06:33:57 +00:00
Hal Finkel
7ad6b7d359 64-bit LR8 load should use X11 not R11 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146021 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 06:32:37 +00:00
Jakob Stoklund Olesen
2fe71c5ef4 Eliminate delta argument from AdjustBBOffsetsAfter. 
The block offset can be computed from the previous block. That is more
robust than keeping track of a delta.

Eliminate one redundant AdjustBBOffsetsAfter call.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146018 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 05:17:30 +00:00
Jakob Stoklund Olesen
a26811ec83 Compute some alignment information for each basic block. 
These fields are not used for anything yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146017 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 04:17:35 +00:00
Eli Friedman
1c663fee56 Zap unnecessary isIntDivCheap() check. PR11485. No testcase because this doesn't affect any in-tree target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146015 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 03:55:52 +00:00
Jim Grosbach
1ceef1a491 ARM tidy up and remove no longer needed InstAlias definitions. 
The TokenAlias handling of data type suffices renders these unnecessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146010 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 01:50:36 +00:00
Jakob Stoklund Olesen
5bb32530bc Move common expression into a method. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146008 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 01:22:52 +00:00
Jim Grosbach
9f3d220c63 ARM Implement ARM ARM Table A7-3 via TokenAlias. 
Data type suffix aliasing. Previously handled via lots of instruction
aliases. Cleanup of those forthcoming.

rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146007 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 01:17:58 +00:00
Jakob Stoklund Olesen
a3f331bd81 Group BBSizes and BBOffsets into a single vector<BasicBlockInfo>. 
No functional change is intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146005 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 01:08:25 +00:00
Jakob Stoklund Olesen
0400345198 Add missing check. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146004 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 01:08:22 +00:00
Jim Grosbach
3b8991cc98 ARM: NEON SHLL instruction immediate operand range checking. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146003 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 01:07:24 +00:00
Eli Friedman
f91abd22be Support vector bitcasts in the AsmPrinter. PR11495. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146001 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 00:50:54 +00:00
Bruno Cardoso Lopes
e3d3572e28 Add a few moreLocal/Global R_MIPS_GOT related fixups and 
make the addend fixup code a bit more generic

Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145998 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 00:28:57 +00:00
Jakob Stoklund Olesen
2068215e85 Add MachineOperand IsInternalRead flag. 
This flag is used when bundling machine instructions.  It indicates
whether the operand reads a value defined inside or outside its bundle.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145997 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 00:22:07 +00:00
Eli Friedman
26323442d5 Fix an optimization involving EXTRACT_SUBVECTOR in DAGCombine so it behaves correctly. PR11494. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145996 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 00:11:56 +00:00
Jakub Staszak
c9040b3b13 Remove unneeded type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145995 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 00:08:00 +00:00
Jim Grosbach
4e4139588c ARM: Parameterize the immediate operand type for NEON VSHLL. 
No functional change yet. Will be implementing range-checked immediates
for better diagnostics and disambiguation of instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145994 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 00:02:17 +00:00
Jakub Staszak
e6d81ad6a5 - Remove unneeded #includes. 
- Remove unused types/fields.
- Add some constantness.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145993 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 23:59:33 +00:00
Jakob Stoklund Olesen
6fbea43b0b Revert r145971: "Use conservative size estimate for tBR_JTr." 
This caused more offset errors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145980 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 22:41:31 +00:00
Bill Wendling
054a8be154 Re-enable compact unwind. It seems to work now. <rdar://problem/10441838> 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145977 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 22:18:12 +00:00
Bill Wendling
84d518af19 Explicitly check for the different SUB instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145976 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 22:14:27 +00:00
Evan Cheng
7c2a4a30e0 First chunk of MachineInstr bundle support. 
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145975 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 22:12:01 +00:00
Jakob Stoklund Olesen
d25c27807e Use conservative size estimate for tBR_JTr. 
This pseudo-instruction contains a .align directive in its expansion, so
the total size may vary by 2 bytes.

It is too difficult to accurately keep track of this alignment
directive, just use the worst-case size instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145971 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 21:55:39 +00:00
Jakob Stoklund Olesen
305e5fe797 Remove alignment from deserted constant islands. 
ARMConstantIslandPass may sometimes leave empty constant islands behind
(it really shouldn't). Remove the alignment from the empty islands so
the size calculations are still correct.

This should fix the many Thumb1 assembler errors in the nightly test
suite.

The reduced test case for this problem is way too big. That is to be
expected for ARMConstantIslandPass bugs.

<rdar://problem/10534709>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145970 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 21:55:35 +00:00
Bill Wendling
581ac2723c Encode the total stack if there isn't a frame. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145969 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 21:34:01 +00:00
Bill Wendling
57a3cd2f32 * Add a macro to remove a magic number. 
* Rename variables to reflect what they're actually used for.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145968 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 21:23:42 +00:00
Jakob Stoklund Olesen
f2e944523c Pretty-print basic block alignment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145965 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 21:08:39 +00:00
Hal Finkel
d21e930eac add RESTORE_CR and support CR unspills 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145961 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 20:55:36 +00:00
Hal Finkel
16588e794c remove old FIXME 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145960 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 20:52:56 +00:00
Bill Wendling
5b2c4978ce Check the correct value for small stack sizes. Also modify some comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145954 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 19:16:17 +00:00
Bill Wendling
75e14e0ebd For a small sized stack, we encode that value directly with no "stack adjust" value. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145952 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 19:09:06 +00:00
Justin Holewinski
4c7ffb6a7e PTX: Continue to fix up the register mess. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145947 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 17:39:48 +00:00
Justin Holewinski
e37a83f66b PTX: Encode registers as unsigned values in the MC asm printer instead of using external symbols 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145946 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 17:39:46 +00:00
Sebastian Pop
464f3a332f use space star instead of star space 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145944 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 17:34:16 +00:00
Sebastian Pop
f6f77e90a1 add missing point at the end of sentences 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145943 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 17:34:11 +00:00
Benjamin Kramer
88c09143b6 Simplify common predecessor finding. 
- Walking over pred_begin/pred_end is an expensive operation.
- PHINodes contain a value for each predecessor anyway.
- While it may look like we used to save a few iterations with the set,
  be aware that getIncomingValueForBlock does a linear search on
  the values of the phi node.
- Another -5% on ARMDisassembler.cpp (Release build). This was the last
  entry in the profile that was obviously wasting time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145937 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 16:14:29 +00:00
Benjamin Kramer
85dadecbd6 Push StringRefs through the metadata interface. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145934 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 11:50:26 +00:00
Craig Topper
fe03315925 Add X86ISD::HADD/HSUB to getTargetNodeName 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145929 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 09:31:36 +00:00
Craig Topper
cb6bd11bd6 Fix a bunch of SSE/AVX patterns to use v2i64/v4i64 loads since all other integer vector loads are promoted to those. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145927 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 09:04:59 +00:00
Craig Topper
34671b812a Merge floating point and integer UNPCK X86ISD node types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145926 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 08:21:25 +00:00
Craig Topper
3d8c2ce3e4 Clean up some of the shuffle decoding code for UNPCK instructions. Add instruction commenting for AVX/AVX2 forms for integer UNPCKs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145924 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 05:31:16 +00:00
Jim Grosbach
23261af193 ARM mode 'mul' operand ordering tweak. 
Same as r145922, just for ARM mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145923 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 05:28:00 +00:00
Jim Grosbach
cf9814ddd2 Thumb2: MUL two-operand form encoding operand order fix. 
Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.

rdar://10532439

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145922 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 05:03:45 +00:00
Craig Topper
1ff73d7a67 Merge isSHUFPMask and isCommutedSHUFPMask into single function that can do both. Do the same for the 256-bit version. Use loops to reduce size of isVSHUFPYMask. Fix test cases that were incorrectly passing due to isCommutedSHUFPMask not checking for the vector being 128-bit. This caused some 256-bit shuffles to be incorrectly commuted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145921 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 04:59:07 +00:00
Jim Grosbach
df33e0d05e Thumb2 encoding choice correction for PLD. 
Using encoding T1 for offset of #0 and encoding T2 for #-0.

rdar://10532413

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145919 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 04:49:29 +00:00
Bruno Cardoso Lopes
ff452f5349 Use branches instead of jumps + variable cleanup. Testcase coming next. Patch by Jack Carter 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145912 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 03:34:48 +00:00
Bruno Cardoso Lopes
a00a62acd0 Explicit symbols for gnu mimicing relocations. Patch by Jack Carter 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145911 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 03:34:42 +00:00
Bruno Cardoso Lopes
2bcc789a9d Add register HWR29 numbering. Patch by Jack Carter 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145910 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 03:34:36 +00:00
Andrew Trick
8a5d792944 LSR: prune undesirable formulae early. 
It's always good to prune early, but formulae that are unsatisfactory
in their own right need to be removed before running any other pruning
heuristics. We easily avoid generating such formulae, but we need them
as an intermediate basis for forming other good formulae.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145906 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 03:13:31 +00:00
Evan Cheng
89dae971b1 Mix some minor misuse of MachineBasicBlock iterator. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145903 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 02:49:06 +00:00
Pete Cooper
d3743fc092 Removed isWinToJoinCrossClass from the register coalescer. 
The new register allocator is much more able to split back up ranges too constrained by register classes.

Fixes <rdar://problem/10466609>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145899 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 02:06:50 +00:00
Lang Hames
bae56b4c21 Kill off the LoopSplitter. It's not being used or maintained. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145897 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:57:59 +00:00
Bill Wendling
80caf9c273 Add a comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145896 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:57:48 +00:00
Jim Grosbach
cb86509e7a Tidy up value checking. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145895 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:53:17 +00:00
NAKAMURA Takumi
6482e91149 MipsAsmBackend.cpp, PPCAsmBackend.cpp: Fix -Asserts build to appease msvc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145894 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:48:32 +00:00
Lang Hames
9ad7e07a0f Update PBQP's analysis usage to reflect the requirements of the inline spiller. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145893 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:45:57 +00:00
Chad Rosier
ed42c5f778 [arm-fast-isel] Doublewords only require word-alignment. 
rdar://10528060

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145891 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:44:17 +00:00
Jakob Stoklund Olesen
3e572ac2fb Align ARM constant pool islands via their basic block. 
Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired
alignment of 4 bytes emitted by ARMAsmPrinter.  Now the same alignment
is set on the basic block.

This is in preparation of supporting ARM constant pool islands with
different alignments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145890 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:43:02 +00:00
Jakob Stoklund Olesen
8c741b8064 Use logarithmic units for basic block alignment. 
This was actually a bit of a mess. TLI.setPrefLoopAlignment was clearly
documented as taking log2(bytes) units, but the x86 target would still
set a preferred loop alignment of '16'.

CodePlacementOpt passed this number on to the basic block, and
AsmPrinter interpreted it as bytes.

Now both MachineFunction and MachineBasicBlock use logarithmic
alignments.

Obviously, MachineConstantPool still measures alignments in bytes, so we
can emulate the thrill of using as.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145889 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:26:19 +00:00
Bill Wendling
79df986c60 The compact encoding of the registers are 3-bits each. Make sure we shift the 
value over that much.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145888 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:26:14 +00:00
Jim Grosbach
d9a6e8978d Fix ARM handling of tBcc branch relaxation. 
rdar://10069056

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145885 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:08:19 +00:00
Jakob Stoklund Olesen
e80fba0e6c Use an existing function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145883 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 00:51:12 +00:00
Jim Grosbach
370b78d795 Move target-specific logic out of generic MCAssembler. 
Whether a fixup needs relaxation for the associated instruction is a
target-specific function, as the FIXME indicated. Create a hook for that
and use it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145881 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 00:47:03 +00:00
Nick Lewycky
7c06741004 Expose a switch for the new gcov format. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145880 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 00:29:13 +00:00
Chad Rosier
dce42b75dc Probably not a good idea to convert a single vector load into a memcpy. We 
don't do this now, but add a test case to prevent this from happening in the
future.
Additional test for rdar://9892684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145879 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 00:19:08 +00:00
Jim Grosbach
f68a26b5d8 Tidy up. Hard tabs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145878 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 00:13:09 +00:00
Jim Grosbach
f77d5b14af Switch MCAssembler to method names starting w/ lower-case. 
per http://llvm.org/docs/CodingStandards.html#ll_naming

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145873 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 00:03:48 +00:00
Jim Grosbach
f503ef6800 Simple branch relaxation for Thumb2 Bcc instructions. 
Not right yet, as the rules for when to relax in the MCAssembler aren't
(yet) correct for ARM. This is a step in the proper direction, though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145871 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 23:45:46 +00:00
Nick Lewycky
aa21e417f2 Silence tsan false-positives (tsan can't track things which are only safe due to 
memory fences) in statistics registration, which works the same way that
ManagedStatic registration does.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145869 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 23:07:05 +00:00
Chad Rosier
a4b6fd5be0 Update comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145866 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 22:53:09 +00:00
Chad Rosier
d8bd26ee24 Make the MemCpyOptimizer a bit more aggressive. I can't think of a scenerio 
where this would be bad as the backend shouldn't have a problem inlining small
memcpys.
rdar://10510150

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145865 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 22:37:00 +00:00
Jim Grosbach
713c70238c Tweak ADDrr fix. Bad check for explicit .w 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145863 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 22:27:04 +00:00
Jim Grosbach
927b9df4c6 Thumb2 prefer ADD register encoding T2 to T3 when possible. 
rdar://10529664


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145860 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 22:16:39 +00:00
Akira Hatanaka
d6bc5237d8 Add definitions of 64-bit extract and insert instrucions and make 
PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145853 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 21:26:34 +00:00
Akira Hatanaka
cee46abc16 Split ExtIns into two base classes and have instructions EXT and INS derive from 
them.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145852 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 21:14:28 +00:00
Jim Grosbach
da84786bee Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions. 
rdar://10529348


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145851 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 21:06:26 +00:00
Akira Hatanaka
2bf08ec854 Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 and 
O32 with relocation-model=pic too.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145850 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 21:03:03 +00:00
Jim Grosbach
253ef7a779 ARM assembly parsing for the rest of the VMUL data type aliases. 
Finish up rdar://10522016.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145846 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 20:29:59 +00:00
Jim Grosbach
422faab909 Fix previous commit. Oops. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145844 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 20:12:26 +00:00
Jim Grosbach
45755a77ec Tidy up. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145843 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 20:09:44 +00:00
Jim Grosbach
afb500ace1 ARM assmebler parsing for two-operand VMUL instructions. 
Combined destination and first source operand for f32 variant of the VMUL
(by scalar) instruction.

rdar://10522016

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145842 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 19:55:46 +00:00
Hal Finkel
3fd0018af1 enable PPC register scavenging by default (update tests and remove some FIXMEs) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145819 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 17:55:17 +00:00
Hal Finkel
9489487f98 don't include CR bit subregs in callee-saved list 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145818 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 17:55:12 +00:00
Hal Finkel
2e313caa36 add register pressure for CR regs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145816 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 17:54:17 +00:00
Benjamin Kramer
4da7f90b17 Add a little heuristic to Value::isUsedInBasicBlock to speed it up for small basic blocks. 
- Calling getUser in a loop is much more expensive than iterating over a few instructions.
- Use it instead of the open-coded loop in AddrModeMatcher.
- 5% speedup on ARMDisassembler.cpp Release builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145810 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 17:23:27 +00:00
Craig Topper
1dc0fbc168 Remove some leftover remnants that once tried to create 64-bit MMX PALIGNR instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145804 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 07:27:14 +00:00
Craig Topper
beabc6cc6d Clean up and optimizations to the X86 shuffle lowering code. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145803 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 06:56:46 +00:00
Nadav Rotem
1608769abe Add support for vectors of pointers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145801 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 06:29:09 +00:00
Eric Christopher
309bedd7bc Add inline subprogram names to the name lookup table since they may 
not get there any other way.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145789 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-04 06:02:38 +00:00
Bob Wilson
6ce2deacef Fix 80-column issues. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145783 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-04 00:52:23 +00:00
Anton Korobeynikov
0cb2a45cce Emit the ctors in the proper order on ARM/EABI. 
Maybe some targets should use this as well.

Patch by Evgeniy Stepanov!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145781 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 23:49:37 +00:00
Venkatraman Govindaraju
80b1ae9292 Sparc CodeGen: Fix AnalyzeBranch for PR 10282. Removing addSuccessor() since 
AnalyzeBranch doesn't change the successor, just the order.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145779 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 21:24:48 +00:00
Benjamin Kramer
a86bfc1071 Simplify code. No functionality change. 
-3% on ARMDissasembler.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145773 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 16:18:22 +00:00
Benjamin Kramer
c00c05f8f5 Clear the new cache. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145771 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 15:19:55 +00:00
Benjamin Kramer
feb9b4bc3b Add a "seen blocks" cache to LVI to avoid a linear scan over the whole cache just to remove no blocks from the maps. 
-15% on ARMDisassembler.cpp (Release build).  It's not that great to add another
layer of caching to the caching-heavy LVI but I don't see a better way.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145770 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 15:16:45 +00:00
Sanjoy Das
199ce33b3b Check for stack space more intelligently. 
libgcc sets the stack limit field in TCB to 256 bytes above the actual
allocated stack limit.  This means if the function's stack frame needs
less than 256 bytes, we can just compare the stack pointer with the
stack limit.  This should result in lesser calls to __morestack.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145766 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 09:32:07 +00:00
Sanjoy Das
40f8222e1e Fix a bug in the x86-32 code generated for segmented stacks. 
Currently LLVM pads the call to __morestack with a add and sub of 8
bytes to esp.  This isn't correct since __morestack expects the call
to be followed directly by a ret.

This commit also adjusts the relevant test-case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145765 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 09:21:07 +00:00
Nick Lewycky
3604924799 Creating multiple JITs on X86 in multiple threads causes multiple writes (of 
the same value) to this variable. This code could be refactored, but it doesn't
matter since the old JIT is going away. Add tsan annotations to ignore the
race.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145745 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 02:45:50 +00:00
Chad Rosier
9eff1e33f6 [arm-fast-isel] Unaligned stores of floats require special care. 
rdar://10510150

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145742 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 02:21:57 +00:00
Pete Cooper
de2e27cc52 Fixed deadstoreelimination bug where negative indices were incorrectly causing the optimisation to occur 
Turns out long long + unsigned long long is unsigned.  Doh!

Fixes http://llvm.org/bugs/show_bug.cgi?id=11455

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145731 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 00:04:30 +00:00
Chad Rosier
24fbf2bf16 Add support for constant folding the pow intrinsic. 
rdar://10514247

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145730 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 00:00:03 +00:00
Jim Grosbach
587f5062b9 ARM NEON VEXT aliases for data type suffices. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145726 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 23:34:39 +00:00
Jim Grosbach
e40ab244c1 ARM VEXT tighten up operand classes a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145722 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 22:57:57 +00:00
Jim Grosbach
84defb51ca ARM VST1 single lane assembly parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145718 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 22:34:51 +00:00
Nick Lewycky
8a8d479214 Move global variables in TargetMachine into new TargetOptions class. As an API 
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.

One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145714 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 22:16:29 +00:00
Jim Grosbach
872eedbb3a ARM VLD1 single lane assembly parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145712 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 22:01:52 +00:00
Jim Grosbach
204aa64f30 ARM encoder method needs the physical register number, not the enum. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145711 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 22:01:25 +00:00
Chad Rosier
b74c865841 [arm-fast-isel] After promoting a function parameter be sure to update the 
argument value type.  Otherwise, the sign/zero-extend has no effect on arguments
passed via the stack (i.e., undefined high-order bits).
rdar://10515467

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145701 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 20:25:18 +00:00
Jim Grosbach
dad2f8e7fb Clean up aliases for ARM VLD1 single-lane assembly parsing a bit. 
Add the 16-bit lane variants while I'm at it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145693 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 18:52:30 +00:00
Benjamin Kramer
30fe1ae20d Fix quadratic behavior in InlineFunction by fetching the personality function of the callee once and not for every invoke in the caller. 
The callee is usually smaller than the caller, too. This reduces the compile
time of ARMDisassembler.cpp by 32% (Release build). It still takes ages to
compile though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145690 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 18:37:31 +00:00
Jim Grosbach
94f2dc90a5 Check for error after InstantiateMultclassDef. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145689 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 18:33:03 +00:00
Jan Sjödin
ce25d26b40 Add XOP feature flag. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145682 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 15:14:37 +00:00
Craig Topper
f8363305eb Reduce duplicate code in isHorizontalBinOp and add some asserts to protect assumptions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145681 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 08:18:41 +00:00
Craig Topper
138a5c66b9 Add instruction selection support for horizontal add/sub of 256-bit floating point vectors. Also add the test case for 256-bit integer vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145680 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 07:16:01 +00:00
Hal Finkel
826941a0af remove unneeded FIXME comment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145679 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 04:58:17 +00:00
Hal Finkel
db809e0eb7 make sure ScheduleDAGInstrs::EmitSchedule does not crash when the first instruction in Sequence is a Noop 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145677 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 04:58:07 +00:00
Hal Finkel
64c34e2535 update PPC 940 hazard rec. to function in postRA mode 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145676 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 04:58:02 +00:00
Chad Rosier
aab8e28d5e Fix a few more places where TargetData/TargetLibraryInfo is not being passed. 
Add FIXMEs to places that are non-trivial to fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145661 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 01:26:24 +00:00
Jim Grosbach
7636bf6530 ARM start parsing VLD1 single lane instructions. 
The alias pseudos need cleaned up for size suffix handling, but this gets
the basics working. Will be cleaning up and adding more.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145655 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 00:35:16 +00:00
Chad Rosier
21646e8bec Abuse of mass replace isn't warranted even when the build is failing. Thanks 
for the suggestion, Eric.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145643 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 23:16:03 +00:00
Chad Rosier
ca3043101f Fix build by not assuming TLI is guaranteed. Will have to track down cases where 
TLI isn't being passed to ensure we don't miss opportunities to fold calls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145641 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 22:38:31 +00:00
Chad Rosier
aebc3aae3f Prevent library calls from being folded if -fno-builtin has been specified. 
rdar://10500969

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145639 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 22:14:50 +00:00
Dylan Noblesmith
fe0926d773 CodeGen: fix CMake build 
Missing file from r145629.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145634 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 21:49:23 +00:00
Dylan Noblesmith
d95e67dac0 ExecutionEngine: honor optimization level 
It was getting ignored after r144788.

Also fix an accidental implicit cast from the OptLevel enum
to an optional bool argument. MSVC warned on this, but gcc
didn't.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145633 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 21:49:21 +00:00
Chad Rosier
00737bdb48 Last bit of TargetLibraryInfo propagation. Also fixed a case for TargetData 
where it appeared beneficial to pass.
More of rdar://10500969

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145630 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 21:29:16 +00:00
Anshuman Dasgupta
dc81e5da27 Add a deterministic finite automaton based packetizer for VLIW architectures 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145629 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 21:10:21 +00:00
David Blaikie
18c7ec1344 Fix unreachable return & simplify some branches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145627 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 20:58:30 +00:00
Sanjoy Das
fc9261279a Dummy commit to check commit access. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145619 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 19:15:08 +00:00
Pete Cooper
165695d261 Improved fix for abs(val) != 0 to check other similar case. Also fixed style issues and confusing comment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145618 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 19:13:26 +00:00
Kostya Serebryany
cc1d856d8e [asan] two minor fixes: use UnreachableInst after the neverreturn function call; use report_fatal_error when blacklist file can not be found 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145611 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 18:54:53 +00:00
Chad Rosier
fbd828d8e1 Add missing functions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145608 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 18:26:19 +00:00
Benjamin Kramer
618f89f22a Autodetect bulldozers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145607 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 18:24:17 +00:00
Chad Rosier
32b6c59ad0 Add a few more functions to TargetLibraryInfo. More of rdar://10500969. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145596 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 17:54:37 +00:00
Eric Christopher
7d5a61e975 For 64-bit the rest of the general regs are ok for the q constraint. Make 
sure we can emit both the high and low versions of those registers.

Fixes rdar://10392864

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145579 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 08:12:41 +00:00
David Blaikie
0becc96b24 Add some missing anchors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145578 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 08:00:17 +00:00
Eli Friedman
522fb8cc01 Pass AVX vectors which are arguments to varargs functions on the stack. <rdar://problem/10463281>. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145573 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 04:49:21 +00:00