involves removing the [bwl] suffixes from instruction names, as well
as some other distinguishing marks (32/64/80 on fp insns, _i suffixes, etc.)
Lowercase all instr. names as well for consistency's sake.
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to print various things on a module-by-module basis (currently, only the
former is used).
Don't print < > around names. The assembler can't take it.
Print pseudoinstructions only as comments. The poor little assembler can't
take that, either.
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Move LowerAllocations, PrintFunction, and SymbolStripping passes, and
the corresponding -disable-strip and -d options, over here to the SPARC
target-specific bits of llc. Rename -d to -dump-asm.
tools/llc/Makefile:
Reindent. Add x86 library so that llc compiles again.
tools/llc/llc.cpp:
Remove support for running arbitrary optimization passes. Use opt instead.
Remove LowerAllocations, PrintFunction, and SymbolStripping passes, as noted
above.
Allow user to select a backend (x86 or SPARC); default to guessing from
the endianness/pointer size of the input bytecode file.
Fix typos.
Delete empty .s file and exit with error status if target does not support
static compilation.
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into a new function FPCSafeToPrint(), and use it in printConstant()
and printFunction() to decide whether we should output ConstantFPs as
floating-point constants or as references to stack-allocated variables.
lib/VMCore/AsmWriter.cpp: Fix an apparent typo in the code mentioned above.
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instead of a variable pointer and an alloca. All accesses to the variable then
use the address-of operator to access it. This plays better with the internal
GCC code generation phases, which bail early on functions which contain allocas.
It also makes the code a bit easier to read.
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SETTING the operand to be an immediate or have verified that one of the operands
is really a SignExtended or Unextended immediate value already, which warrants
an 'i' opcode.
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* BPA and BPN do not take a %cc register as a parameter
* SLL/SRL/SRA{r,i}5 are there for a reason - they are ONLY 32-bit instructions
* Likewise, SLL/SRL/SRAX{r,i}6 are only 64-bit
* Added WRCCR{r,i} opcodes
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* Removed instruction scheduling as it is too slow to run in a JIT environment
* Removed other passes because they aren't necessary and can slow JIT down
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This avoid generating a register to hold C, which in turn speeds up the
register allocator by a lot: ~9% on 164.gzip and ~17% on 256.bzip2. This
also speeds up other passes. This also speeds up execution of the program
marginally, and makes the asm much easier to read. :)
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Special cases: STFSRx and STXFSRx - they operate on predefined rd=0 or rd=1, and
expect %fsr as the parameter in assembly. They are disabled (since not used)
until an encoding, both for code generation and output, is chosen.
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Update file comment to contain a bunch of the overview mapping-info
documentation previously buried within the file.
Remove some unnecessary include/using stmts.
Rename pass to MappingInfoCollector.
Rewrite a lot of it so it doesn't use global instance variables and so
it outputs into MappingInfo objects and then dumps those out, instead of going
straight to an assembly file.
Change name of factory to getMappingInfoCollector.
Fold prologue & epilogue writers into MappingInfo methods.
lib/Target/Sparc/FInfo.cpp:
Correct file comment to reflect above change
lib/Target/Sparc/Sparc.cpp:
Change name of factory to getMappingInfoCollector.
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in Emitter.cpp, just convert the Sparc version of the constant pool into
what's already supported and inter-operate.
* Implemented a first pass at lazy function resolution in the JITResolver. That
required adding a SparcV9CodeEmitter pointer to simplify generating
bit-patterns of the instructions.
* SparcV9CodeEmitter now creates and destroys static TheJITResolver, which makes
sense because the SparcV9CodeEmitter is the only user of TheJITResolver, and
lives for the entire duration of the JIT (via PassManager which lives in VM).
* Changed all return values in the JITResolver to uint64_t because of the 64-bit
Sparc architecture.
* Added a new version of getting the value of a GlobalValue in the
SparcV9CodeEmitter, which now works for already-generated functions (JITted or
library functions).
* Removed little-used and unused functions, cleaning up the internal view of the
SparcV9CodeEmitter.
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the loop, and in both cases. In the first case, it is a VReg that is a constant
so it may be actually converted to a constant. In the second case, it is already
a constant, but then if it doesn't change its type (e.g. to become a register
and have the value loaded from memory if it is too large to live in its
instruction field), we must change the opcode BEFORE the 'continue', otherwise
we miss the opportunity.
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rewriting it. I also vacuumed out all the commented-out code and
inaccurate comments, etc.
(We need to put the mapping information in a data structure so that we can
pass it out to the JIT, instead of automagically converting it to .byte
directives.)
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they prefer the destination register to be last. Thus, two new classes were made
for them that accomodate for having this layout of operands (F3_1rd, F3_2rd).
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* Labeled sections that are not currently used in the Sparc backend as not
requiring completion at this time.
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* Added instruction classes which start building from rs1, then rs2, and rd.
* Fixed order of operands in classes 4.1 and 4.2; added 4.6 .
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* Added new classes which start building from rs1, adding rs2, and then rd.
* Fixed order of operands in classes 3.11, 3.12, 3.16, and 3.17 .
* Fixed comments to reflect Real Life (tm).
* Removed "don't care" commented out assignments and dead classes (#if 0).
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In particular these classes are the last that link the noncopyable classes
with the hash_map, vector, and list classes.
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None of these instructions are actually used in the Sparc backend, so no changes
were required in the instruction selector.
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SparcInstrSelection.cpp:
* Fixed opcodes to return correct 'i' version since the two functions are each
only used in one place.
* Changed name of function to have an 'i' in the name to signify that they each
return an immediate form of the opcode.
* Added a warning if either of the functions is ever used in a context which
requires a register-version opcode.
SparcV9_F4.td: fixed class F4_3, added F4_4 and notes that F4_{1,2} need fixing
SparcV9.td: added the MOV(F)cc instructions
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