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2039 Commits

Author SHA1 Message Date
Devang Patel
3e08131185 Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI] 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148721 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 20:20:06 +00:00
Jim Grosbach
8b31f95bdd Simplify some NEON assembly pseudo definitions. 
Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148718 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 19:39:08 +00:00
Devang Patel
7c64fe651a Intel syntax: Parse segment registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148712 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 18:31:58 +00:00
Devang Patel
1aea430b88 Intel syntax: Robustify register parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148591 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 22:32:05 +00:00
Devang Patel
fdd3b30151 Intel syntax: Parse ... PTR [-8] 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148570 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 21:21:01 +00:00
Devang Patel
cf0e269d16 Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148569 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 21:14:06 +00:00
Jim Grosbach
51222d1551 NEON use vmov.i32 to splat some f32 values into vectors. 
For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.

rdar://10616677

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148556 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 18:09:51 +00:00
Devang Patel
a951f77ca3 Post process 'and', 'sub' instructions and select better encoding, if available. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148489 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-19 18:40:55 +00:00
Devang Patel
e60540f380 Intel syntax: There is no need to create unary expr for simple negative displacement. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148486 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-19 18:15:51 +00:00
Devang Patel
ac0f048602 Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148485 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-19 17:53:25 +00:00
Jim Grosbach
904b7be27e Add testcase. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148454 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-19 01:36:59 +00:00
Jim Grosbach
0b4c673886 Thumb2 alternate syntax for LDR(literal) and friends. 
Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".

rdar://10250964

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148432 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-18 22:46:46 +00:00
Devang Patel
b8ba13f009 Process instructions after match to select alternative encoding which may be more desirable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148431 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-18 22:42:29 +00:00
Jim Grosbach
256ba4f42a Thumb2 relaxation for LDR(literal). 
If the fixup is out of range for the Thumb1 instruction, relax it
to the Thumb2 encoding instead.

rdar://10711829

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148424 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-18 21:54:16 +00:00
Jim Grosbach
8b9300b972 MC tweak symbol difference resolution for non-local symbols. 
When the non-local symbol in the expression is in the same fragment
as the second symbol, the assembler can still evaluate the expression
without needing a relocation.

For example, on ARM:
_foo:
	ldr lr, (_foo - 4)

rdar://10348687



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148341 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 22:14:39 +00:00
Jim Grosbach
283f1fff47 Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148339 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 22:03:42 +00:00
Devang Patel
2f8af1d643 Intel syntax: Fix parser match class to check memory operand size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148338 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 21:48:03 +00:00
Devang Patel
6220fea2a8 Intel syntax: Parse "BYTE PTR [RDX + RCX]" 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148334 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 21:25:10 +00:00
Devang Patel
9a3d293cf3 Intel syntax: Do not unncessarily create plus expression for memory operand displacement. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148321 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 19:08:07 +00:00
Devang Patel
40bced0306 Intel syntax: Ignore mnemonic aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148316 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 18:30:45 +00:00
Devang Patel
d37ad247cc Intel syntax: Robustify memory operand parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148312 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 18:00:18 +00:00
Devang Patel
4a5c0fd70e Add new test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148128 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 18:45:31 +00:00
Devang Patel
989a681464 Remove test case, as Chris suggested. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148039 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 19:54:02 +00:00
Devang Patel
21d3c40fb0 Add test case to check intel syntax parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148034 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 18:40:46 +00:00
Kevin Enderby
8704b7897d The error check for using -g with a .s file already containing dwarf .file 
directives was in the wrong place and getting triggered incorectly with a
cpp .file directive.  This change fixes that and adds a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147951 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-11 18:04:47 +00:00
Rafael Espindola
29a17145ad Add big endian mips support. Based on a patch by Jack Carter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147924 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-11 04:04:14 +00:00
Rafael Espindola
fddf804597 Add the skeleton of an asm parser for mips. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147923 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-11 03:56:41 +00:00
Kevin Enderby
38fdb7d9fc Various crash reporting tools have a problem with the dwarf generated for 
assembly source when it generates the TAG_subprogram dwarf debug info for
the labels that have nothing between them as in this bit of assembly source:

% cat ZeroLength.s 
_func1:
_func2:
 nop

One solution would be to not emit the subsequent labels with the same address
and use the next label with a different address or the end of the section for
the AT_high_pc value of the TAG_subprogram.

Turns out in llvm-mc it is not possible in all cases to determine of two
symbols have the same value at the point we put out the TAG_subprogram dwarf
debug info.

So we will have llvm-mc instead of putting out TAG_subprogram's put out
DW_TAG_label's.  And the DW_TAG_label does not have a AT_high_pc value which
avoids the problem.

This commit is only the functional change to make the diffs clear as to what is
really being changed.  The next commit will be to clean up the names of such
things like MCGenDwarfSubprogramEntry to something like MCGenDwarfLabelEntry.

rdar://10666925


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147860 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-10 17:52:29 +00:00
Rafael Espindola
99b4237c16 Split Finish into Finish and FinishImpl to have a common place to do end of 
file error checking. Use that to error on an unfinished cfi_startproc.

The error is not nice, but is already better than a segmentation fault.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147717 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-07 03:13:18 +00:00
Craig Topper
06f554d06a Add disassembler support for VPERMIL2PD and VPERMIL2PS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147368 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 06:23:39 +00:00
Craig Topper
e6a3a2990e Add FMA4 instructions to disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147367 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 05:20:36 +00:00
Rafael Espindola
ed23bdb65f Implement cfi_restore. Patch by Brian Anderson! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147356 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 21:43:03 +00:00
Craig Topper
1604ccfc01 Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147353 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 20:43:40 +00:00
Rafael Espindola
6f0b181bc7 Implement .cfi_escape. Patch by Brian Anderson! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147352 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 20:24:47 +00:00
Craig Topper
19f18be449 Expose FMA3 instructions to the disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147351 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 20:03:14 +00:00
Jim Grosbach
4050bc4cab ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point). 
rdar://10558523

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147189 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 22:19:05 +00:00
Rafael Espindola
b975c27adc Fix incorrect relocation generation. Patch by Kristof Beyls. 
Fixes PR11214.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147180 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 21:36:43 +00:00
Jim Grosbach
8d9550bde9 ARM assembler should accept shift-by-zero for any shifted-immediate operand. 
Just treat it as-if the shift wasn't there at all. 'as' compatibility.

rdar://10604767

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147153 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 18:04:04 +00:00
Akira Hatanaka
bc24985c5f Local dynamic TLS model for direct object output. Create the correct TLS MIPS 
ELF relocations.

Patch by Jack Carter.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147118 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 01:05:17 +00:00
Jim Grosbach
af33a0cfe0 ARM VFP optional data type on VMOV GPR<-->SPR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147104 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 23:24:15 +00:00
Jim Grosbach
520dc78d92 Thumb2 assembly parsing of 'mov rd, rn, rrx'. 
Maps to the RRX instruction. Missed this case earlier.

rdar://10615373

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147096 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 21:04:19 +00:00
Jim Grosbach
2cc5cda464 Thumb2 assembly parsing of 'mov(register shifted register)' aliases. 
These map to the ASR, LSR, LSL, ROR instruction definitions.

rdar://10615373

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147094 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 20:54:00 +00:00
Jim Grosbach
e6949b1399 ARM NEON assmebly parsing for VLD2 to all lanes instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147069 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 19:40:55 +00:00
Jim Grosbach
3471d4fbbd ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147025 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 00:38:54 +00:00
Jim Grosbach
06d738c76a Enable and fix a test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147011 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:20:00 +00:00
Jim Grosbach
5b484312c6 ARM assembly parsing and encoding for VST2 single-element, double spaced. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146990 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 20:46:29 +00:00
Jim Grosbach
514806b52e ARM enable a few more tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146985 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 20:03:00 +00:00
Jim Grosbach
95fad1c603 ARM assembly parsing and encoding for VLD2 single-element, double spaced. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146983 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 19:21:26 +00:00
Jim Grosbach
04b5d93250 ARM assembly shifts by zero should be plain 'mov' instructions. 
"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.

rdar://10604663

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146937 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 00:59:38 +00:00
Jim Grosbach
2f196747f1 ARM assembly parsing and encoding support for LDRD(label). 
rdar://9932658

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146921 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 23:06:24 +00:00
Jim Grosbach
d22170e16a ARM NEON two-operand aliases for VPADD. 
rdar://10602276

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146895 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 19:51:03 +00:00
Jim Grosbach
61b74b4247 ARM NEON implied destination aliases for VMAX/VMIN. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146885 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 18:57:38 +00:00
Jim Grosbach
eeaf1c1636 ARM NEON relax parse time diagnostics for alignment specifiers. 
There's more variation that we need to handle. Error checking will need
to be on operand predicates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146884 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 18:31:43 +00:00
Rafael Espindola
8f7d12ccfd Add back the MC bits of 126425. Original patch by Nathan Jeffords. I added the 
asm parsing and testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146801 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-17 01:14:52 +00:00
Eli Friedman
7e840efc23 Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146709 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 23:46:18 +00:00
Jim Grosbach
a738da7bd3 ARM NEON VCLE is an alias for VCGE w/ the source operands reversed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146699 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 22:56:33 +00:00
Jim Grosbach
60d99a5278 ARM NEON VTBL/VTBX assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146691 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 22:27:11 +00:00
Jim Grosbach
9b1b390288 ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146605 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 23:25:46 +00:00
Kevin Enderby
c3fc3136a1 Improve the implementation of .incbin directive by replacing a loop by using 
getStreamer().EmitBytes.  Suggestion by Benjamin Kramer!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146599 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 22:34:45 +00:00
Jim Grosbach
ec04a3f8db ARM NEON fix alignment encoding for VST2 w/ writeback. 
Add tests for w/ writeback instruction parsing and encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146594 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 21:49:24 +00:00
Kevin Enderby
c55accaddb Add the .incbin directive which takes the binary data from a file and emits 
it to the streamer.  rdar://10383898


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146592 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 21:47:48 +00:00
Jim Grosbach
e90ac9bce9 ARM NEON VST2 assembly parsing and encoding. 
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146579 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 19:35:22 +00:00
Jim Grosbach
8d11c6349f ARM/Thumb2 'cmp rn, #imm' alias to cmn. 
When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.

rdar://10552389

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146567 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 17:30:24 +00:00
Jim Grosbach
a39cda7aff ARM assembler support for the target-specific .req directive. 
rdar://10549683


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146543 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 02:16:11 +00:00
Jim Grosbach
863d2af947 Thumb2 assembler aliases for "mov(shifted register)" 
rdar://10549767


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146520 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 22:45:11 +00:00
Jim Grosbach
27debd60a1 ARM LDM/STM system instruction variants. 
rdar://10550269

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146519 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 21:48:29 +00:00
Jim Grosbach
0da6e867cf Test for 146516 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146517 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 21:06:59 +00:00
Jim Grosbach
55b02f28c1 ARM thumb2 parsing of "rsb rd, rn, #0". 
rdar://10549741


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146515 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 20:50:38 +00:00
Jim Grosbach
0f293de207 ARM NEON two-operand aliases for VQDMULH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146514 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 20:40:37 +00:00
Jim Grosbach
e91e7bcadc ARM pre-UAL NEG mnemonic for convenience when porting old code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146511 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 20:23:22 +00:00
Akira Hatanaka
d1472e8657 Add test/MC/Mips/dg.exp. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146472 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 04:12:49 +00:00
Akira Hatanaka
692be5491a Move direct object emitter test to directory test/MC/Mips. Rename it to 
elf-relsym.ll.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146470 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 03:50:34 +00:00
Nick Lewycky
5a3d4c9830 Don't rely on a particular version string for llvm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146456 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 00:34:14 +00:00
Jan Sjödin
37e7ecf52b XOP instructions and encoding tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146407 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-12 19:37:49 +00:00
Roman Divacky
a0c17a495b Add support for gnu_indirect_function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146377 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-12 17:34:04 +00:00
Chandler Carruth
59164b731b Don't assume things about the exact details of the LLVM version number, 
such as what VCS information is attached.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146333 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-10 21:40:31 +00:00
Rafael Espindola
f3aefb56de Handle expressions of the form _GLOBAL_OFFSET_TABLE_-symbol the same way gas 
does. The _GLOBAL_OFFSET_TABLE_ is still magical in that we get a R_386_GOTPC,
but it doesn't change the immediate in the same way as when the expression
has no right hand side symbol.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146311 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-10 02:28:43 +00:00
Jim Grosbach
840bf7eda7 ARM assembly aliases for BIC<-->AND (immediate). 
When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.

rdar://10550057


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146283 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-09 22:02:17 +00:00
Jim Grosbach
a4e3c7fc4b ARM assembly parsing and encoding for VLD2 with writeback. 
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.

Add tests for the instruction variants now supported.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146278 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-09 21:28:25 +00:00
Rafael Espindola
3c68acd202 Handle reloc_signed_4byte in here. Not doing so was a regression from my 
previous commit. It is strange that we see it in 32 bits. We already
have a fixme about it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146273 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-09 19:57:29 +00:00
Kevin Enderby
94c2e85bea The second part of support for generating dwarf for assembly source files. This 
generates the dwarf Compile Unit DIE and a dwarf subprogram DIE for each
non-temporary label.

The next part will be to get the clang driver to enable this when assembling
a .s file.  rdar://9275556


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146262 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-09 18:09:40 +00:00
Rafael Espindola
1d5969d839 Handle the case of the magical _GLOBAL_OFFSET_TABLE_ showing up in a 
symbol difference. This matches gas behavior and fixes PR11513.

We still don't handle _GLOBAL_OFFSET_TABLE_ in data sections.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146238 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-09 03:03:58 +00:00
Jim Grosbach
8759c3f548 ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146194 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 22:19:04 +00:00
Jim Grosbach
6b044c2609 ARM VSHR implied destination operand form aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146192 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 22:06:06 +00:00
Jim Grosbach
318df74104 Tidy up a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146190 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 22:04:40 +00:00
Jim Grosbach
120313435d ARM VSUB implied destination operand form aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146182 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 20:56:26 +00:00
Jim Grosbach
beef39ab63 Tidy up a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146181 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 20:53:19 +00:00
Jim Grosbach
9e7b42a40e ARM VQADD implied destination operand form aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146179 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 20:49:43 +00:00
Jim Grosbach
1c2c8a9389 ARM a few more VMUL implied destination operand form aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146177 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 20:42:35 +00:00
Jim Grosbach
730fe6c1b6 ARM NEON two-operand aliases for VSHL(immediate). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146125 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 01:30:04 +00:00
Jim Grosbach
ff4cbb4c9a ARM NEON two-operand aliases for VSHL(register). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146123 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 01:12:35 +00:00
Jim Grosbach
a44f2c4a28 ARM optional destination operand variants for VEXT instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146114 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:43:47 +00:00
Jim Grosbach
71a0a2ec0b Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146113 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:41:54 +00:00
Jim Grosbach
3bc8a3d3af ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146111 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:31:07 +00:00
Jim Grosbach
af4edea67b ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands. 
For 'gas' compatibility.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146106 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 23:40:58 +00:00
Jim Grosbach
9fa0a743e6 ARM two-operand aliases for VAND/VEOR/VORR instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146095 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 23:08:12 +00:00
Jim Grosbach
30a264eb7f ARM two-operand aliases for VADDW instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146093 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 23:01:10 +00:00
Jim Grosbach
d900441e13 ARM two-operand aliases for VADD instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146091 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 22:52:54 +00:00
Jim Grosbach
577b09155f Darwin assembler improved relocs when w/o subsections_via_symbols. 
When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146054 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 19:46:59 +00:00
Jim Grosbach
8524bca750 Thumb2 alias for long-form pop and friends. 
rdar://10542474

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146046 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 18:32:28 +00:00
Jim Grosbach
9a70df99ca ARM support the .arm and .thumb directives for assembly mode switching. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146042 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 18:04:19 +00:00
Jim Grosbach
470855b24f ARM NEON VCLT(register) is a pseudo aliasing VCGT(register). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146039 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 17:51:15 +00:00
Jim Grosbach
d552a644be Tidy up. Move MachO tests to MachO directory. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146038 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 17:50:28 +00:00
NAKAMURA Takumi
18851edbc4 test/MC: Introduce MC/MachO/ARM, and relocate relax-thumb2-branches.s into it. 
FIXME: Restore more other arch-dependent MachO tests. (eg. r126401 and r133856)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145925 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 06:48:26 +00:00
Jim Grosbach
23261af193 ARM mode 'mul' operand ordering tweak. 
Same as r145922, just for ARM mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145923 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 05:28:00 +00:00
Jim Grosbach
cf9814ddd2 Thumb2: MUL two-operand form encoding operand order fix. 
Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.

rdar://10532439

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145922 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 05:03:45 +00:00
Jim Grosbach
df33e0d05e Thumb2 encoding choice correction for PLD. 
Using encoding T1 for offset of #0 and encoding T2 for #-0.

rdar://10532413

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145919 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 04:49:29 +00:00
NAKAMURA Takumi
286ea03382 test/MC: Move relax-thumb2-branches.s from MC/MachO/ to MC/ARM. 
MC/MachO assumes x86.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145916 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 03:56:05 +00:00
Jim Grosbach
d9a6e8978d Fix ARM handling of tBcc branch relaxation. 
rdar://10069056

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145885 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:08:19 +00:00
Jim Grosbach
713c70238c Tweak ADDrr fix. Bad check for explicit .w 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145863 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 22:27:04 +00:00
Jim Grosbach
6e507c645d Update tests for r145860. Add a few new ones. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145861 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 22:21:28 +00:00
Jim Grosbach
da84786bee Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions. 
rdar://10529348


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145851 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 21:06:26 +00:00
Jim Grosbach
253ef7a779 ARM assembly parsing for the rest of the VMUL data type aliases. 
Finish up rdar://10522016.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145846 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 20:29:59 +00:00
Jim Grosbach
c4f0b309ee ARM tests for VLD1 single lane w/ writeback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145713 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 22:03:52 +00:00
Jim Grosbach
dad2f8e7fb Clean up aliases for ARM VLD1 single-lane assembly parsing a bit. 
Add the 16-bit lane variants while I'm at it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145693 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 18:52:30 +00:00
Jan Sjödin
dd649e35e5 Support for encoding all FMA4 instructions and tablegen patterns for all 
remaining FMA4 instructions and intrinsics with tests.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 22:09:42 +00:00
Jim Grosbach
e30171ba0c Add some tests for all-lanes VLD1 parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145512 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 19:37:38 +00:00
Jim Grosbach
4c7edb3ad8 ARM assembly parsing and encoding for four-register VST1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145450 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 22:58:48 +00:00
Jim Grosbach
ed1f83f9af Enable some VST1 tests and add a few more. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145443 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 22:40:32 +00:00
Michael J. Spencer
116bc795da MC/X86/COFF: Allow quotes in names when targeting MS/Windows, 
as MC is the only assembler we support.

This splits MS/Windows and GNU/Windows ASM infos into two seperate classes.
While there is currently only one difference, full MS C++ ABI support will
require many more.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145409 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 18:00:06 +00:00
Chris Lattner
d2bf432b2b Upgrade syntax of tests using volatile instructions to use 'load volatile' instead of 'volatile load', which is archaic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145171 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-27 06:54:59 +00:00
Wesley Peck
4c729f1152 Add several new instructions supported by the latest MicroBlaze. 
These instructions are not generated by the backend yet, this will come in a later commit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145161 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-27 05:16:58 +00:00
Bruno Cardoso Lopes
1b9b377975 This patch contains support for encoding FMA4 instructions and 
tablegen patterns for scalar FMA4 operations and intrinsic. Also
add tests for vfmaddsd.

Patch by Jan Sjodin

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145133 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-25 19:33:42 +00:00
Benjamin Kramer
9d399b1fc2 X86: alias cqo to cqto. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145121 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-24 12:02:46 +00:00
Jim Grosbach
9b1671bae7 Remove obsolete test. 
The PLD encoding is checked via the .s file now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144853 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 22:50:38 +00:00
Jim Grosbach
2abba8496c Generalize the fixup info for ARM mode. 
We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144852 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 22:48:37 +00:00
Jim Grosbach
47a906ac23 Update test for r144842. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144851 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 22:46:27 +00:00
Jim Grosbach
e43862b6a6 ARM assembly parsing for register range syntax for VLD/VST register lists. 
For example,
vld1.f64 {d2-d5}, [r2,:128]!

Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!

It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.

rdar://10451128


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144727 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 23:19:15 +00:00
Jim Grosbach
9f302c4fb3 ARM assembly parsing two operand forms for shift instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144713 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 22:27:54 +00:00
Jim Grosbach
19885de61d ARM alternate size suffices for VTRN instructions. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144694 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 20:49:46 +00:00
Jim Grosbach
a68e90c36e ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns. 
Yet more of rdar://10435076.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144691 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 20:29:42 +00:00
Jim Grosbach
bfb0a1717b ARM assembly parsing for two-operand form of 'mul' instruction. 
rdar://10449856.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144689 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 20:14:51 +00:00
Jim Grosbach
d2586daf06 ARM assembly parsing for two-operand form of 'mul' instruction. 
Ongoing rdar://10435114.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144688 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 20:02:06 +00:00
Jim Grosbach
908f923cfc Testcase for r144684. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144685 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 19:56:17 +00:00
Owen Anderson
b589be9334 Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144683 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 19:55:00 +00:00
Jim Grosbach
1de0bd1945 Thumb2 assembly parsing for mul.w in IT block fix. 
When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.

rdar://10449281

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144679 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 19:29:45 +00:00
Jim Grosbach
dd47e0b5d4 ARM parsing datatype suffix variants for non-writeback VST1 instructions. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144593 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:43:46 +00:00
Jim Grosbach
e052b9afa1 ARM parsing datatype suffix variants for non-writeback VLD1 instructions. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144592 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:32:59 +00:00
Jim Grosbach
ef448767a3 ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144587 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:11:19 +00:00
Jim Grosbach
ffc658b056 ARM VLDR/VSTR instructions don't need a size suffix. 
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:03:21 +00:00
Jim Grosbach
c7352f8ca0 ARM optional size suffix for VLDR/VSTR syntax. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144427 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 23:34:43 +00:00
Jim Grosbach
ce485e7f70 ARM allow Q registers in vldm/vstm register lists. 
rdar://9672822

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144407 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 21:27:40 +00:00
Jim Grosbach
5402637ff2 Thumb2 parsing for push/pop w/ hi registers in the reglist. 
rdar://10130228.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144331 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 23:17:11 +00:00
Jim Grosbach
1b332860ae Thumb MUL assembly parsing for 3-operand form. 
Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.

rdar://10428630

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144322 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 22:10:12 +00:00
Jim Grosbach
ee10ff89a2 ARM assembly parsing for LSR/LSL/ROR(immediate). 
More of rdar://9704684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144301 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 19:18:01 +00:00
Jim Grosbach
71810ab7c0 ARM assembly parsing for ASR(immediate). 
Start of rdar://9704684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144293 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 16:44:55 +00:00
Jim Grosbach
3c5d6e4df4 Thumb2 assembly parsing STMDB w/ optional .w suffix. 
rdar://10422955


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144242 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 23:44:23 +00:00
Benjamin Kramer
70be28a5ad Simplify some uses of utohexstr. 
As a side effect hex is printed lowercase instead of uppercase now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144013 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 21:00:59 +00:00
Owen Anderson
81550dc0a8 Fix the issue that r143552 was trying to address the _right_ way. One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143557 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-02 18:03:14 +00:00
Kevin Enderby
064e48a3dc Fixed a bug in the code to create a dwarf file and directory table entires when 
it is separating the directory part from the basename of the FileName.  Noticed 
that this:

  .file 1 "dir/foo"

when assembled got the two parts switched.  Using the Mac OS X dwarfdump tool
it can be seen easily:

% dwarfdump -a a.out
include_directories[  1] = 'foo'
                Dir  Mod Time   File Len   File Name
                ---- ---------- ---------- ---------------------------
file_names[  1]    1 0x00000000 0x00000000 dir
...

Which should be:
...
include_directories[  1] = 'dir'
                Dir  Mod Time   File Len   File Name
                ---- ---------- ---------- ---------------------------
file_names[  1]    1 0x00000000 0x00000000 foo


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143521 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-01 23:39:05 +00:00