Anton Korobeynikov
dfd0dffa36
Cleanup
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75934 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 13:47:36 +00:00
Anton Korobeynikov
c8301d17a8
Add mem-imm stores
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75933 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 13:47:14 +00:00
Anton Korobeynikov
30da5380e0
[PATCH 023/155] Typo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75932 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 13:45:22 +00:00
Anton Korobeynikov
961bb6f430
Add stores and truncstores
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75931 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 13:45:00 +00:00
Anton Korobeynikov
dc28955b3f
Add patterns for various extloads
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75930 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 13:44:30 +00:00
Anton Korobeynikov
3360da9772
Do some heroic rri address matching (shamelessly stolen from x86 backend). Not tested though.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75929 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 13:44:00 +00:00
Anton Korobeynikov
4cad7d29fc
Change register allocation order, so R0 will be allocated the last among scratch. This will make address-calculation code much more happy.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75928 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 13:43:40 +00:00
Anton Korobeynikov
9e4816e09f
Add shifts and reg-imm address matching
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75927 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 13:43:18 +00:00
Anton Korobeynikov
a51752cbea
Add bunch of 32-bit patterns... Uffff :)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75926 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 13:42:31 +00:00
Anton Korobeynikov
e0167c1d5a
Add 32 bit subregs
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75923 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 13:35:30 +00:00
Anton Korobeynikov
9342d3180a
Add another bunch of reg-imm patterns for add/or/and/xor
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75922 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 13:35:08 +00:00
Anton Korobeynikov
da308c9a67
Add bunch of reg-imm movs
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75921 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 13:34:50 +00:00
Anton Korobeynikov
fc9ceeaad8
Proper match halfword-imm operands for mov and add
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75920 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 13:34:24 +00:00
Anton Korobeynikov
89edcd0927
Provide masked reg-imm 'or' and 'and'
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75919 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 13:33:57 +00:00
Anton Korobeynikov
e6220fb230
Add reg-reg and pattern
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75917 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 13:32:49 +00:00
Anton Korobeynikov
bdc9081693
Add sub reg-reg pattern
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75916 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 13:32:16 +00:00
Anton Korobeynikov
b573f99ab7
Add xor reg-reg pattern
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75915 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 13:31:28 +00:00
Anton Korobeynikov
26ba0b1ec5
Add or reg-reg pattern.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75914 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 13:30:53 +00:00
Anton Korobeynikov
0676d2887a
Add add reg-reg and reg-imm patterns
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75913 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 13:30:15 +00:00
Anton Korobeynikov
1cc9dc7267
Add simple reg-reg and reg-imm moves
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75912 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 13:29:38 +00:00
Anton Korobeynikov
87a24e3ee4
Minimal lowering for formal_arguments / ret
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75911 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 13:28:59 +00:00
Anton Korobeynikov
4403b930f8
Let's start another backend :)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75909 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 13:27:25 +00:00
Richard Osborne
db9e697725
Combine an unaligned store of unaligned load into a memmove.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75908 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 12:50:48 +00:00
Richard Osborne
787e90f862
Lower the threshold at which memcpy / memmove / memset stop being expanded
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inline in the XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75906 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 12:41:34 +00:00
Richard Osborne
ff4149b903
Fix typo in last commit on expansion of unaligned loads.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75903 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 10:48:47 +00:00
Richard Osborne
ccb7e96ef0
Expand unaligned 32 bit loads from an address which is a constant
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offset from a 32 bit aligned base as follows:
ldw low, base[offset >> 2]
ldw high, base[(offset >> 2) + 1]
shr low_shifted, low, (offset & 0x3) * 8
shl high_shifted, high, 32 - (offset & 0x3) * 8
or result, low_shifted, high_shifted
Expand 32 bit loads / stores with 16 bit alignment into two 16 bit
loads / stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75902 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 10:42:35 +00:00
Richard Osborne
7f47ce9662
Custom lower unaligned 32 bit stores and loads into libcalls. This is
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a big code size win since before they were expanding to upto 16
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75901 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 10:21:18 +00:00
Evan Cheng
378445303b
Let callers decide the sub-register index on the def operand of rematerialized instructions.
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Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75900 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 09:20:10 +00:00
Chris Lattner
6ef40b11f8
use SUBREG_TO_REG instead of INSERT_SUBREG, this way the code
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generator can know the top bits are zero, not undefined.
Thanks to Dan for pointing this out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75899 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 06:31:37 +00:00
Chris Lattner
c2b443a698
fix some casts that I improperly refactored, patch by Artur Pietrek!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75894 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 04:34:33 +00:00
Daniel Dunbar
64cc972123
Kill off <TARGET>MachineModule variables, and <TARGETASMPRINTER>ForceLink
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variables.
- Module initialization functions supplanted the need for these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75886 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 01:55:13 +00:00
Chris Lattner
fe2fe7094e
fix section switching to ensure that stubs are emitted to the right
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section on ppc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75881 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 01:23:26 +00:00
Daniel Dunbar
5d77cad60b
Lift addAssemblyEmitter into LLVMTargetMachine.
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- No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75859 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 23:34:19 +00:00
Daniel Dunbar
1e1f8ba28c
Register AsmPrinter for XCore, MSP430, and PIC16 targets.
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- Switch to standard addAssemblyEmitter logic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75854 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 23:17:20 +00:00
Daniel Dunbar
cfe9a605ee
Lift DumpAsm / -print-emitted-asm functionality into LLVMTargetMachine.
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- No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75848 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 22:33:19 +00:00
Daniel Dunbar
f05522974b
Remove old style hacks to register AsmPrinter into TargetMachine.
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- No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75843 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 22:01:32 +00:00
Owen Anderson
a90b3dc2f1
Move a few more convenience factory functions from Constant to LLVMContext.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75840 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 21:51:10 +00:00
Chris Lattner
7add5ff1d1
move createAlphaLLRPPass out of addAssemblyEmitter to make Alpha
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more like other targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75839 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 21:40:24 +00:00
Ted Kremenek
1935629829
Lexically order files in CMakeLists.txt files.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75831 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 21:08:16 +00:00
Daniel Dunbar
f1459cf1f2
Remove unused function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75829 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 20:59:20 +00:00
Bruno Cardoso Lopes
4b70fab658
use std::vector instead of std::list for both Section and Symbol lists because
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we care more about random access than insertion/deletion of elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75828 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 20:49:10 +00:00
Daniel Dunbar
f0a5ec0934
Update CMakeLists for reapplication.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75825 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 20:34:36 +00:00
Daniel Dunbar
51b198af83
Reapply TargetRegistry refactoring commits.
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--- Reverse-merging r75799 into '.':
U test/Analysis/PointerTracking
U include/llvm/Target/TargetMachineRegistry.h
U include/llvm/Target/TargetMachine.h
U include/llvm/Target/TargetRegistry.h
U include/llvm/Target/TargetSelect.h
U tools/lto/LTOCodeGenerator.cpp
U tools/lto/LTOModule.cpp
U tools/llc/llc.cpp
U lib/Target/PowerPC/PPCTargetMachine.h
U lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
U lib/Target/PowerPC/PPCTargetMachine.cpp
U lib/Target/PowerPC/PPC.h
U lib/Target/ARM/ARMTargetMachine.cpp
U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U lib/Target/ARM/ARMTargetMachine.h
U lib/Target/ARM/ARM.h
U lib/Target/XCore/XCoreTargetMachine.cpp
U lib/Target/XCore/XCoreTargetMachine.h
U lib/Target/PIC16/PIC16TargetMachine.cpp
U lib/Target/PIC16/PIC16TargetMachine.h
U lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
U lib/Target/Alpha/AlphaTargetMachine.cpp
U lib/Target/Alpha/AlphaTargetMachine.h
U lib/Target/X86/X86TargetMachine.h
U lib/Target/X86/X86.h
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
U lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
U lib/Target/X86/X86TargetMachine.cpp
U lib/Target/MSP430/MSP430TargetMachine.cpp
U lib/Target/MSP430/MSP430TargetMachine.h
U lib/Target/CppBackend/CPPTargetMachine.h
U lib/Target/CppBackend/CPPBackend.cpp
U lib/Target/CBackend/CTargetMachine.h
U lib/Target/CBackend/CBackend.cpp
U lib/Target/TargetMachine.cpp
U lib/Target/IA64/IA64TargetMachine.cpp
U lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
U lib/Target/IA64/IA64TargetMachine.h
U lib/Target/IA64/IA64.h
U lib/Target/MSIL/MSILWriter.cpp
U lib/Target/CellSPU/SPUTargetMachine.h
U lib/Target/CellSPU/SPU.h
U lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
U lib/Target/CellSPU/SPUTargetMachine.cpp
U lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
U lib/Target/Mips/MipsTargetMachine.cpp
U lib/Target/Mips/MipsTargetMachine.h
U lib/Target/Mips/Mips.h
U lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
U lib/Target/Sparc/SparcTargetMachine.cpp
U lib/Target/Sparc/SparcTargetMachine.h
U lib/ExecutionEngine/JIT/TargetSelect.cpp
U lib/Support/TargetRegistry.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75820 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 20:24:03 +00:00
Xerxes Ranby
908e058b85
Fix cmake build, add TargetMachineRegistry.cpp that got restored in r75807
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75817 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 19:58:35 +00:00
Stuart Hastings
823d9914a1
Restore file lost during reversion.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75807 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 18:30:44 +00:00
Stuart Hastings
2286f8dc4c
Revert 75762, 75763, 75766..75769, 75772..75775, 75778, 75780, 75782 to repair broken LLVM-GCC build.
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Will revert 75770 in the llvm-gcc trunk.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75799 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 17:27:11 +00:00
Richard Osborne
1d05b237a5
Fix pattern for LD16S_3r, add basic tests to check load / store instructions
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are being properly selected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75797 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 17:06:59 +00:00
David Goodwin
7ecc850cf1
Thumb-2 only support [base_reg + offset_reg] addressing, not [base_reg - offset_reg].
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75789 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 15:50:19 +00:00
Richard Osborne
3af282f16a
Fix XCoreTargetLowering::isLegalAddressingMode to handle non simple VTs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75788 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 15:46:56 +00:00
Richard Osborne
f301c2299c
Remove the xcore-file-directive option now that LLVM has proper support for
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emitting file directives with one parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75787 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 15:36:37 +00:00