Jakob Stoklund Olesen
4f3fb6d08b
Flag unallocatable register classes instead of giving them empty
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allocation orders.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132509 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02 23:07:24 +00:00
Jakob Stoklund Olesen
f462e3fac7
Make it possible to have unallocatable register classes.
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Some register classes are only used for instruction operand constraints.
They should never be used for virtual registers. Previously, those
register classes were given an empty allocation order, but now you can
say 'let isAllocatable=0' in the register class definition.
TableGen calculates if a register is part of any allocatable register
class, and makes that information available in TargetRegisterDesc::inAllocatableClass.
The goal here is to eliminate use cases for overriding allocation_order_*
methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132508 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02 23:07:20 +00:00
Tanya Lattner
201cfcd6de
Fix encoding for VEXTdf.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132486 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02 21:25:24 +00:00
Rafael Espindola
251b4a0405
Revert 132424 to fix PR10068.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132479 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02 19:57:47 +00:00
Stuart Hastings
84be958ed8
Omit unnecessary stack copy when x87 input is a load.
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rdar://problem/6373334
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132458 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02 15:57:11 +00:00
Jakob Stoklund Olesen
fa226bccaa
Use TRI::has{Sub,Super}ClassEq() where possible.
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No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132455 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02 05:43:46 +00:00
Rafael Espindola
cde4ce411b
Don't hardcode the %reg format in the streamer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132451 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02 02:34:55 +00:00
Akira Hatanaka
5e06903e66
Detect FI|cst pattern in MipsDAGToDAGISel::SelectAddr. Patch by Sasa Stankovic.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132448 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02 01:03:14 +00:00
Akira Hatanaka
2e591477af
Custom-lower FRAMEADDR. Patch by Sasa Stankovic.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132444 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02 00:24:44 +00:00
Stuart Hastings
ec880283b3
Recommit 132404 with fixes. rdar://problem/5993888
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132424 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01 21:33:14 +00:00
Stuart Hastings
4abc5fea9c
Revert 132404 to appease a buildbot. rdar://problem/5993888
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132419 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01 19:52:20 +00:00
Stuart Hastings
10ff0bbdfb
Add support for x86 CMPEQSS and friends. These instructions do a
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floating-point comparison, generate a mask of 0s or 1s, and generally
DTRT with NaNs. Only profitable when the user wants a materialized 0
or 1 at runtime. rdar://problem/5993888
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132404 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01 17:17:45 +00:00
Jakob Stoklund Olesen
1f9a09c614
Fix PR10059 and future variations by handling all register subclasses.
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Add TargetRegisterInfo::hasSubClassEq and use it to check for compatible
register classes instead of trying to list all register classes in
X86's getLoadStoreRegOpcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132398 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01 15:32:10 +00:00
Stuart Hastings
4fd0dee3bf
FGETSIGN support for x86, using movmskps/pd. Will be enabled with a
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patch to TargetLowering.cpp. rdar://problem/5660695
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132388 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01 04:39:42 +00:00
Bruno Cardoso Lopes
cada2d0966
Fix uninitialized variables and silence warnings
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132355 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-31 20:25:26 +00:00
Richard Osborne
a9b08aa25e
Fix 80 column violations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132341 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-31 16:30:33 +00:00
Richard Osborne
9497466190
Add XCore intrinsic for crc8.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132340 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-31 16:24:49 +00:00
Richard Osborne
7736c37c14
Add XCore intrinsic for crc32.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132336 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-31 14:47:36 +00:00
Bruno Cardoso Lopes
895c1e2dee
Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value
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must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132324 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-31 03:33:27 +00:00
Bruno Cardoso Lopes
4e694c96f1
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor,
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nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions.
The intrinsics are implemented by creating pseudo-instructions, which are
then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter.
Patch by Sasa Stankovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132323 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-31 02:54:07 +00:00
Bruno Cardoso Lopes
d979686bb4
This patch implements the thread local storage. Implemented are General
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Dynamic, Initial Exec and Local Exec TLS models.
Patch by Sasa Stankovic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132322 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-31 02:53:58 +00:00
Rafael Espindola
6e032942cf
Use the dwarf->llvm mapping to print register names in the cfi
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directives.
Fixes PR9826.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132317 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-30 20:20:15 +00:00
Rafael Espindola
67dc11352d
Split ppc dwarf regnums into ppc64 and ppc32 flavours.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132315 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-30 18:24:44 +00:00
Rafael Espindola
7a067cc6e0
Introduce the DwarfRegAlias class for declaring that two registers have the
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same dwarf number. This will be used for creating a dwarf number to register
mapping.
The only case that needs this so far is the XMM/YMM registers that unfortunately
do have the same numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132314 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-30 17:49:59 +00:00
Rafael Espindola
e99f75a300
Mark the 32 bit registers as invalid in 64 bit mode. In 64 bit mode they are
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subregisters of the 64 bit ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132313 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-30 16:04:54 +00:00
Rafael Espindola
053ba4fed6
Remove the DwarfNumbers from the subregisters. They should use DW_OP_bit_piece
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and for now the generic dwarf emission will automatically use the superregister
numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132312 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-30 15:56:04 +00:00
John McCall
5f8fd54f08
On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume.
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This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).
Take 2, now with more basic competence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132295 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-29 19:50:32 +00:00
John McCall
7eebab2a82
I didn't mean to commit these residues of a personal project.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132293 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-29 19:41:56 +00:00
John McCall
832a9d1a76
On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume.
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This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132291 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-29 19:39:04 +00:00
Rafael Espindola
03dc1868d1
Fix to match the dwarf register numbers that gdb uses.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132278 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-29 03:58:16 +00:00
Rafael Espindola
11fd5c0cd9
Dwarf register 0 is r0, remove incorrect entries.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132276 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-29 03:17:01 +00:00
Rafael Espindola
01eaf907b0
Remove the dwarf numbers from the D registers. They don't have dwarf numbers
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and should probably be encoded as
DW_OP_reg 32 DW_OP_piece 4 DW_OP_reg 33
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132274 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-29 02:21:01 +00:00
Cameron Zwarich
c152aa6c86
Fix ARM fast isel to correctly flag memory operands to stores. This fixes
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-verify-machineinstrs failures on several tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132268 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28 20:34:49 +00:00
Bruno Cardoso Lopes
a0112d0c39
Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairs
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to load/store i64 values. Since there's no current support to explicitly
declare such restrictions, implement it by using specific hardcoded register
pairs during isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132248 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28 04:07:29 +00:00
Eric Christopher
fea51fc007
This actually starts at offset 0, not 1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132246 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28 03:16:22 +00:00
Akira Hatanaka
5e93d1c615
Change the set of callee-saved registers for non-MIPS32 architectures specified
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in MipsRegisterInfo::getCalleeSavedRegs so that both registers paired for a
double precision register get saved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132243 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28 01:41:05 +00:00
Eric Christopher
3c14f24c9d
Implement the 'M' output modifier for arm inline asm. This is fairly
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register allocation dependent and will occasionally break. WIP in the
register allocator to model paired/etc registers.
rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132242 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28 01:40:44 +00:00
Akira Hatanaka
342837d0dc
Define a wrapper node for target constant nodes (tglobaladdr, etc.).
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Need this to prevent emitting illegal conditional move instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132240 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28 01:07:07 +00:00
Rafael Espindola
36ea4f0206
Add 132187 back now that the real problem is fixed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132238 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28 00:24:37 +00:00
Cameron Zwarich
de64aaf6c8
Fix the remaining atomic intrinsics to use the right register classes on Thumb2,
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and add some basic tests for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132235 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 23:54:00 +00:00
Bruno Cardoso Lopes
be64b39431
ARM asm parser wasn't able to parse a "mov" instruction while in Thumb
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mode (only the "mov.w" variant). Now, when parsing "mov" in thumb mode,
default to the Thumb 1 versions/encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132233 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 23:46:09 +00:00
Rafael Espindola
157371f376
It looks like 132187 might have broken the llvm-gcc bootstrap. Revert while I check.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132230 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 23:36:02 +00:00
Cameron Zwarich
f5e771db37
Add a GR32_NOREX_NOSP register class and fix a bug where getMatchingSuperRegClass()
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was saying that the matching superregister class of GR32_NOREX in GR64_NOREX_NOSP
is GR64_NOREX, which drops the NOSP constraint. This fixes PR10032.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132225 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 22:26:04 +00:00
Rafael Espindola
5b23b7fe31
Make size computation less brittle.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132222 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 22:05:41 +00:00
Evan Cheng
4abce0c90b
Don't use movw / movt for iOS static codegen for now to workaround some tools issues. rdar://9514789
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132211 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 20:11:27 +00:00
Jakob Stoklund Olesen
11f6cc96bf
Delete MethodBodies that only filtered reserved registers.
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The register allocators know to filter reserved registers from the allocation
orders, so we don't need all of this boilerplate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132199 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 18:27:13 +00:00
Eli Friedman
a4d487fc1e
Fix a silly mistake (which trips over an assertion) in r132099. rdar://9515076
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132194 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 18:02:04 +00:00
Rafael Espindola
25b15d8502
Remove DwarfRegNum from the individual bits of the condition register.
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These should be DW_OP_bit_piece of CR (64).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132192 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 16:15:27 +00:00
Rafael Espindola
81a2745830
Remove DwarfRegNum from CARRY. I should be encoded with DW_OP_bit_piece.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132190 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 16:01:08 +00:00
Rafael Espindola
81e193cc1f
Remove dwarf numbers from subregs. We should use DW_OP_bit_piece to
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refer to them.
I tested this with both check-all and the gdb testsuite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132187 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 15:08:24 +00:00
Eric Christopher
33281b2361
Make the branch encoding for tBcc more obvious that it's a 4-byte opcode
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followed by a conditional and imm8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132179 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 03:50:53 +00:00
Eric Christopher
86bbcbf4b0
Fix comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132178 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 03:46:51 +00:00
Chad Rosier
62660310d9
Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist.
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crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and
crc64.[8|16|32] have been renamed to .crc32.64.[8|64].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132163 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 23:13:19 +00:00
Akira Hatanaka
33458fedb6
Use MachineFrameInfo::hasCalls instead of MipsFunctionInfo::hasCall to check if
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a function has any function calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132140 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 20:30:31 +00:00
Rafael Espindola
a5e62019d7
Fix some dwarf register numbers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132136 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 19:25:47 +00:00
Akira Hatanaka
cf0cd8005c
Add support for C++ exception handling.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132131 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 18:59:03 +00:00
Eric Christopher
32bfb2c513
Reorganize these slightly according to operand type.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132128 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 18:22:26 +00:00
Akira Hatanaka
78e72d60ec
Set HasSetDirective to true.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132127 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 18:16:18 +00:00
Stuart Hastings
2aa0f23e1c
Reverting 132105: it broke some LLVM-GCC DejaGNU tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132108 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 04:09:49 +00:00
Cameron Zwarich
421b106872
Mark tBX as an indirect branch rather than a return.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132107 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 03:41:12 +00:00
Stuart Hastings
aa4e6afc9b
Correctly handle a one-word struct passed byval on x86_64.
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rdar://problem/6920088
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132105 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 02:44:56 +00:00
Eli Friedman
76927d7303
Rewrite fast-isel integer cast handling to handle more cases, and to be simpler and more consistent.
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The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts).
rdar://9437928 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132099 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 23:49:02 +00:00
Akira Hatanaka
37d22d92df
Define WeakRefDirective.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132098 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 23:30:30 +00:00
Cameron Zwarich
ad70f6d2b1
Convert tBX_CALL / tBXr9_CALL to actual pseudoinstructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132086 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 21:53:50 +00:00
Eric Christopher
7bb1c40549
Clean up comment a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132083 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 21:19:19 +00:00
Eric Christopher
8f89463894
Implement the 'm' modifier. Note that it only works for memory operands.
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Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132081 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 20:51:58 +00:00
Akira Hatanaka
d85b3ecbb3
Remove MipsTargetLowering::LowerFP_TO_SINT. Patterns for fp_to_sint have already
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been defined in MipsInstrFPU.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132076 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 20:08:05 +00:00
Akira Hatanaka
9c3d57c45e
Custom-lower FCOPYSIGN nodes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132074 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 19:32:07 +00:00
Eli Friedman
783c66414a
Prepare ARMFastISel::SelectSIToFP for getRegForValue returning registers for i8 and i16 values.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132073 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 19:09:45 +00:00
Akira Hatanaka
4c62f765a3
Update MaxCallFrameSize regardless of the relocation model selected.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132070 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 18:08:32 +00:00
Akira Hatanaka
f15f498507
Change initial value of MaxCallFrameSize. MipsFI::getMaxCallFrameSize() should
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return 0 if there are no function calls made.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132065 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 17:52:48 +00:00
Akira Hatanaka
edacba83dc
Coding style fixes. Added comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132063 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 17:32:06 +00:00
Francois Pichet
1b47720391
Remove unused OpcodeMask enumerator.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132062 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 17:02:53 +00:00
Francois Pichet
d9e57c146d
Fix MSVC warning: "is out of range for enum constant"
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MSVC doesn't support 64 bit enum.
OpcodeMask is not used anywhere in the code base.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132057 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 15:58:10 +00:00
Cameron Zwarich
da86a08284
Restore an accidentally removed comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132044 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 04:48:17 +00:00
Cameron Zwarich
8e9bace414
Move some code to a more logical place.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132043 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 04:45:29 +00:00
Cameron Zwarich
106acd4158
Make tTAILJMPr/tTAILJMPrND emit a tBX without a preceding MOV of PC to LR. This
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fixes <rdar://problem/9495913>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132042 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 04:45:27 +00:00
Cameron Zwarich
328634598f
Change the order of tBX's operands so that the predicate operands come after the
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target register, matching BX. I filed this bug because I was confused at first:
PR10007 - ARM branch instructions have inconsistent predicate operand placement
<http://llvm.org/bugs/show_bug.cgi?id=10007 >
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132041 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 04:45:23 +00:00
Cameron Zwarich
8f161c3a95
Rename tBX_Rm to tBX.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132040 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 04:45:20 +00:00
Cameron Zwarich
b36c1ae6d5
Rename the existing tBX/tBXr9 instructions to tBX_CALL/tBXr9_CALL to better
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reflect their actual meaning and match the ARM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132039 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 04:45:14 +00:00
Rafael Espindola
fc2bb8c444
Replace the -unwind-tables option with a per function flag. This is more
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LTO friendly as we can now correctly merge files compiled with or without
-fasynchronous-unwind-tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132033 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 03:44:17 +00:00
Akira Hatanaka
053546c31e
Fix lowering of DYNAMIC_STACKALLOC nodes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132030 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 02:20:00 +00:00
Bruno Cardoso Lopes
56926a3961
Fix PR9762
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Enable the parsing of the operand "cpsr_all" for the ARM msr instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132026 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 00:35:03 +00:00
Eric Christopher
4db7dec70b
Implement the arm 'L' asm modifier.
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Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132024 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-24 23:27:13 +00:00
Eric Christopher
e1739d598d
Implement the immediate part of the 'B' modifier.
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Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132023 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-24 23:15:43 +00:00
Eric Christopher
fef50062ea
Add more unimplemented asm modifiers and some documentation of what they
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do.
Part of rdar://9119939.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132015 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-24 22:27:43 +00:00
Eric Christopher
0628d38085
Add support for the arm 'y' asm modifier.
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Fixes part of rdar://9444657
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132011 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-24 22:10:34 +00:00
Akira Hatanaka
ce98deb9f5
Enable printing of immediates that do not fit in 16-bit. .cprestore can have
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offsets that are larger than 0x10000.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-24 21:22:21 +00:00
Akira Hatanaka
4231c7ea6d
Implement byval structure argument passing. The following limitations or
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deficiencies exist:
- Works only if ABI is o32.
- Zero-sized structures cannot be passed.
- There is a lot of redundancy in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131986 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-24 19:18:33 +00:00
Devang Patel
8ec0c1c07b
Remove dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131974 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-24 18:27:52 +00:00
Charles Davis
6b918b8466
Add a method to TargetRegisterInfo to get the register number that the Win64 EH
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scheme uses internally. Implement it for x86 (the only architecture that LLVM
supports for which this matters right now).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131969 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-24 16:57:53 +00:00
Evan Cheng
b5a55d979c
- Teach SelectionDAG::isKnownNeverZero to return true (op x, c) when c is
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non-zero.
- Teach X86 cmov optimization to eliminate the cmov from ctlz, cttz extension
when the source of X86ISD::BSR / X86ISD::BSF is proven to be non-zero.
rdar://9490949
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131948 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-24 01:48:22 +00:00
Akira Hatanaka
b4d8d31e59
Simplify offset calculation of stack frame objects for $gp restore location and
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variable arguments in LowerCall and LowerFormalArguments. This should also fix
the bug in which handling of variable arguments is incorrect when the front-end
optimizes away unused fixed arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131942 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-24 00:23:52 +00:00
Akira Hatanaka
46da136ec7
Expand f64 FPOW.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131928 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-23 22:23:58 +00:00
Akira Hatanaka
f89532f8f6
Add pattern for double-to-integer conversion. Patch by Sasa Stankovic.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131927 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-23 22:16:43 +00:00
Akira Hatanaka
bdd2ce9741
Fixes related to coding style.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131922 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-23 21:13:59 +00:00
Akira Hatanaka
f8928c07e7
Fix MipsAsmPrinter::printSavedRegsBitmaskChange. Remove functions and variables
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in MipsFunctionInfo that are no longer used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131917 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-23 20:34:30 +00:00
Chris Lattner
32232fc2b5
clarify this, apparently it is confusing :)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131916 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-23 20:17:44 +00:00
Akira Hatanaka
69c19f7316
Change StackDirection from StackGrowsUp to StackGrowsDown.
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The following improvements are accomplished as a result of applying this patch:
- Fixed frame objects' offsets (relative to either the virtual frame pointer or
the stack pointer) are set before instruction selection is completed. There is
no need to wait until Prologue/Epilogue Insertion is run to set them.
- Calculation of final offsets of fixed frame objects is straightforward. It is
no longer necessary to assign negative offsets to fixed objects for incoming
arguments in order to distinguish them from the others.
- Since a fixed object has its relative offset set during instruction
selection, there is no need to conservatively set its alignment to 4.
- It is no longer necessary to reorder non-fixed frame objects in
MipsFrameLowering::adjustMipsStackFrame.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131915 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-23 20:16:59 +00:00
Cameron Zwarich
d34d429401
Fix <rdar://problem/9476260> by having tail calls always generate 32-bit branches
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in Darwin Thumb2 code. Tail calls are already disabled on Thumb1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131894 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-23 01:57:17 +00:00