Commit Graph

1137 Commits

Author SHA1 Message Date
Bob Wilson
1f595bb429 Use CallConvLower.h and TableGen descriptions of the calling conventions
for ARM.  Patch by Sandeep Patel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69371 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-17 19:07:39 +00:00
Dan Gohman
7beace5d06 Fix doxygen comment syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69128 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-15 01:44:07 +00:00
Dan Gohman
88c7af096b Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalize
it accordingly. Thanks to Jakob Stoklund Olesen for pointing
out how this might be useful.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 21:06:25 +00:00
Devang Patel
0f7fef3872 Reapply 68847.
Now debug_inlined section is covered by TAI->doesDwarfUsesInlineInfoSection(), which is false by default.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68964 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 17:02:03 +00:00
Dan Gohman
f8c7394781 Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.
This will be used to replace things like X86's MOV32to32_.

Enhance ScheduleDAGSDNodesEmit to be more flexible and robust
in the presense of subregister superclasses and subclasses. It
can now cope with the definition of a virtual register being in
a subclass of a use.

Re-introduce the code for recording register superreg classes and
subreg classes. This is needed because when subreg extracts and
inserts get coalesced away, the virtual registers are left in
the correct subclass.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68961 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 15:38:05 +00:00
Dan Gohman
73099b1058 Add comments to INSERT_SUBREG, EXTRACT_SURBEG, SUBREG_TO_REG,
and IMPLICIT_DEF.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68949 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 15:12:29 +00:00
Owen Anderson
ddeed50d76 Use a hashtable for TargetRegisterClass::contains.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68922 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-12 22:31:17 +00:00
Chris Lattner
0461c0a8f5 Add new TargetInstrDesc::hasImplicitUseOfPhysReg and
hasImplicitDefOfPhysReg methods.  Use them to remove a 
look in X86 fast isel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68886 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-12 07:26:51 +00:00
Dan Gohman
c6fa3ff0bd Revert r68847. It breaks the build on non-Darwin targets, with this message
from the assembler:

Error: unknown pseudo-op: `.debug_inlined'


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68863 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-11 15:57:04 +00:00
Devang Patel
2057532679 Keep track of inlined functions and their locations. This information is collected when nested llvm.dbg.func.start intrinsics are seen. (Right now, inliner removes nested llvm.dbg.func.start intrinisics during inlining.)
Create debug_inlined dwarf section using these information. This info is used by gdb, at least on Darwin, to enable better experience debugging inlined functions. See DwarfWriter.cpp for more information on structure of debug_inlined section.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68847 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-11 00:16:47 +00:00
Owen Anderson
3ca15c989c Give register alias checking the hash table treatment too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68730 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-09 22:19:30 +00:00
Bob Wilson
d9df501704 Fix pr3954. The register scavenger asserts for inline assembly with
register destinations that are tied to source operands.  The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly.  The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68714 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-09 17:16:43 +00:00
Owen Anderson
7d770be047 Convert TargetRegisterInfo's super-register checking to use a pre-computed hash table just like subregister checking does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68669 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-09 03:50:16 +00:00
Dan Gohman
97121ba2af Implement support for using modeling implicit-zero-extension on x86-64
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.

This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.

Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.

Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.

Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.

Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68576 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-08 00:15:30 +00:00
Jim Grosbach
30eae3c022 PR2985 / <rdar://problem/6584986>
When compiling in Thumb mode, only the low (R0-R7) registers are available
for most instructions. Breaking the low registers into a new register class
handles this. Uses of R12, SP, etc, are handled explicitly where needed
with copies inserted to move results into low registers where the rest of
the code generator can deal with them.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68545 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-07 20:34:09 +00:00
Chris Lattner
41c90738e9 "This adds a getName() method to TargetRegisterClass, just like in TargetRegisterInfo.
This makes debugging register classes a bit easier."

Patch by Jakob Stoklund Olesen!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68400 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-03 20:25:41 +00:00
Dan Gohman
8f9643f0f7 Delete ISD::INSERT_SUBREG and ISD::EXTRACT_SUBREG, which are unused.
Note that these are distinct from TargetInstrInfo::INSERT_SUBREG
and TargetInstrInfo::EXTRACT_SUBREG, which are used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68355 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-03 00:25:26 +00:00
Anton Korobeynikov
fca82deecb Do not propagate ELF-specific stuff (data.rel) into other targets. This simplifies code and also ensures correctness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68032 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-30 15:27:43 +00:00
Anton Korobeynikov
71a7c6cde0 Add data.rel stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68031 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-30 15:27:03 +00:00
Anton Korobeynikov
db2323148b Honour relocation behaviour stuff for ro objects
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68005 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-29 17:13:49 +00:00
Arnold Schwaighofer
e75fd69f15 Enable tail call optimization for functions that return a struct (bug 3664) and for functions that return types that need extending (e.g i1).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67934 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-28 08:33:27 +00:00
Evan Cheng
0b0cd9113a Optimize some 64-bit multiplication by constants into two lea's or one lea + shl since imulq is slow (latency 5). e.g.
x * 40
=>
shlq    $3, %rdi
leaq    (%rdi,%rdi,4), %rax

This has the added benefit of allowing more multiply to be folded into addressing mode. e.g.
a * 24 + b
=>
leaq    (%rdi,%rdi,2), %rax
leaq    (%rsi,%rax,8), %rax


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67917 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-28 05:57:29 +00:00
Evan Cheng
42bf74be14 CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67668 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-25 01:47:28 +00:00
Mon P Wang
bc65ca8de5 Added option to enable generating less precise mad (multiply addition)
for those architectures that support the instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67363 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-20 05:06:58 +00:00
Bill Wendling
f9abd7e33e Add a -no-implicit-float flag. This acts like -soft-float, but may generate
floating point instructions that are explicitly specified by the user.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66719 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-11 22:30:01 +00:00
Dan Gohman
0f8b53f19d Fix a bunch of Doxygen syntax issues. Escape special characters,
and put @file directives on their own comment line.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65920 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-03 02:55:14 +00:00
Rafael Espindola
9a58023c6c Refactor TLS code and add some tests. The tests and expected results are:
pic |  declaration | linkage  | visibility |

!pic |  declaration | external | default    | tls1.ll     tls2.ll     | local exec
 pic |  declaration | external | default    | tls1-pic.ll tls2-pic.ll | general dynamic
!pic | !declaration | external | default    | tls3.ll     tls4.ll     | initial exec
 pic | !declaration | external | default    | tls3-pic.ll tls4-pic.ll | general dynamic

!pic |  declaration | external | hidden     | tls7.ll     tls8.ll     | local exec
 pic |  declaration | external | hidden     | X                       | local dynamic
!pic | !declaration | external | hidden     | tls9.ll     tls10.ll    | local exec
 pic | !declaration | external | hidden     | X                       | local dynamic

!pic |  declaration | internal | default    | tls5.ll     tls6.ll     | local exec
 pic |  declaration | internal | default    | X                       | local dynamic

The ones marked with an X have not been implemented since local dynamic is not implemented.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65632 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-27 13:37:18 +00:00
Mon P Wang
0d52ff1f7b Added support to have TableGen provide information if an intrinsic (core
or target) can be overloaded or not.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65404 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-24 23:17:49 +00:00
Dale Johannesen
c1c9d7e6a9 Describe tail merging's use of InsertBranch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65062 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-19 19:40:21 +00:00
Nate Begeman
d6b7a242d3 Add support to the JIT for true non-lazy operation. When a call to a function
that has not been JIT'd yet, the callee is put on a list of pending functions
to JIT.  The call is directed through a stub, which is updated with the address
of the function after it has been JIT'd.  A new interface for allocating and
updating empty stubs is provided.

Add support for removing the ModuleProvider the JIT was created with, which
would otherwise invalidate the JIT's PassManager, which is initialized with the
ModuleProvider's Module.

Add support under a new ExecutionEngine flag for emitting the infomration 
necessary to update Function and GlobalVariable stubs after JITing them, by
recording the address of the stub and the name of the GlobalValue.  This allows
code to be copied from one address space to another, where libraries may live
at different virtual addresses, and have the stubs updated with their new
correct target addresses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64906 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-18 08:31:02 +00:00
Dan Gohman
865f006bb4 Eliminate several more unnecessary intptr_t casts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64888 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-18 05:09:16 +00:00
Evan Cheng
dc54d317e7 Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty
suprise to some callers, e.g. register coalescer. For now, add an parameter
that tells AnalyzeBranch whether it's safe to modify the mbb. A better
solution is out there, but I don't have time to deal with it right now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64124 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-09 07:14:22 +00:00
Dan Gohman
1fdbc1dd4e Constify TargetInstrInfo::EmitInstrWithCustomInserter, allowing
ScheduleDAG's TLI member to use const.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64018 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-07 16:15:20 +00:00
Evan Cheng
37059d52b7 We don't really need the abort here. This unbreak x86_64 linux build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63940 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-06 17:51:34 +00:00
Evan Cheng
770bcc7b15 Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63938 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-06 17:43:24 +00:00
Evan Cheng
4350eb86a7 Add TargetInstrInfo::isSafeToMoveRegisterClassDefs. It returns true if it's safe to move an instruction which defines a value in the register class. Replace pre-splitting specific IgnoreRegisterClassBarriers with this new hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63936 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-06 17:17:30 +00:00
Evan Cheng
b3a021cdb3 Change -1 => negative number.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63935 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-06 17:12:56 +00:00
Evan Cheng
6f8d762e6b Document the meaning of -1 for getCopyCost.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63933 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-06 17:01:33 +00:00
Evan Cheng
758d20f653 Clarify comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63851 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-05 08:41:53 +00:00
Dale Johannesen
49de98214b Reapply 63765. Patches for clang and llvm-gcc to follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63812 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-05 01:49:45 +00:00
Dale Johannesen
4d452de150 Reverting 63765. This broke the build of both clang
and llvm-gcc.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63786 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-04 22:47:25 +00:00
Nate Begeman
d24479730a New feature: add support for target intrinsics being defined in the
target directories themselves.  This also means that VMCore no longer
needs to know about every target's list of intrinsics.  Future work
will include converting the PowerPC target to this interface as an
example implementation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63765 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-04 19:47:21 +00:00
Chris Lattner
e20e790074 add a friend needed by a stringmap change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63706 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-04 01:51:53 +00:00
Dale Johannesen
0f502f6f44 Add some DL propagation to places that didn't
have it yet.  More coming.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63673 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-03 22:26:09 +00:00
Dale Johannesen
ff97d4fe81 Propagation in TargetLowering. Includes passing a DL
into SimplifySetCC which gets called elsewhere.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63583 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-03 00:47:48 +00:00
Sanjiv Gupta
3b020feb57 Made the common case of default address space directive as non-virtual for performance reasons. Provide a single virtual interface for directives of all sizes in non-default address spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63521 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-02 16:53:06 +00:00
Dale Johannesen
f8a0a763d5 Fix build on case-sensitive filesystems (i.e. everybody else)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63448 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-30 23:20:42 +00:00
Dale Johannesen
7d2ad624fa Make LowerCallTo and LowerArguments take a DebugLoc
argument.  Adjust all callers and overloaded versions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63444 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-30 23:10:59 +00:00
Sanjiv Gupta
c8d7bc850d Enable emitting of constant values in non-default address space as well. The APIs emitting constants now take an additional parameter signifying the address space in which to emit. The APIs like getData8BitsDirective() etc are made virtual enabling targets to be able to define appropirate directivers for various sizes and address spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63377 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-30 04:25:10 +00:00
Dan Gohman
e5af2d3a22 Make x86's BT instruction matching more thorough, and add some
dagcombines that help it match in several more cases. Add
several more cases to test/CodeGen/X86/bt.ll. This doesn't
yet include matching for BT with an immediate operand, it
just covers more register+register cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63266 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-29 01:59:02 +00:00
Dan Gohman
f560ffae1f Make isOperationLegal do what its name suggests, and introduce a
new isOperationLegalOrCustom, which does what isOperationLegal
previously did.

Update a bunch of callers to use isOperationLegalOrCustom
instead of isOperationLegal. In some case it wasn't obvious
which behavior is desired; when in doubt I changed then to
isOperationLegalOrCustom as that preserves their previous
behavior.

This is for the second half of PR3376.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63212 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-28 17:46:25 +00:00
Scott Michel
210de72cd7 Make the Dwarf macro information section optional; CellSPU's assembler
doesn't support it. The default is set to 'true', so this should not
impact any other target backends.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63058 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-26 22:32:51 +00:00
Dan Gohman
92f4f16a19 Implement Red Zone utilization on x86-64. This is currently
disabled by default; I'll enable it when I hook it up with
the llvm-gcc flag which controls it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63056 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-26 22:22:31 +00:00
Evan Cheng
8c08d8c77c Cross register class coalescing. Not yet enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62832 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-23 02:15:19 +00:00
Evan Cheng
536ab130ec Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62762 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-22 09:10:11 +00:00
Duncan Sands
9fbc7e2e7a Cleanup whitespace and comments, and tweak some
prototypes, in operand type legalization.  No
functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62680 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-21 09:00:29 +00:00
Sanjiv Gupta
bb326bbe88 Allow targets to legalize operations (with illegal operands) that produces multiple values. For example, a load with an illegal operand (a load produces two values, a value and chain).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62663 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-21 04:48:39 +00:00
Evan Cheng
04ee5a1d92 Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62600 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-20 19:12:24 +00:00
Mikhail Glushenkov
2388a588bd Registry.h should not depend on CommandLine.h.
Split Support/Registry.h into two files so that we have less to
recompile every time CommandLine.h is changed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62312 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-16 07:02:28 +00:00
Mikhail Glushenkov
5c1799b293 Delete trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62307 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-16 06:53:46 +00:00
Dan Gohman
c13cf130c4 Make getWidenVectorType const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62265 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-15 17:34:08 +00:00
Dan Gohman
73e0914848 Const-qualify getPreIndexedAddressParts and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62259 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-15 16:29:45 +00:00
Devang Patel
83489bb770 Use DebugInfo interface to lower dbg_* intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62127 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-13 00:35:13 +00:00
Duncan Sands
ceb4d1aecb Rename getABITypeSize to getTypePaddedSize, as
suggested by Chris.


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2009-01-12 20:38:59 +00:00
Chris Lattner
6688d75114 fit in 80 cols
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2009-01-09 04:58:01 +00:00
Bill Wendling
d60de51878 Revert r61415 and r61484. Duncan was correct that these weren't needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61765 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-05 22:53:45 +00:00
Duncan Sands
676b9dfe2f Add a note about passing MVT::Other to getSetCCResultType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61756 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-05 21:33:06 +00:00
Dan Gohman
50b84f44e4 Add <climits>, to get the definition of CHAR_BIT. This should fix
build errors.


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2009-01-05 19:47:30 +00:00
Dan Gohman
11df7e5157 TargetLowering.h #includes SelectionDAGNodes.h, so it doesn't need its
own OpActionsCapacity magic number; it can just use ISD::BUILTIN_OP_END,
as long as it takes care to round up when needed.


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2009-01-05 19:40:39 +00:00
Dan Gohman
d68a07650c Tidy up #includes, deleting a bunch of unnecessary #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61715 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-05 17:59:02 +00:00
Duncan Sands
5480c0469e Fix PR3274: when promoting the condition of a BRCOND node,
promote from i1 all the way up to the canonical SetCC type.
In order to discover an appropriate type to use, pass
MVT::Other to getSetCCResultType.  In order to be able to
do this, change getSetCCResultType to take a type as an
argument, not a value (this is also more logical).


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2009-01-01 15:52:00 +00:00
Bill Wendling
998dee96d3 Linux wants the FDE initial location and address range to be forced to 32-bit.
Darwin doesn't. Make this optional for platforms.


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2008-12-29 22:12:11 +00:00
Bill Wendling
722f5f1cfb Darwin likes for the EH frame to be non-local.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61420 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-24 08:05:17 +00:00
Bill Wendling
d4121bef3c GCC doesn't emit DW_EH_PE_sdata4 for the FDE encoding on Darwin. I'm not sure
about other platforms.


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2008-12-24 05:25:49 +00:00
Dan Gohman
0b1d4a798d Clean up the atomic opcodes in SelectionDAG.
This removes all the _8, _16, _32, and _64 opcodes and replaces each
group with an unsuffixed opcode. The MemoryVT field of the AtomicSDNode
is now used to carry the size information. In tablegen, the size-specific
opcodes are replaced by size-independent opcodes that utilize the
ability to compose them with predicates.

This shrinks the per-opcode tables and makes the code that handles
atomics much more concise.


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2008-12-23 21:37:04 +00:00
Dan Gohman
b5544940c1 Clarify a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61338 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-22 19:44:39 +00:00
Rafael Espindola
2f6fea90a5 Fix bug 3202.
The EH_frame and .eh symbols are now private, except for darwin9 and earlier.
The patch also fixes the definition of PrivateGlobalPrefix on pcc linux.



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2008-12-19 10:55:56 +00:00
Mon P Wang
87c8a8f304 Added support for vector widening.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61209 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-18 20:03:17 +00:00
Dan Gohman
8749b61178 Add initial support for back-scheduling address computations,
especially in the case of addresses computed from loop induction
variables.


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2008-12-16 03:35:01 +00:00
Dan Gohman
2b00aebda9 Fix a typo in a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61035 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-15 17:26:50 +00:00
Evan Cheng
5788d1a169 Fix MachineCodeEmitter to use uintptr_t instead of intptr_t. This avoids some overflow issues. Patch by Thomas Jablin.
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2008-12-10 02:32:19 +00:00
Bill Wendling
74c3765291 Add sub/mul overflow intrinsics. This currently doesn't have a
target-independent way of determining overflow on multiplication. It's very
tricky. Patch by Zoltan Varga!


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2008-12-09 22:08:41 +00:00
Dan Gohman
5fb580efd6 Fix the name of ISD::TokenFactor in a comment. Thanks Gabor!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60736 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-09 02:18:52 +00:00
Chris Lattner
bedb8c1d35 introduce a new RoundUpAlignment helper function, use it to
remove some more 64-bit divs and rems from the StructLayout 
ctor.


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2008-12-08 07:11:56 +00:00
Chris Lattner
0a3ba71a05 Speed up getABITypeSize by turning a i64 mul and div into an
AND.  This is speedup on any reasonable target, but particularly
on 32-bit targets where this often turns into a libcall like udivdi3.

We know that alignments are a power of two but the compiler doesn't.


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2008-12-08 06:50:51 +00:00
Dan Gohman
fb4b58c9aa Clarify a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60685 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-08 04:54:58 +00:00
Dan Gohman
c54baa2d43 Split foldMemoryOperand into public non-virtual and protected virtual
parts, and add target-independent code to add/preserve
MachineMemOperands.


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2008-12-03 18:43:12 +00:00
Dan Gohman
15511cf166 Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60487 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-03 18:15:48 +00:00
Rafael Espindola
952b839ce9 Fix bug 3140.
Print a single parameter .file directive if we have an ELF target.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60480 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-03 11:01:37 +00:00
Dan Gohman
62c939d7d5 Mark x86's V_SET0 and V_SETALLONES with isSimpleLoad, and teach X86's
foldMemoryOperand how to "fold" them, by converting them into constant-pool
loads. When they aren't folded, they use xorps/cmpeqd, but for example when
register pressure is high, they may now be folded as memory operands, which
reduces register pressure.

Also, mark V_SET0 isAsCheapAsAMove so that two-address-elimination will
remat it instead of copying zeros around (V_SETALLONES was already marked).


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2008-12-03 05:21:24 +00:00
Duncan Sands
1607f05cb7 Change the interface to the type legalization method
ReplaceNodeResults: rather than returning a node which
must have the same number of results as the original
node (which means mucking around with MERGE_VALUES,
and which is also easy to get wrong since SelectionDAG
folding may mean you don't get the node you expect),
return the results in a vector.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60348 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-01 11:39:25 +00:00
Duncan Sands
25cf2275ff If the type legalizer actually legalized anything
(this doesn't happen that often, since most code
does not use illegal types) then follow it by a
DAG combiner run that is allowed to generate
illegal operations but not illegal types.  I didn't
modify the target combiner code to distinguish like
this between illegal operations and illegal types,
so it will not produce illegal operations as well
as not producing illegal types.


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2008-11-24 14:53:14 +00:00
Evan Cheng
027fdbe3ba Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59953 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-24 07:34:46 +00:00
Duncan Sands
03228089d5 Rename SetCCResultContents to BooleanContents. In
practice these booleans are mostly produced by SetCC,
however the concept is more general.


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2008-11-23 15:47:28 +00:00
Dan Gohman
c8c2827993 Implement ComputeLatency for MachineInstr ScheduleDAGs. Factor
some of the latency computation logic out of the SDNode
ScheduleDAG code into a TargetInstrItineraries helper method
to help with this.


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2008-11-21 00:12:10 +00:00
Dan Gohman
eb3904bc25 Delete redundant inline keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59754 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-20 22:10:21 +00:00
Dan Gohman
33372a18c5 Doxygenate comments.
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2008-11-20 22:09:52 +00:00
Dan Gohman
cbad42cfd1 Add more const qualifiers. This fixes build breakage from r59540.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59542 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-18 19:49:32 +00:00
Dale Johannesen
330169fa3e Extend InlineAsm::C_Register to allow multiple specific registers
(actually, code already all worked, only the comment
changed).  Use this to implement 'A' constraint on x86.
Fixes PR 1779.



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2008-11-13 21:52:36 +00:00
Evan Cheng
9ed2f80910 Rename isGVNonLazyPtr to isIndirectSym to reflect how it will be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58949 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-10 01:08:07 +00:00