more fixes to settings import/export

* fix compatibility with Windows
* add RAW export option

ip/altera_epcq_controller_mod/altera_epcq_controller.sv

@@ -1,611 +0,0 @@
-// (C) 2001-2015 Altera Corporation. All rights reserved.
-// Your use of Altera Corporation's design tools, logic functions and other 
-// software and tools, and its AMPP partner logic functions, and any output 
-// files any of the foregoing (including device programming or simulation 
-// files), and any associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License Subscription 
-// Agreement, Altera MegaCore Function License Agreement, or other applicable 
-// license agreement, including, without limitation, that your use is for the 
-// sole purpose of programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the applicable 
-// agreement for further details.
-
-
-// (C) 2001-2015 Altera Corporation. All rights reserved.
-// Your use of Altera Corporation's design tools, logic functions and other 
-// software and tools, and its AMPP partner logic functions, and any output 
-// files any of the foregoing (including device programming or simulation 
-// files), and any associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License Subscription 
-// Agreement, Altera MegaCore Function License Agreement, or other applicable 
-// license agreement, including, without limitation, that your use is for the 
-// sole purpose of programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the applicable 
-// agreement for further details.
-
-
-
-`timescale 1ps / 1ps
-
-module altera_epcq_controller #(
-	parameter CS_WIDTH		= 1,
-	parameter ENABLE_4BYTE_ADDR = 1,
-	parameter ADDR_WIDTH	= 22,
-	parameter ASI_WIDTH		= 1,
-	parameter DEVICE_FAMILY = "CYCLONE V",
-	parameter ASMI_ADDR_WIDTH = 22,
-	parameter CHIP_SELS = 1
-)(
-	input 	wire		  								clk,
-	input 	wire		  								reset_n,
-	                                        			
-	// ports to access csr                        			
-	input 	wire										avl_csr_write,
-	input 	wire		  								avl_csr_read,
-	input 	wire 	[2:0] 								avl_csr_addr,
-	input 	wire 	[31:0] 								avl_csr_wrdata,
-	output 	reg 	[31:0] 								avl_csr_rddata,
-	output 	reg 		 								avl_csr_rddata_valid,
-	output 	reg 			 							avl_csr_waitrequest,
-	                                        			
-	// ports to access memory        			
-	input	wire		  								avl_mem_write,
-	input	wire										avl_mem_read,
-	input	wire  	[ADDR_WIDTH-1:0]					avl_mem_addr,			
-	input	wire	[31:0]								avl_mem_wrdata,
-	input	wire 	[3:0]								avl_mem_byteenable,
-	input	wire	[6:0]								avl_mem_burstcount,
-	output	wire	[31:0]								avl_mem_rddata,
-	output	reg											avl_mem_rddata_valid,
-	output 	reg 			 							avl_mem_waitrequest,
-	
-	// interrupt signal
-	output	reg 										irq,
-	
-	// Disable dedicated active serial interface
-	input  	wire	[ASI_WIDTH-1:0]						epcq_dataout,
-	output  reg											epcq_dclk,
-	output  reg		[CS_WIDTH-1:0] 						epcq_scein,
-	output  reg		[ASI_WIDTH-1:0]						epcq_sdoin,
-	output  reg		[ASI_WIDTH-1:0]						epcq_dataoe,
-	
-	// ASMI PARALLEL interface
-	input   wire	[ASI_WIDTH-1:0]						ddasi_dataoe,
-	output  reg 	[ASI_WIDTH-1:0]						ddasi_dataout,
-	input   wire 										ddasi_dclk,
-	input   wire 	[CS_WIDTH-1:0] 						ddasi_scein,
-	input   reg		[ASI_WIDTH-1:0]  					ddasi_sdoin,
-	
-	input   wire										asmi_busy,
-	input   wire										asmi_data_valid,
-	input   wire	[7:0]  								asmi_dataout,
-	output  reg											asmi_clkin,
-	output  reg											asmi_reset,
-	output  reg		[CS_WIDTH-1:0] 						asmi_sce,
-	output	reg	    [ASMI_ADDR_WIDTH-1:0]  				asmi_addr,
-	output  reg		[7:0]  								asmi_datain,
-	output  reg											asmi_fast_read,
-	output  wire										asmi_rden,
-	output  reg											asmi_shift_bytes,
-	output  reg 										asmi_en4b_addr,
-	output  wire										asmi_wren,
-	output  reg											asmi_write,
-	
-	input   wire										asmi_illegal_erase,
-	input   wire										asmi_illegal_write,
-	input   wire	[7:0]  								asmi_rdid_out,
-	input   wire	[7:0]  								asmi_status_out,
-	input   wire	[7:0]  								asmi_epcs_id,
-	output  reg											asmi_read_rdid,
-	output  reg											asmi_read_status,
-	output	reg											asmi_read_sid,
-	output  reg 										asmi_bulk_erase,
-	output  reg											asmi_sector_erase,
-	output  reg											asmi_sector_protect
-);
-	localparam LOCAL_ADDR_WIDTH = ADDR_WIDTH+2;
-	localparam CSR_DATA_WIDTH   = 32;
-	localparam LAST_ADDR_BIT    = (ASMI_ADDR_WIDTH == 24) ? 15 :
-									(ASMI_ADDR_WIDTH == 32) ? 23 : 15;
-	
-	reg  [8:0] wr_burstcount_cnt, rd_burstcount_cnt;
-	reg	 [8:0] rd_mem_burstcount, wr_mem_burstcount;
-	
-	wire last_wr_byte;
-	wire access_csr_status, access_csr_sid, access_csr_rdid, access_csr_mem_op, access_isr, access_imr, access_sce;
-	wire read_status_combi, read_sid_combi, read_rdid_combi, read_isr_combi, read_imr_combi, write_isr_combi, write_imr_combi, write_sce_combi;
-	wire bulk_erase_combi, sector_erase_combi, sector_protect_combi;
-	wire wren_combi, illegal_write_combi, illegal_erase_combi;
-	wire m_illegal_write_combi, m_illegal_erase_combi;
-	wire read_mem_combi, write_mem_combi;
-	wire data_valid_combi, pending_wr_data;
-	wire detect_addroffset;
-	wire [8:0] wfifo_data_in_0, wfifo_data_in_1, wfifo_data_in_2, wfifo_data_in_3;
-	wire [ADDR_WIDTH-1:0] temp_mem_addr;
-	
-	reg reset_n_reg;
-	reg wr_mem_waitrequest, local_waitrequest;
-	reg illegal_write_reg, illegal_erase_reg, m_illegal_write_reg, m_illegal_erase_reg;
-	reg read_status_valid, read_sid_valid, read_rdid_valid, read_isr_valid, read_imr_valid;
-	reg read_status_en, read_sid_en, read_rdid_en;
-	reg wren_internal;
-	reg [LOCAL_ADDR_WIDTH-1:0] wr_mem_addr;
-	reg [7:0] rd_data_reg [4];
-	reg [3:0][8:0] wr_data_reg;
-	reg [1:0] rd_cnt;
-	reg [1:0] wr_cnt;
-	reg [3:0] wr_data_reg_full;
-	reg detect_addroffset_reg, asmi_busy_reg;
-	reg [2:0] temp_sce;
-	
-	// Direct connection
-	assign asmi_clkin 		= clk;
-	assign asmi_reset 		= ~reset_n;
-	assign ddasi_dataout 	= epcq_dataout;
-	assign epcq_dclk 		= ddasi_dclk;
-	assign epcq_scein		= ddasi_scein;
-	assign epcq_sdoin		= ddasi_sdoin;
-	assign epcq_dataoe		= ddasi_dataoe;
-	
-	// chip select
-	generate if (DEVICE_FAMILY == "Arria 10") begin
-		always @(posedge clk or negedge reset_n) begin
-			if (~reset_n) begin
-				asmi_sce			<= {CS_WIDTH{1'b0}};
-			end 
-// to pack the address space this is needed
-			else if (write_mem_combi || read_mem_combi) begin
-				if (CHIP_SELS == 1 ) 					
-					asmi_sce			<= 3'b001;
-				else if (CHIP_SELS == 2 && avl_mem_addr[ADDR_WIDTH-1] == 0) 
-					asmi_sce			<= 3'b001;
-				else if (CHIP_SELS == 2 && avl_mem_addr[ADDR_WIDTH-1] == 1) 
-					asmi_sce			<= 3'b010;
-				else if (CHIP_SELS == 3 && avl_mem_addr[ADDR_WIDTH-1] == 1)	
-					asmi_sce			<= 3'b100;
-				else if (CHIP_SELS == 3 && avl_mem_addr[ADDR_WIDTH-1:ADDR_WIDTH-2] == 0) 	
-					asmi_sce			<= 3'b001;
-				else if (CHIP_SELS == 3 && avl_mem_addr[ADDR_WIDTH-1:ADDR_WIDTH-2] == 1) 	
-					asmi_sce			<= 3'b010;
-				else
-					asmi_sce			<= {CS_WIDTH{1'b0}};
-			end
-			else if (write_sce_combi) begin
-				asmi_sce			<= avl_csr_wrdata[2:0];
-			end
-			else if (asmi_en4b_addr) begin
-				asmi_sce			<= temp_sce;
-			end
-		end
-// decoder ring  if the CHIP_SEL is only 1 then avalon address is the temp address
-//		if the chipsele is 2 then need to remove top address bit
-//		if the chipelect is 3 then remove the top 2 address bits.  
-		assign temp_mem_addr	= CHIP_SELS == 1 ? avl_mem_addr:( CHIP_SELS == 2 ? {1'b0,avl_mem_addr[ADDR_WIDTH-2:0]}:{2'b00,avl_mem_addr[ADDR_WIDTH-3:0]});
-	end
-	else begin
-		always @(posedge clk) begin
-			asmi_sce				<= {CS_WIDTH{1'b0}};
-		end
-		assign temp_mem_addr	= avl_mem_addr;
-	end
-	endgenerate
-	
-	// wait_request generation logic
-	assign avl_mem_waitrequest = (asmi_busy || asmi_busy_reg) ? 1'b1 : (local_waitrequest || wr_mem_waitrequest);
-	assign avl_csr_waitrequest = (asmi_busy || asmi_busy_reg) ? 1'b1 : (local_waitrequest || wr_mem_waitrequest);
-	
-	// access CSR decoding logic
-	assign access_csr_status	= (avl_csr_addr == 3'b000);
-	assign access_csr_sid		= (avl_csr_addr == 3'b001);
-	assign access_csr_rdid		= (avl_csr_addr == 3'b010);
-	assign access_csr_mem_op	= (avl_csr_addr == 3'b011);
-	assign access_isr			= (avl_csr_addr == 3'b100);
-	assign access_imr			= (avl_csr_addr == 3'b101);
-	assign access_sce			= (avl_csr_addr == 3'b110);
-	
-	// read/write memory combi logic
-	assign read_mem_combi		= (avl_mem_read && ~avl_mem_waitrequest);
-	assign write_mem_combi		= (avl_mem_write && ~avl_mem_waitrequest);
-
-	// read csr logic
-	assign read_status_combi	= (avl_csr_read && access_csr_status && ~avl_csr_waitrequest);
-	assign read_sid_combi		= (avl_csr_read && access_csr_sid && ~avl_csr_waitrequest);
-	assign read_rdid_combi		= (avl_csr_read && access_csr_rdid && ~avl_csr_waitrequest);
-	assign read_isr_combi		= (avl_csr_read && access_isr && ~avl_csr_waitrequest);
-	assign read_imr_combi		= (avl_csr_read && access_imr && ~avl_csr_waitrequest);
-	assign write_isr_combi		= (avl_csr_write && access_isr && ~avl_csr_waitrequest);
-	assign write_imr_combi		= (avl_csr_write && access_imr && ~avl_csr_waitrequest);
-	assign write_sce_combi		= (avl_csr_write && access_sce && ~avl_csr_waitrequest);
-	
-	// write csr logic
-	assign bulk_erase_combi		= (avl_csr_write && access_csr_mem_op && ~avl_csr_waitrequest && avl_csr_wrdata[1:0] == 2'b01);
-	assign sector_erase_combi	= (avl_csr_write && access_csr_mem_op && ~avl_csr_waitrequest && avl_csr_wrdata[1:0] == 2'b10);
-	assign sector_protect_combi	= (avl_csr_write && access_csr_mem_op && ~avl_csr_waitrequest && avl_csr_wrdata[1:0] == 2'b11);
-	assign illegal_write_combi	= (asmi_illegal_write) ? 1'b1 :
-									(write_isr_combi && avl_csr_wrdata[1]) ? 1'b0 : 
-										illegal_write_reg;
-	assign illegal_erase_combi	= (asmi_illegal_erase) ? 1'b1 :
-									(write_isr_combi && avl_csr_wrdata[0]) ? 1'b0 : 
-										illegal_erase_reg;
-	assign m_illegal_write_combi= (write_imr_combi) ? avl_csr_wrdata[1] : m_illegal_write_reg;
-	assign m_illegal_erase_combi= (write_imr_combi) ? avl_csr_wrdata[0] : m_illegal_erase_reg;
-	assign wren_combi			= (sector_protect_combi || sector_erase_combi || bulk_erase_combi);
-										
-	assign asmi_rden			= (rd_burstcount_cnt > 9'd0);		// deasserted at the last 2 byte - refer to ASMI_PARALLEL UG
-
-	// interrupt signal
-	assign irq = (illegal_write_reg && m_illegal_write_reg) || (illegal_erase_reg && m_illegal_erase_reg);
-	
-	assign last_wr_byte = (wr_burstcount_cnt == wr_mem_burstcount - 9'd1) ? 1'b1 : 1'b0;
-	
-	assign asmi_wren = wren_internal || asmi_en4b_addr || asmi_shift_bytes || asmi_write;
-	
-	assign data_valid_combi = (rd_burstcount_cnt[1:0] == 2'b00) ? asmi_data_valid : 1'b0;
-	
-	assign wfifo_data_in_0 = {avl_mem_byteenable[0], avl_mem_wrdata[7:0]   };
-	assign wfifo_data_in_1 = {avl_mem_byteenable[1], avl_mem_wrdata[15:8]  };
-	assign wfifo_data_in_2 = {avl_mem_byteenable[2], avl_mem_wrdata[23:16] };
-	assign wfifo_data_in_3 = {avl_mem_byteenable[3], avl_mem_wrdata[31:24] };
-	
-	assign avl_mem_rddata  = {rd_data_reg[3], rd_data_reg[2], rd_data_reg[1], rd_data_reg[0]};
-	assign pending_wr_data = (|wr_data_reg_full) ? 1'b1 : 1'b0;
-	assign detect_addroffset = (pending_wr_data && wr_data_reg[wr_cnt][8]) ? 1'b1 : 
-								(wr_burstcount_cnt == {9{1'b0}}) ? 1'b0 : detect_addroffset_reg;
-
-	//-------------------------------- array to store write data -------------------------------------
-	always @(posedge clk or negedge reset_n) begin
-		if (~reset_n) begin
-			wr_data_reg			<= '{{9{1'b0}}, {9{1'b0}}, {9{1'b0}}, {9{1'b0}}};
-			wr_data_reg_full	<= {4{1'b0}};
-		end 
-		else if (write_mem_combi) begin
-			wr_data_reg			<= {wfifo_data_in_3, wfifo_data_in_2, wfifo_data_in_1, wfifo_data_in_0};
-			wr_data_reg_full	<= {4{1'b1}};
-		end
-		else if (wr_data_reg_full > 4'b0000) begin
-			wr_data_reg_full	<= wr_data_reg_full << 1;
-		end
-	end
-	
-	//-------------------------------- array to store read data -------------------------------------
-	always @(posedge clk or negedge reset_n) begin
-		if (~reset_n) begin
-			rd_data_reg			<= '{{8{1'b0}}, {8{1'b0}}, {8{1'b0}}, {8{1'b0}}};
-			rd_cnt				<= {2{1'b0}};
-		end 
-		else if (asmi_data_valid) begin
-			rd_data_reg[rd_cnt]	<= asmi_dataout;
-			rd_cnt				<= rd_cnt + 2'b01;
-		end
-	end
-	
-	//------------------------------- Enable 4-byte addressing out of reset ----------------------
-	generate 
-	if (ENABLE_4BYTE_ADDR) begin
-		typedef enum logic[1:0] {EN4B_CHIP1, EN4B_CHIP2, EN4B_CHIP3, IDLE} state_t;
-		state_t state;
-	
-		always @(posedge clk or negedge reset_n_reg) begin	// use reset_n_reg because user is allow to send cmd to ASMI_PARALLEL 2 clock cycles after reset
-			if (~reset_n_reg) begin	
-				state					<= EN4B_CHIP1;
-				asmi_en4b_addr			<= 1'b1;
-				temp_sce				<= 3'b001;
-			end
-			else begin
-				case (state)
-					EN4B_CHIP1 : begin
-									asmi_en4b_addr			<= 1'b1;
-									if (~asmi_busy) begin
-										if (CHIP_SELS > 1) begin
-											state					<= EN4B_CHIP2;
-											temp_sce				<= 3'b010;
-										end
-										else begin
-											state					<= IDLE;
-											temp_sce				<= 3'b000;
-										end
-									end
-								 end
-					EN4B_CHIP2 : begin
-									asmi_en4b_addr			<= 1'b1;
-									if (~asmi_busy) begin
-										if (CHIP_SELS > 2) begin
-											state					<= EN4B_CHIP3;
-											temp_sce				<= 3'b100;
-										end
-										else begin
-											state					<= IDLE;
-											temp_sce				<= 3'b000;
-										end
-									end
-								 end
-					EN4B_CHIP3 : begin
-									asmi_en4b_addr			<= 1'b1;
-									if (~asmi_busy) begin
-										state					<= IDLE;
-										temp_sce				<= 3'b000;
-									end
-								 end
-					IDLE	   : begin
-									asmi_en4b_addr			<= 1'b0;
-									state					<= IDLE;
-									temp_sce				<= 3'b000;
-								 end
-					default : 	 begin
-									asmi_en4b_addr			<= 1'b0;
-									state					<= IDLE;
-									temp_sce				<= 3'b000;
-								 end
-				endcase
-			end
-		end
-	end
-	else begin
-		always @(posedge clk) begin
-			asmi_en4b_addr				<= 1'b0;
-			temp_sce					<= 3'b000;
-		end
-	end
-	endgenerate
-	
-	//--------------------------------------- Waitrequest logic ----------------------------------
-	always @(posedge clk or negedge reset_n) begin
-		if (~reset_n) begin
-			wr_mem_waitrequest			<= 1'b0;
-			local_waitrequest			<= 1'b0;
-		end
-		else begin
-			if (read_mem_combi || read_status_combi || read_sid_combi || read_rdid_combi || bulk_erase_combi || sector_erase_combi || sector_protect_combi || asmi_en4b_addr) begin		// no back pressure during imr & isr access
-				local_waitrequest		<= 1'b1;
-			end
-			else if (asmi_busy_reg && ~asmi_busy) begin
-				local_waitrequest		<= 1'b0;
-			end
-			
-			if (write_mem_combi) begin
-				wr_mem_waitrequest	<= 1'b1;
-			end
-			else if ((~pending_wr_data && ~asmi_write) || asmi_busy_reg && ~asmi_busy) begin
-				wr_mem_waitrequest	<= 1'b0;
-			end
-		end
-	end
-	
-	// -------------------------------------- MEM ACCESS -----------------------------------------
-	always @(posedge clk or negedge reset_n) begin
-		if (~reset_n) begin
-			rd_mem_burstcount			<= {9{1'b0}};
-			wr_mem_burstcount			<= {9{1'b0}};
-			wr_mem_addr					<= {LOCAL_ADDR_WIDTH{1'b0}};
-		end
-		else begin
-			if (read_mem_combi) begin
-				rd_mem_burstcount		<= {avl_mem_burstcount, 2'b00}; 
-			end
-			if (write_mem_combi && (wr_burstcount_cnt == {9{1'b0}})) begin
-				wr_mem_addr				<= {temp_mem_addr, 2'b00};
-				wr_mem_burstcount		<= {avl_mem_burstcount, 2'b00}; 
-			end
-		end
-	end
-	
-	always @(posedge clk or negedge reset_n) begin
-		if (~reset_n) begin
-			wr_burstcount_cnt				<= {9{1'b0}};
-		end
-		else begin
-			if (pending_wr_data) begin
-				wr_burstcount_cnt			<= wr_burstcount_cnt + 9'd1;
-			end
-			else if (wr_burstcount_cnt == wr_mem_burstcount) begin
-				wr_burstcount_cnt			<= {9{1'b0}};
-			end
-		end
-	end
-	
-	always @(posedge clk or negedge reset_n) begin
-		if (~reset_n) begin
-			rd_burstcount_cnt				<= {9{1'b0}};
-		end
-		else begin
-			if (read_mem_combi) begin
-				rd_burstcount_cnt			<= 9'd1;
-			end
-			else if (rd_burstcount_cnt == rd_mem_burstcount) begin		// each rd 4 burst
-				rd_burstcount_cnt			<= {9{1'b0}};
-			end
-			else if (asmi_data_valid && rd_burstcount_cnt > 0) begin
-				rd_burstcount_cnt			<= rd_burstcount_cnt + 9'd1;
-			end
-		end
-	end
-	
-	always @(posedge clk or negedge reset_n) begin
-		if (~reset_n) begin
-			asmi_addr					<= {ASMI_ADDR_WIDTH{1'b0}};
-		end
-		else begin
-			if (sector_erase_combi) begin // set lower 16 bits to zero so that erase at starting address of each sector
-				asmi_addr				<= {avl_csr_wrdata[LAST_ADDR_BIT : 8], {16{1'b0}}};	
-			end
-			if (read_mem_combi) begin
-				asmi_addr				<= {temp_mem_addr, 2'b00};
-			end
-			
-			if (detect_addroffset && ~detect_addroffset_reg) begin
-				asmi_addr			<= wr_mem_addr + {{LOCAL_ADDR_WIDTH-9{1'b0}}, wr_burstcount_cnt};
-			end
-
-		end
-	end
-	
-	always @(posedge clk or negedge reset_n) begin
-		if (~reset_n) begin
-			asmi_datain					<= {8{1'b0}};
-			wr_cnt						<= {2{1'b0}};
-			asmi_shift_bytes			<= 1'b0;
-		end
-		else begin
-			if (sector_protect_combi) begin
-				asmi_datain				<= {{1{1'b0}}, avl_csr_wrdata[11], avl_csr_wrdata[12], avl_csr_wrdata[10:8], {2{1'b0}}};	// BP3, TB, BP2, BP1, BP0
-			end
-			if (pending_wr_data) begin
-				asmi_datain				<= wr_data_reg[wr_cnt][7:0];
-				wr_cnt					<= wr_cnt + 2'd1;
-			end
-			if (pending_wr_data && wr_data_reg[wr_cnt][8]) begin
-				asmi_shift_bytes		<= 1'b1;
-			end
-			else begin
-				asmi_shift_bytes		<= 1'b0;
-			end
-		end
-	end
-	
-	always @(posedge clk or negedge reset_n) begin
-		if (~reset_n) begin
-			asmi_read_status			<= 1'b0;
-			asmi_read_sid				<= 1'b0;
-			asmi_read_rdid				<= 1'b0;
-			asmi_bulk_erase				<= 1'b0;
-			asmi_sector_erase			<= 1'b0;
-			asmi_sector_protect			<= 1'b0;
-			wren_internal				<= 1'b0;
-			asmi_write					<= 1'b0;
-			asmi_fast_read				<= 1'b0;
-			asmi_busy_reg				<= 1'b0;
-			avl_mem_rddata_valid		<= 1'b0;
-			detect_addroffset_reg		<= 1'b0;
-			reset_n_reg					<= 1'b0;
-		end
-		else begin
-			asmi_read_status			<= read_status_combi;
-			asmi_read_sid				<= read_sid_combi;
-			asmi_read_rdid				<= read_rdid_combi;
-			asmi_bulk_erase				<= bulk_erase_combi;
-			asmi_sector_erase			<= sector_erase_combi;				
-			asmi_sector_protect			<= sector_protect_combi;
-			wren_internal				<= wren_combi;
-			asmi_write					<= last_wr_byte;
-			asmi_fast_read				<= read_mem_combi;
-			asmi_busy_reg				<= asmi_busy;
-			avl_mem_rddata_valid		<= data_valid_combi;
-			detect_addroffset_reg		<= detect_addroffset;
-			reset_n_reg					<= 1'b1;
-		end
-	end
-	
-	// --------------------------------------------- CSR ACCESS -------------------------------------
-	always @(posedge clk or negedge reset_n) begin
-		if (~reset_n) begin
-			illegal_write_reg			<= 1'b0;
-			illegal_erase_reg			<= 1'b0;
-			m_illegal_write_reg			<= 1'b0;
-			m_illegal_erase_reg			<= 1'b0;
-		end
-		else begin
-			illegal_write_reg			<= illegal_write_combi;
-			illegal_erase_reg			<= illegal_erase_combi;
-			m_illegal_write_reg			<= m_illegal_write_combi;
-			m_illegal_erase_reg			<= m_illegal_erase_combi;
-		end
-	end
-	
-	// csr read only registers enable logic
-	always @(posedge clk or negedge reset_n) begin
-		if (~reset_n) begin
-			read_status_en				<= 1'b0;
-			read_sid_en 				<= 1'b0;
-			read_rdid_en				<= 1'b0;
-		end
-		else if (asmi_read_status) begin
-			read_status_en				<= 1'b1;
-		end
-		else if (asmi_read_sid) begin
-			read_sid_en					<= 1'b1;
-		end
-		else if (asmi_read_rdid) begin
-			read_rdid_en				<= 1'b1;
-		end
-		else if (asmi_busy == 0) begin
-			read_status_en				<= 1'b0;
-			read_sid_en 				<= 1'b0;
-			read_rdid_en				<= 1'b0;
-		end
-	end
-	
-	// generation logic for avl csr read data valid
-	assign avl_csr_rddata_valid	= read_status_valid || read_sid_valid || read_rdid_valid || read_isr_valid || read_imr_valid;
-	
-	always @(posedge clk or negedge reset_n) begin
-		if (~reset_n) begin
-			read_status_valid			<= 1'b0;
-			read_sid_valid				<= 1'b0;
-			read_rdid_valid				<= 1'b0;
-			read_isr_valid				<= 1'b0;
-			read_imr_valid				<= 1'b0;
-		end
-		else begin
-			if (read_status_en && asmi_busy == 0) begin
-				read_status_valid			<= 1'b1;
-			end
-			else begin
-				read_status_valid			<= 1'b0;
-			end
-			
-			if (read_sid_en && asmi_busy == 0) begin
-				read_sid_valid				<= 1'b1;
-			end
-			else begin
-				read_sid_valid				<= 1'b0;
-			end
-			
-			if (read_rdid_en && asmi_busy == 0) begin
-				read_rdid_valid				<= 1'b1;
-			end
-			else begin
-				read_rdid_valid				<= 1'b0;
-			end
-			
-			if (read_isr_combi) begin
-				read_isr_valid				<= 1'b1;
-			end
-			else begin
-				read_isr_valid				<= 1'b0;
-			end
-			
-			if (read_imr_combi) begin
-				read_imr_valid				<= 1'b1;
-			end
-			else begin
-				read_imr_valid				<= 1'b0;
-			end
-		end
-	end
-	
-	// generation logic for avl csr read data
-	always @(posedge clk or negedge reset_n) begin
-		if (~reset_n) begin
-			avl_csr_rddata				<= {CSR_DATA_WIDTH{1'b0}};
-		end
-		else begin
-			if (read_status_en && asmi_busy == 0) begin
-				avl_csr_rddata				<= {{CSR_DATA_WIDTH-8{1'b0}}, asmi_status_out};
-			end
-			if (read_sid_en && asmi_busy == 0) begin
-				avl_csr_rddata				<= {{CSR_DATA_WIDTH-8{1'b0}}, asmi_epcs_id};
-			end
-			if (read_rdid_en && asmi_busy == 0) begin
-				avl_csr_rddata				<= {{CSR_DATA_WIDTH-8{1'b0}}, asmi_rdid_out};
-			end
-			if (read_isr_combi) begin
-				avl_csr_rddata				<= {{CSR_DATA_WIDTH-2{1'b0}}, illegal_write_reg, illegal_erase_reg};
-			end
-			if (read_imr_combi) begin
-				avl_csr_rddata				<= {{CSR_DATA_WIDTH-2{1'b0}}, m_illegal_write_reg, m_illegal_erase_reg};
-			end
-		end
-	end
-	
-
-endmodule

ip/altera_epcq_controller_mod/altera_epcq_controller_arb.sv

@@ -1,230 +0,0 @@
-// (C) 2001-2015 Altera Corporation. All rights reserved.
-// Your use of Altera Corporation's design tools, logic functions and other 
-// software and tools, and its AMPP partner logic functions, and any output 
-// files any of the foregoing (including device programming or simulation 
-// files), and any associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License Subscription 
-// Agreement, Altera MegaCore Function License Agreement, or other applicable 
-// license agreement, including, without limitation, that your use is for the 
-// sole purpose of programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the applicable 
-// agreement for further details.
-
-
-// (C) 2001-2014 Altera Corporation. All rights reserved.
-// Your use of Altera Corporation's design tools, logic functions and other 
-// software and tools, and its AMPP partner logic functions, and any output 
-// files any of the foregoing (including device programming or simulation 
-// files), and any associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License Subscription 
-// Agreement, Altera MegaCore Function License Agreement, or other applicable 
-// license agreement, including, without limitation, that your use is for the 
-// sole purpose of programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the applicable 
-// agreement for further details.
-
-`timescale 1ps / 1ps
-
-module altera_epcq_controller_arb #(
-	parameter CS_WIDTH		= 1,
-	parameter ENABLE_4BYTE_ADDR = 1,
-	parameter ADDR_WIDTH	= 22,
-	parameter ASI_WIDTH		= 1,
-	parameter DEVICE_FAMILY = "CYCLONE V",
-	parameter ASMI_ADDR_WIDTH = 22,
-	parameter CHIP_SELS = 1
-)(
-	input 	wire		  								clk,
-	input 	wire		  								reset_n,
-	                                        			
-	// ports to access csr                        			
-	input 	wire										avl_csr_write,
-	input 	wire		  								avl_csr_read,
-	input 	wire 	[2:0] 								avl_csr_addr,
-	input 	wire 	[31:0] 								avl_csr_wrdata,
-	output 	reg 	[31:0] 								avl_csr_rddata,
-	output 	reg 		 								avl_csr_rddata_valid,
-	output 	reg 			 							avl_csr_waitrequest,
-	                                        			
-	// ports to access memory        			
-	input	wire		  								avl_mem_write,
-	input	wire										avl_mem_read,
-	input	wire  	[ADDR_WIDTH-1:0]					avl_mem_addr,			
-	input	wire	[31:0]								avl_mem_wrdata,
-	input	wire 	[3:0]								avl_mem_byteenable,
-	input	wire	[6:0]								avl_mem_burstcount,
-	output	wire	[31:0]								avl_mem_rddata,
-	output	reg											avl_mem_rddata_valid,
-	output 	reg 			 							avl_mem_waitrequest,
-	
-	// interrupt signal
-	output	reg 										irq,
-	
-	// Disable dedicated active serial interface
-	input  	wire	[ASI_WIDTH-1:0]						epcq_dataout,
-	output  reg											epcq_dclk,
-	output  reg		[CS_WIDTH-1:0] 						epcq_scein,
-	output  reg		[ASI_WIDTH-1:0]						epcq_sdoin,
-	output  reg		[ASI_WIDTH-1:0]						epcq_dataoe,
-	
-	// ASMI PARALLEL interface
-	input   wire	[ASI_WIDTH-1:0]						ddasi_dataoe,
-	output  reg 	[ASI_WIDTH-1:0]						ddasi_dataout,
-	input   wire 										ddasi_dclk,
-	input   wire 	[CS_WIDTH-1:0] 						ddasi_scein,
-	input   reg		[ASI_WIDTH-1:0]  					ddasi_sdoin,
-	
-	input   wire										asmi_busy,
-	input   wire										asmi_data_valid,
-	input   wire	[7:0]  								asmi_dataout,
-	output  reg											asmi_clkin,
-	output  reg											asmi_reset,
-	output  reg		[CS_WIDTH-1:0] 						asmi_sce,
-	output	reg	    [ASMI_ADDR_WIDTH-1:0]  				asmi_addr,
-	output  reg		[7:0]  								asmi_datain,
-	output  reg											asmi_fast_read,
-	output  wire										asmi_rden,
-	output  reg											asmi_shift_bytes,
-	output  reg 										asmi_en4b_addr,
-	output  wire										asmi_wren,
-	output  reg											asmi_write,
-	
-	input   wire										asmi_illegal_erase,
-	input   wire										asmi_illegal_write,
-	input   wire	[7:0]  								asmi_rdid_out,
-	input   wire	[7:0]  								asmi_status_out,
-	input   wire	[7:0]  								asmi_epcs_id,
-	output  reg											asmi_read_rdid,
-	output  reg											asmi_read_status,
-	output	reg											asmi_read_sid,
-	output  reg 										asmi_bulk_erase,
-	output  reg											asmi_sector_erase,
-	output  reg											asmi_sector_protect
-);
-
-	reg temp_mem_write, temp_mem_read, mem_write, mem_read, back_pressured_ctrl;
-	reg [ADDR_WIDTH-1:0] temp_mem_addr, mem_addr;		
-	reg [31:0] temp_mem_wrdata, mem_wrdata;
-	reg [3:0] temp_mem_byteenable, mem_byteenable;
-	reg [6:0] temp_mem_burstcount, mem_burstcount;
-	
-	wire back_pressured, temp_csr_waitrequest, temp_mem_waitrequest;
-
-	//-------------------- Arbitration logic between avalon csr and mem interface -----------
-	always @(posedge clk or negedge reset_n) begin
-		if (~reset_n) begin
-			back_pressured_ctrl		<= 1'b0;
-		end 
-		else if (back_pressured) begin
-			back_pressured_ctrl		<= 1'b1;
-		end
-		else if (~temp_csr_waitrequest) begin
-			back_pressured_ctrl		<= 1'b0;
-		end
-	end
-
-	always @(posedge clk or negedge reset_n) begin
-		if (~reset_n) begin
-			mem_write 			<= 1'b0;
-			mem_read 			<= 1'b0;
-			mem_addr			<= {ADDR_WIDTH{1'b0}};
-			mem_wrdata			<= {32{1'b0}};
-			mem_byteenable		<= {4{1'b0}};
-			mem_burstcount		<= {7{1'b0}};
-		end 
-		else if ((avl_csr_write || avl_csr_read) && ~avl_csr_waitrequest && (avl_mem_write || avl_mem_read) && ~avl_mem_waitrequest) begin
-			// to back pressure master
-			mem_write 			<= avl_mem_write;
-			mem_read 			<= avl_mem_read;
-			mem_addr			<= avl_mem_addr;
-			mem_wrdata			<= avl_mem_wrdata;
-			mem_byteenable		<= avl_mem_byteenable;
-			mem_burstcount		<= avl_mem_burstcount;
-		end
-	end
-	
-	assign back_pressured	   = ((avl_csr_write || avl_csr_read) && ~temp_csr_waitrequest && (avl_mem_write || avl_mem_read)) ? 1'b1 : 1'b0; // to back pressure controller
-	assign avl_csr_waitrequest = (~avl_csr_write && ~avl_csr_read && back_pressured_ctrl) ? 1'b1 : temp_csr_waitrequest;
-	assign avl_mem_waitrequest = (back_pressured_ctrl) ? 1'b1 : temp_mem_waitrequest;
-	assign temp_mem_write	   = (back_pressured) ? 1'b0 :
-									(back_pressured_ctrl) ? mem_write : avl_mem_write;
-	assign temp_mem_read	   = (back_pressured) ? 1'b0 :
-									(back_pressured_ctrl) ? mem_read : avl_mem_read;
-	assign temp_mem_addr	   = (back_pressured) ? {ADDR_WIDTH{1'b0}} :
-									(back_pressured_ctrl) ? mem_addr : avl_mem_addr;
-	assign temp_mem_wrdata	   = (back_pressured) ? {32{1'b0}} :
-									(back_pressured_ctrl) ? mem_wrdata : avl_mem_wrdata;
-	assign temp_mem_byteenable = (back_pressured) ? {4{1'b0}} :
-									(back_pressured_ctrl) ? mem_byteenable : avl_mem_byteenable;
-	assign temp_mem_burstcount = (back_pressured) ? {7{1'b0}} :
-									(back_pressured_ctrl) ? mem_burstcount : avl_mem_burstcount;
-	
-	
-	//---------------------------------------------------------------------------------------//
-	
-	altera_epcq_controller #(
-		.CS_WIDTH		   (CS_WIDTH),
-		.DEVICE_FAMILY     (DEVICE_FAMILY),
-		.ADDR_WIDTH        (ADDR_WIDTH),
-		.ASMI_ADDR_WIDTH   (ASMI_ADDR_WIDTH),
-		.ASI_WIDTH         (ASI_WIDTH),
-		.CHIP_SELS	 (CHIP_SELS),
-		.ENABLE_4BYTE_ADDR (ENABLE_4BYTE_ADDR)
-	) controller (
-		.clk                  (clk),                  
-		.reset_n              (reset_n),              
-		.avl_csr_read         (avl_csr_read),         
-		.avl_csr_waitrequest  (temp_csr_waitrequest),  
-		.avl_csr_write        (avl_csr_write),        
-		.avl_csr_addr         (avl_csr_addr),         
-		.avl_csr_wrdata       (avl_csr_wrdata),       
-		.avl_csr_rddata       (avl_csr_rddata),       
-		.avl_csr_rddata_valid (avl_csr_rddata_valid), 
-		.avl_mem_write        (temp_mem_write),        
-		.avl_mem_burstcount   (temp_mem_burstcount),   
-		.avl_mem_waitrequest  (temp_mem_waitrequest),  
-		.avl_mem_read         (temp_mem_read),         
-		.avl_mem_addr         (temp_mem_addr),         
-		.avl_mem_wrdata       (temp_mem_wrdata),
-		.avl_mem_byteenable   (temp_mem_byteenable),
-		.avl_mem_rddata       (avl_mem_rddata),       
-		.avl_mem_rddata_valid (avl_mem_rddata_valid), 
-		.asmi_status_out      (asmi_status_out),      
-		.asmi_epcs_id         (asmi_epcs_id),         
-		.asmi_illegal_erase   (asmi_illegal_erase),   
-		.asmi_illegal_write   (asmi_illegal_write),   
-		.ddasi_dataoe         (ddasi_dataoe),         
-		.ddasi_dclk           (ddasi_dclk),           
-		.ddasi_scein          (ddasi_scein),          
-		.ddasi_sdoin          (ddasi_sdoin),          
-		.asmi_busy            (asmi_busy),            
-		.asmi_data_valid      (asmi_data_valid),      
-		.asmi_dataout         (asmi_dataout),         
-		.epcq_dataout         (epcq_dataout),         
-		.ddasi_dataout        (ddasi_dataout),        
-		.asmi_read_rdid       (asmi_read_rdid),       
-		.asmi_read_status     (asmi_read_status),     
-		.asmi_read_sid        (asmi_read_sid),        
-		.asmi_bulk_erase      (asmi_bulk_erase),      
-		.asmi_sector_erase    (asmi_sector_erase),    
-		.asmi_sector_protect  (asmi_sector_protect),  
-		.epcq_dclk            (epcq_dclk),            
-		.epcq_scein           (epcq_scein),           
-		.epcq_sdoin           (epcq_sdoin),           
-		.epcq_dataoe          (epcq_dataoe),          
-		.asmi_clkin           (asmi_clkin),           
-		.asmi_reset           (asmi_reset),           
-		.asmi_sce			  (asmi_sce),
-		.asmi_addr            (asmi_addr),            
-		.asmi_datain          (asmi_datain),          
-		.asmi_fast_read       (asmi_fast_read),       
-		.asmi_rden            (asmi_rden),            
-		.asmi_shift_bytes     (asmi_shift_bytes),     
-		.asmi_wren            (asmi_wren),            
-		.asmi_write           (asmi_write),           
-		.asmi_rdid_out        (asmi_rdid_out),        
-		.asmi_en4b_addr       (asmi_en4b_addr),       
-		.irq                  (irq)                   
-	);                                                
-
-endmodule

ip/altera_epcq_controller_mod/altera_epcq_controller_fifo.v

@@ -1,176 +0,0 @@
-// (C) 2001-2015 Altera Corporation. All rights reserved.
-// Your use of Altera Corporation's design tools, logic functions and other 
-// software and tools, and its AMPP partner logic functions, and any output 
-// files any of the foregoing (including device programming or simulation 
-// files), and any associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License Subscription 
-// Agreement, Altera MegaCore Function License Agreement, or other applicable 
-// license agreement, including, without limitation, that your use is for the 
-// sole purpose of programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the applicable 
-// agreement for further details.
-
-
-// megafunction wizard: %FIFO%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: scfifo 
-
-// ============================================================
-// File Name: altera_epcq_controller_fifo.v
-// Megafunction Name(s):
-// 			scfifo
-//
-// Simulation Library Files(s):
-// 			altera_mf
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 14.1.0 Internal Build 64 05/14/2014 PN Full Version
-// ************************************************************
-
-
-//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
-//Your use of Altera Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic 
-//functions, and any output files from any of the foregoing 
-//(including device programming or simulation files), and any 
-//associated documentation or information are expressly subject 
-//to the terms and conditions of the Altera Program License 
-//Subscription Agreement, the Altera Quartus II License Agreement,
-//the Altera MegaCore Function License Agreement, or other 
-//applicable license agreement, including, without limitation, 
-//that your use is for the sole purpose of programming logic 
-//devices manufactured by Altera and sold by Altera or its 
-//authorized distributors.  Please refer to the applicable 
-//agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module altera_epcq_controller_fifo #(
-	parameter DEVICE_FAMILY = "CYCLONE V",
-	parameter MEMORY_TYPE	= "RAM_BLOCK_TYPE=MLAB"
-)(
-	clock,
-	data,
-	rdreq,
-	wrreq,
-	empty,
-	full,
-	q);
-
-	input	  clock;
-	input	[35:0]  data;
-	input	  rdreq;
-	input	  wrreq;
-	output	  empty;
-	output	  full;
-	output	[35:0]  q;
-
-	wire  sub_wire0;
-	wire  sub_wire1;
-	wire [35:0] sub_wire2;
-	wire  empty = sub_wire0;
-	wire  full = sub_wire1;
-	wire [35:0] q = sub_wire2[35:0];
-
-	scfifo	scfifo_component (
-				.clock (clock),
-				.data (data),
-				.rdreq (rdreq),
-				.wrreq (wrreq),
-				.empty (sub_wire0),
-				.full (sub_wire1),
-				.q (sub_wire2),
-				.aclr (),
-				.almost_empty (),
-				.almost_full (),
-				.sclr (),
-				.usedw ());
-	defparam
-		scfifo_component.add_ram_output_register = "OFF",
-		scfifo_component.intended_device_family = DEVICE_FAMILY,
-		scfifo_component.lpm_hint = MEMORY_TYPE,
-		scfifo_component.lpm_numwords = 1024,
-		scfifo_component.lpm_showahead = "ON",
-		scfifo_component.lpm_type = "scfifo",
-		scfifo_component.lpm_width = 36,
-		scfifo_component.lpm_widthu = 10,
-		scfifo_component.overflow_checking = "ON",
-		scfifo_component.underflow_checking = "ON",
-		scfifo_component.use_eab = "ON";
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-// Retrieval info: PRIVATE: Clock NUMERIC "0"
-// Retrieval info: PRIVATE: Depth NUMERIC "1024"
-// Retrieval info: PRIVATE: Empty NUMERIC "1"
-// Retrieval info: PRIVATE: Full NUMERIC "1"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
-// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-// Retrieval info: PRIVATE: Optimize NUMERIC "0"
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-// Retrieval info: PRIVATE: UsedW NUMERIC "0"
-// Retrieval info: PRIVATE: Width NUMERIC "8"
-// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-// Retrieval info: PRIVATE: output_width NUMERIC "8"
-// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-// Retrieval info: PRIVATE: rsFull NUMERIC "0"
-// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-// Retrieval info: PRIVATE: wsFull NUMERIC "1"
-// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M9K"
-// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
-// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
-// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-// Retrieval info: CONSTANT: USE_EAB STRING "ON"
-// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
-// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
-// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
-// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
-// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_bb.v FALSE
-// Retrieval info: LIB_FILE: altera_mf

ip/altera_epcq_controller_mod/altera_epcq_controller_hw.tcl

@@ -1,453 +0,0 @@
-# (C) 2001-2015 Altera Corporation. All rights reserved.
-# Your use of Altera Corporation's design tools, logic functions and other 
-# software and tools, and its AMPP partner logic functions, and any output 
-# files any of the foregoing (including device programming or simulation 
-# files), and any associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License Subscription 
-# Agreement, Altera MegaCore Function License Agreement, or other applicable 
-# license agreement, including, without limitation, that your use is for the 
-# sole purpose of programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the applicable 
-# agreement for further details.
-
-
-# TCL File Generated by Component Editor 14.1
-# Fri May 09 18:08:10 MYT 2014
-# DO NOT MODIFY
-
-
-# 
-# altera_epcq_controller_core "Altera EPCQ Serial Flash controller core" v14.1
-# Altera Coorperation 2014.05.23.15:01:29
-# This component is a serial flash controller which allows user to access Altera EPCQ devices
-# 
-
-# 
-# request TCL package from ACDS 14.1
-# 
-package require -exact qsys 14.1
-
-
-
-# 
-# module altera_epcq_controller
-# 
-set_module_property DESCRIPTION "This component is a serial flash controller which allows user to access Altera EPCQ devices"
-set_module_property NAME altera_epcq_controller_core
-set_module_property VERSION 16.1
-set_module_property INTERNAL true
-set_module_property OPAQUE_ADDRESS_MAP true
-set_module_property AUTHOR "Altera Corporation"
-set_module_property DISPLAY_NAME "Altera EPCQ Serial Flash controller core"
-set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
-set_module_property HIDE_FROM_QUARTUS true
-set_module_property EDITABLE true
-set_module_property REPORT_TO_TALKBACK false
-set_module_property ALLOW_GREYBOX_GENERATION false
-set_module_property REPORT_HIERARCHY false
-set_module_property VALIDATION_CALLBACK "validate"
-# 
-# file sets
-# 
-add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
-set_fileset_property QUARTUS_SYNTH TOP_LEVEL altera_epcq_controller_arb
-set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
-set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
-add_fileset_file altera_epcq_controller_arb.sv SYSTEM_VERILOG PATH altera_epcq_controller_arb.sv TOP_LEVEL_FILE
-add_fileset_file altera_epcq_controller.sv SYSTEM_VERILOG PATH altera_epcq_controller.sv 
-
-add_fileset SIM_VERILOG SIM_VERILOG "" ""
-set_fileset_property SIM_VERILOG TOP_LEVEL altera_epcq_controller_arb
-set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
-set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE true
-add_fileset_file altera_epcq_controller_arb.sv SYSTEM_VERILOG PATH altera_epcq_controller_arb.sv TOP_LEVEL_FILE
-add_fileset_file altera_epcq_controller.sv SYSTEM_VERILOG PATH altera_epcq_controller.sv
-
-#
-# add system info parameter
-add_parameter           deviceFeaturesSystemInfo   STRING 			"None"
-set_parameter_property  deviceFeaturesSystemInfo   system_info		"DEVICE_FEATURES"
-set_parameter_property  deviceFeaturesSystemInfo   VISIBLE false
-
-# 
-# parameters
-# 
-add_parameter           DEVICE_FAMILY		STRING          ""
-set_parameter_property  DEVICE_FAMILY		SYSTEM_INFO     "DEVICE_FAMILY"
-set_parameter_property  DEVICE_FAMILY		HDL_PARAMETER   true
-set_parameter_property  DEVICE_FAMILY		VISIBLE	      	false
-
-add_parameter ADDR_WIDTH INTEGER 19
-set_parameter_property ADDR_WIDTH DEFAULT_VALUE 19
-set_parameter_property ADDR_WIDTH DISPLAY_NAME ADDR_WIDTH
-set_parameter_property ADDR_WIDTH DERIVED true
-set_parameter_property ADDR_WIDTH TYPE INTEGER
-set_parameter_property ADDR_WIDTH VISIBLE false
-set_parameter_property ADDR_WIDTH UNITS None
-set_parameter_property ADDR_WIDTH ALLOWED_RANGES {19, 20, 21, 22, 23, 24, 25, 26, 27, 28}		
-set_parameter_property ADDR_WIDTH HDL_PARAMETER true
-
-add_parameter ASMI_ADDR_WIDTH INTEGER 24
-set_parameter_property ASMI_ADDR_WIDTH DEFAULT_VALUE 24
-set_parameter_property ASMI_ADDR_WIDTH DISPLAY_NAME ASMI_ADDR_WIDTH
-set_parameter_property ASMI_ADDR_WIDTH DERIVED true
-set_parameter_property ASMI_ADDR_WIDTH TYPE INTEGER
-set_parameter_property ASMI_ADDR_WIDTH VISIBLE false
-set_parameter_property ASMI_ADDR_WIDTH UNITS None
-set_parameter_property ASMI_ADDR_WIDTH ALLOWED_RANGES {24, 32}		
-set_parameter_property ASMI_ADDR_WIDTH HDL_PARAMETER true
-
-add_parameter ASI_WIDTH INTEGER 1
-set_parameter_property ASI_WIDTH DEFAULT_VALUE 1
-set_parameter_property ASI_WIDTH DISPLAY_NAME ASI_WIDTH
-set_parameter_property ASI_WIDTH DERIVED true
-set_parameter_property ASI_WIDTH TYPE INTEGER
-set_parameter_property ASI_WIDTH VISIBLE false
-set_parameter_property ASI_WIDTH UNITS None
-set_parameter_property ASI_WIDTH ALLOWED_RANGES {1, 4}
-set_parameter_property ASI_WIDTH HDL_PARAMETER true
-
-add_parameter CS_WIDTH INTEGER 1
-set_parameter_property CS_WIDTH DEFAULT_VALUE 1
-set_parameter_property CS_WIDTH DISPLAY_NAME CS_WIDTH
-set_parameter_property CS_WIDTH DERIVED true
-set_parameter_property CS_WIDTH TYPE INTEGER
-set_parameter_property CS_WIDTH VISIBLE false
-set_parameter_property CS_WIDTH UNITS None
-set_parameter_property CS_WIDTH ALLOWED_RANGES {1, 3}
-set_parameter_property CS_WIDTH HDL_PARAMETER true
-
-add_parameter CHIP_SELS INTEGER "1"
-set_parameter_property CHIP_SELS DISPLAY_NAME "Number of Chip Selects used"
-set_parameter_property CHIP_SELS ALLOWED_RANGES {1 2 3}
-set_parameter_property CHIP_SELS DESCRIPTION "Number of EPCQ(L) devices that are attached and need a CHIPSEL"
-set_parameter_property CHIP_SELS HDL_PARAMETER true
-set_parameter_property CHIP_SELS AFFECTS_GENERATION true
-
-add_parameter DDASI	INTEGER "0"
-set_parameter_property DDASI DISPLAY_NAME "Disable dedicated Active Serial interface"
-set_parameter_property DDASI DESCRIPTION "Check to route ASMIBLOCK signals to top level of design"
-set_parameter_property DDASI AFFECTS_GENERATION true
-set_parameter_property DDASI VISIBLE false
-set_parameter_property DDASI DERIVED false
-
-add_parameter ENABLE_4BYTE_ADDR	INTEGER "0"
-set_parameter_property ENABLE_4BYTE_ADDR DISPLAY_NAME "Enable 4-byte addressing mode"
-set_parameter_property ENABLE_4BYTE_ADDR DESCRIPTION "Check to enable 4-byte addressing mode for device larger than 128Mbyte"
-set_parameter_property ENABLE_4BYTE_ADDR AFFECTS_GENERATION true
-set_parameter_property ENABLE_4BYTE_ADDR VISIBLE false
-set_parameter_property ENABLE_4BYTE_ADDR HDL_PARAMETER true
-set_parameter_property ENABLE_4BYTE_ADDR DERIVED true
-
-# SPI device selection
-add_parameter FLASH_TYPE STRING "EPCQ16"
-set_parameter_property FLASH_TYPE DISPLAY_NAME "Configuration device type"
-set_parameter_property FLASH_TYPE DESCRIPTION "Select targeted EPCS/EPCQ devices"
-set_parameter_property FLASH_TYPE AFFECTS_GENERATION true
-set_parameter_property FLASH_TYPE VISIBLE true
-set_parameter_property FLASH_TYPE DERIVED false
-
-add_parameter IO_MODE STRING "STANDARD"
-set_parameter_property IO_MODE DISPLAY_NAME "Choose I/O mode"
-set_parameter_property IO_MODE ALLOWED_RANGES {"STANDARD" "QUAD"}
-set_parameter_property IO_MODE DESCRIPTION "Select extended data width when Fast Read operation is enabled"
-
-# 
-# display items
-# 
-
-
-# 
-# connection point clock_sink
-# 
-add_interface clock_sink clock end
-set_interface_property clock_sink clockRate 0
-set_interface_property clock_sink ENABLED true
-set_interface_property clock_sink EXPORT_OF ""
-set_interface_property clock_sink PORT_NAME_MAP ""
-set_interface_property clock_sink CMSIS_SVD_VARIABLES ""
-set_interface_property clock_sink SVD_ADDRESS_GROUP ""
-
-add_interface_port clock_sink clk clk Input 1
-
-
-# 
-# connection point reset
-# 
-add_interface reset reset end
-set_interface_property reset associatedClock clock_sink
-set_interface_property reset synchronousEdges DEASSERT
-set_interface_property reset ENABLED true
-set_interface_property reset EXPORT_OF ""
-set_interface_property reset PORT_NAME_MAP ""
-set_interface_property reset CMSIS_SVD_VARIABLES ""
-set_interface_property reset SVD_ADDRESS_GROUP ""
-
-add_interface_port reset reset_n reset_n Input 1
-
-
-# 
-# connection point avl_csr
-# 
-add_interface avl_csr avalon end
-set_interface_property avl_csr addressUnits WORDS
-set_interface_property avl_csr associatedClock clock_sink
-set_interface_property avl_csr associatedReset reset
-set_interface_property avl_csr bitsPerSymbol 8
-set_interface_property avl_csr burstOnBurstBoundariesOnly false
-set_interface_property avl_csr burstcountUnits WORDS
-set_interface_property avl_csr explicitAddressSpan 0
-set_interface_property avl_csr holdTime 0
-set_interface_property avl_csr linewrapBursts false
-set_interface_property avl_csr maximumPendingReadTransactions 1
-set_interface_property avl_csr maximumPendingWriteTransactions 0
-set_interface_property avl_csr readLatency 0
-set_interface_property avl_csr readWaitTime 0
-set_interface_property avl_csr setupTime 0
-set_interface_property avl_csr timingUnits Cycles
-set_interface_property avl_csr writeWaitTime 0
-set_interface_property avl_csr ENABLED true
-set_interface_property avl_csr EXPORT_OF ""
-set_interface_property avl_csr PORT_NAME_MAP ""
-set_interface_property avl_csr CMSIS_SVD_VARIABLES ""
-set_interface_property avl_csr SVD_ADDRESS_GROUP ""
-
-add_interface_port avl_csr avl_csr_read read Input 1
-add_interface_port avl_csr avl_csr_waitrequest waitrequest Output 1
-add_interface_port avl_csr avl_csr_write write Input 1
-add_interface_port avl_csr avl_csr_addr address Input 3
-add_interface_port avl_csr avl_csr_wrdata writedata Input 32
-add_interface_port avl_csr avl_csr_rddata readdata Output 32
-add_interface_port avl_csr avl_csr_rddata_valid readdatavalid Output 1
-
-
-# 
-# connection point avl_mem
-# 
-add_interface avl_mem avalon end
-set_interface_property avl_mem addressUnits WORDS
-set_interface_property avl_mem associatedClock clock_sink
-set_interface_property avl_mem associatedReset reset
-set_interface_property avl_mem bitsPerSymbol 8
-set_interface_property avl_mem burstOnBurstBoundariesOnly false
-set_interface_property avl_mem burstcountUnits WORDS
-set_interface_property avl_mem explicitAddressSpan 0
-set_interface_property avl_mem holdTime 0
-set_interface_property avl_mem linewrapBursts true
-set_interface_property avl_mem maximumPendingReadTransactions 1
-set_interface_property avl_mem maximumPendingWriteTransactions 0
-set_interface_property avl_mem constantBurstBehavior true
-set_interface_property avl_mem readLatency 0
-set_interface_property avl_mem readWaitTime 0
-set_interface_property avl_mem setupTime 0
-set_interface_property avl_mem timingUnits Cycles
-set_interface_property avl_mem writeWaitTime 0
-set_interface_property avl_mem ENABLED true
-set_interface_property avl_mem EXPORT_OF ""
-set_interface_property avl_mem PORT_NAME_MAP ""
-set_interface_property avl_mem CMSIS_SVD_VARIABLES ""
-set_interface_property avl_mem SVD_ADDRESS_GROUP ""
-
-add_interface_port avl_mem avl_mem_write write Input 1
-add_interface_port avl_mem avl_mem_burstcount burstcount Input 7
-add_interface_port avl_mem avl_mem_waitrequest waitrequest Output 1
-add_interface_port avl_mem avl_mem_read read Input 1
-add_interface_port avl_mem avl_mem_addr address Input ADDR_WIDTH
-add_interface_port avl_mem avl_mem_wrdata writedata Input 32
-add_interface_port avl_mem avl_mem_rddata readdata Output 32
-add_interface_port avl_mem avl_mem_rddata_valid readdatavalid Output 1
-add_interface_port avl_mem avl_mem_byteenable byteenable Input 4
-
-
-# 
-# connection point conduit_out
-# 
-add_interface asmi_status_out conduit end
-add_interface_port asmi_status_out asmi_status_out conduit_status_out Input 8
-
-add_interface asmi_epcs_id conduit end
-add_interface_port asmi_epcs_id asmi_epcs_id conduit_epcs_id Input 8
-
-add_interface asmi_illegal_erase conduit end
-add_interface_port asmi_illegal_erase asmi_illegal_erase conduit_illegal_erase Input 1
-
-add_interface asmi_illegal_write conduit end
-add_interface_port asmi_illegal_write asmi_illegal_write conduit_illegal_write Input 1
-
-add_interface ddasi_dataoe conduit end
-add_interface_port ddasi_dataoe ddasi_dataoe conduit_ddasi_dataoe Input ASI_WIDTH
-
-add_interface ddasi_dclk conduit end
-add_interface_port ddasi_dclk ddasi_dclk conduit_ddasi_dclk Input 1
-
-add_interface ddasi_scein conduit end
-add_interface_port ddasi_scein ddasi_scein conduit_ddasi_scein Input CS_WIDTH
-
-add_interface ddasi_sdoin conduit end
-add_interface_port ddasi_sdoin ddasi_sdoin conduit_ddasi_sdoin Input ASI_WIDTH
-
-add_interface asmi_busy conduit end
-add_interface_port asmi_busy asmi_busy conduit_busy Input 1
-
-add_interface asmi_data_valid conduit end
-add_interface_port asmi_data_valid asmi_data_valid conduit_data_valid Input 1
-
-add_interface asmi_dataout conduit end
-add_interface_port asmi_dataout asmi_dataout conduit_dataout Input 8
-
-add_interface epcq_dataout conduit end
-add_interface_port epcq_dataout epcq_dataout conduit_epcq_dataout Input ASI_WIDTH
-
-add_interface ddasi_dataout conduit end
-add_interface_port ddasi_dataout ddasi_dataout conduit_ddasi_dataout Output ASI_WIDTH
-
-add_interface asmi_read_rdid conduit end
-add_interface_port asmi_read_rdid asmi_read_rdid conduit_read_rdid Output 1
-
-add_interface asmi_read_status conduit end
-add_interface_port asmi_read_status asmi_read_status conduit_read_status Output 1
-
-add_interface asmi_read_sid conduit end
-add_interface_port asmi_read_sid asmi_read_sid conduit_read_sid Output 1
-
-add_interface asmi_bulk_erase conduit end
-add_interface_port asmi_bulk_erase asmi_bulk_erase conduit_bulk_erase Output 1
-
-add_interface asmi_sector_erase conduit end
-add_interface_port asmi_sector_erase asmi_sector_erase conduit_sector_erase Output 1
-
-add_interface asmi_sector_protect conduit end
-add_interface_port asmi_sector_protect asmi_sector_protect conduit_sector_protect Output 1
-
-add_interface epcq_dclk conduit end
-add_interface_port epcq_dclk epcq_dclk conduit_epcq_dclk Output 1
-
-add_interface epcq_scein conduit end
-add_interface_port epcq_scein epcq_scein conduit_epcq_scein Output CS_WIDTH
-
-add_interface epcq_sdoin conduit end
-add_interface_port epcq_sdoin epcq_sdoin conduit_epcq_sdoin Output ASI_WIDTH
-
-add_interface epcq_dataoe conduit end
-add_interface_port epcq_dataoe epcq_dataoe conduit_epcq_dataoe Output ASI_WIDTH
-
-add_interface asmi_clkin conduit end
-add_interface_port asmi_clkin asmi_clkin conduit_clkin Output 1
-
-add_interface asmi_reset conduit end
-add_interface_port asmi_reset asmi_reset conduit_reset Output 1
-
-add_interface asmi_sce conduit end
-add_interface_port asmi_sce asmi_sce conduit_asmi_sce Output CS_WIDTH
-
-add_interface asmi_addr conduit end
-add_interface_port asmi_addr asmi_addr conduit_addr Output ASMI_ADDR_WIDTH
-
-add_interface asmi_datain conduit end
-add_interface_port asmi_datain asmi_datain conduit_datain Output 8
-
-add_interface asmi_fast_read conduit end
-add_interface_port asmi_fast_read asmi_fast_read conduit_fast_read Output 1
-
-add_interface asmi_rden conduit end
-add_interface_port asmi_rden asmi_rden conduit_rden Output 1
-
-add_interface asmi_shift_bytes conduit end
-add_interface_port asmi_shift_bytes asmi_shift_bytes conduit_shift_bytes Output 1
-
-add_interface asmi_wren conduit end
-add_interface_port asmi_wren asmi_wren conduit_wren Output 1
-
-add_interface asmi_write conduit end
-add_interface_port asmi_write asmi_write conduit_write Output 1
-
-add_interface asmi_rdid_out conduit end
-add_interface_port asmi_rdid_out asmi_rdid_out conduit_rdid_out Input 8
-
-add_interface asmi_en4b_addr conduit end
-add_interface_port asmi_en4b_addr asmi_en4b_addr conduit_en4b_addr Output 1
-
-# 
-# connection point interrupt_sender
-# 
-add_interface interrupt_sender interrupt end
-set_interface_property interrupt_sender associatedAddressablePoint avl_csr
-set_interface_property interrupt_sender associatedClock clock_sink
-set_interface_property interrupt_sender associatedReset reset
-set_interface_property interrupt_sender bridgedReceiverOffset ""
-set_interface_property interrupt_sender bridgesToReceiver ""
-set_interface_property interrupt_sender ENABLED true
-set_interface_property interrupt_sender EXPORT_OF ""
-set_interface_property interrupt_sender PORT_NAME_MAP ""
-set_interface_property interrupt_sender CMSIS_SVD_VARIABLES ""
-set_interface_property interrupt_sender SVD_ADDRESS_GROUP ""
-
-add_interface_port interrupt_sender irq irq Output 1
-
-proc validate {} {
-	set all_supported_SPI_list {"EPCS16" "EPCS64" "EPCS128" "EPCQ16" "EPCQ32" "EPCQ64" "EPCQ128" "EPCQ256" \
-							"EPCQ512" "EPCQL256" "EPCQL512" "EPCQL1024"}
-							
-	set_parameter_property  FLASH_TYPE  	"ALLOWED_RANGES"  $all_supported_SPI_list
-	set DEVICE_FAMILY 		[ get_parameter_value DEVICE_FAMILY ]
-	set CHIP_SELS			    [ get_parameter_value CHIP_SELS]
-	set temp_addr_width 	[ proc_get_derive_addr_width [ get_parameter_value FLASH_TYPE ] ]
-	set_parameter_value		ENABLE_4BYTE_ADDR	[ proc_get_derive_enable_2byte_addr  [ get_parameter_value FLASH_TYPE ] ]
-	
-	if { [ get_parameter_value ENABLE_4BYTE_ADDR ] } {
-		set_parameter_value ASMI_ADDR_WIDTH 32
-	} else {
-		set_parameter_value ASMI_ADDR_WIDTH 24
-	}
-	
-	# check whether devices supporting multiple flash - only for Arria 10
-	if {[check_device_family_equivalence $DEVICE_FAMILY "Arria 10"]} {
-		set is_multi_flash_support	"true"
-		if {$CHIP_SELS eq 3 } {set_parameter_value 	ADDR_WIDTH 		[ expr $temp_addr_width + 2]}
-		if {$CHIP_SELS eq 2 } {set_parameter_value 	ADDR_WIDTH 		[ expr $temp_addr_width + 1]}
-		if {$CHIP_SELS eq 1 } {set_parameter_value 	ADDR_WIDTH 		$temp_addr_width }
-	} else {
-		set is_multi_flash_support	"false"
-		set_parameter_value 	ADDR_WIDTH 		$temp_addr_width
-	}
-	
-}
-
-proc proc_get_derive_enable_2byte_addr {flash_type} {
-    if { [ string match "*256*" "$flash_type" ] || [ string match "*512*" "$flash_type" ] || [ string match "*1024*" "$flash_type" ]} {
-		return true
-	} else {
-		return false
-	}
-}
-
-proc proc_get_derive_addr_width {flash_type} {
-    switch $flash_type {
-        "EPCS16" - "EPCQ16" {
-            return 19 
-        }
-        "EPCS64" - "EPCQ64" {
-            return 21
-        }
-        "EPCS128" - "EPCQ128" {
-            return 22
-        }
-		"EPCQ32" {
-            return 20
-		}
-        "EPCQ256" - "EPCQL256" {
-            return 23
-        }
-        "EPCQ512" - "EPCQL512" {
-            return 24
-        }
-        "EPCQL1024" {
-            return 25
-        }
-        default {
-            # Should never enter this function
-            send_message error "$flash_type is not a valid flash type"
-        }
-    
-    }
-}

ip/altera_epcq_controller_mod/altera_epcq_controller_sw.tcl

@@ -1,58 +0,0 @@
-# (C) 2001-2015 Altera Corporation. All rights reserved.
-# Your use of Altera Corporation's design tools, logic functions and other 
-# software and tools, and its AMPP partner logic functions, and any output 
-# files any of the foregoing (including device programming or simulation 
-# files), and any associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License Subscription 
-# Agreement, Altera MegaCore Function License Agreement, or other applicable 
-# license agreement, including, without limitation, that your use is for the 
-# sole purpose of programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the applicable 
-# agreement for further details.
-
-
-#
-# altera_epcq_controller_sw.tcl
-#
-
-# Create a new driver
-create_driver altera_epcq_controller_mod_driver
-
-# Associate it with some hardware known as "altera_epcq_controller"
-set_sw_property hw_class_name altera_epcq_controller_mod
-
-# The version of this driver
-set_sw_property version 14.1
-
-# This driver may be incompatible with versions of hardware less
-# than specified below. Updates to hardware and device drivers
-# rendering the driver incompatible with older versions of
-# hardware are noted with this property assignment.
-set_sw_property min_compatible_hw_version 14.1
-
-# Initialize the driver in alt_sys_init()
-set_sw_property auto_initialize true
-
-# This driver only works when the following combinations of interfaces 
-# are enabled and connected as a group of CSR interfaces.
-set_sw_property csr_interfaces "avl_mem,avl_csr"
-
-# The EPCQ interrupt has an interrupt but it is not used in the driver. 
-# These assignments are still required by the Nios II SBT
-set_sw_property isr_preemption_supported true
-set_sw_property supported_interrupt_apis "legacy_interrupt_api enhanced_interrupt_api"
-
-# Location in generated BSP that above sources will be copied into
-set_sw_property bsp_subdirectory drivers
-
-# Header files
-add_sw_property include_source HAL/inc/altera_epcq_controller_mod.h
-add_sw_property include_source inc/altera_epcq_controller_mod_regs.h
-
-# C/C++ source files
-add_sw_property c_source HAL/src/altera_epcq_controller_mod.c
-
-
-# This driver supports HAL & UCOSII BSP (OS) types
-add_sw_property supported_bsp_type HAL 
-add_sw_property supported_bsp_type UCOSII

ip/altera_epcq_controller_mod/altera_epcq_controller_wrapper.sv.terp

@@ -1,248 +0,0 @@
-// (C) 2001-2015 Altera Corporation. All rights reserved.
-// Your use of Altera Corporation's design tools, logic functions and other 
-// software and tools, and its AMPP partner logic functions, and any output 
-// files any of the foregoing (including device programming or simulation 
-// files), and any associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License Subscription 
-// Agreement, Altera MegaCore Function License Agreement, or other applicable 
-// license agreement, including, without limitation, that your use is for the 
-// sole purpose of programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the applicable 
-// agreement for further details.
-
-
-
-`timescale 1ps / 1ps
-
-${MULTICHIP}
-${DDASI_ON}		
-${SID_EN}
-${BULK_ERASE_EN}
-${4BYTE_ADDR_EN}
-
-module altera_epcq_controller_wrapper #(
-	parameter CS_WIDTH		= 1,
-	parameter DEVICE_FAMILY = "Arria V",
-	parameter ADDR_WIDTH	= 24,
-	parameter ASI_WIDTH		= 1,
-	parameter ENABLE_4BYTE_ADDR = 1,
-	parameter ASMI_ADDR_WIDTH = 22,
-	parameter CHIP_SELS       = 1
-)(
-	input 	wire		  								clk,
-	input 	wire		  								reset_n,
-	                                        			
-	// ports to access csr                        			
-	input 	wire										avl_csr_write,
-	input 	wire		  								avl_csr_read,
-	input 	wire 	[2:0] 								avl_csr_addr,
-	input 	wire 	[31:0] 								avl_csr_wrdata,
-	output 	wire	[31:0] 								avl_csr_rddata,
-	output 	wire		 								avl_csr_rddata_valid,
-	output 	wire			 							avl_csr_waitrequest,
-	                                        			
-	// ports to access memory        			
-	input	wire		  								avl_mem_write,
-	input	wire										avl_mem_read,
-	input	wire  	[ADDR_WIDTH-1:0]					avl_mem_addr,			
-	input	wire	[31:0]								avl_mem_wrdata,
-	input	wire	[6:0]								avl_mem_burstcount,
-	input	wire 	[3:0]								avl_mem_byteenable,
-	output	wire	[31:0]								avl_mem_rddata,
-	output	wire										avl_mem_rddata_valid,
-	output 	wire			 							avl_mem_waitrequest,
-
-`ifdef DDASI_ON
-	output 	wire	[ASI_WIDTH-1:0]						epcq_dataout, 
-    output 	wire			 							epcq_dclk,    
-    output 	wire	[CS_WIDTH-1:0]  					epcq_scein,   
-    output 	wire	[ASI_WIDTH-1:0]						epcq_sdoin,   
-    output 	wire	[ASI_WIDTH-1:0]						epcq_dataoe,  
-`endif
-
-	// interrupt signal
-	output	reg 										irq
-);
-
-`ifdef DDASI_ON
-	wire	[ASI_WIDTH-1:0]						ddasi_dataoe;
-	wire 	[ASI_WIDTH-1:0]						ddasi_dataout;
-	wire 										ddasi_dclk;
-	wire 	[CS_WIDTH-1:0]						ddasi_scein;
-	wire	[ASI_WIDTH-1:0]  					ddasi_sdoin;
-`endif
-	wire										asmi_busy;
-	wire										asmi_data_valid;
-	wire	[7:0]  								asmi_dataout;
-	wire										asmi_clkin;
-	wire										asmi_reset;
-`ifdef MULTICHIP
-	wire	[CS_WIDTH-1:0]  					asmi_sce;
-`endif
-	wire    [ASMI_ADDR_WIDTH-1:0]  				asmi_addr;
-	wire	[7:0]  								asmi_datain;
-	wire										asmi_fast_read;
-	wire										asmi_rden;
-	wire										asmi_shift_bytes;
-	wire										asmi_wren;
-	wire										asmi_write;
-	
-	wire										asmi_illegal_erase;
-	wire										asmi_illegal_write;
-	wire	[7:0]  								asmi_rdid_out;
-	wire	[7:0]  								asmi_status_out;
-`ifdef ENABLE_SID
-	wire	[7:0]  								asmi_epcs_id;
-`endif
-	wire										asmi_read_rdid;
-	wire										asmi_read_status;
-	wire										asmi_read_sid;
-`ifdef ENABLE_4BYTE_ADDR_CODE
-	wire										asmi_en4b_addr;
-`endif
-`ifdef ENABLE_BULK_ERASE
-	wire										asmi_bulk_erase;
-`endif
-	wire										asmi_sector_erase;
-	wire										asmi_sector_protect;
-
-	altera_epcq_controller_core	#(
-		.DEVICE_FAMILY 		(DEVICE_FAMILY),
-		.ADDR_WIDTH			(ADDR_WIDTH),
-		.ASI_WIDTH			(ASI_WIDTH),
-		.ASMI_ADDR_WIDTH   	(ASMI_ADDR_WIDTH),
-		.CS_WIDTH			(CS_WIDTH),
-		.ENABLE_4BYTE_ADDR	(ENABLE_4BYTE_ADDR),
-		.CHIP_SELS          (CHIP_SELS)
-	) epcq_controller_inst (
-		.clk						 (clk					 ),
-		.reset_n                     (reset_n                ),
-		.avl_csr_write               (avl_csr_write          ),
-		.avl_csr_read                (avl_csr_read           ),
-		.avl_csr_addr                (avl_csr_addr           ),
-		.avl_csr_wrdata              (avl_csr_wrdata         ),
-		.avl_csr_rddata              (avl_csr_rddata         ),
-		.avl_csr_rddata_valid        (avl_csr_rddata_valid   ),
-		.avl_csr_waitrequest         (avl_csr_waitrequest    ),
-		.avl_mem_write               (avl_mem_write          ),
-		.avl_mem_read                (avl_mem_read           ),
-		.avl_mem_addr			     (avl_mem_addr			 ),					
-		.avl_mem_wrdata              (avl_mem_wrdata         ),
-		.avl_mem_burstcount          (avl_mem_burstcount     ),
-		.avl_mem_byteenable          (avl_mem_byteenable     ),
-		.avl_mem_rddata              (avl_mem_rddata         ),
-		.avl_mem_rddata_valid        (avl_mem_rddata_valid   ),
-		.avl_mem_waitrequest         (avl_mem_waitrequest    ),
-		.irq                         (irq                    ),
-`ifdef DDASI_ON
-		.epcq_dataout                (epcq_dataout           ),
-		.epcq_dclk                   (epcq_dclk              ),
-		.epcq_scein                  (epcq_scein             ),
-		.epcq_sdoin                  (epcq_sdoin             ),
-		.epcq_dataoe                 (epcq_dataoe            ),
-		.ddasi_dataoe                (ddasi_dataoe           ),
-		.ddasi_dataout               (ddasi_dataout          ),
-		.ddasi_dclk                  (ddasi_dclk             ),
-		.ddasi_scein                 (ddasi_scein            ),
-		.ddasi_sdoin                 (ddasi_sdoin            ),
-`else
-		.epcq_dataout                ({ASI_WIDTH{1'b0}}	     ),
-		.epcq_dclk                   (	         	         ),
-		.epcq_scein                  (	         	         ),
-		.epcq_sdoin                  (	         	         ),
-		.epcq_dataoe                 (	         	         ),
-		.ddasi_dataoe                ({ASI_WIDTH{1'b0}}      ),
-		.ddasi_dataout               (				         ),
-		.ddasi_dclk                  (1'b0	         	     ),
-		.ddasi_scein                 ({CS_WIDTH{1'b0}}       ),
-		.ddasi_sdoin                 ({ASI_WIDTH{1'b0}}      ),
-`endif
-		.asmi_busy                   (asmi_busy              ),
-		.asmi_data_valid             (asmi_data_valid        ),
-		.asmi_dataout                (asmi_dataout           ),
-		.asmi_clkin                  (asmi_clkin             ),
-		.asmi_reset                  (asmi_reset             ),
-`ifdef MULTICHIP
-		.asmi_sce					 (asmi_sce				),
-`else
-		.asmi_sce					 (						),
-`endif
-		.asmi_addr                   (asmi_addr              ),
-		.asmi_datain                 (asmi_datain            ),
-		.asmi_fast_read              (asmi_fast_read         ),
-		.asmi_rden                   (asmi_rden              ),
-		.asmi_shift_bytes            (asmi_shift_bytes       ),
-		.asmi_wren                   (asmi_wren              ),
-		.asmi_write                  (asmi_write             ),
-		.asmi_illegal_erase          (asmi_illegal_erase     ),
-		.asmi_illegal_write          (asmi_illegal_write     ),
-		.asmi_rdid_out               (asmi_rdid_out          ),
-		.asmi_status_out             (asmi_status_out        ),
-`ifdef ENABLE_SID
-		.asmi_epcs_id                (asmi_epcs_id			 ),
-		.asmi_read_sid               (asmi_read_sid			 ),
-`else
-		.asmi_epcs_id                ({8{1'b0}}			 	 ),
-		.asmi_read_sid               (						 ),
-`endif
-		.asmi_read_rdid              (asmi_read_rdid         ),
-		.asmi_read_status            (asmi_read_status       ),
-`ifdef ENABLE_4BYTE_ADDR_CODE
-		.asmi_en4b_addr              (asmi_en4b_addr         ),
-`else
-		.asmi_en4b_addr              (				         ),
-`endif
-`ifdef ENABLE_BULK_ERASE
-		.asmi_bulk_erase             (asmi_bulk_erase        ),
-`else
-		.asmi_bulk_erase             (				        ),
-`endif
-		.asmi_sector_erase           (asmi_sector_erase      ),
-		.asmi_sector_protect         (asmi_sector_protect    )
-	);
-	
-	altera_asmi_parallel asmi_parallel_inst (
-		.busy                   (asmi_busy              ),
-		.data_valid             (asmi_data_valid        ),
-		.dataout                (asmi_dataout           ),
-		.clkin                  (asmi_clkin             ),
-		.reset                  (asmi_reset             ),
-`ifdef MULTICHIP
-		.sce					(asmi_sce				),
-`endif
-		.addr                   (asmi_addr				),
-		.datain                 (asmi_datain            ),
-		.fast_read              (asmi_fast_read         ),
-		.rden                   (asmi_rden              ),
-		.shift_bytes            (asmi_shift_bytes       ),
-		.wren                   (asmi_wren              ),
-		.write                  (asmi_write             ),
-		.illegal_erase          (asmi_illegal_erase     ),
-		.illegal_write          (asmi_illegal_write     ),
-		.rdid_out               (asmi_rdid_out          ),
-		.status_out             (asmi_status_out        ),
-		.read_dummyclk			(1'b0),
-`ifdef ENABLE_SID
-		.epcs_id                (asmi_epcs_id           ),
-		.read_sid               (asmi_read_sid          ),
-`endif
-		.read_rdid              (asmi_read_rdid         ),
-		.read_status            (asmi_read_status       ),
-`ifdef ENABLE_4BYTE_ADDR_CODE
-		.en4b_addr              (asmi_en4b_addr         ),
-`endif
-`ifdef ENABLE_BULK_ERASE
-		.bulk_erase             (asmi_bulk_erase        ),
-`endif
-`ifdef DDASI_ON
-		.asmi_dataoe            (ddasi_dataoe           ),   
-		.asmi_dataout           (ddasi_dataout          ),   
-		.asmi_dclk              (ddasi_dclk             ),   
-		.asmi_scein             (ddasi_scein            ),   
-		.asmi_sdoin             (ddasi_sdoin            )    
-`endif           
-		.sector_erase           (asmi_sector_erase      ),
-		.sector_protect         (asmi_sector_protect    )
-	);
-	
-endmodule

ip/altera_epcq_controller_mod/altera_epcq_controller_wrapper_hw.tcl

@@ -1,648 +0,0 @@
-# (C) 2001-2015 Altera Corporation. All rights reserved.
-# Your use of Altera Corporation's design tools, logic functions and other 
-# software and tools, and its AMPP partner logic functions, and any output 
-# files any of the foregoing (including device programming or simulation 
-# files), and any associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License Subscription 
-# Agreement, Altera MegaCore Function License Agreement, or other applicable 
-# license agreement, including, without limitation, that your use is for the 
-# sole purpose of programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the applicable 
-# agreement for further details.
-
-
-package require -exact qsys 14.1
-package require -exact altera_terp 1.0
-
-
-# 
-# module altera_trace_wrapper
-# 
-set_module_property DESCRIPTION "This component is a serial flash controller which allows user to access Altera EPCQ devices"
-set_module_property NAME altera_epcq_controller_mod
-set_module_property VERSION 17.1
-set_module_property INTERNAL false
-set_module_property OPAQUE_ADDRESS_MAP true
-set_module_property GROUP "Basic Functions/Configuration and Programming"
-set_module_property AUTHOR "Altera Corporation"
-set_module_property DISPLAY_NAME "Altera Serial Flash Controller"
-set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
-set_module_property HIDE_FROM_QUARTUS true
-set_module_property EDITABLE true
-set_module_property ALLOW_GREYBOX_GENERATION false
-set_module_property REPORT_HIERARCHY false
-set_module_property ELABORATION_CALLBACK	elaboration
-
-add_fileset QUARTUS_SYNTH QUARTUS_SYNTH add_topwrapper_fileset_proc
-set_fileset_property QUARTUS_SYNTH TOP_LEVEL altera_epcq_controller_wrapper
-set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
-set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
-
-add_fileset SIM_VERILOG SIM_VERILOG add_topwrapper_fileset_proc
-set_fileset_property SIM_VERILOG TOP_LEVEL altera_epcq_controller_wrapper
-set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
-set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE true
-# 
-# parameters
-#
-# +-----------------------------------
-# | device family info
-# +-----------------------------------
-set all_supported_device_families_list {"Arria 10" "Cyclone V" "Arria V GZ" "Arria V" "Stratix V" "Stratix IV" \
-											"Cyclone IV GX" "Cyclone IV E" "Cyclone III GL" "Arria II GZ" "Arria II GX"}
-									
-proc check_device_ini {device_families_list}     {
-
-    set enable_max10    [get_quartus_ini enable_max10_active_serial ENABLED]
-    
-    if {$enable_max10 == 1} {
-        lappend device_families_list    "MAX 10 FPGA"
-     } 
-    return $device_families_list
-}
-
-set device_list    [check_device_ini $all_supported_device_families_list]
-set_module_property SUPPORTED_DEVICE_FAMILIES    $device_list
-
-add_parameter 			DEVICE_FAMILY 	STRING
-set_parameter_property 	DEVICE_FAMILY 	SYSTEM_INFO 	{DEVICE_FAMILY}
-set_parameter_property 	DEVICE_FAMILY 	VISIBLE 		false
-set_parameter_property  DEVICE_FAMILY 	HDL_PARAMETER true
-
-add_parameter ASI_WIDTH INTEGER 1
-set_parameter_property ASI_WIDTH DEFAULT_VALUE 1
-set_parameter_property ASI_WIDTH DISPLAY_NAME ASI_WIDTH
-set_parameter_property ASI_WIDTH DERIVED true
-set_parameter_property ASI_WIDTH TYPE INTEGER
-set_parameter_property ASI_WIDTH VISIBLE false
-set_parameter_property ASI_WIDTH UNITS None
-set_parameter_property ASI_WIDTH ALLOWED_RANGES {1, 4}
-set_parameter_property ASI_WIDTH HDL_PARAMETER true
-
-add_parameter CS_WIDTH INTEGER 1
-set_parameter_property CS_WIDTH DEFAULT_VALUE 1
-set_parameter_property CS_WIDTH DISPLAY_NAME CS_WIDTH
-set_parameter_property CS_WIDTH DERIVED true
-set_parameter_property CS_WIDTH TYPE INTEGER
-set_parameter_property CS_WIDTH VISIBLE false
-set_parameter_property CS_WIDTH UNITS None
-set_parameter_property CS_WIDTH ALLOWED_RANGES {1, 3}
-set_parameter_property CS_WIDTH HDL_PARAMETER true
-
-add_parameter ADDR_WIDTH INTEGER 19
-set_parameter_property ADDR_WIDTH DEFAULT_VALUE 19
-set_parameter_property ADDR_WIDTH DISPLAY_NAME ADDR_WIDTH
-set_parameter_property ADDR_WIDTH DERIVED true
-set_parameter_property ADDR_WIDTH TYPE INTEGER
-set_parameter_property ADDR_WIDTH VISIBLE false
-set_parameter_property ADDR_WIDTH UNITS None
-# 16M-19bit, 32M-20bit, 64M-21bit, 128M-22bit, 256M-23bit, 512M-24bit, 1024M-25bit, 2048M-26bit...
-set_parameter_property ADDR_WIDTH ALLOWED_RANGES {19, 20, 21, 22, 23, 24, 25, 26, 27, 28}	
-set_parameter_property ADDR_WIDTH HDL_PARAMETER true
-
-add_parameter ASMI_ADDR_WIDTH INTEGER 24
-set_parameter_property ASMI_ADDR_WIDTH DEFAULT_VALUE 24
-set_parameter_property ASMI_ADDR_WIDTH DISPLAY_NAME ASMI_ADDR_WIDTH
-set_parameter_property ASMI_ADDR_WIDTH DERIVED true
-set_parameter_property ASMI_ADDR_WIDTH TYPE INTEGER
-set_parameter_property ASMI_ADDR_WIDTH VISIBLE false
-set_parameter_property ASMI_ADDR_WIDTH UNITS None
-set_parameter_property ASMI_ADDR_WIDTH ALLOWED_RANGES {24, 32}		
-set_parameter_property ASMI_ADDR_WIDTH HDL_PARAMETER true
-
-add_parameter ENABLE_4BYTE_ADDR	INTEGER "0"
-set_parameter_property ENABLE_4BYTE_ADDR DISPLAY_NAME "Enable 4-byte addressing mode"
-set_parameter_property ENABLE_4BYTE_ADDR DESCRIPTION "Check to enable 4-byte addressing mode for device larger than 128Mbyte"
-set_parameter_property ENABLE_4BYTE_ADDR AFFECTS_GENERATION true
-set_parameter_property ENABLE_4BYTE_ADDR VISIBLE false
-set_parameter_property ENABLE_4BYTE_ADDR HDL_PARAMETER true
-set_parameter_property ENABLE_4BYTE_ADDR DERIVED true
-
-# +-----------------------------------
-
-# add system info parameter
-add_parameter           deviceFeaturesSystemInfo   STRING 			"None"
-set_parameter_property  deviceFeaturesSystemInfo   system_info		"DEVICE_FEATURES"
-set_parameter_property  deviceFeaturesSystemInfo   VISIBLE false
-
-add_parameter DDASI	INTEGER "0"
-set_parameter_property DDASI DISPLAY_NAME "Disable dedicated Active Serial interface"
-set_parameter_property DDASI DESCRIPTION "Check to route ASMIBLOCK signals to top level of design"
-set_parameter_property DDASI AFFECTS_GENERATION true
-set_parameter_property DDASI VISIBLE false
-set_parameter_property DDASI DERIVED false
-
-add_parameter clkFreq LONG
-set_parameter_property clkFreq DEFAULT_VALUE {0}
-set_parameter_property clkFreq DISPLAY_NAME {clkFreq}
-set_parameter_property clkFreq VISIBLE {0}
-set_parameter_property clkFreq AFFECTS_GENERATION {1}
-set_parameter_property clkFreq HDL_PARAMETER {0}
-set_parameter_property clkFreq SYSTEM_INFO {clock_rate clk}
-set_parameter_property clkFreq SYSTEM_INFO_TYPE {CLOCK_RATE}
-set_parameter_property clkFreq SYSTEM_INFO_ARG {clock_sink}
-
-# 
-# connection point clock_sink
-# 
-add_interface clock_sink clock end
-set_interface_property clock_sink clockRate 0
-set_interface_property clock_sink ENABLED true
-set_interface_property clock_sink EXPORT_OF ""
-set_interface_property clock_sink PORT_NAME_MAP ""
-set_interface_property clock_sink CMSIS_SVD_VARIABLES ""
-set_interface_property clock_sink SVD_ADDRESS_GROUP ""
-
-add_interface_port clock_sink clk clk Input 1
-
-
-# 
-# connection point reset
-# 
-add_interface reset reset end
-set_interface_property reset associatedClock clock_sink
-set_interface_property reset synchronousEdges DEASSERT
-set_interface_property reset ENABLED true
-set_interface_property reset EXPORT_OF ""
-set_interface_property reset PORT_NAME_MAP ""
-set_interface_property reset CMSIS_SVD_VARIABLES ""
-set_interface_property reset SVD_ADDRESS_GROUP ""
-
-add_interface_port reset reset_n reset_n Input 1
-
-
-# 
-# connection point avl_csr
-# 
-add_interface avl_csr avalon end
-set_interface_property avl_csr addressUnits WORDS
-set_interface_property avl_csr associatedClock clock_sink
-set_interface_property avl_csr associatedReset reset
-set_interface_property avl_csr bitsPerSymbol 8
-set_interface_property avl_csr burstOnBurstBoundariesOnly false
-set_interface_property avl_csr burstcountUnits WORDS
-set_interface_property avl_csr explicitAddressSpan 0
-set_interface_property avl_csr holdTime 0
-set_interface_property avl_csr linewrapBursts false
-set_interface_property avl_csr maximumPendingReadTransactions 1
-set_interface_property avl_csr maximumPendingWriteTransactions 0
-set_interface_property avl_csr readLatency 0
-set_interface_property avl_csr readWaitTime 0
-set_interface_property avl_csr setupTime 0
-set_interface_property avl_csr timingUnits Cycles
-set_interface_property avl_csr writeWaitTime 0
-set_interface_property avl_csr ENABLED true
-set_interface_property avl_csr EXPORT_OF ""
-set_interface_property avl_csr PORT_NAME_MAP ""
-set_interface_property avl_csr CMSIS_SVD_VARIABLES ""
-set_interface_property avl_csr SVD_ADDRESS_GROUP ""
-
-add_interface_port avl_csr avl_csr_read read Input 1
-add_interface_port avl_csr avl_csr_waitrequest waitrequest Output 1
-add_interface_port avl_csr avl_csr_write write Input 1
-add_interface_port avl_csr avl_csr_addr address Input 3
-add_interface_port avl_csr avl_csr_wrdata writedata Input 32
-add_interface_port avl_csr avl_csr_rddata readdata Output 32
-add_interface_port avl_csr avl_csr_rddata_valid readdatavalid Output 1
-
-# 
-# connection point avl_mem
-# 
-add_interface avl_mem avalon end
-set_interface_property avl_mem addressUnits WORDS
-set_interface_property avl_mem associatedClock clock_sink
-set_interface_property avl_mem associatedReset reset
-set_interface_property avl_mem bitsPerSymbol 8
-set_interface_property avl_mem burstOnBurstBoundariesOnly false
-set_interface_property avl_mem burstcountUnits WORDS
-set_interface_property avl_mem explicitAddressSpan 0
-set_interface_property avl_mem holdTime 0
-set_interface_property avl_mem linewrapBursts true
-set_interface_property avl_mem maximumPendingReadTransactions 1
-set_interface_property avl_mem maximumPendingWriteTransactions 0
-set_interface_property avl_mem constantBurstBehavior true
-set_interface_property avl_mem readLatency 0
-set_interface_property avl_mem readWaitTime 0
-set_interface_property avl_mem setupTime 0
-set_interface_property avl_mem timingUnits Cycles
-set_interface_property avl_mem writeWaitTime 0
-set_interface_property avl_mem ENABLED true
-set_interface_property avl_mem EXPORT_OF ""
-set_interface_property avl_mem PORT_NAME_MAP ""
-set_interface_property avl_mem CMSIS_SVD_VARIABLES ""
-set_interface_property avl_mem SVD_ADDRESS_GROUP ""
-
-add_interface_port avl_mem avl_mem_write write Input 1
-add_interface_port avl_mem avl_mem_burstcount burstcount Input 7
-add_interface_port avl_mem avl_mem_waitrequest waitrequest Output 1
-add_interface_port avl_mem avl_mem_read read Input 1
-add_interface_port avl_mem avl_mem_addr address Input ADDR_WIDTH
-add_interface_port avl_mem avl_mem_wrdata writedata Input 32
-add_interface_port avl_mem avl_mem_rddata readdata Output 32
-add_interface_port avl_mem avl_mem_rddata_valid readdatavalid Output 1
-add_interface_port avl_mem avl_mem_byteenable byteenable Input 4
-
-# 
-# connection point interrupt_sender
-# 
-add_interface interrupt_sender interrupt end
-set_interface_property interrupt_sender associatedAddressablePoint avl_csr
-set_interface_property interrupt_sender associatedClock clock_sink
-set_interface_property interrupt_sender associatedReset reset
-set_interface_property interrupt_sender bridgedReceiverOffset ""
-set_interface_property interrupt_sender bridgesToReceiver ""
-set_interface_property interrupt_sender ENABLED true
-set_interface_property interrupt_sender EXPORT_OF ""
-set_interface_property interrupt_sender PORT_NAME_MAP ""
-set_interface_property interrupt_sender CMSIS_SVD_VARIABLES ""
-set_interface_property interrupt_sender SVD_ADDRESS_GROUP ""
-
-add_interface_port interrupt_sender irq irq Output 1
-
-proc proc_get_derive_addr_width {flash_type} {
-    switch $flash_type {
-        "EPCS16" - "EPCQ16" {
-            return 19 
-        }
-        "EPCS64" - "EPCQ64" {
-            return 21
-        }
-        "EPCS128" - "EPCQ128" {
-            return 22
-        }
-		"EPCQ32" {
-            return 20
-		}
-        "EPCQ256" - "EPCQL256" {
-            return 23
-        }
-        "EPCQ512" - "EPCQL512" {
-            return 24
-        }
-        "EPCQL1024" {
-            return 25
-        }
-        default {
-            # Should never enter this function
-            send_message error "$flash_type is not a valid flash type"
-        }
-    
-    }
-}
-
-set all_supported_SPI_list {"EPCS16" "EPCS64" "EPCS128" "EPCQ16" "EPCQ32" "EPCQ64" "EPCQ128" "EPCQ256" \
-							"EPCQ512" "EPCQL256" "EPCQL512" "EPCQL1024"}
-							
-# SPI device selection
-add_parameter FLASH_TYPE STRING "EPCQ16"
-set_parameter_property FLASH_TYPE DISPLAY_NAME "Configuration device type"
-set_parameter_property FLASH_TYPE ALLOWED_RANGES $all_supported_SPI_list
-set_parameter_property FLASH_TYPE DESCRIPTION "Select targeted EPCS/EPCQ devices"
-set_parameter_property FLASH_TYPE AFFECTS_GENERATION true
-set_parameter_property FLASH_TYPE VISIBLE true
-set_parameter_property FLASH_TYPE DERIVED false
-
-add_parameter IO_MODE STRING "STANDARD"
-set_parameter_property IO_MODE DISPLAY_NAME "Choose I/O mode"
-set_parameter_property IO_MODE ALLOWED_RANGES {"STANDARD" "QUAD"}
-set_parameter_property IO_MODE DESCRIPTION "Select extended data width when Fast Read operation is enabled"
-
-add_parameter CHIP_SELS INTEGER "1"
-set_parameter_property CHIP_SELS DISPLAY_NAME "Number of Chip Selects used"
-set_parameter_property CHIP_SELS ALLOWED_RANGES {1 2 3}
-set_parameter_property CHIP_SELS DESCRIPTION "Number of EPCQ(L) devices that are attached and need a CHIPSEL"
-set_parameter_property CHIP_SELS HDL_PARAMETER true
-set_parameter_property CHIP_SELS AFFECTS_GENERATION true
-#
-# Add instance 
-#
-proc add_topwrapper_fileset_proc {altera_epcq_controller} {
-	# QSPI that supported for 4-byte addressing - en4b_addr, ex4b_addr
-	set supported_4byte_addr 	{"EPCQ256" "EPCQ512" "EPCQL256" "EPCQL512" "EPCQL1024" "N25Q512"}
-	set DDASI 					[ get_parameter_value DDASI ]
-	set DEVICE_FAMILY 			[ get_parameter_value DEVICE_FAMILY ]
-	set FLASH_TYPE 				[ get_parameter_value FLASH_TYPE ]
-	set ADDR_WIDTH				[ get_parameter_value ADDR_WIDTH ]
-	set is_4byte_addr_support	"false"
-	
-	# check whether devices supporting multiple flash - only for Arria 10
-	if {[check_device_family_equivalence $DEVICE_FAMILY "Arria 10"]} {
-		set MULTICHIP 1
-	} else {
-		set MULTICHIP 0
-	}
-	
-	if { $DDASI eq "1" } {
-		set DDASI_ON 1
-	} else {
-		set DDASI_ON 0
-	}
-	
-	if { $FLASH_TYPE eq "EPCS16" || $FLASH_TYPE eq "EPCS64" } {
-		set ENABLE_SID 1
-	} else {
-		set ENABLE_SID 0
-	}
-	
-	if { $FLASH_TYPE eq "EPCQL512" || $FLASH_TYPE eq "EPCQL1024" } {
-		set ENABLE_BULK_ERASE 0
-	} else {
-		set ENABLE_BULK_ERASE 1
-	}
-	
-	 # check whether SPI device support 4-byte addressing
-	foreach re_spi_1   $supported_4byte_addr {
-		if {$re_spi_1 eq $FLASH_TYPE} {
-			set is_4byte_addr_support	"true"
-			break;
-		 }
-	 }
-	 
-	if {$is_4byte_addr_support eq "true"} {
-		set ENABLE_4BYTE_ADDR_CODE 1
-	} else {
-		set ENABLE_4BYTE_ADDR_CODE 0
-	}
-	
-	# ---------------------------------
-	#   Terp for top level wrapper
-	# ---------------------------------
-	#Do Terp
-	set template_file [ file join "./" "altera_epcq_controller_wrapper.sv.terp" ]  
-	set template   [ read [ open $template_file r ] ]
-	
-	if {$DDASI_ON} {
-		set params(DDASI_ON) 		"`define DDASI_ON" 	
-	} else {
-		set params(DDASI_ON) 		"" 	
-	}
-	
-	if {$MULTICHIP} {
-		set params(MULTICHIP) 		"`define MULTICHIP" 	
-	} else {
-		set params(MULTICHIP) 		"" 	
-	}
-	
-	if {$ENABLE_SID} {
-		set params(SID_EN) 			"`define ENABLE_SID"
-	} else {
-		set params(SID_EN) 			""
-	}
-	
-	if {$ENABLE_BULK_ERASE} {
-		set params(BULK_ERASE_EN) 	"`define ENABLE_BULK_ERASE"
-	} else {
-		set params(BULK_ERASE_EN) 	""
-	}
-	
-	if {$ENABLE_4BYTE_ADDR_CODE} {
-		set params(4BYTE_ADDR_EN) 		"`define ENABLE_4BYTE_ADDR_CODE"
-	} else {
-		set params(4BYTE_ADDR_EN) 		""
-	}
-	
-	set result   					[ altera_terp $template params ]
-	
-	#Add top wrapper file
-	add_fileset_file ./altera_epcq_controller_wrapper.sv SYSTEM_VERILOG TEXT $result 
-}
-
-# This proc is called by elaboration proc to set embeddedsw C Macros assignments 
-# used by downstream tools
-proc set_cmacros {is_qspi flash_type} {
-    if {$is_qspi eq "true"} {
-        set_module_assignment embeddedsw.CMacro.IS_EPCS 0
-    } else {
-        set_module_assignment embeddedsw.CMacro.IS_EPCS 1
-    }
-
-    #string name of flash
-    set_module_assignment embeddedsw.CMacro.FLASH_TYPE $flash_type
-
-    #page size in bytes
-    set_module_assignment embeddedsw.CMacro.PAGE_SIZE 256
-    
-    #sector and subsector size in bytes
-    set_module_assignment embeddedsw.CMacro.SUBSECTOR_SIZE 4096
-    set_module_assignment embeddedsw.CMacro.SECTOR_SIZE 65536
-
-    #set number of sectors
-    switch $flash_type {
-        "EPCS16" - "EPCQ16" {
-            set_module_assignment embeddedsw.CMacro.NUMBER_OF_SECTORS 32
-        }
-        "EPCQ32" {
-            set_module_assignment embeddedsw.CMacro.NUMBER_OF_SECTORS 64
-		}
-        "EPCS64" - "EPCQ64" {
-            set_module_assignment embeddedsw.CMacro.NUMBER_OF_SECTORS 128
-        }
-        "EPCS128" - "EPCQ128" {
-            set_module_assignment embeddedsw.CMacro.NUMBER_OF_SECTORS 256
-        }
-        "EPCQ256" - "EPCQL256" {
-            set_module_assignment embeddedsw.CMacro.NUMBER_OF_SECTORS 512
-        }
-        "EPCQ512" - "EPCQL512" {
-            set_module_assignment embeddedsw.CMacro.NUMBER_OF_SECTORS 1024
-        }
-        "EPCQL1024" {
-            set_module_assignment embeddedsw.CMacro.NUMBER_OF_SECTORS 2048
-        }
-        default {
-            # Should never enter this function
-            send_message error "$flash_type is not a valid flash type"
-        }
-    }
-}
-
-proc elaboration {} {
-	# QSPI that supported for 4-byte addressing - en4b_addr, ex4b_addr
-	set supported_4byte_addr 	{"EPCQ256" "EPCQ512" "EPCQL256" "EPCQL512" "EPCQL1024" "N25Q512"}
-	set DDASI_ON 				[ get_parameter_value DDASI ]
-	set FLASH_TYPE 				[ get_parameter_value FLASH_TYPE ]
-	set IO_MODE 				[ get_parameter_value IO_MODE ]
-	set DEVICE_FAMILY 			[ get_parameter_value DEVICE_FAMILY ]
-	set ASI_WIDTH 				[ get_parameter_value ASI_WIDTH ]
-	set CS_WIDTH 				[ get_parameter_value CS_WIDTH ]
-	set ASMI_ADDR_WIDTH 		[ get_parameter_value ASMI_ADDR_WIDTH ]
-	set CHIP_SELS			    [ get_parameter_value CHIP_SELS]
-	set temp_addr_width 		[ proc_get_derive_addr_width [ get_parameter_value FLASH_TYPE ] ]
-	set clkFreq 				[ get_parameter_value clkFreq ]
-	set is_4byte_addr_support	"false"
-	set is_qspi					"false"
-
-    # we're not using slow and expensive EPCS flash, thus higher frequency allowed
-	if { $clkFreq > 50000000 } {
-		send_message error "The maximum input clock frequency for Altera Serial Flash controller is 25Mhz."
-	}
-	
-	# check whether SPI device support 4-byte addressing
-	foreach re_spi_1   $supported_4byte_addr {
-		if {$re_spi_1 eq $FLASH_TYPE} {
-			set is_4byte_addr_support	"true"
-			break;
-		 }
-	 }
-	 
-	if {$is_4byte_addr_support eq "true"} {
-		set_parameter_value 	ENABLE_4BYTE_ADDR "1"
-		set_parameter_value		ASMI_ADDR_WIDTH 32
-	} else {
-		set_parameter_value 	ENABLE_4BYTE_ADDR "0"
-		set_parameter_value		ASMI_ADDR_WIDTH 24
-	}
-	
-	# check whether devices supporting multiple flash - only for Arria 10
-	if {[check_device_family_equivalence $DEVICE_FAMILY "Arria 10"]} {
-		set is_multi_flash_support	"true"
-		if {$CHIP_SELS eq 3 } {set_parameter_value 	ADDR_WIDTH 		[ expr $temp_addr_width + 2]}
-		if {$CHIP_SELS eq 2 } {set_parameter_value 	ADDR_WIDTH 		[ expr $temp_addr_width + 1]}
-		if {$CHIP_SELS eq 1 } {set_parameter_value 	ADDR_WIDTH 		$temp_addr_width }
-	} else {
-		set is_multi_flash_support	"false"
-		set_parameter_value 	ADDR_WIDTH 		$temp_addr_width
-	}
-	
-	
-	set_instance_parameter_value	altera_epcq_controller_core DDASI $DDASI_ON
-	set_instance_parameter_value	altera_epcq_controller_core FLASH_TYPE $FLASH_TYPE
-	set_instance_parameter_value	altera_epcq_controller_core IO_MODE $IO_MODE
-	set_instance_parameter_value	altera_epcq_controller_core ASI_WIDTH $ASI_WIDTH
-	set_instance_parameter_value	altera_epcq_controller_core CS_WIDTH $CS_WIDTH
-	set_instance_parameter_value	altera_epcq_controller_core CHIP_SELS $CHIP_SELS
-	set_instance_parameter_value	altera_epcq_controller_core ASMI_ADDR_WIDTH [ get_parameter_value ASMI_ADDR_WIDTH ]
-	set_instance_parameter_value	altera_epcq_controller_core ADDR_WIDTH [ get_parameter_value ADDR_WIDTH ]
-	set_instance_parameter_value	altera_epcq_controller_core ENABLE_4BYTE_ADDR [ get_parameter_value ENABLE_4BYTE_ADDR ]
-
-	set QSPI_list {"EPCQ16" "EPCQ32" "EPCQ64" "EPCQ128" "EPCQ256" "EPCQ512" "EPCQL256" "EPCQL512" "EPCQL1024" \
-					"N25Q512" "S25FL127S"}
-	
-	# devices that supported QSPI - Quad/Dual data width, asmi_dataout, asmi_sdoin, asmi_dataoe
-	set supported_QSPI_devices_list {"Arria 10" "Cyclone V" "Arria V GZ" "Arria V" "Stratix V"}
-	
-	# devices that supported simulation
-	set supported_sim_devices_list {"Arria 10" "Cyclone V" "Arria V GZ" "Arria V" "Stratix V" "MAX 10 FPGA"}
-	
-	# check whether is QSPI devices
-	foreach re_spi_0   $QSPI_list {
-		if {$re_spi_0 eq $FLASH_TYPE} { 
-			set is_qspi		"true"
-			break;
-		 }
-	 }
-	 
-	if {[check_device_family_equivalence $DEVICE_FAMILY $supported_QSPI_devices_list]} {
-		set is_qspi_devices_list	"true"
-	} else {
-		set is_qspi_devices_list	"false"
-	}
-	
-	if {[check_device_family_equivalence $DEVICE_FAMILY $supported_sim_devices_list]} {
-		set is_sim_devices_list	"true"
-	} else {
-		set is_sim_devices_list	"false"
-	}
-	
-	if {$is_qspi_devices_list eq "true" && $is_qspi eq "true"} {
-		set_parameter_property	IO_MODE	ENABLED		true
-		set_instance_parameter_value 	altera_asmi_parallel DATA_WIDTH 		$IO_MODE
-		set_parameter_value ASI_WIDTH 4
-    } else {
-		set_parameter_property	IO_MODE	ENABLED		false
-		set_parameter_value ASI_WIDTH 1
-	}
-	
-	if { $FLASH_TYPE eq "EPCQL512" || $FLASH_TYPE eq "EPCQL1024" } {
-		set_instance_parameter_value 	altera_asmi_parallel gui_bulk_erase 		false
-		set ENABLE_BULK_ERASE 0
-	} else {
-		set_instance_parameter_value 	altera_asmi_parallel gui_bulk_erase 		true
-		set ENABLE_BULK_ERASE 1
-	}
-	
-	if { $is_multi_flash_support eq "true"} {
-		set_parameter_value CS_WIDTH 3
-		set_parameter_property	CHIP_SELS	ENABLED		true
-	} else {
-		set_parameter_value CS_WIDTH 1
-		set_parameter_property	CHIP_SELS	ENABLED		false
-	}
-	
-	set_instance_parameter_value 	altera_asmi_parallel EPCS_TYPE 				$FLASH_TYPE
-	set_instance_parameter_value 	altera_asmi_parallel gui_fast_read 			true
-	set_instance_parameter_value 	altera_asmi_parallel gui_page_write 		true
-	
-	if { $FLASH_TYPE eq "EPCS16" || $FLASH_TYPE eq "EPCS64" } {
-		set_instance_parameter_value 	altera_asmi_parallel gui_read_sid 		true
-	} else {
-		set_instance_parameter_value 	altera_asmi_parallel gui_read_sid 		false
-	}
-	
-	set_instance_parameter_value 	altera_asmi_parallel gui_read_rdid 			true
-	set_instance_parameter_value 	altera_asmi_parallel gui_read_status 		true
-	set_instance_parameter_value 	altera_asmi_parallel gui_sector_erase 		true
-	set_instance_parameter_value 	altera_asmi_parallel gui_sector_protect 	true
-	set_instance_parameter_value 	altera_asmi_parallel gui_wren 				true
-	set_instance_parameter_value 	altera_asmi_parallel gui_write 				true
-	set_instance_parameter_value 	altera_asmi_parallel gui_read_dummyclk		true
-	set_instance_parameter_value 	altera_asmi_parallel PAGE_SIZE 				256
-	set_instance_parameter_value 	altera_asmi_parallel gui_use_asmiblock		$DDASI_ON
-	
-	if {$is_sim_devices_list eq "true"} {
-		set_instance_parameter_value 	altera_asmi_parallel ENABLE_SIM			true
-	} else {
-		set_instance_parameter_value 	altera_asmi_parallel ENABLE_SIM			false
-	}
-
-    set_cmacros $is_qspi $FLASH_TYPE
-}
-
-# add ASMI PARALLEL
-add_hdl_instance 		altera_asmi_parallel altera_asmi_parallel
-
-# add EPCQ CONTROLLER
-add_hdl_instance 		altera_epcq_controller_core altera_epcq_controller_core
-
-# +-------------------------------------
-# | Add settings needed by Nios tools
-# +-------------------------------------
-# Tells us component is a flash 
-set_module_assignment embeddedsw.memoryInfo.IS_FLASH 1
-
-# interface assignments for embedded software
-set_interface_assignment avl_mem embeddedsw.configuration.isFlash 1
-set_interface_assignment avl_mem embeddedsw.configuration.isMemoryDevice 1
-set_interface_assignment avl_mem embeddedsw.configuration.isNonVolatileStorage 1
-set_interface_assignment avl_mem embeddedsw.configuration.isPrintableDevice 0
-
-# These assignments tells tools to create byte-addressed .hex files only
-set_module_assignment embeddedsw.memoryInfo.GENERATE_HEX 1
-set_module_assignment embeddedsw.memoryInfo.USE_BYTE_ADDRESSING_FOR_HEX 1
-set_module_assignment embeddedsw.memoryInfo.GENERATE_DAT_SYM 0
-set_module_assignment embeddedsw.memoryInfo.GENERATE_FLASH 0
-
-# Width of memory
-set_module_assignment embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH 32
-
-# Output directories for programming files
-#set_module_assignment embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR {SIM_DIR}
-#set_module_assignment embeddedsw.memoryInfo.FLASH_INSTALL_DIR {APP_DIR}
-set_module_assignment embeddedsw.memoryInfo.HEX_INSTALL_DIR {QPF_DIR}
-
-# Module assignments related to names of simulation files
-#set_module_assignment postgeneration.simulation.init_file.param_name {INIT_FILENAME}
-#set_module_assignment postgeneration.simulation.init_file.type {MEM_INIT}
-
-# +-------------------------------------
-# | Add settings needed by DTG tools
-# +-------------------------------------
-# add device tree properties
-set_module_assignment embeddedsw.dts.vendor "altr"
-set_module_assignment embeddedsw.dts.name "epcq"
-set_module_assignment embeddedsw.dts.group "epcq"
-set_module_assignment embeddedsw.dts.compatible "altr,epcq-1.0"
-
-## Add documentation links for user guide and/or release notes
-add_documentation_link "User Guide" https://documentation.altera.com/#/link/sfo1400787952932/iga1431459459085 
-add_documentation_link "Release Notes" https://documentation.altera.com/#/link/hco1421698042087/hco1421697689300

ip/altera_epcq_controller_mod/inc/altera_epcq_controller_mod_regs.h

@@ -1,260 +0,0 @@
-/******************************************************************************
-*                                                                             *
-* License Agreement                                                           *
-*                                                                             *
-* Copyright (c) 2014 Altera Corporation, San Jose, California, USA.           *
-* All rights reserved.                                                        *
-*                                                                             *
-* Permission is hereby granted, free of charge, to any person obtaining a     *
-* copy of this software and associated documentation files (the "Software"),  *
-* to deal in the Software without restriction, including without limitation   *
-* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
-* and/or sell copies of the Software, and to permit persons to whom the       *
-* Software is furnished to do so, subject to the following conditions:        *
-*                                                                             *
-* The above copyright notice and this permission notice shall be included in  *
-* all copies or substantial portions of the Software.                         *
-*                                                                             *
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
-* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
-* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
-* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
-* DEALINGS IN THE SOFTWARE.                                                   *
-*                                                                             *
-* This agreement shall be governed in all respects by the laws of the State   *
-* of California and by the laws of the United States of America.              *
-*                                                                             *
-******************************************************************************/
-
-#ifndef __ALTERA_EPCQ_CONTROLLER_REGS_H__
-#define __ALTERA_EPCQ_CONTROLLER_REGS_H__
-
-#include <io.h>
-
-/*
- * EPCQ_RD_STATUS register offset
- *
- * The EPCQ_RD_STATUS register contains information from the read status 
- * register operation. A full description of the register can be found in the 
- * data sheet,
- *
- */
-#define ALTERA_EPCQ_CONTROLLER_STATUS_REG                       (0x0)
-
-/*
- * EPCQ_RD_STATUS register access macros
- */
-#define IOADDR_ALTERA_EPCQ_CONTROLLER_STATUS(base) \
-    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_STATUS_REG)
-
-#define IORD_ALTERA_EPCQ_CONTROLLER_STATUS(base) \
-    IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_STATUS_REG)
-
-#define IOWR_ALTERA_EPCQ_CONTROLLER_STATUS(base, data) \
-    IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_STATUS_REG, data)
-
-/*
- * EPCQ_RD_STATUS register description macros
- */
-
-/** Write in progress bit */
-#define ALTERA_EPCQ_CONTROLLER_STATUS_WIP_MASK                  (0x00000001)
-#define ALTERA_EPCQ_CONTROLLER_STATUS_WIP_AVAILABLE             (0x00000000)
-#define ALTERA_EPCQ_CONTROLLER_STATUS_WIP_BUSY                  (0x00000001)
-/** When to time out a poll of the write in progress bit */
-/* 0.7 sec time out */
-#define ALTERA_EPCQ_CONTROLLER_1US_TIMEOUT_VALUE    		    700000 
-
-/*
- * EPCQ_RD_SID register offset
- *
- * The EPCQ_RD_SID register contains the information from the read silicon ID 
- * operation and can be used to determine what type of EPCS device we have.
- * Only support in EPCS16 and EPCS64.
- *
- * This register is valid only if the device is an EPCS.
- *
- */
-#define ALTERA_EPCQ_CONTROLLER_SID_REG                          (0x4)
-
-/*
- * EPCQ_RD_SID register access macros
- */
-#define IOADDR_ALTERA_EPCQ_CONTROLLER_SID(base) \
-    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_SID_REG)
-
-#define IORD_ALTERA_EPCQ_CONTROLLER_SID(base) \
-    IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_SID_REG)
-
-#define IOWR_ALTERA_EPCQ_CONTROLLER_SID(base, data) \
-    IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_SID_REG, data)
-
-/*
- * EPCQ_RD_SID register description macros
- * 
- * Specific device values obtained from Table 14 of: 
- * "Serial Configuration (EPCS) Devices Datasheet"
- */
-#define ALTERA_EPCQ_CONTROLLER_SID_MASK                         (0x000000FF)
-#define ALTERA_EPCQ_CONTROLLER_SID_EPCS16                       (0x00000014)
-#define ALTERA_EPCQ_CONTROLLER_SID_EPCS64                       (0x00000016)
-#define ALTERA_EPCQ_CONTROLLER_SID_EPCS128                      (0x00000018)
-
-/*
- * EPCQ_RD_RDID register offset
- *
- * The EPCQ_RD_RDID register contains the information from the read memory 
- * capacity operation and can be used to determine what type of EPCQ device 
- * we have.
- *
- * This register is only valid if the device is an EPCQ.
- *
- */
-#define ALTERA_EPCQ_CONTROLLER_RDID_REG                         (0x8)
-
-/*
- * EPCQ_RD_RDID register access macros
- */
-#define IOADDR_ALTERA_EPCQ_CONTROLLER_RDID(base) \
-    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_RDID_REG)
-
-#define IORD_ALTERA_EPCQ_CONTROLLER_RDID(base) \
-    IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_RDID_REG)
-
-#define IOWR_ALTERA_EPCQ_CONTROLLER_RDID(base, data) \
-    IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_RDID_REG, data)
-
-/*
- * EPCQ_RD_RDID register description macros
- * 
- * Specific device values obtained from Table 28 of: 
- *  "Quad-Serial Configuration (EPCQ (www.altera.com/literature/hb/cfg/cfg_cf52012.pdf))
- *  Devices Datasheet"
- */
-#define ALTERA_EPCQ_CONTROLLER_RDID_MASK                         (0x000000FF)
-#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ16                       (0x00000015)
-#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ32                       (0x00000016)
-#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ64                       (0x00000017)
-#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ128                      (0x00000018)
-#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ256                      (0x00000019)
-#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ512                      (0x00000020)
-#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ1024                     (0x00000021)
-
-/*
- * EPCQ_MEM_OP register offset
- *
- * The EPCQ_MEM_OP register is used to do memory protect and erase operations
- *
- */
-#define ALTERA_EPCQ_CONTROLLER_MEM_OP_REG                       (0xC)
-
-/*
- * EPCQ_MEM_OP register access macros
- */
-#define IOADDR_ALTERA_EPCQ_CONTROLLER_MEM_OP(base) \
-    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_MEM_OP_REG)
-
-#define IORD_ALTERA_EPCQ_CONTROLLER_MEM_OP(base) \
-    IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_MEM_OP_REG)
-
-#define IOWR_ALTERA_EPCQ_CONTROLLER_MEM_OP(base, data) \
-    IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_MEM_OP_REG, data)
-
-/*
- * EPCQ_MEM_OP register description macros
- */
-#define ALTERA_EPCQ_CONTROLLER_MEM_OP_CMD_MASK                  (0x00000003)
-#define ALTERA_EPCQ_CONTROLLER_MEM_OP_BULK_ERASE_CMD            (0x00000001)
-#define ALTERA_EPCQ_CONTROLLER_MEM_OP_SECTOR_ERASE_CMD          (0x00000002)
-#define ALTERA_EPCQ_CONTROLLER_MEM_OP_SECTOR_PROTECT_CMD        (0x00000003)
-
-/** see datasheet for sector values */
-#define ALTERA_EPCQ_CONTROLLER_MEM_OP_SECTOR_VALUE_MASK         (0x00FFFF00)
-
-/*
- * EPCQ_ISR register offset
- *
- * The EPCQ_ISR register is used to determine whether an invalid write or erase 
- * operation triggered an interrupt
- *
- */
-#define ALTERA_EPCQ_CONTROLLER_ISR_REG                          (0x10)
-
-/*
- * EPCQ_ISR register access macros
- */
-#define IOADDR_ALTERA_EPCQ_CONTROLLER_ISR(base) \
-    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_ISR_REG)
-
-#define IORD_ALTERA_EPCQ_CONTROLLER_ISR(base) \
-    IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_ISR_REG)
-
-#define IOWR_ALTERA_EPCQ_CONTROLLER_ISR(base, data) \
-    IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_ISR_REG, data)
-
-/*
- * EPCQ_ISR register description macros
- */
-#define ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_ERASE_MASK           (0x00000001)
-#define ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_ERASE_ACTIVE         (0x00000001)
-
-#define ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_WRITE_MASK           (0x00000002)
-#define ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_WRITE_ACTIVE         (0x00000002)
-
-
-/*
- * EPCQ_IMR register offset
- *
- * The EPCQ_IMR register is used to mask the invalid erase or the invalid write 
- * interrupts.
- *
- */
-#define ALTERA_EPCQ_CONTROLLER_IMR_REG                          (0x14)
-
-/*
- * EPCQ_IMR register access macros
- */
-#define IOADDR_ALTERA_EPCQ_CONTROLLER_IMR(base) \
-    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_IMR_REG)
-
-#define IORD_ALTERA_EPCQ_CONTROLLER_IMR(base) \
-    IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_IMR_REG)
-
-#define IOWR_ALTERA_EPCQ_CONTROLLER_IMR(base, data) \
-    IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_IMR_REG, data)
-
-/*
- * EPCQ_IMR register description macros
- */
-#define ALTERA_EPCQ_CONTROLLER_IMR_ILLEGAL_ERASE_MASK           (0x00000001)
-#define ALTERA_EPCQ_CONTROLLER_IMR_ILLEGAL_ERASE_ENABLED        (0x00000001)
-
-#define ALTERA_EPCQ_CONTROLLER_IMR_ILLEGAL_WRITE_MASK           (0x00000002)
-#define ALTERA_EPCQ_CONTROLLER_IMR_ILLEGAL_WRITE_ENABLED        (0x00000002)
-
-/*
- * EPCQ_CHIP_SELECT register offset
- *
- * The EPCQ_CHIP_SELECT register is used to issue chip select 
- */
-#define ALTERA_EPCQ_CHIP_SELECT_REG                          (0x18)
-
-/*
- * EPCQ_CHIP_SELECT register access macros
- */
-#define IOADDR_ALTERA_EPCQ_CHIP_SELECT(base) \
-    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CHIP_SELECT_REG)
-
-#define IOWR_ALTERA_EPCQ_CHIP_SELECT(base, data) \
-    IOWR_32DIRECT(base, ALTERA_EPCQ_CHIP_SELECT_REG, data)
-
-/*
- * EPCQ_CHIP_SELECT register description macros
- */
-#define ALTERA_EPCQ_CHIP1_SELECT        (0x00000001)
-#define ALTERA_EPCQ_CHIP2_SELECT        (0x00000002)
-#define ALTERA_EPCQ_CHIP3_SELECT        (0x00000003)
-
-#endif /* __ALTERA_EPCQ_CONTROLLER_REGS_H__ */

ip/altera_jtag_avalon_master_mod/altera_jtag_avalon_master_mod_hw.tcl

@@ -0,0 +1,246 @@
+package require -exact sopc 9.1
+
+# +-----------------------------------
+# | module altera_jtag_avalon_master_mod
+# |
+set_module_property NAME altera_jtag_avalon_master_mod
+set_module_property DESCRIPTION "The JTAG to Avalon Master Bridge is a collection of pre-wired components that provide an Avalon Master using the new JTAG channel."
+set_module_property VERSION "20.1"
+set_module_property GROUP "Basic Functions/Bridges and Adaptors/Memory Mapped"
+set_module_property AUTHOR  "Altera Corporation"
+set_module_property DISPLAY_NAME "JTAG to Avalon Master Bridge (customized)"
+set_module_property DATASHEET_URL "http://www.altera.com/literature/hb/nios2/qts_qii55011.pdf"
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE false
+set_module_property ANALYZE_HDL false
+set_module_property VALIDATION_CALLBACK validate
+set_module_property COMPOSE_CALLBACK compose
+
+set_module_assignment debug.hostConnection {type jtag id 110:132}
+# |
+# +-----------------------------------
+
+# +-----------------------------------
+# | parameters
+# |
+add_parameter USE_PLI INTEGER 0
+set_parameter_property USE_PLI DISPLAY_NAME "Use Simulation Link Mode"
+set_parameter_property USE_PLI DISPLAY_HINT boolean
+set_parameter_property USE_PLI UNITS None
+set_parameter_property USE_PLI HDL_PARAMETER true
+
+add_parameter PLI_PORT INTEGER 50000
+set_parameter_property PLI_PORT DISPLAY_NAME "Simulation Link Server Port"
+set_parameter_property PLI_PORT UNITS None
+set_parameter_property PLI_PORT VISIBLE true
+set_parameter_property PLI_PORT ENABLED false
+set_parameter_property PLI_PORT HDL_PARAMETER true
+
+add_parameter COMPONENT_CLOCK INTEGER 0
+set_parameter_property COMPONENT_CLOCK SYSTEM_INFO { CLOCK_RATE clock }
+set_parameter_property COMPONENT_CLOCK VISIBLE false
+
+add_parameter           FAST_VER              "INTEGER" "0" ""
+set_parameter_property  FAST_VER              "VISIBLE" true
+set_parameter_property  FAST_VER              "DISPLAY_NAME" "Enhanced transaction master"
+set_parameter_property  FAST_VER              "DESCRIPTION"  "Increase transaction master throughput"
+set_parameter_property  FAST_VER              "DISPLAY_HINT" "boolean"
+set_parameter_property  FAST_VER              "STATUS" experimental
+
+add_parameter           FIFO_DEPTHS           "INTEGER" "2" ""
+set_parameter_property  FIFO_DEPTHS           "VISIBLE" true
+set_parameter_property  FIFO_DEPTHS           "HDL_PARAMETER" true
+set_parameter_property  FIFO_DEPTHS           "ALLOWED_RANGES" "2:8192"
+set_parameter_property  FIFO_DEPTHS           "DISPLAY_NAME" "FIFO depth"
+set_parameter_property  FIFO_DEPTHS           "DESCRIPTION"  "User need to tweak this to find the sweet spot"
+set_parameter_property  FIFO_DEPTHS           "STATUS" experimental
+
+add_parameter USE_MEMORY_BLOCKS INTEGER 0
+set_parameter_property USE_MEMORY_BLOCKS DISPLAY_NAME "Use memory blocks instead of LEs"
+set_parameter_property USE_MEMORY_BLOCKS DISPLAY_HINT boolean
+set_parameter_property USE_MEMORY_BLOCKS UNITS None
+set_parameter_property USE_MEMORY_BLOCKS HDL_PARAMETER true
+# |
+# +-----------------------------------
+# +-----------------------------------
+# | Validate
+# |
+proc validate {} {
+    set use_pli [ get_parameter_value USE_PLI ]
+    set use_fast [ get_parameter_value FAST_VER ]
+    if {$use_pli == ""} {
+        set_parameter_value USE_PLI 0
+        set use_pli 0
+    }
+    if {$use_fast == ""} {
+        set_parameter_value FAST_VER 0
+        set use_fast 0
+    }
+    if {$use_pli == 0} {
+      set_parameter_property PLI_PORT ENABLED false
+    } else {
+      set_parameter_property PLI_PORT ENABLED true
+    }
+    if {$use_fast == 0} {
+        set_parameter_property FIFO_DEPTHS ENABLED false
+    } else {
+        set_parameter_property FIFO_DEPTHS ENABLED true
+    }
+}
+# |
+# +-----------------------------------
+# +-----------------------------------
+# | Compose
+# |
+proc compose {} {
+
+    # +-----------------------------------
+    # | submodule instantiation
+    # |
+    #add_instance clk_src     clock_source
+    add_instance  clk_src    altera_clock_bridge
+    add_instance  clk_rst    altera_reset_bridge
+    add_instance jtag_phy_embedded_in_jtag_master altera_jtag_dc_streaming
+    add_instance timing_adt  timing_adapter
+    add_instance fifo        altera_avalon_sc_fifo
+    add_instance b2p         altera_avalon_st_bytes_to_packets
+    add_instance p2b         altera_avalon_st_packets_to_bytes
+    add_instance transacto   altera_avalon_packets_to_master
+    add_instance b2p_adapter channel_adapter
+    add_instance p2b_adapter channel_adapter
+
+    # altera_reset_bridge parameters
+    set_instance_parameter clk_rst SYNCHRONOUS_EDGES none
+    # altera_jtag_dc_streaming parameters
+    set_instance_parameter jtag_phy_embedded_in_jtag_master PURPOSE 1
+    set_instance_parameter jtag_phy_embedded_in_jtag_master DOWNSTREAM_FIFO_SIZE 64
+    set_instance_parameter jtag_phy_embedded_in_jtag_master USE_PLI  [ get_parameter_value USE_PLI ]
+    set_instance_parameter jtag_phy_embedded_in_jtag_master PLI_PORT [ get_parameter_value PLI_PORT ]
+    # timing adapter parameters
+    set_instance_parameter timing_adt inBitsPerSymbol   8
+    set_instance_parameter timing_adt inChannelWidth    0
+    set_instance_parameter timing_adt inErrorWidth      0
+    set_instance_parameter timing_adt inMaxChannel      0
+    set_instance_parameter timing_adt inReadyLatency    0
+    set_instance_parameter timing_adt inSymbolsPerBeat  1
+    set_instance_parameter timing_adt inUseEmpty        false
+    set_instance_parameter timing_adt inUseEmptyPort    NO
+    set_instance_parameter timing_adt inUsePackets      false
+    set_instance_parameter timing_adt inUseReady        [ get_parameter_value USE_PLI ]
+    set_instance_parameter timing_adt inUseValid        true
+    set_instance_parameter timing_adt outReadyLatency   0
+    set_instance_parameter timing_adt outUseReady       true
+    set_instance_parameter timing_adt outUseValid       true
+    # b2p channel adapter parameters
+    set_instance_parameter b2p_adapter inBitsPerSymbol   8
+    set_instance_parameter b2p_adapter inChannelWidth    8
+    set_instance_parameter b2p_adapter inErrorWidth      0
+    set_instance_parameter b2p_adapter inMaxChannel      255
+    set_instance_parameter b2p_adapter inReadyLatency    0
+    set_instance_parameter b2p_adapter inSymbolsPerBeat  1
+    set_instance_parameter b2p_adapter inUseEmpty        false
+    set_instance_parameter b2p_adapter inUseEmptyPort    AUTO
+    set_instance_parameter b2p_adapter inUsePackets      true
+    set_instance_parameter b2p_adapter inUseReady        true
+    set_instance_parameter b2p_adapter outChannelWidth   0
+    set_instance_parameter b2p_adapter outMaxChannel     0
+    # p2b channel adapter parameters
+    set_instance_parameter p2b_adapter inBitsPerSymbol   8
+    set_instance_parameter p2b_adapter inChannelWidth    0
+    set_instance_parameter p2b_adapter inErrorWidth      0
+    set_instance_parameter p2b_adapter inMaxChannel      0
+    set_instance_parameter p2b_adapter inReadyLatency    0
+    set_instance_parameter p2b_adapter inSymbolsPerBeat  1
+    set_instance_parameter p2b_adapter inUseEmpty        false
+    set_instance_parameter p2b_adapter inUseEmptyPort    AUTO
+    set_instance_parameter p2b_adapter inUsePackets      true
+    set_instance_parameter p2b_adapter inUseReady        true
+    set_instance_parameter p2b_adapter outChannelWidth   8
+    set_instance_parameter p2b_adapter outMaxChannel     255
+    # sc fifo parameters
+    set_instance_parameter fifo SYMBOLS_PER_BEAT    1
+    set_instance_parameter fifo BITS_PER_SYMBOL     8
+    set_instance_parameter fifo FIFO_DEPTH          64
+    set_instance_parameter fifo CHANNEL_WIDTH       0
+    set_instance_parameter fifo ERROR_WIDTH         0
+    set_instance_parameter fifo USE_PACKETS         0
+    set_instance_parameter fifo USE_FILL_LEVEL      0
+    set_instance_parameter fifo USE_STORE_FORWARD   0
+    set_instance_parameter fifo USE_ALMOST_FULL_IF  0
+    set_instance_parameter fifo USE_ALMOST_EMPTY_IF 0
+    set_instance_parameter fifo USE_MEMORY_BLOCKS  [ get_parameter_value USE_MEMORY_BLOCKS ]
+    # transacto parameters
+    set_instance_parameter transacto EXPORT_MASTER_SIGNALS  0
+    set_instance_parameter transacto FAST_VER               [ get_parameter_value FAST_VER ]
+    set_instance_parameter transacto FIFO_DEPTHS            [ get_parameter_value FIFO_DEPTHS ]
+    # |
+    # +-----------------------------------
+
+    # +-----------------------------------
+    # | connection point clk
+    # |
+    add_interface           clk clock end
+    set_interface_property  clk export_of clk_src.in_clk
+    # |
+    # +-----------------------------------
+    # +-----------------------------------
+    # | connection point clk_reset
+    # |
+    add_interface           clk_reset reset end
+    set_interface_property  clk_reset export_of clk_rst.in_reset
+    # |
+    # +-----------------------------------
+    # +-----------------------------------
+    # | connection point master
+    # |
+    add_interface           master avalon start
+    set_interface_property  master export_of transacto.avalon_master
+    set_interface_assignment master debug.providesServices master
+    set_interface_assignment master debug.visible true
+    # |
+    # +-----------------------------------
+    # +-----------------------------------
+    # | connection point master_reset
+    # |
+    add_interface           master_reset reset start
+    set_interface_property  master_reset export_of jtag_phy_embedded_in_jtag_master.resetrequest
+    # |
+    # +-----------------------------------
+    # +-----------------------------------
+    # | submodule interface connections
+    # |
+    add_connection clk_src.out_clk jtag_phy_embedded_in_jtag_master.clock
+    add_connection clk_src.out_clk timing_adt.clk
+    add_connection clk_src.out_clk fifo.clk
+    add_connection clk_src.out_clk b2p.clk
+    add_connection clk_src.out_clk p2b.clk
+    add_connection clk_src.out_clk transacto.clk
+    add_connection clk_src.out_clk b2p_adapter.clk
+    add_connection clk_src.out_clk p2b_adapter.clk
+
+    add_connection clk_rst.out_reset jtag_phy_embedded_in_jtag_master.clock_reset
+    add_connection clk_rst.out_reset timing_adt.reset
+    add_connection clk_rst.out_reset fifo.clk_reset
+    add_connection clk_rst.out_reset b2p.clk_reset
+    add_connection clk_rst.out_reset p2b.clk_reset
+    add_connection clk_rst.out_reset transacto.clk_reset
+    add_connection clk_rst.out_reset b2p_adapter.reset
+    add_connection clk_rst.out_reset p2b_adapter.reset
+
+    add_connection jtag_phy_embedded_in_jtag_master.src                timing_adt.in
+    add_connection timing_adt.out         fifo.in
+    add_connection fifo.out               b2p.in_bytes_stream
+    add_connection b2p.out_packets_stream b2p_adapter.in
+    add_connection b2p_adapter.out        transacto.in_stream
+    add_connection transacto.out_stream   p2b_adapter.in
+    add_connection p2b_adapter.out        p2b.in_packets_stream
+    add_connection p2b.out_bytes_stream   jtag_phy_embedded_in_jtag_master.sink
+    # |
+    # +-----------------------------------
+}
+# |
+# +-----------------------------------
+
+
+## Add documentation links for user guide and/or release notes
+add_documentation_link "User Guide" https://documentation.altera.com/#/link/sfo1400787952932/iga1401396548170

ip/i2c_opencores/HAL/inc/i2c_opencores.h

@@ -17,7 +17,7 @@ int I2C_start(alt_u32 base, alt_u32 add, alt_u32 read);
 alt_u32 I2C_read(alt_u32 base,alt_u32 last);
 alt_u32 I2C_write(alt_u32 base,alt_u8 data, alt_u32 last);
 void SPI_read(alt_u32 base, alt_u8 *rdata, int len);
-void SPI_write(alt_u32 base, alt_u8 *wdata, int len);
+void SPI_write(alt_u32 base, const alt_u8 *wdata, int len);
 #define I2C_OK (0)
 #define I2C_ACK (0)
 #define I2C_NOACK (1)

ip/i2c_opencores/HAL/src/i2c_opencores.c

@@ -197,7 +197,7 @@ void SPI_read(alt_u32 base, alt_u8 *rdata, int len)
     }
 }
 
-void SPI_write(alt_u32 base, alt_u8 *wdata, int len)
+void SPI_write(alt_u32 base, const alt_u8 *wdata, int len)
 {
     int i;
 

ip/osd_generator/bin/char_rom.hex

@@ -0,0 +1,257 @@
+:080000000000000000000000F8
+:080001007E8199BD81A5817E7D
+:080002007EFFE7C3FFDBFF7E78
+:080003000010387CFEFEFE6CCB
+:080004000010387CFE7C38106E
+:080005007C387CFEFE387C38DB
+:080006007C387CFE7C381010F0
+:080007000000183C3C18000049
+:08000800FFFFE7C3C3E7FFFFA0
+:08000900003C664242663C0027
+:08000A00FFC399BDBD99C3FFBE
+:08000B0078CCCCCC7D0F070F6F
+:08000C00187E183C6666663C94
+:08000D00E0F07030303F333F9A
+:08000E00C0E66763637F637FB6
+:08000F00995A3CE7E73C5A99BD
+:080010000080E0F8FEF8E0803A
+:0800110000020E3EFE3E0E024D
+:08001200183C7E18187E3C1812
+:08001300006600666666666681
+:08001400001B1B1B7BDBDB7FE3
+:0800150078CC386C6C38633EB6
+:08001600007E7E7E0000000068
+:08001700FF183C7E187E3C1826
+:0800180000181818187E3C18AE
+:0800190000183C7E18181818AD
+:08001A000000180CFE0C180098
+:08001B0000003060FE603000BF
+:08001C000000FEC0C0C000009E
+:08001D0000002466FF662400C8
+:08001E000000FFFF7E3C18000A
+:08001F000000183C7EFFFF0009
+:080020000000000000000000D8
+:08002100003000303078783027
+:0800220000000000006C6C6C92
+:08002300006C6CFE6CFE6C6CBD
+:080024000030F80C78C07C30BC
+:0800250000C6663018CCC600CD
+:080026000076CCDC76386C3862
+:080027000000000000C0606051
+:08002800001830606060301820
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ip/osd_generator/inc/osd_generator_regs.h

@@ -0,0 +1,61 @@
+//
+// Copyright (C) 2019-2020  Markus Hiienkari <mhiienka@niksula.hut.fi>
+//
+// This file is part of Open Source Scan Converter project.
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#ifndef OSD_GENERATOR_REGS_H_
+#define OSD_GENERATOR_REGS_H_
+
+#define OSD_CHAR_ROWS 30
+#define OSD_CHAR_COLS 16
+#define OSD_CHAR_SECTIONS 2
+
+#include <stdint.h>
+
+typedef union {
+    struct {
+        uint8_t enable:1;
+        uint8_t status_refresh:1;
+        uint8_t menu_active:1;
+        uint8_t status_timeout:2;
+        uint8_t x_offset:3;
+        uint8_t y_offset:3;
+        uint8_t x_size:2;
+        uint8_t y_size:2;
+        uint8_t border_color:2;
+        uint32_t osd_rsv:15;
+    } __attribute__((packed, __may_alias__));
+    uint32_t data;
+} osd_config_reg;
+
+// char regs
+typedef struct {
+    char data[OSD_CHAR_ROWS][OSD_CHAR_SECTIONS][OSD_CHAR_COLS];
+} osd_char_array;
+
+typedef struct {
+    uint32_t mask;
+} osd_enable_color_reg;
+
+typedef struct {
+    osd_char_array osd_array;
+    osd_config_reg osd_config;
+    osd_enable_color_reg osd_sec_enable[OSD_CHAR_SECTIONS];
+    osd_enable_color_reg osd_row_color;
+} __attribute__((packed, __may_alias__)) osd_regs;
+
+#endif //OSD_GENERATOR_REGS_H_

ip/osd_generator/osd_generator_hw.tcl

@@ -0,0 +1,159 @@
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+# 
+# module
+# 
+set_module_property DESCRIPTION "OSD generator"
+set_module_property NAME osd_generator
+#set_module_property VERSION 18.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property GROUP "Processors and Peripherals"
+set_module_property AUTHOR ""
+set_module_property DISPLAY_NAME osd_generator
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+#
+# parameters
+#
+#add_parameter USE_MEMORY_BLOCKS INTEGER 1
+#set_parameter_property USE_MEMORY_BLOCKS DISPLAY_NAME "Use memory blocks for character array"
+#set_parameter_property USE_MEMORY_BLOCKS DISPLAY_HINT boolean
+#set_parameter_property USE_MEMORY_BLOCKS UNITS None
+#set_parameter_property USE_MEMORY_BLOCKS HDL_PARAMETER true
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL osd_generator_top
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file osd_generator_top.sv VERILOG PATH osd_generator_top.sv
+
+add_fileset SIM_VERILOG SIM_VERILOG "" ""
+set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false
+set_fileset_property SIM_VERILOG TOP_LEVEL osd_generator_top
+add_fileset_file osd_generator_top.sv VERILOG PATH osd_generator_top.sv
+
+# 
+# parameters
+# 
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point clock_sink
+# 
+add_interface clock_sink clock end
+set_interface_property clock_sink clockRate 0
+set_interface_property clock_sink ENABLED true
+set_interface_property clock_sink EXPORT_OF ""
+set_interface_property clock_sink PORT_NAME_MAP ""
+set_interface_property clock_sink CMSIS_SVD_VARIABLES ""
+set_interface_property clock_sink SVD_ADDRESS_GROUP ""
+
+add_interface_port clock_sink clk_i clk Input 1
+
+
+# 
+# connection point reset_sink
+# 
+add_interface reset_sink reset end
+set_interface_property reset_sink associatedClock clock_sink
+set_interface_property reset_sink synchronousEdges DEASSERT
+set_interface_property reset_sink ENABLED true
+set_interface_property reset_sink EXPORT_OF ""
+set_interface_property reset_sink PORT_NAME_MAP ""
+set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
+set_interface_property reset_sink SVD_ADDRESS_GROUP ""
+
+add_interface_port reset_sink rst_i reset Input 1
+
+
+# 
+# connection point avalon_s
+# 
+add_interface avalon_s avalon end
+set_interface_property avalon_s addressUnits WORDS
+set_interface_property avalon_s associatedClock clock_sink
+set_interface_property avalon_s associatedReset reset_sink
+set_interface_property avalon_s bitsPerSymbol 8
+set_interface_property avalon_s burstOnBurstBoundariesOnly false
+set_interface_property avalon_s burstcountUnits WORDS
+set_interface_property avalon_s explicitAddressSpan 0
+set_interface_property avalon_s holdTime 0
+set_interface_property avalon_s linewrapBursts false
+set_interface_property avalon_s maximumPendingReadTransactions 0
+set_interface_property avalon_s maximumPendingWriteTransactions 0
+set_interface_property avalon_s readLatency 0
+set_interface_property avalon_s readWaitTime 1
+set_interface_property avalon_s setupTime 0
+set_interface_property avalon_s timingUnits Cycles
+set_interface_property avalon_s writeWaitTime 0
+set_interface_property avalon_s ENABLED true
+set_interface_property avalon_s EXPORT_OF ""
+set_interface_property avalon_s PORT_NAME_MAP ""
+set_interface_property avalon_s CMSIS_SVD_VARIABLES ""
+set_interface_property avalon_s SVD_ADDRESS_GROUP ""
+
+add_interface_port avalon_s avalon_s_address address Input 8
+add_interface_port avalon_s avalon_s_writedata writedata Input 32
+add_interface_port avalon_s avalon_s_readdata readdata Output 32
+add_interface_port avalon_s avalon_s_byteenable byteenable Input 4
+add_interface_port avalon_s avalon_s_write write Input 1
+add_interface_port avalon_s avalon_s_read read Input 1
+add_interface_port avalon_s avalon_s_chipselect chipselect Input 1
+add_interface_port avalon_s avalon_s_waitrequest_n waitrequest_n Output 1
+set_interface_assignment avalon_s embeddedsw.configuration.isFlash 0
+set_interface_assignment avalon_s embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment avalon_s embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment avalon_s embeddedsw.configuration.isPrintableDevice 0
+
+
+# 
+# connection point bus
+# 
+#add_sv_interface bus osd_if
+
+# Setting the parameter property to add SV interface parameters
+#set_parameter_property my_interface_parameter SV_INTERFACE_PARAMETER bus
+
+# Setting the port properties to add them to SV interface port set_port_property clk SV_INTERFACE_PORT bus #set_port_property p1 SV_INTERFACE_PORT bus
+#set_port_property p2 SV_INTERFACE_PORT bus
+#set_port_property p1 SV_INTERFACE_SIGNAL bus
+#set_port_property p2 SV_INTERFACE_SIGNAL bus
+
+#Adding the SV Interface File
+#add_fileset_file osd_if.sv SYSTEM_VERILOG PATH osd_if.sv SYSTEMVERILOG_INTERFACE
+
+
+# 
+# connection point osd_if
+# 
+add_interface osd_if conduit end
+set_interface_property osd_if associatedClock ""
+set_interface_property osd_if associatedReset ""
+set_interface_property osd_if ENABLED true
+set_interface_property osd_if EXPORT_OF ""
+set_interface_property osd_if PORT_NAME_MAP ""
+set_interface_property osd_if CMSIS_SVD_VARIABLES ""
+set_interface_property osd_if SVD_ADDRESS_GROUP ""
+
+add_interface_port osd_if vclk vclk Input 1
+add_interface_port osd_if xpos xpos Input 11
+add_interface_port osd_if ypos ypos Input 11
+add_interface_port osd_if osd_enable osd_enable Output 1
+add_interface_port osd_if osd_color osd_color Output 2

ip/osd_generator/osd_generator_sw.tcl

@@ -0,0 +1,54 @@
+#
+# osd_generator_sw.tcl
+#
+
+# Create a new driver
+create_driver osd_generator_driver
+
+# Associate it with some hardware known as "opencores_i2c"
+set_sw_property hw_class_name osd_generator
+
+# The version of this driver
+set_sw_property version 1.0
+
+# This driver may be incompatible with versions of hardware less
+# than specified below. Updates to hardware and device drivers
+# rendering the driver incompatible with older versions of
+# hardware are noted with this property assignment.
+#
+# Multiple-Version compatibility was introduced in version 7.1;
+# prior versions are therefore excluded.
+set_sw_property min_compatible_hw_version 1.0
+
+# Initialize the driver in alt_sys_init()
+set_sw_property auto_initialize false
+
+# Location in generated BSP that above sources will be copied into
+set_sw_property bsp_subdirectory drivers
+
+
+# Interrupt properties:
+# This peripheral has an IRQ output but the driver doesn't currently
+# have any interrupt service routine. To ensure that the BSP tools
+# do not otherwise limit the BSP functionality for users of the
+# Nios II enhanced interrupt port, these settings advertise 
+# compliance with both legacy and enhanced interrupt APIs, and to state
+# that any driver ISR supports preemption. If an interrupt handler
+# is added to this driver, these must be re-examined for validity.
+set_sw_property isr_preemption_supported true
+set_sw_property supported_interrupt_apis "legacy_interrupt_api enhanced_interrupt_api"
+
+#
+# Source file listings...
+#
+
+# C/C++ source files
+
+# Include files
+add_sw_property include_source inc/osd_generator_regs.h
+
+# This driver supports HAL & UCOSII BSP (OS) types
+add_sw_property supported_bsp_type HAL
+add_sw_property supported_bsp_type UCOSII
+
+# End of file

ip/osd_generator/osd_generator_top.sv

@@ -0,0 +1,238 @@
+//
+// Copyright (C) 2019-2020  Markus Hiienkari <mhiienka@niksula.hut.fi>
+//
+// This file is part of Open Source Scan Converter project.
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+module osd_generator_top (
+    // common
+    input clk_i,
+    input rst_i,
+    // avalon slave
+    input [31:0] avalon_s_writedata,
+    output [31:0] avalon_s_readdata,
+    input [7:0] avalon_s_address,
+    input [3:0] avalon_s_byteenable,
+    input avalon_s_write,
+    input avalon_s_read,
+    input avalon_s_chipselect,
+    output avalon_s_waitrequest_n,
+    // OSD interface
+    input vclk,
+    input [10:0] xpos,
+    input [10:0] ypos,
+    output reg osd_enable,
+    output reg [1:0] osd_color
+);
+
+localparam CHAR_ROWS = 30;
+localparam CHAR_COLS = 16;
+localparam CHAR_SECTIONS = 2;
+localparam CHAR_SEC_SEPARATOR = 2;
+
+localparam BG_BLACK =   2'h0;
+localparam BG_BLUE =    2'h1;
+localparam BG_YELLOW =  2'h2;
+localparam BG_WHITE =   2'h3;
+
+localparam OSD_CONFIG_REGNUM =          8'hf0;
+localparam OSD_ROW_LSEC_ENABLE_REGNUM = 8'hf1;
+localparam OSD_ROW_RSEC_ENABLE_REGNUM = 8'hf2;
+localparam OSD_ROW_COLOR_REGNUM =       8'hf3;
+
+reg [31:0] osd_config;
+reg [31:0] config_reg[OSD_ROW_LSEC_ENABLE_REGNUM:OSD_ROW_COLOR_REGNUM] /* synthesis ramstyle = "logic" */;
+
+reg [10:0] xpos_osd_area_scaled, xpos_text_scaled;
+reg [10:0] ypos_osd_area_scaled, ypos_text_scaled;
+reg [7:0] x_ptr[2:5], y_ptr[2:5] /* synthesis ramstyle = "logic" */;
+reg osd_text_act_pp[2:6], osd_act_pp[3:6];
+reg [14:0] to_ctr, to_ctr_ms;
+reg char_px;
+
+wire render_enable = osd_config[0];
+wire status_refresh = osd_config[1];
+wire menu_active = osd_config[2];
+wire [1:0] status_timeout = osd_config[4:3];
+wire [2:0] x_offset = osd_config[7:5];
+wire [2:0] y_offset = osd_config[10:8];
+wire [1:0] x_size = osd_config[12:11];
+wire [1:0] y_size = osd_config[14:13];
+wire [1:0] border_color = osd_config[16:15];
+
+wire [10:0] xpos_scaled_w = (xpos >> x_size)-({3'h0, x_offset} << 3);
+wire [10:0] ypos_scaled_w = (ypos >> y_size)-({3'h0, y_offset} << 3);
+wire [7:0] rom_rdaddr;
+wire [0:7] char_data[7:0];
+wire [4:0] char_row = (ypos_text_scaled >> 3);
+wire [5:0] char_col = (xpos_text_scaled >> 3) - (((xpos_text_scaled >> 3) >= CHAR_COLS) ? CHAR_SEC_SEPARATOR : 0);
+wire [9:0] char_idx = 32*char_row + char_col;
+
+assign avalon_s_waitrequest_n = 1'b1;
+
+char_array char_array_inst (
+    .byteena_a(avalon_s_byteenable),
+    .data(avalon_s_writedata),
+    .rdaddress(char_idx),
+    .rdclock(vclk),
+    .wraddress(avalon_s_address),
+    .wrclock(clk_i),
+    .wren(avalon_s_chipselect && avalon_s_write && (avalon_s_address < CHAR_ROWS*CHAR_COLS*CHAR_SECTIONS)),
+    .q(rom_rdaddr)
+);
+
+char_rom char_rom_inst (
+    .clock(vclk),
+    .address(rom_rdaddr),
+    .q({char_data[7],char_data[6],char_data[5],char_data[4],char_data[3],char_data[2],char_data[1],char_data[0]})
+);
+
+// Pipeline structure
+// |    0     |    1     |    2    |    3    |    4    |    5    |   6    |
+// |----------|----------|---------|---------|---------|---------|--------|
+// > POS_TEXT | POS_AREA |         |         |         |         |        |
+// >          |   PTR    |   PTR   |   PTR   |   PTR   |         |        |
+// >          |  ENABLE  | ENABLE  | ENABLE  | ENABLE  | ENABLE  | ENABLE |
+// >          |  INDEX   |  INDEX  |         |         |         |        |
+// >          |          |         | CHARROM | CHARROM | CHAR_PX | COLOR  |
+integer idx, pp_idx;
+always @(posedge vclk) begin
+    xpos_text_scaled <= xpos_scaled_w;
+    ypos_text_scaled <= ypos_scaled_w;
+
+    xpos_osd_area_scaled <= xpos_text_scaled + 3'h4;
+    ypos_osd_area_scaled <= ypos_text_scaled + 3'h4;
+
+    x_ptr[2] <= xpos_text_scaled[7:0];
+    y_ptr[2] <= ypos_text_scaled[7:0];
+    for(pp_idx = 3; pp_idx <= 5; pp_idx = pp_idx+1) begin
+        x_ptr[pp_idx] <= x_ptr[pp_idx-1];
+        y_ptr[pp_idx] <= y_ptr[pp_idx-1];
+    end
+
+    osd_text_act_pp[2] <= render_enable &
+                          (menu_active || (to_ctr_ms > 0)) &
+                          (((xpos_text_scaled < 8*CHAR_COLS) & config_reg[OSD_ROW_LSEC_ENABLE_REGNUM][ypos_text_scaled/8]) |
+                           ((xpos_text_scaled >= 8*(CHAR_COLS+CHAR_SEC_SEPARATOR)) & (xpos_text_scaled < 8*(2*CHAR_COLS+CHAR_SEC_SEPARATOR)) & config_reg[OSD_ROW_RSEC_ENABLE_REGNUM][ypos_text_scaled/8])) &
+                          (ypos_text_scaled < 8*CHAR_ROWS);
+    for(pp_idx = 3; pp_idx <= 6; pp_idx = pp_idx+1) begin
+        osd_text_act_pp[pp_idx] <= osd_text_act_pp[pp_idx-1];
+    end
+
+    osd_act_pp[3] <= render_enable &
+                     (menu_active || (to_ctr_ms > 0)) &
+                     (((xpos_osd_area_scaled/8 < (CHAR_COLS+1)) & config_reg[OSD_ROW_LSEC_ENABLE_REGNUM][(ypos_osd_area_scaled/8) ? ((ypos_osd_area_scaled/8)-1) : 0]) |
+                      ((xpos_osd_area_scaled/8 >= (CHAR_COLS+1)) & (xpos_osd_area_scaled/8 < (2*CHAR_COLS+CHAR_SEC_SEPARATOR+1)) & (config_reg[OSD_ROW_RSEC_ENABLE_REGNUM][(ypos_osd_area_scaled/8)-1] | config_reg[OSD_ROW_RSEC_ENABLE_REGNUM][ypos_osd_area_scaled/8]))) &
+                     (ypos_osd_area_scaled < 8*(CHAR_ROWS+1));
+    for(pp_idx = 4; pp_idx <= 6; pp_idx = pp_idx+1) begin
+        osd_act_pp[pp_idx] <= osd_act_pp[pp_idx-1];
+    end
+
+    char_px <= char_data[y_ptr[5]][x_ptr[5]];
+
+    osd_enable <= osd_act_pp[6];
+
+    if (osd_text_act_pp[6]) begin
+        if (char_px) begin
+            osd_color <= config_reg[OSD_ROW_COLOR_REGNUM][char_row] ? BG_YELLOW : BG_WHITE;
+        end else begin
+            osd_color <= BG_BLUE;
+        end
+    end else begin // border
+        osd_color <= border_color;
+    end
+end
+
+// OSD status timeout counters
+always @(posedge clk_i)
+begin
+    if (status_refresh) begin
+        to_ctr <= 15'd0;
+        case (status_timeout)
+            default: to_ctr_ms <= 2000; // 2s
+            2'b01:   to_ctr_ms <= 5000; // 5s
+            2'b10:   to_ctr_ms <= 10000; // 10s
+            2'b11:   to_ctr_ms <= 0;    // off
+        endcase
+    end else begin
+        if (to_ctr == 27000-1) begin
+            to_ctr <= 0;
+            if (to_ctr_ms != 15'h0)
+                to_ctr_ms <= to_ctr_ms - 1'b1;
+        end else begin
+            to_ctr <= to_ctr + 1'b1;
+        end
+    end
+end
+
+// Avalon register interface
+always @(posedge clk_i or posedge rst_i) begin
+    if (rst_i) begin
+        osd_config <= 32'h0;
+    end else begin
+        if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==OSD_CONFIG_REGNUM)) begin
+            if (avalon_s_byteenable[3])
+                osd_config[31:24] <= avalon_s_writedata[31:24];
+            if (avalon_s_byteenable[2])
+                osd_config[23:16] <= avalon_s_writedata[23:16];
+            if (avalon_s_byteenable[1])
+                osd_config[15:8] <= avalon_s_writedata[15:8];
+            if (avalon_s_byteenable[0])
+                osd_config[7:0] <= avalon_s_writedata[7:0];
+        end else begin
+            osd_config[1] <= 1'b0; // reset timer refresh bit
+        end
+    end
+end
+
+genvar i;
+generate
+    for (i=OSD_ROW_LSEC_ENABLE_REGNUM; i <= OSD_ROW_COLOR_REGNUM; i++) begin : gen_reg
+        always @(posedge clk_i or posedge rst_i) begin
+            if (rst_i) begin
+                config_reg[i] <= 0;
+            end else begin
+                if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==i)) begin
+                    if (avalon_s_byteenable[3])
+                        config_reg[i][31:24] <= avalon_s_writedata[31:24];
+                    if (avalon_s_byteenable[2])
+                        config_reg[i][23:16] <= avalon_s_writedata[23:16];
+                    if (avalon_s_byteenable[1])
+                        config_reg[i][15:8] <= avalon_s_writedata[15:8];
+                    if (avalon_s_byteenable[0])
+                        config_reg[i][7:0] <= avalon_s_writedata[7:0];
+                end
+            end
+        end
+    end
+endgenerate
+
+
+always @(*) begin
+    if (avalon_s_chipselect && avalon_s_read) begin
+        case (avalon_s_address)
+            OSD_CONFIG_REGNUM:              avalon_s_readdata = osd_config;
+            OSD_ROW_LSEC_ENABLE_REGNUM:     avalon_s_readdata = config_reg[OSD_ROW_LSEC_ENABLE_REGNUM];
+            OSD_ROW_RSEC_ENABLE_REGNUM:     avalon_s_readdata = config_reg[OSD_ROW_RSEC_ENABLE_REGNUM];
+            OSD_ROW_COLOR_REGNUM:           avalon_s_readdata = config_reg[OSD_ROW_COLOR_REGNUM];
+            default:                        avalon_s_readdata = 32'h00000000;
+        endcase
+    end else begin
+        avalon_s_readdata = 32'h00000000;
+    end
+end
+
+endmodule

ip/pll_reconfig/inc/pll_reconfig_regs.h

@@ -0,0 +1,47 @@
+//
+// Copyright (C) 2019  Markus Hiienkari <mhiienka@niksula.hut.fi>
+//
+// This file is part of Open Source Scan Converter project.
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#ifndef PLL_RECONFIG_REGS_H_
+#define PLL_RECONFIG_REGS_H_
+
+#include <alt_types.h>
+
+typedef union {
+    struct {
+        alt_u8 reset:1;
+        alt_u8 update:1;
+        alt_u8 t_config_id:4;
+        alt_u32 pll_reconfig_rsv:21;
+        alt_u8 c_config_id:4;
+        alt_u8 busy:1;
+    } __attribute__((packed, __may_alias__));
+    alt_u32 data;
+} pll_config_status_reg;
+
+// char regs
+typedef struct {
+    char data[160];
+} pll_config_data_regs;
+
+typedef struct {
+    pll_config_status_reg pll_config_status;
+    pll_config_data_regs pll_config_data;
+} __attribute__((packed, __may_alias__)) pll_reconfig_regs;
+
+#endif //OSD_GENERATOR_REGS_H_

ip/pll_reconfig/pll_reconfig_hw.tcl

@@ -0,0 +1,151 @@
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+# 
+# module
+# 
+set_module_property DESCRIPTION "PLL reconfig"
+set_module_property NAME pll_reconfig
+#set_module_property VERSION 18.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property GROUP "Processors and Peripherals"
+set_module_property AUTHOR ""
+set_module_property DISPLAY_NAME pll_reconfig
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL pll_reconfig_top
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file pll_reconfig_top.sv VERILOG PATH pll_reconfig_top.sv
+
+add_fileset SIM_VERILOG SIM_VERILOG "" ""
+set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false
+set_fileset_property SIM_VERILOG TOP_LEVEL pll_reconfig_top
+add_fileset_file pll_reconfig_top.sv VERILOG PATH pll_reconfig_top.sv
+
+# 
+# parameters
+# 
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point clock_sink
+# 
+add_interface clock_sink clock end
+set_interface_property clock_sink clockRate 0
+set_interface_property clock_sink ENABLED true
+set_interface_property clock_sink EXPORT_OF ""
+set_interface_property clock_sink PORT_NAME_MAP ""
+set_interface_property clock_sink CMSIS_SVD_VARIABLES ""
+set_interface_property clock_sink SVD_ADDRESS_GROUP ""
+
+add_interface_port clock_sink clk_i clk Input 1
+
+
+# 
+# connection point reset_sink
+# 
+add_interface reset_sink reset end
+set_interface_property reset_sink associatedClock clock_sink
+set_interface_property reset_sink synchronousEdges DEASSERT
+set_interface_property reset_sink ENABLED true
+set_interface_property reset_sink EXPORT_OF ""
+set_interface_property reset_sink PORT_NAME_MAP ""
+set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
+set_interface_property reset_sink SVD_ADDRESS_GROUP ""
+
+add_interface_port reset_sink rst_i reset Input 1
+
+
+# 
+# connection point avalon_s
+# 
+add_interface avalon_s avalon end
+set_interface_property avalon_s addressUnits WORDS
+set_interface_property avalon_s associatedClock clock_sink
+set_interface_property avalon_s associatedReset reset_sink
+set_interface_property avalon_s bitsPerSymbol 8
+set_interface_property avalon_s burstOnBurstBoundariesOnly false
+set_interface_property avalon_s burstcountUnits WORDS
+set_interface_property avalon_s explicitAddressSpan 0
+set_interface_property avalon_s holdTime 0
+set_interface_property avalon_s linewrapBursts false
+set_interface_property avalon_s maximumPendingReadTransactions 0
+set_interface_property avalon_s maximumPendingWriteTransactions 0
+set_interface_property avalon_s readLatency 0
+set_interface_property avalon_s readWaitTime 1
+set_interface_property avalon_s setupTime 0
+set_interface_property avalon_s timingUnits Cycles
+set_interface_property avalon_s writeWaitTime 0
+set_interface_property avalon_s ENABLED true
+set_interface_property avalon_s EXPORT_OF ""
+set_interface_property avalon_s PORT_NAME_MAP ""
+set_interface_property avalon_s CMSIS_SVD_VARIABLES ""
+set_interface_property avalon_s SVD_ADDRESS_GROUP ""
+
+add_interface_port avalon_s avalon_s_address address Input 3
+add_interface_port avalon_s avalon_s_writedata writedata Input 32
+add_interface_port avalon_s avalon_s_readdata readdata Output 32
+add_interface_port avalon_s avalon_s_byteenable byteenable Input 4
+add_interface_port avalon_s avalon_s_write write Input 1
+add_interface_port avalon_s avalon_s_read read Input 1
+add_interface_port avalon_s avalon_s_chipselect chipselect Input 1
+add_interface_port avalon_s avalon_s_waitrequest_n waitrequest_n Output 1
+set_interface_assignment avalon_s embeddedsw.configuration.isFlash 0
+set_interface_assignment avalon_s embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment avalon_s embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment avalon_s embeddedsw.configuration.isPrintableDevice 0
+
+
+# 
+# connection point bus
+# 
+#add_sv_interface bus pll_reconfig_if
+
+# Setting the parameter property to add SV interface parameters
+#set_parameter_property my_interface_parameter SV_INTERFACE_PARAMETER bus
+
+# Setting the port properties to add them to SV interface port set_port_property clk SV_INTERFACE_PORT bus #set_port_property p1 SV_INTERFACE_PORT bus
+#set_port_property p2 SV_INTERFACE_PORT bus
+#set_port_property p1 SV_INTERFACE_SIGNAL bus
+#set_port_property p2 SV_INTERFACE_SIGNAL bus
+
+#Adding the SV Interface File
+#add_fileset_file pll_reconfig_if.sv SYSTEM_VERILOG PATH pll_reconfig_if.sv SYSTEMVERILOG_INTERFACE
+
+
+# 
+# connection point pll_reconfig_if
+# 
+add_interface pll_reconfig_if conduit end
+set_interface_property pll_reconfig_if associatedClock ""
+set_interface_property pll_reconfig_if associatedReset ""
+set_interface_property pll_reconfig_if ENABLED true
+set_interface_property pll_reconfig_if EXPORT_OF ""
+set_interface_property pll_reconfig_if PORT_NAME_MAP ""
+set_interface_property pll_reconfig_if CMSIS_SVD_VARIABLES ""
+set_interface_property pll_reconfig_if SVD_ADDRESS_GROUP ""
+
+add_interface_port pll_reconfig_if areset areset Output 1
+add_interface_port pll_reconfig_if scanclk scanclk Output 1
+add_interface_port pll_reconfig_if scanclkena scanclkena Output 1
+add_interface_port pll_reconfig_if configupdate configupdate Output 1
+add_interface_port pll_reconfig_if scandata scandata Output 1
+add_interface_port pll_reconfig_if scandone scandone Input 1

ip/pll_reconfig/pll_reconfig_sw.tcl

@@ -0,0 +1,54 @@
+#
+# pll_reconfig_sw.tcl
+#
+
+# Create a new driver
+create_driver pll_reconfig_driver
+
+# Associate it with some hardware known as "opencores_i2c"
+set_sw_property hw_class_name pll_reconfig
+
+# The version of this driver
+set_sw_property version 1.0
+
+# This driver may be incompatible with versions of hardware less
+# than specified below. Updates to hardware and device drivers
+# rendering the driver incompatible with older versions of
+# hardware are noted with this property assignment.
+#
+# Multiple-Version compatibility was introduced in version 7.1;
+# prior versions are therefore excluded.
+set_sw_property min_compatible_hw_version 7.1
+
+# Initialize the driver in alt_sys_init()
+set_sw_property auto_initialize false
+
+# Location in generated BSP that above sources will be copied into
+set_sw_property bsp_subdirectory drivers
+
+
+# Interrupt properties:
+# This peripheral has an IRQ output but the driver doesn't currently
+# have any interrupt service routine. To ensure that the BSP tools
+# do not otherwise limit the BSP functionality for users of the
+# Nios II enhanced interrupt port, these settings advertise 
+# compliance with both legacy and enhanced interrupt APIs, and to state
+# that any driver ISR supports preemption. If an interrupt handler
+# is added to this driver, these must be re-examined for validity.
+set_sw_property isr_preemption_supported true
+set_sw_property supported_interrupt_apis "legacy_interrupt_api enhanced_interrupt_api"
+
+#
+# Source file listings...
+#
+
+# C/C++ source files
+
+# Include files
+add_sw_property include_source inc/pll_reconfig_regs.h
+
+# This driver supports HAL & UCOSII BSP (OS) types
+add_sw_property supported_bsp_type HAL
+add_sw_property supported_bsp_type UCOSII
+
+# End of file

ip/pll_reconfig/pll_reconfig_top.sv

@@ -0,0 +1,195 @@
+//
+// Copyright (C) 2019  Markus Hiienkari <mhiienka@niksula.hut.fi>
+//
+// This file is part of Open Source Scan Converter project.
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+module pll_reconfig_top (
+    // common
+    input clk_i,
+    input rst_i,
+    // avalon slave
+    input [31:0] avalon_s_writedata,
+    output [31:0] avalon_s_readdata,
+    input [2:0] avalon_s_address,
+    input [3:0] avalon_s_byteenable,
+    input avalon_s_write,
+    input avalon_s_read,
+    input avalon_s_chipselect,
+    output avalon_s_waitrequest_n,
+    // reconfig interface
+    output areset,
+    output scanclk,
+    output reg scanclkena,
+    output reg configupdate,
+    output scandata,
+    input scandone
+);
+
+localparam PLL_CONFIG_DATA_BITS = 8'd144;
+localparam PLL_CONFIG_DATA_REGS = 5;
+
+localparam PLL_CONFIG_STATUS_REGNUM =   3'h0;
+localparam PLL_CONFIG_DATA_STARTREG =   3'h1;
+
+localparam STATE_IDLE       = 2'h0;
+localparam STATE_SHIFT      = 2'h1;
+localparam STATE_WAITRESP   = 2'h2;
+
+reg [31:0] pll_config_status;
+reg [31:0] config_data[0:(PLL_CONFIG_DATA_REGS-1)] /* synthesis ramstyle = "logic" */;
+reg areset_strobe;
+reg [1:0] state;
+reg scan_shift;
+reg scandone_prev;
+reg configupdate_pre;
+reg [7:0] shift_ctr;
+
+wire pll_reset = pll_config_status[0];
+wire start_update = pll_config_status[1];
+wire [3:0] t_config_id = pll_config_status[5:2];
+wire [3:0] c_config_id = pll_config_status[30:27];
+wire config_busy = pll_config_status[31];
+
+assign areset = pll_reset | areset_strobe;
+assign scanclk = clk_i;
+assign scandata = config_data[0][16];
+
+assign avalon_s_waitrequest_n = 1'b1;
+
+
+// Avalon register interface
+always @(posedge clk_i or posedge rst_i) begin
+    if (rst_i) begin
+        pll_config_status[7:0] <= 8'h0;
+    end else begin
+        if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==PLL_CONFIG_STATUS_REGNUM)) begin
+            /*if (avalon_s_byteenable[3])
+                pll_config_status[31:24] <= avalon_s_writedata[31:24];
+            if (avalon_s_byteenable[2])
+                pll_config_status[23:16] <= avalon_s_writedata[23:16];
+            if (avalon_s_byteenable[1])
+                pll_config_status[15:8] <= avalon_s_writedata[15:8];*/
+            if (avalon_s_byteenable[0])
+                pll_config_status[7:0] <= avalon_s_writedata[7:0];
+        end else begin
+            pll_config_status[1] <= 1'b0; // reset start_update bit
+        end
+    end
+end
+
+
+genvar i;
+generate
+    for (i = 0; i < PLL_CONFIG_DATA_REGS; i = i + 1) begin : genreg
+        always @(posedge clk_i or posedge rst_i) begin
+            if (rst_i) begin
+                config_data[i] <= 32'h0;
+            end else begin
+                if (!scan_shift) begin
+                    if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==(PLL_CONFIG_DATA_STARTREG+PLL_CONFIG_DATA_REGS-1-i))) begin
+                        if (avalon_s_byteenable[3])
+                            config_data[i][31:24] <= avalon_s_writedata[31:24];
+                        if (avalon_s_byteenable[2])
+                            config_data[i][23:16] <= avalon_s_writedata[23:16];
+                        if (avalon_s_byteenable[1])
+                            config_data[i][15:8] <= avalon_s_writedata[15:8];
+                        if (avalon_s_byteenable[0])
+                            config_data[i][7:0] <= avalon_s_writedata[7:0];
+                    end
+                end else begin
+                    if (i==(PLL_CONFIG_DATA_REGS-1)) begin
+                        config_data[i] <= {1'b0, config_data[i][31:1]};
+                    end else begin
+                        config_data[i] <= {config_data[i+1][0], config_data[i][31:1]};
+                    end
+                end
+            end
+        end
+    end
+endgenerate
+
+// Main FSM
+always @(posedge clk_i or posedge rst_i)
+begin
+    if (rst_i) begin
+        state <= STATE_IDLE;
+        scanclkena <= 1'b0;
+        configupdate_pre <= 1'b0;
+        configupdate <= 1'b0;
+        areset_strobe <= 1'b0;
+        scan_shift <= 1'b0;
+        scandone_prev <= 1'b0;
+        pll_config_status[31] <= 1'b0;
+    end else begin
+        case (state)
+            STATE_IDLE:
+                begin
+                    areset_strobe <= 1'b0;
+
+                    if (start_update) begin
+                        pll_config_status[31] <= 1'b1;
+                        scanclkena <= 1'b1;
+                        shift_ctr <= PLL_CONFIG_DATA_BITS;
+                        state <= STATE_SHIFT;
+                    end else begin
+                        pll_config_status[31] <= 1'b0;
+                    end
+                end
+            STATE_SHIFT:
+                begin
+                    scan_shift <= 1'b1;
+                    if (shift_ctr > 0) begin
+                        shift_ctr <= shift_ctr - 1'b1;
+                    end else begin
+                        scan_shift <= 1'b0;
+                        scanclkena <= 1'b0;
+                        configupdate_pre <= 1'b1;
+                        state <= STATE_WAITRESP;
+                    end
+                end    
+            STATE_WAITRESP:
+                begin
+                    configupdate_pre <= 1'b0;
+                    if (pll_reset) begin
+                        state <= STATE_IDLE;
+                    end else if (scandone_prev) begin
+                        areset_strobe <= 1'b1;
+                        pll_config_status[30:27] <= t_config_id;
+                        state <= STATE_IDLE;
+                    end
+                end
+            default:
+                state <= STATE_IDLE;
+        endcase
+
+        scandone_prev <= scandone;
+        configupdate <= configupdate_pre;
+    end
+end
+
+always @(*) begin
+    if (avalon_s_chipselect && avalon_s_read) begin
+        case (avalon_s_address)
+            PLL_CONFIG_STATUS_REGNUM: avalon_s_readdata = pll_config_status;
+            default: avalon_s_readdata = 32'h00000000;
+        endcase
+    end else begin
+        avalon_s_readdata = 32'h00000000;
+    end
+end
+
+endmodule

ip/sc_config/inc/sc_config_regs.h

@@ -81,10 +81,10 @@ typedef union {
 typedef union {
     struct {
         alt_u16 v_active:11;
-        alt_u8 v_backporch:6;
+        alt_u8 v_backporch:8;
         alt_u8 v_synclen:3;
         alt_u8 v_mask:6;
-        alt_u8 v_rsv:3;
+        alt_u8 v_rsv:1;
         alt_u8 v_multmode:3;
     } __attribute__((packed, __may_alias__));
     alt_u32 data;
@@ -93,8 +93,10 @@ typedef union {
 typedef union {
     struct {
         alt_u8 mask_br:4;
+        alt_u8 mask_color:3;
         alt_u8 rev_lpf_str:5;
-        alt_u32 misc_rsv:23;
+        alt_u8 panasonic_hack:1;
+        alt_u32 misc_rsv:19;
     } __attribute__((packed, __may_alias__));
     alt_u32 data;
 } misc_config_reg;

ossc.cof

@@ -10,7 +10,7 @@
 		<user_name>Page_0</user_name>
 		<page_flags>1</page_flags>
 		<bit0>
-			<sof_filename>output_files/ossc.sof</sof_filename> 
+			<sof_filename>output_files/ossc.sof<compress_bitstream>1</compress_bitstream></sof_filename> 
 		</bit0>
 	</sof_data>
 	<version>10</version>

ossc.qsf

@@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP4CE15E22C8
 set_global_assignment -name TOP_LEVEL_ENTITY ossc
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:27:03  MAY 17, 2014"
-set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@@ -162,12 +162,6 @@ set_location_assignment PIN_129 -to btn[1]
 set_location_assignment PIN_128 -to btn[0]
 
 
-set_instance_assignment -name PLL_COMPENSATE ON -to G_in
-set_instance_assignment -name PLL_COMPENSATE ON -to FID_in
-set_instance_assignment -name PLL_COMPENSATE ON -to HSYNC_in
-set_instance_assignment -name PLL_COMPENSATE ON -to R_in
-set_instance_assignment -name PLL_COMPENSATE ON -to VSYNC_in
-set_instance_assignment -name PLL_COMPENSATE ON -to B_in
 
 
 set_global_assignment -name USE_CONFIGURATION_DEVICE ON
@@ -185,7 +179,7 @@ set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS16
 set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
 set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
 
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
 set_global_assignment -name SMART_RECOMPILE ON
 
 set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
@@ -224,11 +218,18 @@ set_global_assignment -name ENABLE_SIGNALTAP OFF
 set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_la.stp
 
 set_global_assignment -name FITTER_EFFORT "AUTO FIT"
-set_global_assignment -name SEED 10
+set_global_assignment -name SEED 2
 
 
 
 
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[3]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[7]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_GD[7]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[5]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[7]
 set_global_assignment -name VERILOG_FILE rtl/videogen.v
 set_global_assignment -name VERILOG_FILE rtl/ir_rcv.v
 set_global_assignment -name VERILOG_FILE rtl/ossc.v
@@ -237,13 +238,13 @@ set_global_assignment -name VERILOG_FILE rtl/lat_tester.v
 set_global_assignment -name QIP_FILE sys/synthesis/sys.qip
 set_global_assignment -name QIP_FILE software/sys_controller/mem_init/meminit.qip
 set_global_assignment -name QIP_FILE rtl/linebuf.qip
+set_global_assignment -name QIP_FILE rtl/char_rom.qip
 set_global_assignment -name QIP_FILE rtl/pll_2x.qip
-set_global_assignment -name QIP_FILE rtl/pll_3x.qip
 set_global_assignment -name QIP_FILE rtl/lpm_mult_4_hybr_ref_pre.qip
 set_global_assignment -name QIP_FILE rtl/lpm_mult_4_hybr_ref.qip
 set_global_assignment -name QIP_FILE rtl/lpm_mult_4_sl.qip
-set_global_assignment -name QIP_FILE rtl/mux5.qip
 set_global_assignment -name SDC_FILE ossc.sdc
 set_global_assignment -name CDF_FILE output_files/Chain1.cdf
 set_global_assignment -name SIGNALTAP_FILE output_files/ossc_la.stp
+set_global_assignment -name QIP_FILE rtl/char_array.qip
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

ossc.sdc

@@ -10,34 +10,37 @@ set_false_path -to {sys:sys_inst|sys_pio_1:pio_1|readdata*}
 ### Scanconverter clock constraints ###
 
 create_clock -period 108MHz -name pclk_1x [get_ports PCLK_in]
-create_clock -period 33MHz -name pclk_2x_source [get_ports PCLK_in] -add
-create_clock -period 33MHz -name pclk_3x_source [get_ports PCLK_in] -add
+create_clock -period 54MHz -name pclk_2x_source [get_ports PCLK_in] -add
+create_clock -period 54MHz -name pclk_3x_source [get_ports PCLK_in] -add
 create_clock -period 33MHz -name pclk_4x_source [get_ports PCLK_in] -add
 create_clock -period 33MHz -name pclk_5x_source [get_ports PCLK_in] -add
 
 #derive_pll_clocks
-create_generated_clock -master_clock pclk_2x_source -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name pclk_2x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[0]}
-create_generated_clock -master_clock pclk_3x_source -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name pclk_3x {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[0]}
-create_generated_clock -master_clock pclk_4x_source -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 4 -duty_cycle 50.00 -name pclk_4x {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[1]}
-create_generated_clock -master_clock pclk_5x_source -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 5 -duty_cycle 50.00 -name pclk_5x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[1]}
+create_generated_clock -name pclk_2x -master_clock pclk_2x_source -source {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|inclk[1]} -multiply_by 2 -duty_cycle 50.00 {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|clk[0]} -add
+create_generated_clock -name pclk_3x -master_clock pclk_3x_source -source {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|inclk[1]} -multiply_by 3 -duty_cycle 50.00 {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|clk[0]} -add
+create_generated_clock -name pclk_4x -master_clock pclk_4x_source -source {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|inclk[1]} -multiply_by 4 -duty_cycle 50.00 {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|clk[1]} -add
+create_generated_clock -name pclk_5x -master_clock pclk_5x_source -source {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|inclk[1]} -multiply_by 5 -duty_cycle 50.00 {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|clk[1]} -add
+create_generated_clock -name pclk_27mhz -master_clock clk27 -source {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 1 -duty_cycle 50.00 {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|clk[0]} -add
 
 # retrieve post-mapping clkmux output pin
-set clkmux_output [get_pins scanconverter_inst|mux5_inst|LPM_MUX_component|auto_generated|muxlut_result*|combout]
+set clkmux_output [get_pins scanconverter_inst|clkctrl1|outclk]
 
 # specify postmux clocks which clock postprocess pipeline
-create_generated_clock -master_clock pclk_1x -source [get_ports PCLK_in] -multiply_by 1 -name pclk_1x_postmux $clkmux_output
-create_generated_clock -master_clock pclk_2x -source [get_pins scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[0]] -multiply_by 1 -name pclk_2x_postmux $clkmux_output -add
-create_generated_clock -master_clock pclk_3x -source [get_pins scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[0]] -multiply_by 1 -name pclk_3x_postmux $clkmux_output -add
-create_generated_clock -master_clock pclk_4x -source [get_pins scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[1]] -multiply_by 1 -name pclk_4x_postmux $clkmux_output -add
-create_generated_clock -master_clock pclk_5x -source [get_pins scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[1]] -multiply_by 1 -name pclk_5x_postmux $clkmux_output -add
+create_generated_clock -name pclk_1x_postmux -master_clock pclk_1x -source [get_pins scanconverter_inst|clkctrl1|inclk[0]] -multiply_by 1 $clkmux_output
+create_generated_clock -name pclk_2x_postmux -master_clock pclk_2x -source [get_pins scanconverter_inst|clkctrl1|inclk[2]] -multiply_by 1 $clkmux_output -add
+create_generated_clock -name pclk_3x_postmux -master_clock pclk_3x -source [get_pins scanconverter_inst|clkctrl1|inclk[2]] -multiply_by 1 $clkmux_output -add
+create_generated_clock -name pclk_4x_postmux -master_clock pclk_4x -source [get_pins scanconverter_inst|clkctrl1|inclk[3]] -multiply_by 1 $clkmux_output -add
+create_generated_clock -name pclk_5x_postmux -master_clock pclk_5x -source [get_pins scanconverter_inst|clkctrl1|inclk[3]] -multiply_by 1 $clkmux_output -add
+create_generated_clock -name pclk_27mhz_postmux -master_clock pclk_27mhz -source [get_pins scanconverter_inst|clkctrl1|inclk[2]] -multiply_by 1 $clkmux_output -add
 
 # specify output clocks that drive PCLK output pin
 set pclk_out_port [get_ports HDMI_TX_PCLK]
-create_generated_clock -master_clock pclk_1x_postmux -source $clkmux_output -multiply_by 1 -name pclk_1x_out $pclk_out_port
-create_generated_clock -master_clock pclk_2x_postmux -source $clkmux_output -multiply_by 1 -name pclk_2x_out $pclk_out_port -add
-create_generated_clock -master_clock pclk_3x_postmux -source $clkmux_output -multiply_by 1 -name pclk_3x_out $pclk_out_port -add
-create_generated_clock -master_clock pclk_4x_postmux -source $clkmux_output -multiply_by 1 -name pclk_4x_out $pclk_out_port -add
-create_generated_clock -master_clock pclk_5x_postmux -source $clkmux_output -multiply_by 1 -name pclk_5x_out $pclk_out_port -add
+create_generated_clock -name pclk_1x_out -master_clock pclk_1x_postmux -source $clkmux_output -multiply_by 1 $pclk_out_port
+create_generated_clock -name pclk_2x_out -master_clock pclk_2x_postmux -source $clkmux_output -multiply_by 1 $pclk_out_port -add
+create_generated_clock -name pclk_3x_out -master_clock pclk_3x_postmux -source $clkmux_output -multiply_by 1 $pclk_out_port -add
+create_generated_clock -name pclk_4x_out -master_clock pclk_4x_postmux -source $clkmux_output -multiply_by 1 $pclk_out_port -add
+create_generated_clock -name pclk_5x_out -master_clock pclk_5x_postmux -source $clkmux_output -multiply_by 1 $pclk_out_port -add
+create_generated_clock -name pclk_27mhz_out -master_clock pclk_27mhz_postmux -source $clkmux_output -multiply_by 1 $pclk_out_port -add
 
 derive_clock_uncertainty
 
@@ -50,8 +53,9 @@ foreach_in_collection c [get_clocks "pclk_1x pclk_*_source"] {
     set_input_delay -clock $c -max $TVP_dmax $critinputs -add_delay
 }
 
-# output delay constraints
-set IT_Tsu 1.0
+# output delay constraints as documented in the IT6613 datasheet
+# -- increased IT_Tsu from 1.0 to 1.5 due to #52
+set IT_Tsu 1.5
 set IT_Th -0.5
 set critoutputs_hdmi [get_ports {HDMI_TX_RD* HDMI_TX_GD* HDMI_TX_BD* HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
 foreach_in_collection c [get_clocks pclk_*_out] {
@@ -65,7 +69,7 @@ set_false_path -to [remove_from_collection [all_outputs] $critoutputs_hdmi]
 
 # Treat CPU clock asynchronous to pixel clocks 
 set_clock_groups -asynchronous -group \
-                            {clk27} \
+                            {clk27 pclk_27mhz pclk_27mhz_postmux pclk_27mhz_out} \
                             {pclk_1x pclk_1x_postmux pclk_1x_out} \
                             {pclk_2x_source pclk_2x pclk_2x_postmux pclk_2x_out} \
                             {pclk_3x_source pclk_3x pclk_3x_postmux pclk_3x_out} \
@@ -73,10 +77,14 @@ set_clock_groups -asynchronous -group \
                             {pclk_5x_source pclk_5x pclk_5x_postmux pclk_5x_out}
 
 # Ignore paths from registers which are updated only at leading edge of vsync
-set_false_path -from [get_registers {scanconverter_inst|H_* scanconverter_inst|V_* scanconverter_inst|X_* scanconverter_inst|SL_* scanconverter_inst|LT_POS_* scanconverter_inst|FID_1x}]
+set_false_path -from [get_registers {scanconverter_inst|H_* scanconverter_inst|V_* scanconverter_inst|X_* scanconverter_inst|SL_* scanconverter_inst|LT_POS_*}]
 
 # Ignore paths from registers which are updated only at leading edge of hsync
-set_false_path -from [get_registers {scanconverter:scanconverter_inst|line_idx scanconverter:scanconverter_inst|line_out_idx* scanconverter:scanconverter_inst|hmax*}]
+#set_false_path -from [get_registers {scanconverter:scanconverter_inst|line_idx scanconverter:scanconverter_inst|line_out_idx* scanconverter:scanconverter_inst|hmax*}]
+
+# Ignore paths that cross clock domains from 3x to 2x and 5x to 4x, since they share a clock line, but cannot co-occur.
+set_false_path -from [get_clocks {pclk_3x*}] -to [get_registers {scanconverter:scanconverter_inst|*_2x*}]
+set_false_path -from [get_clocks {pclk_5x*}] -to [get_registers {scanconverter:scanconverter_inst|*_4x*}]
 
 # Ignore paths to latency tester sync regs
 set_false_path -to [get_registers {lat_tester:lt0|mode_synced* lat_tester:lt0|VSYNC_in_* lat_tester:lt0|trigger_*}]

ossc_rtl.project

@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<CodeLite_Project Name="ossc_rtl" InternalType="">
+<CodeLite_Project Name="ossc_rtl" InternalType="" Version="11000">
   <VirtualDirectory Name="ip">
     <VirtualDirectory Name="nios2_hw_crc">
       <VirtualDirectory Name="hdl">
@@ -24,6 +24,23 @@
   </VirtualDirectory>
   <Description/>
   <Dependencies/>
+  <VirtualDirectory Name="rtl">
+    <File Name="rtl/ir_rcv.v"/>
+    <File Name="rtl/ossc.v"/>
+    <File Name="rtl/pll_2x.v"/>
+    <File Name="rtl/pll_3x_lowfreq.v"/>
+    <File Name="rtl/pll_3x_lowfreq_bb.v"/>
+    <File Name="rtl/linebuf_inst.v"/>
+    <File Name="rtl/videogen.v"/>
+    <File Name="rtl/timescale.v"/>
+    <File Name="rtl/pll_2x_bb.v"/>
+    <File Name="rtl/linebuf.v"/>
+    <File Name="rtl/pll_3x.v"/>
+    <File Name="rtl/scanconverter.v"/>
+    <File Name="rtl/linebuf_bb.v"/>
+  </VirtualDirectory>
+  <Dependencies Name="Debug"/>
+  <Dependencies Name="Release"/>
   <Settings Type="Dynamic Library">
     <GlobalSettings>
       <Compiler Options="" C_Options="" Assembler="">
@@ -41,6 +58,7 @@
       <Linker Options="" Required="yes"/>
       <ResourceCompiler Options="" Required="no"/>
       <General OutputFile="" IntermediateDirectory="./Debug" Command="" CommandArguments="" UseSeparateDebugArgs="no" DebugArguments="" WorkingDirectory="$(IntermediateDirectory)" PauseExecWhenProcTerminates="yes" IsGUIProgram="no" IsEnabled="yes"/>
+      <BuildSystem Name="Default"/>
       <Environment EnvVarSetName="&lt;Use Defaults&gt;" DbgSetName="&lt;Use Defaults&gt;">
         <![CDATA[]]>
       </Environment>
@@ -79,6 +97,7 @@
       <Linker Options="-O2" Required="yes"/>
       <ResourceCompiler Options="" Required="no"/>
       <General OutputFile="" IntermediateDirectory="./Release" Command="" CommandArguments="" UseSeparateDebugArgs="no" DebugArguments="" WorkingDirectory="$(IntermediateDirectory)" PauseExecWhenProcTerminates="yes" IsGUIProgram="no" IsEnabled="yes"/>
+      <BuildSystem Name="Default"/>
       <Environment EnvVarSetName="&lt;Use Defaults&gt;" DbgSetName="&lt;Use Defaults&gt;">
         <![CDATA[]]>
       </Environment>
@@ -111,21 +130,4 @@
       </Completion>
     </Configuration>
   </Settings>
-  <VirtualDirectory Name="rtl">
-    <File Name="rtl/ir_rcv.v"/>
-    <File Name="rtl/ossc.v"/>
-    <File Name="rtl/pll_2x.v"/>
-    <File Name="rtl/pll_3x_lowfreq.v"/>
-    <File Name="rtl/pll_3x_lowfreq_bb.v"/>
-    <File Name="rtl/linebuf_inst.v"/>
-    <File Name="rtl/videogen.v"/>
-    <File Name="rtl/timescale.v"/>
-    <File Name="rtl/pll_2x_bb.v"/>
-    <File Name="rtl/linebuf.v"/>
-    <File Name="rtl/pll_3x.v"/>
-    <File Name="rtl/scanconverter.v"/>
-    <File Name="rtl/linebuf_bb.v"/>
-  </VirtualDirectory>
-  <Dependencies Name="Debug"/>
-  <Dependencies Name="Release"/>
 </CodeLite_Project>

ossc_sw_bsp.project

@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<CodeLite_Project Name="ossc_sw_bsp" InternalType="" Version="10.0.0">
+<CodeLite_Project Name="ossc_sw_bsp" InternalType="" Version="11000">
   <Plugins>
     <Plugin Name="qmake">
       <![CDATA[00020001N0005Debug0000000000000001N0007Release000000000000]]>
@@ -26,24 +26,41 @@
  }]]]>
     </Plugin>
   </Plugins>
+  <Reconciliation>
+    <Regexes/>
+    <Excludepaths/>
+    <Ignorefiles/>
+    <Extensions>
+      <![CDATA[*.cpp;*.c;*.h;*.hpp;*.xrc;*.wxcp;*.fbp]]>
+    </Extensions>
+    <Topleveldir>/home/markus/Code/ossc/software</Topleveldir>
+  </Reconciliation>
   <VirtualDirectory Name="software">
     <VirtualDirectory Name="sys_controller_bsp">
       <VirtualDirectory Name="drivers">
         <VirtualDirectory Name="inc">
+          <File Name="software/sys_controller_bsp/drivers/inc/altera_epcq_controller2_regs.h"/>
+          <File Name="software/sys_controller_bsp/drivers/inc/altera_epcq_controller2.h"/>
+          <File Name="software/sys_controller_bsp/drivers/inc/pll_reconfig_regs.h"/>
+          <File Name="software/sys_controller_bsp/drivers/inc/osd_generator_regs.h"/>
+          <File Name="software/sys_controller_bsp/drivers/inc/sc_config_regs.h"/>
+          <File Name="software/sys_controller_bsp/drivers/inc/altera_avalon_timer_regs.h"/>
+          <File Name="software/sys_controller_bsp/drivers/inc/altera_avalon_timer.h"/>
           <File Name="software/sys_controller_bsp/drivers/inc/altera_avalon_jtag_uart.h"/>
           <File Name="software/sys_controller_bsp/drivers/inc/altera_avalon_jtag_uart_regs.h"/>
           <File Name="software/sys_controller_bsp/drivers/inc/ci_crc.h"/>
           <File Name="software/sys_controller_bsp/drivers/inc/crc.h"/>
-          <File Name="software/sys_controller_bsp/drivers/inc/altera_epcq_controller_mod_regs.h"/>
           <File Name="software/sys_controller_bsp/drivers/inc/altera_avalon_jtag_uart_fd.h"/>
-          <File Name="software/sys_controller_bsp/drivers/inc/altera_epcq_controller_mod.h"/>
           <File Name="software/sys_controller_bsp/drivers/inc/i2c_opencores_regs.h"/>
           <File Name="software/sys_controller_bsp/drivers/inc/i2c_opencores.h"/>
           <File Name="software/sys_controller_bsp/drivers/inc/Altera_UP_SD_Card_Avalon_Interface_mod.h"/>
           <File Name="software/sys_controller_bsp/drivers/inc/altera_avalon_pio_regs.h"/>
         </VirtualDirectory>
         <VirtualDirectory Name="src">
-          <File Name="software/sys_controller_bsp/drivers/src/altera_epcq_controller_mod.c"/>
+          <File Name="software/sys_controller_bsp/drivers/src/altera_epcq_controller2.c"/>
+          <File Name="software/sys_controller_bsp/drivers/src/altera_avalon_timer_vars.c"/>
+          <File Name="software/sys_controller_bsp/drivers/src/altera_avalon_timer_ts.c"/>
+          <File Name="software/sys_controller_bsp/drivers/src/altera_avalon_timer_sc.c"/>
           <File Name="software/sys_controller_bsp/drivers/src/altera_avalon_jtag_uart_read.c"/>
           <File Name="software/sys_controller_bsp/drivers/src/altera_avalon_jtag_uart_ioctl.c"/>
           <File Name="software/sys_controller_bsp/drivers/src/ci_crc.c"/>
@@ -191,62 +208,6 @@
       <File Name="software/sys_controller_bsp/system.h"/>
     </VirtualDirectory>
   </VirtualDirectory>
-  <VirtualDirectory Name="ip">
-    <VirtualDirectory Name="i2c_opencores">
-      <VirtualDirectory Name="HAL">
-        <VirtualDirectory Name="inc">
-          <File Name="ip/i2c_opencores/HAL/inc/i2c_opencores.h"/>
-        </VirtualDirectory>
-        <VirtualDirectory Name="src">
-          <File Name="ip/i2c_opencores/HAL/src/i2c_opencores.c"/>
-        </VirtualDirectory>
-      </VirtualDirectory>
-      <VirtualDirectory Name="Docs">
-        <File Name="ip/i2c_opencores/Docs/I2C_tests.c"/>
-      </VirtualDirectory>
-      <VirtualDirectory Name="inc">
-        <File Name="ip/i2c_opencores/inc/i2c_opencores_regs.h"/>
-      </VirtualDirectory>
-    </VirtualDirectory>
-    <VirtualDirectory Name="nios2_hw_crc">
-      <VirtualDirectory Name="HAL">
-        <VirtualDirectory Name="doc">
-          <File Name="ip/nios2_hw_crc/HAL/doc/crc_main.c"/>
-        </VirtualDirectory>
-        <VirtualDirectory Name="inc">
-          <File Name="ip/nios2_hw_crc/HAL/inc/ci_crc.h"/>
-          <File Name="ip/nios2_hw_crc/HAL/inc/crc.h"/>
-        </VirtualDirectory>
-        <VirtualDirectory Name="src">
-          <File Name="ip/nios2_hw_crc/HAL/src/ci_crc.c"/>
-          <File Name="ip/nios2_hw_crc/HAL/src/crc.c"/>
-        </VirtualDirectory>
-      </VirtualDirectory>
-    </VirtualDirectory>
-    <VirtualDirectory Name="altera_up_sd_card_avalon_interface_mod">
-      <VirtualDirectory Name="HAL">
-        <VirtualDirectory Name="inc">
-          <File Name="ip/altera_up_sd_card_avalon_interface_mod/HAL/inc/Altera_UP_SD_Card_Avalon_Interface_mod.h"/>
-        </VirtualDirectory>
-        <VirtualDirectory Name="src">
-          <File Name="ip/altera_up_sd_card_avalon_interface_mod/HAL/src/Altera_UP_SD_Card_Avalon_Interface_mod.c"/>
-        </VirtualDirectory>
-      </VirtualDirectory>
-    </VirtualDirectory>
-    <VirtualDirectory Name="altera_epcq_controller_mod">
-      <VirtualDirectory Name="HAL">
-        <VirtualDirectory Name="inc">
-          <File Name="ip/altera_epcq_controller_mod/HAL/inc/altera_epcq_controller_mod.h"/>
-        </VirtualDirectory>
-        <VirtualDirectory Name="src">
-          <File Name="ip/altera_epcq_controller_mod/HAL/src/altera_epcq_controller_mod.c"/>
-        </VirtualDirectory>
-      </VirtualDirectory>
-      <VirtualDirectory Name="inc">
-        <File Name="ip/altera_epcq_controller_mod/inc/altera_epcq_controller_mod_regs.h"/>
-      </VirtualDirectory>
-    </VirtualDirectory>
-  </VirtualDirectory>
   <Description/>
   <Dependencies/>
   <Dependencies Name="Debug"/>

rtl/char_array.qip

@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "char_array.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_array_inst.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_array_bb.v"]

rtl/char_array.v

@@ -0,0 +1,223 @@
+// megafunction wizard: %RAM: 2-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: char_array.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module char_array (
+	byteena_a,
+	data,
+	rdaddress,
+	rdclock,
+	wraddress,
+	wrclock,
+	wren,
+	q);
+
+	input	[3:0]  byteena_a;
+	input	[31:0]  data;
+	input	[9:0]  rdaddress;
+	input	  rdclock;
+	input	[7:0]  wraddress;
+	input	  wrclock;
+	input	  wren;
+	output	[7:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	[3:0]  byteena_a;
+	tri1	  wrclock;
+	tri0	  wren;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [7:0] sub_wire0;
+	wire [7:0] q = sub_wire0[7:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (wraddress),
+				.address_b (rdaddress),
+				.byteena_a (byteena_a),
+				.clock0 (wrclock),
+				.clock1 (rdclock),
+				.data_a (data),
+				.wren_a (wren),
+				.q_b (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_b (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_b ({8{1'b1}}),
+				.eccstatus (),
+				.q_a (),
+				.rden_a (1'b1),
+				.rden_b (1'b1),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_b = "NONE",
+		altsyncram_component.address_reg_b = "CLOCK1",
+		altsyncram_component.byte_size = 8,
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_input_b = "BYPASS",
+		altsyncram_component.clock_enable_output_b = "BYPASS",
+		altsyncram_component.intended_device_family = "Cyclone IV E",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 256,
+		altsyncram_component.numwords_b = 1024,
+		altsyncram_component.operation_mode = "DUAL_PORT",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_b = "CLOCK1",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.widthad_a = 8,
+		altsyncram_component.widthad_b = 10,
+		altsyncram_component.width_a = 32,
+		altsyncram_component.width_b = 8,
+		altsyncram_component.width_byteena_a = 4;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "1"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "1"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGrren NUMERIC "1"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
+// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
+// Retrieval info: USED_PORT: byteena_a 0 0 4 0 INPUT VCC "byteena_a[3..0]"
+// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
+// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+// Retrieval info: USED_PORT: rdaddress 0 0 10 0 INPUT NODEFVAL "rdaddress[9..0]"
+// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
+// Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL "wraddress[7..0]"
+// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
+// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
+// Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0
+// Retrieval info: CONNECT: @address_b 0 0 10 0 rdaddress 0 0 10 0
+// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena_a 0 0 4 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
+// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL char_array.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL char_array.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL char_array.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL char_array.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL char_array_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL char_array_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf

rtl/char_rom.qip

@@ -1,6 +1,6 @@
-set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
-set_global_assignment -name IP_TOOL_VERSION "17.1"
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "mux5.v"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mux5_inst.v"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mux5_bb.v"]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "char_rom.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_rom_inst.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_rom_bb.v"]

rtl/char_rom.v

@@ -0,0 +1,165 @@
+// megafunction wizard: %ROM: 1-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: char_rom.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module char_rom (
+	address,
+	clock,
+	q);
+
+	input	[7:0]  address;
+	input	  clock;
+	output	[63:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [63:0] sub_wire0;
+	wire [63:0] q = sub_wire0[63:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (address),
+				.clock0 (clock),
+				.q_a (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.address_b (1'b1),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_a ({64{1'b1}}),
+				.data_b (1'b1),
+				.eccstatus (),
+				.q_b (),
+				.rden_a (1'b1),
+				.rden_b (1'b1),
+				.wren_a (1'b0),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_a = "NONE",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_output_a = "BYPASS",
+`ifdef NO_PLI
+		altsyncram_component.init_file = "./ip/osd_generator/bin/char_rom.rif"
+`else
+		altsyncram_component.init_file = "./ip/osd_generator/bin/char_rom.hex"
+`endif
+,
+		altsyncram_component.intended_device_family = "Cyclone IV E",
+		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 256,
+		altsyncram_component.operation_mode = "ROM",
+		altsyncram_component.outdata_aclr_a = "NONE",
+		altsyncram_component.outdata_reg_a = "CLOCK0",
+		altsyncram_component.widthad_a = 8,
+		altsyncram_component.width_a = 64,
+		altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clken NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING "./ip/osd_generator/bin/char_rom.hex"
+// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
+// Retrieval info: PRIVATE: WidthData NUMERIC "64"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: INIT_FILE STRING "./ip/osd_generator/bin/char_rom.hex"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "64"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL "q[63..0]"
+// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 64 0 @q_a 0 0 64 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL char_rom.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL char_rom.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL char_rom.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL char_rom.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL char_rom_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL char_rom_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf

rtl/lat_tester.v

@@ -34,6 +34,7 @@ module lat_tester (
     output reg [2:0] mode_synced,
     output reg [15:0] lat_result,
     output reg [11:0] stb_result,
+    output trig_waiting,
     output reg finished
 );
 
@@ -41,6 +42,8 @@ reg VSYNC_in_L, VSYNC_in_LL, trigger_L, trigger_LL;
 reg [8:0] clk27_ctr;
 reg [1:0] state;
 
+assign trig_waiting = (state == `LT_STATE_LAT_MEAS);
+
 always @(posedge pclk) begin
     VSYNC_in_L <= VSYNC_in;
     VSYNC_in_LL <= VSYNC_in_L;

rtl/linebuf.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
-set_global_assignment -name IP_TOOL_VERSION "17.1"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "linebuf.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "linebuf_inst.v"]

rtl/linebuf.v

@@ -14,13 +14,13 @@
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
+// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 2017  Intel Corporation. All rights reserved.
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic 
+//and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 
 //(including device programming or simulation files), and any 
 //associated documentation or information are expressly subject 
@@ -30,7 +30,8 @@
 //agreement, including, without limitation, that your use is for
 //the sole purpose of programming logic devices manufactured by
 //Intel and sold by Intel or its authorized distributors.  Please
-//refer to the applicable agreement for further details.
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
 
 
 // synopsys translate_off

rtl/lpm_mult_4_hybr_ref.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "LPM_MULT"
-set_global_assignment -name IP_TOOL_VERSION "17.1"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_4_hybr_ref.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mult_4_hybr_ref_bb.v"]

rtl/lpm_mult_4_hybr_ref.v

@@ -14,13 +14,13 @@
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition
+// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 2017  Intel Corporation. All rights reserved.
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic 
+//and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 
 //(including device programming or simulation files), and any 
 //associated documentation or information are expressly subject 
@@ -30,7 +30,8 @@
 //agreement, including, without limitation, that your use is for
 //the sole purpose of programming logic devices manufactured by
 //Intel and sold by Intel or its authorized distributors.  Please
-//refer to the applicable agreement for further details.
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
 
 
 // synopsys translate_off

rtl/lpm_mult_4_hybr_ref_pre.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "LPM_MULT"
-set_global_assignment -name IP_TOOL_VERSION "17.1"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_4_hybr_ref_pre.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mult_4_hybr_ref_pre_bb.v"]

rtl/lpm_mult_4_hybr_ref_pre.v

@@ -14,13 +14,13 @@
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition
+// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 2017  Intel Corporation. All rights reserved.
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic 
+//and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 
 //(including device programming or simulation files), and any 
 //associated documentation or information are expressly subject 
@@ -30,7 +30,8 @@
 //agreement, including, without limitation, that your use is for
 //the sole purpose of programming logic devices manufactured by
 //Intel and sold by Intel or its authorized distributors.  Please
-//refer to the applicable agreement for further details.
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
 
 
 // synopsys translate_off

rtl/lpm_mult_4_sl.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "LPM_MULT"
-set_global_assignment -name IP_TOOL_VERSION "17.1"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_4_sl.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mult_4_sl_bb.v"]

rtl/lpm_mult_4_sl.v

@@ -14,13 +14,13 @@
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition
+// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 2017  Intel Corporation. All rights reserved.
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic 
+//and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 
 //(including device programming or simulation files), and any 
 //associated documentation or information are expressly subject 
@@ -30,7 +30,8 @@
 //agreement, including, without limitation, that your use is for
 //the sole purpose of programming logic devices manufactured by
 //Intel and sold by Intel or its authorized distributors.  Please
-//refer to the applicable agreement for further details.
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
 
 
 // synopsys translate_off

rtl/mux5.v

@@ -1,117 +0,0 @@
-// megafunction wizard: %LPM_MUX%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: LPM_MUX 
-
-// ============================================================
-// File Name: mux5.v
-// Megafunction Name(s):
-// 			LPM_MUX
-//
-// Simulation Library Files(s):
-// 			lpm
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
-// ************************************************************
-
-
-//Copyright (C) 2017  Intel Corporation. All rights reserved.
-//Your use of Intel Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic 
-//functions, and any output files from any of the foregoing 
-//(including device programming or simulation files), and any 
-//associated documentation or information are expressly subject 
-//to the terms and conditions of the Intel Program License 
-//Subscription Agreement, the Intel Quartus Prime License Agreement,
-//the Intel FPGA IP License Agreement, or other applicable license
-//agreement, including, without limitation, that your use is for
-//the sole purpose of programming logic devices manufactured by
-//Intel and sold by Intel or its authorized distributors.  Please
-//refer to the applicable agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module mux5 (
-	data0,
-	data1,
-	data2,
-	data3,
-	data4,
-	sel,
-	result);
-
-	input	  data0;
-	input	  data1;
-	input	  data2;
-	input	  data3;
-	input	  data4;
-	input	[2:0]  sel;
-	output	  result;
-
-	wire [0:0] sub_wire0;
-	wire  sub_wire7 = data4;
-	wire  sub_wire6 = data3;
-	wire  sub_wire5 = data2;
-	wire  sub_wire4 = data1;
-	wire [0:0] sub_wire1 = sub_wire0[0:0];
-	wire  result = sub_wire1;
-	wire  sub_wire2 = data0;
-	wire [4:0] sub_wire3 = {sub_wire7, sub_wire6, sub_wire5, sub_wire4, sub_wire2};
-
-	lpm_mux	LPM_MUX_component (
-				.data (sub_wire3),
-				.sel (sel),
-				.result (sub_wire0)
-				// synopsys translate_off
-				,
-				.aclr (),
-				.clken (),
-				.clock ()
-				// synopsys translate_on
-				);
-	defparam
-		LPM_MUX_component.lpm_size = 5,
-		LPM_MUX_component.lpm_type = "LPM_MUX",
-		LPM_MUX_component.lpm_width = 1,
-		LPM_MUX_component.lpm_widths = 3;
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: new_diagram STRING "1"
-// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "5"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3"
-// Retrieval info: USED_PORT: data0 0 0 0 0 INPUT NODEFVAL "data0"
-// Retrieval info: USED_PORT: data1 0 0 0 0 INPUT NODEFVAL "data1"
-// Retrieval info: USED_PORT: data2 0 0 0 0 INPUT NODEFVAL "data2"
-// Retrieval info: USED_PORT: data3 0 0 0 0 INPUT NODEFVAL "data3"
-// Retrieval info: USED_PORT: data4 0 0 0 0 INPUT NODEFVAL "data4"
-// Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL "result"
-// Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL "sel[2..0]"
-// Retrieval info: CONNECT: @data 0 0 1 0 data0 0 0 0 0
-// Retrieval info: CONNECT: @data 0 0 1 1 data1 0 0 0 0
-// Retrieval info: CONNECT: @data 0 0 1 2 data2 0 0 0 0
-// Retrieval info: CONNECT: @data 0 0 1 3 data3 0 0 0 0
-// Retrieval info: CONNECT: @data 0 0 1 4 data4 0 0 0 0
-// Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0
-// Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL mux5.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL mux5.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL mux5.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL mux5.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL mux5_inst.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL mux5_bb.v TRUE
-// Retrieval info: LIB_FILE: lpm

rtl/ossc.v

@@ -18,7 +18,6 @@
 //
 
 //`define DEBUG
-`define VIDEOGEN
 `define PO_RESET_WIDTH 27  //1us
 
 module ossc (
@@ -34,13 +33,13 @@ module ossc (
     input VSYNC_in,
     input HSYNC_in,
     input PCLK_in,
-    output [7:0] HDMI_TX_RD,
-    output [7:0] HDMI_TX_GD,
-    output [7:0] HDMI_TX_BD,
-    output HDMI_TX_DE,
-    output HDMI_TX_HS,
-    output HDMI_TX_VS,
     output HDMI_TX_PCLK,
+    output reg [7:0] HDMI_TX_RD,
+    output reg [7:0] HDMI_TX_GD,
+    output reg [7:0] HDMI_TX_BD,
+    output reg HDMI_TX_DE,
+    output reg HDMI_TX_HS,
+    output reg HDMI_TX_VS,
     input HDMI_TX_INT_N,
     input HDMI_TX_MODE,
     output hw_reset_n,
@@ -56,9 +55,7 @@ module ossc (
 
 
 wire [15:0] sys_ctrl;
-wire h_unstable;
-wire [1:0] pclk_lock;
-wire [1:0] pll_lock_lost;
+wire h_unstable, pll_lock_lost;
 wire [31:0] h_config, h_config2, v_config, misc_config, sl_config, sl_config2;
 wire [10:0] vmax, vmax_tvp;
 wire [1:0] fpga_vsyncgen;
@@ -68,17 +65,16 @@ wire [19:0] pcnt_frame;
 wire [15:0] ir_code;
 wire [7:0] ir_code_cnt;
 
-wire [7:0] R_out, G_out, B_out;
-wire HSYNC_out;
-wire VSYNC_out;
+wire [7:0] R_out_sc, G_out_sc, B_out_sc;
+wire HSYNC_out_sc;
+wire VSYNC_out_sc;
 wire PCLK_out;
-wire DE_out;
+wire DE_out_sc;
 
-wire [7:0] R_out_videogen, G_out_videogen, B_out_videogen;
-wire HSYNC_out_videogen;
-wire VSYNC_out_videogen;
-wire PCLK_out_videogen;
-wire DE_out_videogen;
+wire [7:0] R_out_vg, G_out_vg, B_out_vg;
+wire HSYNC_out_vg;
+wire VSYNC_out_vg;
+wire DE_out_vg;
 
 
 reg [7:0] po_reset_ctr = 0;
@@ -92,12 +88,15 @@ reg HSYNC_in_L, VSYNC_in_L, FID_in_L;
 reg [1:0] btn_L, btn_LL;
 reg ir_rx_L, ir_rx_LL, HDMI_TX_INT_N_L, HDMI_TX_INT_N_LL, HDMI_TX_MODE_L, HDMI_TX_MODE_LL;
 
+wire lt_sensor = btn_LL[1];
 wire lt_active = sys_ctrl[15];
 wire lt_armed = sys_ctrl[14];
+wire lt_trigger = HDMI_TX_DE & HDMI_TX_GD[0];
 wire [1:0] lt_mode = sys_ctrl[13:12];
 wire [1:0] lt_mode_synced;
 wire [15:0] lt_lat_result;
 wire [11:0] lt_stb_result;
+wire lt_trig_waiting;
 wire lt_finished;
 
 wire remote_event = sys_ctrl[8];
@@ -105,6 +104,14 @@ reg remove_event_prev;
 reg [14:0] to_ctr, to_ctr_ms;
 wire lcd_bl_timeout;
 
+wire [1:0] osd_color;
+wire osd_enable_pre;
+wire osd_enable = osd_enable_pre & ~lt_active;
+wire [10:0] xpos, xpos_sc, xpos_vg;
+wire [10:0] ypos, ypos_sc, ypos_vg;
+
+wire pll_areset, pll_scanclk, pll_scanclkena, pll_configupdate, pll_scandata, pll_scandone, pll_activeclock;
+
 
 // Latch inputs from TVP7002 (synchronized to PCLK_in)
 always @(posedge PCLK_in or negedge hw_reset_n)
@@ -166,8 +173,8 @@ assign hw_reset_n = sys_ctrl[0];   //HDMI_TX_RST_N in v1.2 PCB
 assign LED_R = HSYNC_in_L;
 assign LED_G = VSYNC_in_L;
 `else
-assign LED_R = videogen_sel ? 1'b0 : ((pll_lock_lost != 2'h0)|h_unstable);
-assign LED_G = (ir_code == 0);
+assign LED_R = lt_active ? lt_trig_waiting : (pll_lock_lost|h_unstable);
+assign LED_G = lt_active ? ~lt_sensor : (ir_code == 0);
 `endif
 
 assign SD_DAT[3] = sys_ctrl[7]; //SD_SPI_SS_N
@@ -177,27 +184,32 @@ wire lcd_bl_on = sys_ctrl[4];    //hw_reset_n in v1.2 PCB
 wire [1:0] lcd_bl_time = sys_ctrl[3:2];
 assign LCD_BL = lcd_bl_on ? (~lcd_bl_timeout | lt_active) : 1'b0;
 
-`ifdef VIDEOGEN
-wire videogen_sel;
-assign videogen_sel = ~sys_ctrl[1];
-assign HDMI_TX_RD = videogen_sel ? R_out_videogen : R_out;
-assign HDMI_TX_GD = videogen_sel ? G_out_videogen : G_out;
-assign HDMI_TX_BD = videogen_sel ? B_out_videogen : B_out;
-assign HDMI_TX_HS = videogen_sel ? HSYNC_out_videogen : HSYNC_out;
-assign HDMI_TX_VS = videogen_sel ? VSYNC_out_videogen : VSYNC_out;
-assign HDMI_TX_PCLK = videogen_sel ? PCLK_out_videogen : PCLK_out;
-assign HDMI_TX_DE = videogen_sel ? DE_out_videogen : DE_out;
-`else
-wire videogen_sel;
-assign videogen_sel = 1'b0;
-assign HDMI_TX_RD = R_out;
-assign HDMI_TX_GD = G_out;
-assign HDMI_TX_BD = B_out;
-assign HDMI_TX_HS = HSYNC_out;
-assign HDMI_TX_VS = VSYNC_out;
+wire enable_sc = sys_ctrl[1];
+assign xpos = enable_sc ? xpos_sc : xpos_vg;
+assign ypos = enable_sc ? ypos_sc : ypos_vg;
 assign HDMI_TX_PCLK = PCLK_out;
-assign HDMI_TX_DE = DE_out;
-`endif
+
+always @(posedge PCLK_out) begin
+    if (osd_enable) begin
+        if (osd_color == 2'h0) begin
+            {HDMI_TX_RD, HDMI_TX_GD, HDMI_TX_BD} <= 24'h000000;
+        end else if (osd_color == 2'h1) begin
+            {HDMI_TX_RD, HDMI_TX_GD, HDMI_TX_BD} <= 24'h0000ff;
+        end else if (osd_color == 2'h2) begin
+            {HDMI_TX_RD, HDMI_TX_GD, HDMI_TX_BD} <= 24'hffff00;
+        end else begin
+            {HDMI_TX_RD, HDMI_TX_GD, HDMI_TX_BD} <= 24'hffffff;
+        end
+    end else if (enable_sc) begin
+        {HDMI_TX_RD, HDMI_TX_GD, HDMI_TX_BD} <= {R_out_sc, G_out_sc, B_out_sc};
+    end else begin
+        {HDMI_TX_RD, HDMI_TX_GD, HDMI_TX_BD} <= {R_out_vg, G_out_vg, B_out_vg};
+    end
+
+    HDMI_TX_HS <= enable_sc ? HSYNC_out_sc : HSYNC_out_vg;
+    HDMI_TX_VS <= enable_sc ? VSYNC_out_sc : VSYNC_out_vg;
+    HDMI_TX_DE <= enable_sc ? DE_out_sc : DE_out_vg;
+end
 
 // LCD backlight timeout counters
 always @(posedge clk27)
@@ -241,7 +253,7 @@ sys sys_inst(
     .i2c_opencores_1_export_sda_pad_io      (SD_CMD),
     .i2c_opencores_1_export_spi_miso_pad_i  (SD_DAT[0]),
     .pio_0_sys_ctrl_out_export              (sys_ctrl),
-    .pio_1_controls_in_export               ({ir_code_cnt, 5'b00000, HDMI_TX_MODE_LL, btn_LL, ir_code}),
+    .pio_1_controls_in_export               ({ir_code_cnt, 4'b0000, pll_activeclock, HDMI_TX_MODE_LL, btn_LL, ir_code}),
     .sc_config_0_sc_if_sc_status_i          ({vsync_flag, 2'b00, vmax_tvp, fpga_vsyncgen, 4'h0, ilace_flag, vmax}),
     .sc_config_0_sc_if_sc_status2_i         ({12'h000, pcnt_frame}),
     .sc_config_0_sc_if_lt_status_i          ({lt_finished, 3'h0, lt_stb_result, lt_lat_result}),
@@ -250,13 +262,25 @@ sys sys_inst(
     .sc_config_0_sc_if_v_config_o           (v_config),
     .sc_config_0_sc_if_misc_config_o        (misc_config),
     .sc_config_0_sc_if_sl_config_o          (sl_config),
-    .sc_config_0_sc_if_sl_config2_o         (sl_config2)
+    .sc_config_0_sc_if_sl_config2_o         (sl_config2),
+    .osd_generator_0_osd_if_vclk            (PCLK_out),
+    .osd_generator_0_osd_if_xpos            (xpos),
+    .osd_generator_0_osd_if_ypos            (ypos),
+    .osd_generator_0_osd_if_osd_enable      (osd_enable_pre),
+    .osd_generator_0_osd_if_osd_color       (osd_color),
+    .pll_reconfig_0_pll_reconfig_if_areset       (pll_areset),
+    .pll_reconfig_0_pll_reconfig_if_scanclk      (pll_scanclk),
+    .pll_reconfig_0_pll_reconfig_if_scanclkena   (pll_scanclkena),
+    .pll_reconfig_0_pll_reconfig_if_configupdate (pll_configupdate),
+    .pll_reconfig_0_pll_reconfig_if_scandata     (pll_scandata),
+    .pll_reconfig_0_pll_reconfig_if_scandone     (pll_scandone)
 );
 
 scanconverter scanconverter_inst (
     .reset_n        (hw_reset_n),
     .PCLK_in        (PCLK_in),
     .clk27          (clk27),
+    .enable_sc      (enable_sc),
     .HSYNC_in       (HSYNC_in_L),
     .VSYNC_in       (VSYNC_in_L),
     .FID_in         (FID_in_L),
@@ -269,16 +293,15 @@ scanconverter scanconverter_inst (
     .misc_config    (misc_config),
     .sl_config      (sl_config),
     .sl_config2     (sl_config2),
-    .R_out          (R_out),
-    .G_out          (G_out),
-    .B_out          (B_out),
-    .HSYNC_out      (HSYNC_out),
-    .VSYNC_out      (VSYNC_out),
+    .R_out          (R_out_sc),
+    .G_out          (G_out_sc),
+    .B_out          (B_out_sc),
     .PCLK_out       (PCLK_out),
-    .DE_out         (DE_out),
+    .HSYNC_out      (HSYNC_out_sc),
+    .VSYNC_out      (VSYNC_out_sc),
+    .DE_out         (DE_out_sc),
     .h_unstable     (h_unstable),
     .fpga_vsyncgen  (fpga_vsyncgen),
-    .pclk_lock      (pclk_lock),
     .pll_lock_lost  (pll_lock_lost),
     .vmax           (vmax),
     .vmax_tvp       (vmax_tvp),
@@ -286,7 +309,16 @@ scanconverter scanconverter_inst (
     .ilace_flag     (ilace_flag),
     .vsync_flag     (vsync_flag),
     .lt_active      (lt_active),
-    .lt_mode        (lt_mode_synced)
+    .lt_mode        (lt_mode_synced),
+    .xpos           (xpos_sc),
+    .ypos           (ypos_sc),
+    .pll_areset       (pll_areset),
+    .pll_scanclk      (pll_scanclk),
+    .pll_scanclkena   (pll_scanclkena),
+    .pll_configupdate (pll_configupdate),
+    .pll_scandata     (pll_scandata),
+    .pll_scandone     (pll_scandone),
+    .pll_activeclock  (pll_activeclock)
 );
 
 ir_rcv ir0 (
@@ -300,33 +332,33 @@ ir_rcv ir0 (
 
 lat_tester lt0 (
     .clk27          (clk27),
-    .pclk           (HDMI_TX_PCLK),
+    .pclk           (PCLK_out),
     .active         (lt_active),
     .armed          (lt_armed),
-    .sensor         (btn_LL[1]),
-    .trigger        (HDMI_TX_DE & HDMI_TX_GD[0]),
+    .sensor         (lt_sensor),
+    .trigger        (lt_trigger),
     .VSYNC_in       (HDMI_TX_VS),
     .mode_in        (lt_mode),
     .mode_synced    (lt_mode_synced),
     .lat_result     (lt_lat_result),
     .stb_result     (lt_stb_result),
+    .trig_waiting   (lt_trig_waiting),
     .finished       (lt_finished)
 );
 
-`ifdef VIDEOGEN
 videogen vg0 (
-    .clk27          (clk27),
-    .reset_n        (po_reset_n & videogen_sel),
+    .clk27          (PCLK_out),
+    .reset_n        (po_reset_n & ~enable_sc),
     .lt_active      (lt_active),
     .lt_mode        (lt_mode_synced),
-    .R_out          (R_out_videogen),
-    .G_out          (G_out_videogen),
-    .B_out          (B_out_videogen),
-    .HSYNC_out      (HSYNC_out_videogen),
-    .VSYNC_out      (VSYNC_out_videogen),
-    .PCLK_out       (PCLK_out_videogen),
-    .ENABLE_out     (DE_out_videogen)
+    .R_out          (R_out_vg),
+    .G_out          (G_out_vg),
+    .B_out          (B_out_vg),
+    .HSYNC_out      (HSYNC_out_vg),
+    .VSYNC_out      (VSYNC_out_vg),
+    .DE_out         (DE_out_vg),
+    .xpos           (xpos_vg),
+    .ypos           (ypos_vg)
 );
-`endif
 
 endmodule

rtl/pll_2x.ppf

@@ -3,10 +3,19 @@
 <pinplan intended_family="Cyclone IV E" variation_name="pll_2x" megafunction_name="ALTPLL" specifies="all_ports">
 <global>
 <pin name="areset" direction="input" scope="external"  />
+<pin name="clkswitch" direction="input" scope="external"  />
+<pin name="configupdate" direction="input" scope="external"  />
 <pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="inclk1" direction="input" scope="external" source="clock"  />
+<pin name="scanclk" direction="input" scope="external" source="clock"  />
+<pin name="scanclkena" direction="input" scope="external"  />
+<pin name="scandata" direction="input" scope="external"  />
+<pin name="activeclock" direction="output" scope="external"  />
 <pin name="c0" direction="output" scope="external" source="clock"  />
 <pin name="c1" direction="output" scope="external" source="clock"  />
 <pin name="locked" direction="output" scope="external"  />
+<pin name="scandataout" direction="output" scope="external"  />
+<pin name="scandone" direction="output" scope="external"  />
 
 </global>
 </pinplan>

rtl/pll_2x.qip

@@ -1,6 +1,7 @@
 set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "17.1"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_2x.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x_inst.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x_bb.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x.ppf"]

rtl/pll_2x.v

@@ -9,18 +9,18 @@
 // 			altpll
 //
 // Simulation Library Files(s):
-// 			
+// 			altera_mf
 // ============================================================
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
+// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 2017  Intel Corporation. All rights reserved.
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic 
+//and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 
 //(including device programming or simulation files), and any 
 //associated documentation or information are expressly subject 
@@ -30,7 +30,8 @@
 //agreement, including, without limitation, that your use is for
 //the sole purpose of programming logic devices manufactured by
 //Intel and sold by Intel or its authorized distributors.  Please
-//refer to the applicable agreement for further details.
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
 
 
 // synopsys translate_off
@@ -38,46 +39,79 @@
 // synopsys translate_on
 module pll_2x (
 	areset,
+	clkswitch,
+	configupdate,
 	inclk0,
+	inclk1,
+	scanclk,
+	scanclkena,
+	scandata,
+	activeclock,
 	c0,
 	c1,
-	locked);
+	locked,
+	scandataout,
+	scandone);
 
 	input	  areset;
+	input	  clkswitch;
+	input	  configupdate;
 	input	  inclk0;
+	input	  inclk1;
+	input	  scanclk;
+	input	  scanclkena;
+	input	  scandata;
+	output	  activeclock;
 	output	  c0;
 	output	  c1;
 	output	  locked;
+	output	  scandataout;
+	output	  scandone;
 `ifndef ALTERA_RESERVED_QIS
 // synopsys translate_off
 `endif
 	tri0	  areset;
+	tri0	  clkswitch;
+	tri0	  configupdate;
+	tri0	  scanclkena;
+	tri0	  scandata;
 `ifndef ALTERA_RESERVED_QIS
 // synopsys translate_on
 `endif
 
-	wire [4:0] sub_wire0;
-	wire  sub_wire3;
-	wire [0:0] sub_wire6 = 1'h0;
-	wire [1:1] sub_wire2 = sub_wire0[1:1];
-	wire [0:0] sub_wire1 = sub_wire0[0:0];
-	wire  c0 = sub_wire1;
-	wire  c1 = sub_wire2;
-	wire  locked = sub_wire3;
-	wire  sub_wire4 = inclk0;
-	wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
+	wire  sub_wire0;
+	wire [4:0] sub_wire1;
+	wire  sub_wire4;
+	wire  sub_wire5;
+	wire  sub_wire6;
+	wire  sub_wire9 = inclk1;
+	wire  activeclock = sub_wire0;
+	wire [1:1] sub_wire3 = sub_wire1[1:1];
+	wire [0:0] sub_wire2 = sub_wire1[0:0];
+	wire  c0 = sub_wire2;
+	wire  c1 = sub_wire3;
+	wire  locked = sub_wire4;
+	wire  scandataout = sub_wire5;
+	wire  scandone = sub_wire6;
+	wire  sub_wire7 = inclk0;
+	wire [1:0] sub_wire8 = {sub_wire9, sub_wire7};
 
 	altpll	altpll_component (
 				.areset (areset),
-				.inclk (sub_wire5),
-				.clk (sub_wire0),
-				.locked (sub_wire3),
-				.activeclock (),
+				.clkswitch (clkswitch),
+				.configupdate (configupdate),
+				.inclk (sub_wire8),
+				.scanclk (scanclk),
+				.scanclkena (scanclkena),
+				.scandata (scandata),
+				.activeclock (sub_wire0),
+				.clk (sub_wire1),
+				.locked (sub_wire4),
+				.scandataout (sub_wire5),
+				.scandone (sub_wire6),
 				.clkbad (),
 				.clkena ({6{1'b1}}),
 				.clkloss (),
-				.clkswitch (1'b0),
-				.configupdate (1'b0),
 				.enable0 (),
 				.enable1 (),
 				.extclk (),
@@ -94,11 +128,6 @@ module pll_2x (
 				.phaseupdown (1'b1),
 				.pllena (1'b1),
 				.scanaclr (1'b0),
-				.scanclk (1'b0),
-				.scanclkena (1'b1),
-				.scandata (1'b0),
-				.scandataout (),
-				.scandone (),
 				.scanread (1'b0),
 				.scanwrite (1'b0),
 				.sclkout0 (),
@@ -109,29 +138,30 @@ module pll_2x (
 		altpll_component.bandwidth_type = "HIGH",
 		altpll_component.clk0_divide_by = 1,
 		altpll_component.clk0_duty_cycle = 50,
-		altpll_component.clk0_multiply_by = 2,
+		altpll_component.clk0_multiply_by = 1,
 		altpll_component.clk0_phase_shift = "0",
 		altpll_component.clk1_divide_by = 1,
 		altpll_component.clk1_duty_cycle = 50,
-		altpll_component.clk1_multiply_by = 5,
+		altpll_component.clk1_multiply_by = 1,
 		altpll_component.clk1_phase_shift = "0",
 		altpll_component.compensate_clock = "CLK0",
 		altpll_component.inclk0_input_frequency = 37037,
+		altpll_component.inclk1_input_frequency = 37037,
 		altpll_component.intended_device_family = "Cyclone IV E",
 		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_2x",
 		altpll_component.lpm_type = "altpll",
-		altpll_component.operation_mode = "SOURCE_SYNCHRONOUS",
+		altpll_component.operation_mode = "NORMAL",
 		altpll_component.pll_type = "AUTO",
-		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_activeclock = "PORT_USED",
 		altpll_component.port_areset = "PORT_USED",
 		altpll_component.port_clkbad0 = "PORT_UNUSED",
 		altpll_component.port_clkbad1 = "PORT_UNUSED",
 		altpll_component.port_clkloss = "PORT_UNUSED",
-		altpll_component.port_clkswitch = "PORT_UNUSED",
-		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_USED",
+		altpll_component.port_configupdate = "PORT_USED",
 		altpll_component.port_fbin = "PORT_UNUSED",
 		altpll_component.port_inclk0 = "PORT_USED",
-		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_inclk1 = "PORT_USED",
 		altpll_component.port_locked = "PORT_USED",
 		altpll_component.port_pfdena = "PORT_UNUSED",
 		altpll_component.port_phasecounterselect = "PORT_UNUSED",
@@ -140,11 +170,11 @@ module pll_2x (
 		altpll_component.port_phaseupdown = "PORT_UNUSED",
 		altpll_component.port_pllena = "PORT_UNUSED",
 		altpll_component.port_scanaclr = "PORT_UNUSED",
-		altpll_component.port_scanclk = "PORT_UNUSED",
-		altpll_component.port_scanclkena = "PORT_UNUSED",
-		altpll_component.port_scandata = "PORT_UNUSED",
-		altpll_component.port_scandataout = "PORT_UNUSED",
-		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_USED",
+		altpll_component.port_scanclkena = "PORT_USED",
+		altpll_component.port_scandata = "PORT_USED",
+		altpll_component.port_scandataout = "PORT_USED",
+		altpll_component.port_scandone = "PORT_USED",
 		altpll_component.port_scanread = "PORT_UNUSED",
 		altpll_component.port_scanwrite = "PORT_UNUSED",
 		altpll_component.port_clk0 = "PORT_USED",
@@ -163,8 +193,16 @@ module pll_2x (
 		altpll_component.port_extclk1 = "PORT_UNUSED",
 		altpll_component.port_extclk2 = "PORT_UNUSED",
 		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.primary_clock = "inclk0",
 		altpll_component.self_reset_on_loss_lock = "OFF",
-		altpll_component.width_clock = 5;
+		altpll_component.switch_over_type = "MANUAL",
+		altpll_component.width_clock = 5,
+`ifdef NO_PLI
+		altpll_component.scan_chain_mif_file = "pll_2x.rif"
+`else
+		altpll_component.scan_chain_mif_file = "pll_2x.hex"
+`endif
+;
 
 
 endmodule
@@ -172,7 +210,7 @@ endmodule
 // ============================================================
 // CNX file retrieval info
 // ============================================================
-// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "1"
 // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
 // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
@@ -184,16 +222,16 @@ endmodule
 // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
 // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
 // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "1"
 // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
 // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
 // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
 // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
 // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "54.000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "135.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "27.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "27.000000"
 // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -203,7 +241,7 @@ endmodule
 // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
 // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
 // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "27.000"
 // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
 // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
 // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
@@ -218,9 +256,9 @@ endmodule
 // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
 // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
 // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
-// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "5"
-// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
 // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
@@ -244,8 +282,8 @@ endmodule
 // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
 // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
 // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_2x.mif"
-// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_2x.hex"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "1"
 // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
 // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
@@ -254,7 +292,7 @@ endmodule
 // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
 // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
 // Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
 // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
 // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
 // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
@@ -270,28 +308,29 @@ endmodule
 // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "HIGH"
 // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
 // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
 // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
 // Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
 // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
 // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+// Retrieval info: CONSTANT: INCLK1_INPUT_FREQUENCY NUMERIC "37037"
 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
 // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
 // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
@@ -300,11 +339,11 @@ endmodule
 // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
@@ -323,25 +362,48 @@ endmodule
 // Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PRIMARY_CLOCK STRING "inclk0"
 // Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+// Retrieval info: CONSTANT: SWITCH_OVER_TYPE STRING "MANUAL"
 // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: CONSTANT: scan_chain_mif_file STRING "pll_2x.hex"
 // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: activeclock 0 0 0 0 OUTPUT GND "activeclock"
 // Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
 // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
 // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: clkswitch 0 0 0 0 INPUT GND "clkswitch"
+// Retrieval info: USED_PORT: configupdate 0 0 0 0 INPUT GND "configupdate"
 // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: inclk1 0 0 0 0 INPUT_CLK_EXT GND "inclk1"
 // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
+// Retrieval info: USED_PORT: scanclkena 0 0 0 0 INPUT GND "scanclkena"
+// Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata"
+// Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout"
+// Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone"
 // Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkswitch 0 0 0 0 clkswitch 0 0 0 0
+// Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0
 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 inclk1 0 0 0 0
+// Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
+// Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0
+// Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0
+// Retrieval info: CONNECT: activeclock 0 0 0 0 @activeclock 0 0 0 0
 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
 // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0
+// Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.v TRUE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.ppf TRUE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.inc FALSE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.cmp FALSE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x_inst.v TRUE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.mif TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.hex TRUE
+// Retrieval info: LIB_FILE: altera_mf
 // Retrieval info: CBX_MODULE_PREFIX: ON

rtl/pll_3x.ppf

@@ -1,12 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" ?>
-<!DOCTYPE pinplan>
-<pinplan intended_family="Cyclone IV E" variation_name="pll_3x" megafunction_name="ALTPLL" specifies="all_ports">
-<global>
-<pin name="areset" direction="input" scope="external"  />
-<pin name="inclk0" direction="input" scope="external" source="clock"  />
-<pin name="c0" direction="output" scope="external" source="clock"  />
-<pin name="c1" direction="output" scope="external" source="clock"  />
-<pin name="locked" direction="output" scope="external"  />
-
-</global>
-</pinplan>

rtl/pll_3x.qip

@@ -1,5 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "17.1"
-set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_3x.v"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_3x.ppf"]

rtl/pll_3x.v

@@ -1,347 +0,0 @@
-// megafunction wizard: %ALTPLL%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altpll 
-
-// ============================================================
-// File Name: pll_3x.v
-// Megafunction Name(s):
-// 			altpll
-//
-// Simulation Library Files(s):
-// 			
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
-// ************************************************************
-
-
-//Copyright (C) 2017  Intel Corporation. All rights reserved.
-//Your use of Intel Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic 
-//functions, and any output files from any of the foregoing 
-//(including device programming or simulation files), and any 
-//associated documentation or information are expressly subject 
-//to the terms and conditions of the Intel Program License 
-//Subscription Agreement, the Intel Quartus Prime License Agreement,
-//the Intel FPGA IP License Agreement, or other applicable license
-//agreement, including, without limitation, that your use is for
-//the sole purpose of programming logic devices manufactured by
-//Intel and sold by Intel or its authorized distributors.  Please
-//refer to the applicable agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module pll_3x (
-	areset,
-	inclk0,
-	c0,
-	c1,
-	locked);
-
-	input	  areset;
-	input	  inclk0;
-	output	  c0;
-	output	  c1;
-	output	  locked;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_off
-`endif
-	tri0	  areset;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_on
-`endif
-
-	wire [4:0] sub_wire0;
-	wire  sub_wire3;
-	wire [0:0] sub_wire6 = 1'h0;
-	wire [1:1] sub_wire2 = sub_wire0[1:1];
-	wire [0:0] sub_wire1 = sub_wire0[0:0];
-	wire  c0 = sub_wire1;
-	wire  c1 = sub_wire2;
-	wire  locked = sub_wire3;
-	wire  sub_wire4 = inclk0;
-	wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
-
-	altpll	altpll_component (
-				.areset (areset),
-				.inclk (sub_wire5),
-				.clk (sub_wire0),
-				.locked (sub_wire3),
-				.activeclock (),
-				.clkbad (),
-				.clkena ({6{1'b1}}),
-				.clkloss (),
-				.clkswitch (1'b0),
-				.configupdate (1'b0),
-				.enable0 (),
-				.enable1 (),
-				.extclk (),
-				.extclkena ({4{1'b1}}),
-				.fbin (1'b1),
-				.fbmimicbidir (),
-				.fbout (),
-				.fref (),
-				.icdrclk (),
-				.pfdena (1'b1),
-				.phasecounterselect ({4{1'b1}}),
-				.phasedone (),
-				.phasestep (1'b1),
-				.phaseupdown (1'b1),
-				.pllena (1'b1),
-				.scanaclr (1'b0),
-				.scanclk (1'b0),
-				.scanclkena (1'b1),
-				.scandata (1'b0),
-				.scandataout (),
-				.scandone (),
-				.scanread (1'b0),
-				.scanwrite (1'b0),
-				.sclkout0 (),
-				.sclkout1 (),
-				.vcooverrange (),
-				.vcounderrange ());
-	defparam
-		altpll_component.bandwidth_type = "HIGH",
-		altpll_component.clk0_divide_by = 1,
-		altpll_component.clk0_duty_cycle = 50,
-		altpll_component.clk0_multiply_by = 3,
-		altpll_component.clk0_phase_shift = "0",
-		altpll_component.clk1_divide_by = 1,
-		altpll_component.clk1_duty_cycle = 50,
-		altpll_component.clk1_multiply_by = 4,
-		altpll_component.clk1_phase_shift = "0",
-		altpll_component.compensate_clock = "CLK0",
-		altpll_component.inclk0_input_frequency = 37037,
-		altpll_component.intended_device_family = "Cyclone IV E",
-		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_3x",
-		altpll_component.lpm_type = "altpll",
-		altpll_component.operation_mode = "SOURCE_SYNCHRONOUS",
-		altpll_component.pll_type = "AUTO",
-		altpll_component.port_activeclock = "PORT_UNUSED",
-		altpll_component.port_areset = "PORT_USED",
-		altpll_component.port_clkbad0 = "PORT_UNUSED",
-		altpll_component.port_clkbad1 = "PORT_UNUSED",
-		altpll_component.port_clkloss = "PORT_UNUSED",
-		altpll_component.port_clkswitch = "PORT_UNUSED",
-		altpll_component.port_configupdate = "PORT_UNUSED",
-		altpll_component.port_fbin = "PORT_UNUSED",
-		altpll_component.port_inclk0 = "PORT_USED",
-		altpll_component.port_inclk1 = "PORT_UNUSED",
-		altpll_component.port_locked = "PORT_USED",
-		altpll_component.port_pfdena = "PORT_UNUSED",
-		altpll_component.port_phasecounterselect = "PORT_UNUSED",
-		altpll_component.port_phasedone = "PORT_UNUSED",
-		altpll_component.port_phasestep = "PORT_UNUSED",
-		altpll_component.port_phaseupdown = "PORT_UNUSED",
-		altpll_component.port_pllena = "PORT_UNUSED",
-		altpll_component.port_scanaclr = "PORT_UNUSED",
-		altpll_component.port_scanclk = "PORT_UNUSED",
-		altpll_component.port_scanclkena = "PORT_UNUSED",
-		altpll_component.port_scandata = "PORT_UNUSED",
-		altpll_component.port_scandataout = "PORT_UNUSED",
-		altpll_component.port_scandone = "PORT_UNUSED",
-		altpll_component.port_scanread = "PORT_UNUSED",
-		altpll_component.port_scanwrite = "PORT_UNUSED",
-		altpll_component.port_clk0 = "PORT_USED",
-		altpll_component.port_clk1 = "PORT_USED",
-		altpll_component.port_clk2 = "PORT_UNUSED",
-		altpll_component.port_clk3 = "PORT_UNUSED",
-		altpll_component.port_clk4 = "PORT_UNUSED",
-		altpll_component.port_clk5 = "PORT_UNUSED",
-		altpll_component.port_clkena0 = "PORT_UNUSED",
-		altpll_component.port_clkena1 = "PORT_UNUSED",
-		altpll_component.port_clkena2 = "PORT_UNUSED",
-		altpll_component.port_clkena3 = "PORT_UNUSED",
-		altpll_component.port_clkena4 = "PORT_UNUSED",
-		altpll_component.port_clkena5 = "PORT_UNUSED",
-		altpll_component.port_extclk0 = "PORT_UNUSED",
-		altpll_component.port_extclk1 = "PORT_UNUSED",
-		altpll_component.port_extclk2 = "PORT_UNUSED",
-		altpll_component.port_extclk3 = "PORT_UNUSED",
-		altpll_component.self_reset_on_loss_lock = "OFF",
-		altpll_component.width_clock = 5;
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "High"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
-// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "81.000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "108.000000"
-// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "3"
-// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
-// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_2x.mif"
-// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "HIGH"
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "3"
-// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
-// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
-// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x.ppf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_bb.v FALSE
-// Retrieval info: CBX_MODULE_PREFIX: ON

rtl/pll_config_2x_5x_data.mif

@@ -0,0 +1,174 @@
+-- Copyright (C) 2017  Intel Corporation. All rights reserved.
+-- Your use of Intel Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Intel Program License 
+-- Subscription Agreement, the Intel Quartus Prime License Agreement,
+-- the Intel FPGA IP License Agreement, or other applicable license
+-- agreement, including, without limitation, that your use is for
+-- the sole purpose of programming logic devices manufactured by
+-- Intel and sold by Intel or its authorized distributors.  Please
+-- refer to the applicable agreement for further details.
+
+-- MIF file representing initial state of PLL Scan Chain
+--    Device Family: Cyclone IV E
+--    Device Part: -
+--    Device Speed Grade: 8
+--    PLL Scan Chain: Fast PLL (144 bits)
+--    File Name: /home/markus/Code/ossc/rtl/pll_config_2x_5x_data.mif
+--    Generated: Sat Oct  5 23:56:40 2019
+
+WIDTH=1;
+DEPTH=144;
+
+ADDRESS_RADIX=UNS;
+DATA_RADIX=UNS;
+
+CONTENT BEGIN
+	0    :   0; -- Reserved Bits = 0 (1 bit(s))
+	1    :   0; -- Reserved Bits = 0 (1 bit(s))
+	2    :   0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
+	3    :   0;
+	4    :   1; -- Loop Filter Resistance = 27 (5 bit(s)) (Setting 27)
+	5    :   1;
+	6    :   0;
+	7    :   1;
+	8    :   1;
+	9    :   1; -- VCO Post Scale = 1 (1 bit(s)) (VCO post-scale divider counter value = 1)
+	10   :   0; -- Reserved Bits = 0 (5 bit(s))
+	11   :   0;
+	12   :   0;
+	13   :   0;
+	14   :   0;
+	15   :   0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
+	16   :   0;
+	17   :   1;
+	18   :   1; -- N counter: Bypass = 1 (1 bit(s))
+	19   :   0; -- N counter: High Count = 0 (8 bit(s))
+	20   :   0;
+	21   :   0;
+	22   :   0;
+	23   :   0;
+	24   :   0;
+	25   :   0;
+	26   :   0;
+	27   :   0; -- N counter: Odd Division = 0 (1 bit(s))
+	28   :   0; -- N counter: Low Count = 0 (8 bit(s))
+	29   :   0;
+	30   :   0;
+	31   :   0;
+	32   :   0;
+	33   :   0;
+	34   :   0;
+	35   :   0;
+	36   :   0; -- M counter: Bypass = 0 (1 bit(s))
+	37   :   0; -- M counter: High Count = 15 (8 bit(s))
+	38   :   0;
+	39   :   0;
+	40   :   0;
+	41   :   1;
+	42   :   1;
+	43   :   1;
+	44   :   1;
+	45   :   0; -- M counter: Odd Division = 0 (1 bit(s))
+	46   :   0; -- M counter: Low Count = 15 (8 bit(s))
+	47   :   0;
+	48   :   0;
+	49   :   0;
+	50   :   1;
+	51   :   1;
+	52   :   1;
+	53   :   1;
+	54   :   0; -- clk0 counter: Bypass = 0 (1 bit(s))
+	55   :   0; -- clk0 counter: High Count = 8 (8 bit(s))
+	56   :   0;
+	57   :   0;
+	58   :   0;
+	59   :   1;
+	60   :   0;
+	61   :   0;
+	62   :   0;
+	63   :   1; -- clk0 counter: Odd Division = 1 (1 bit(s))
+	64   :   0; -- clk0 counter: Low Count = 7 (8 bit(s))
+	65   :   0;
+	66   :   0;
+	67   :   0;
+	68   :   0;
+	69   :   1;
+	70   :   1;
+	71   :   1;
+	72   :   0; -- clk1 counter: Bypass = 0 (1 bit(s))
+	73   :   0; -- clk1 counter: High Count = 3 (8 bit(s))
+	74   :   0;
+	75   :   0;
+	76   :   0;
+	77   :   0;
+	78   :   0;
+	79   :   1;
+	80   :   1;
+	81   :   0; -- clk1 counter: Odd Division = 0 (1 bit(s))
+	82   :   0; -- clk1 counter: Low Count = 3 (8 bit(s))
+	83   :   0;
+	84   :   0;
+	85   :   0;
+	86   :   0;
+	87   :   0;
+	88   :   1;
+	89   :   1;
+	90   :   1; -- clk2 counter: Bypass = 1 (1 bit(s))
+	91   :   0; -- clk2 counter: High Count = 0 (8 bit(s))
+	92   :   0;
+	93   :   0;
+	94   :   0;
+	95   :   0;
+	96   :   0;
+	97   :   0;
+	98   :   0;
+	99   :   0; -- clk2 counter: Odd Division = 0 (1 bit(s))
+	100  :   0; -- clk2 counter: Low Count = 0 (8 bit(s))
+	101  :   0;
+	102  :   0;
+	103  :   0;
+	104  :   0;
+	105  :   0;
+	106  :   0;
+	107  :   0;
+	108  :   1; -- clk3 counter: Bypass = 1 (1 bit(s))
+	109  :   0; -- clk3 counter: High Count = 0 (8 bit(s))
+	110  :   0;
+	111  :   0;
+	112  :   0;
+	113  :   0;
+	114  :   0;
+	115  :   0;
+	116  :   0;
+	117  :   0; -- clk3 counter: Odd Division = 0 (1 bit(s))
+	118  :   0; -- clk3 counter: Low Count = 0 (8 bit(s))
+	119  :   0;
+	120  :   0;
+	121  :   0;
+	122  :   0;
+	123  :   0;
+	124  :   0;
+	125  :   0;
+	126  :   1; -- clk4 counter: Bypass = 1 (1 bit(s))
+	127  :   0; -- clk4 counter: High Count = 0 (8 bit(s))
+	128  :   0;
+	129  :   0;
+	130  :   0;
+	131  :   0;
+	132  :   0;
+	133  :   0;
+	134  :   0;
+	135  :   0; -- clk4 counter: Odd Division = 0 (1 bit(s))
+	136  :   0; -- clk4 counter: Low Count = 0 (8 bit(s))
+	137  :   0;
+	138  :   0;
+	139  :   0;
+	140  :   0;
+	141  :   0;
+	142  :   0;
+	143  :   0;
+END;

rtl/pll_config_3x_4x_data.mif

@@ -0,0 +1,174 @@
+-- Copyright (C) 2017  Intel Corporation. All rights reserved.
+-- Your use of Intel Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Intel Program License 
+-- Subscription Agreement, the Intel Quartus Prime License Agreement,
+-- the Intel FPGA IP License Agreement, or other applicable license
+-- agreement, including, without limitation, that your use is for
+-- the sole purpose of programming logic devices manufactured by
+-- Intel and sold by Intel or its authorized distributors.  Please
+-- refer to the applicable agreement for further details.
+
+-- MIF file representing initial state of PLL Scan Chain
+--    Device Family: Cyclone IV E
+--    Device Part: -
+--    Device Speed Grade: 8
+--    PLL Scan Chain: Fast PLL (144 bits)
+--    File Name: /home/markus/Code/ossc/rtl/pll_config_3x_4x_data.mif
+--    Generated: Sat Oct  5 23:58:13 2019
+
+WIDTH=1;
+DEPTH=144;
+
+ADDRESS_RADIX=UNS;
+DATA_RADIX=UNS;
+
+CONTENT BEGIN
+	0    :   0; -- Reserved Bits = 0 (1 bit(s))
+	1    :   0; -- Reserved Bits = 0 (1 bit(s))
+	2    :   0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
+	3    :   0;
+	4    :   1; -- Loop Filter Resistance = 27 (5 bit(s)) (Setting 27)
+	5    :   1;
+	6    :   0;
+	7    :   1;
+	8    :   1;
+	9    :   0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2)
+	10   :   0; -- Reserved Bits = 0 (5 bit(s))
+	11   :   0;
+	12   :   0;
+	13   :   0;
+	14   :   0;
+	15   :   0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
+	16   :   0;
+	17   :   1;
+	18   :   1; -- N counter: Bypass = 1 (1 bit(s))
+	19   :   0; -- N counter: High Count = 0 (8 bit(s))
+	20   :   0;
+	21   :   0;
+	22   :   0;
+	23   :   0;
+	24   :   0;
+	25   :   0;
+	26   :   0;
+	27   :   0; -- N counter: Odd Division = 0 (1 bit(s))
+	28   :   0; -- N counter: Low Count = 0 (8 bit(s))
+	29   :   0;
+	30   :   0;
+	31   :   0;
+	32   :   0;
+	33   :   0;
+	34   :   0;
+	35   :   0;
+	36   :   0; -- M counter: Bypass = 0 (1 bit(s))
+	37   :   0; -- M counter: High Count = 6 (8 bit(s))
+	38   :   0;
+	39   :   0;
+	40   :   0;
+	41   :   0;
+	42   :   1;
+	43   :   1;
+	44   :   0;
+	45   :   0; -- M counter: Odd Division = 0 (1 bit(s))
+	46   :   0; -- M counter: Low Count = 6 (8 bit(s))
+	47   :   0;
+	48   :   0;
+	49   :   0;
+	50   :   0;
+	51   :   1;
+	52   :   1;
+	53   :   0;
+	54   :   0; -- clk0 counter: Bypass = 0 (1 bit(s))
+	55   :   0; -- clk0 counter: High Count = 2 (8 bit(s))
+	56   :   0;
+	57   :   0;
+	58   :   0;
+	59   :   0;
+	60   :   0;
+	61   :   1;
+	62   :   0;
+	63   :   0; -- clk0 counter: Odd Division = 0 (1 bit(s))
+	64   :   0; -- clk0 counter: Low Count = 2 (8 bit(s))
+	65   :   0;
+	66   :   0;
+	67   :   0;
+	68   :   0;
+	69   :   0;
+	70   :   1;
+	71   :   0;
+	72   :   0; -- clk1 counter: Bypass = 0 (1 bit(s))
+	73   :   0; -- clk1 counter: High Count = 2 (8 bit(s))
+	74   :   0;
+	75   :   0;
+	76   :   0;
+	77   :   0;
+	78   :   0;
+	79   :   1;
+	80   :   0;
+	81   :   1; -- clk1 counter: Odd Division = 1 (1 bit(s))
+	82   :   0; -- clk1 counter: Low Count = 1 (8 bit(s))
+	83   :   0;
+	84   :   0;
+	85   :   0;
+	86   :   0;
+	87   :   0;
+	88   :   0;
+	89   :   1;
+	90   :   1; -- clk2 counter: Bypass = 1 (1 bit(s))
+	91   :   0; -- clk2 counter: High Count = 0 (8 bit(s))
+	92   :   0;
+	93   :   0;
+	94   :   0;
+	95   :   0;
+	96   :   0;
+	97   :   0;
+	98   :   0;
+	99   :   0; -- clk2 counter: Odd Division = 0 (1 bit(s))
+	100  :   0; -- clk2 counter: Low Count = 0 (8 bit(s))
+	101  :   0;
+	102  :   0;
+	103  :   0;
+	104  :   0;
+	105  :   0;
+	106  :   0;
+	107  :   0;
+	108  :   1; -- clk3 counter: Bypass = 1 (1 bit(s))
+	109  :   0; -- clk3 counter: High Count = 0 (8 bit(s))
+	110  :   0;
+	111  :   0;
+	112  :   0;
+	113  :   0;
+	114  :   0;
+	115  :   0;
+	116  :   0;
+	117  :   0; -- clk3 counter: Odd Division = 0 (1 bit(s))
+	118  :   0; -- clk3 counter: Low Count = 0 (8 bit(s))
+	119  :   0;
+	120  :   0;
+	121  :   0;
+	122  :   0;
+	123  :   0;
+	124  :   0;
+	125  :   0;
+	126  :   1; -- clk4 counter: Bypass = 1 (1 bit(s))
+	127  :   0; -- clk4 counter: High Count = 0 (8 bit(s))
+	128  :   0;
+	129  :   0;
+	130  :   0;
+	131  :   0;
+	132  :   0;
+	133  :   0;
+	134  :   0;
+	135  :   0; -- clk4 counter: Odd Division = 0 (1 bit(s))
+	136  :   0; -- clk4 counter: Low Count = 0 (8 bit(s))
+	137  :   0;
+	138  :   0;
+	139  :   0;
+	140  :   0;
+	141  :   0;
+	142  :   0;
+	143  :   0;
+END;

rtl/pll_config_default_data.mif

@@ -0,0 +1,174 @@
+-- Copyright (C) 2017  Intel Corporation. All rights reserved.
+-- Your use of Intel Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Intel Program License 
+-- Subscription Agreement, the Intel Quartus Prime License Agreement,
+-- the Intel FPGA IP License Agreement, or other applicable license
+-- agreement, including, without limitation, that your use is for
+-- the sole purpose of programming logic devices manufactured by
+-- Intel and sold by Intel or its authorized distributors.  Please
+-- refer to the applicable agreement for further details.
+
+-- MIF file representing initial state of PLL Scan Chain
+--    Device Family: Cyclone IV E
+--    Device Part: -
+--    Device Speed Grade: 8
+--    PLL Scan Chain: Fast PLL (144 bits)
+--    File Name: /home/markus/Code/ossc/rtl/pll_config_default_data.mif
+--    Generated: Wed Oct  9 22:20:06 2019
+
+WIDTH=1;
+DEPTH=144;
+
+ADDRESS_RADIX=UNS;
+DATA_RADIX=UNS;
+
+CONTENT BEGIN
+	0    :   0; -- Reserved Bits = 0 (1 bit(s))
+	1    :   0; -- Reserved Bits = 0 (1 bit(s))
+	2    :   0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
+	3    :   0;
+	4    :   1; -- Loop Filter Resistance = 27 (5 bit(s)) (Setting 27)
+	5    :   1;
+	6    :   0;
+	7    :   1;
+	8    :   1;
+	9    :   0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2)
+	10   :   0; -- Reserved Bits = 0 (5 bit(s))
+	11   :   0;
+	12   :   0;
+	13   :   0;
+	14   :   0;
+	15   :   0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
+	16   :   0;
+	17   :   1;
+	18   :   1; -- N counter: Bypass = 1 (1 bit(s))
+	19   :   0; -- N counter: High Count = 0 (8 bit(s))
+	20   :   0;
+	21   :   0;
+	22   :   0;
+	23   :   0;
+	24   :   0;
+	25   :   0;
+	26   :   0;
+	27   :   0; -- N counter: Odd Division = 0 (1 bit(s))
+	28   :   0; -- N counter: Low Count = 0 (8 bit(s))
+	29   :   0;
+	30   :   0;
+	31   :   0;
+	32   :   0;
+	33   :   0;
+	34   :   0;
+	35   :   0;
+	36   :   0; -- M counter: Bypass = 0 (1 bit(s))
+	37   :   0; -- M counter: High Count = 8 (8 bit(s))
+	38   :   0;
+	39   :   0;
+	40   :   0;
+	41   :   1;
+	42   :   0;
+	43   :   0;
+	44   :   0;
+	45   :   0; -- M counter: Odd Division = 0 (1 bit(s))
+	46   :   0; -- M counter: Low Count = 8 (8 bit(s))
+	47   :   0;
+	48   :   0;
+	49   :   0;
+	50   :   1;
+	51   :   0;
+	52   :   0;
+	53   :   0;
+	54   :   0; -- clk0 counter: Bypass = 0 (1 bit(s))
+	55   :   0; -- clk0 counter: High Count = 8 (8 bit(s))
+	56   :   0;
+	57   :   0;
+	58   :   0;
+	59   :   1;
+	60   :   0;
+	61   :   0;
+	62   :   0;
+	63   :   0; -- clk0 counter: Odd Division = 0 (1 bit(s))
+	64   :   0; -- clk0 counter: Low Count = 8 (8 bit(s))
+	65   :   0;
+	66   :   0;
+	67   :   0;
+	68   :   1;
+	69   :   0;
+	70   :   0;
+	71   :   0;
+	72   :   0; -- clk1 counter: Bypass = 0 (1 bit(s))
+	73   :   0; -- clk1 counter: High Count = 8 (8 bit(s))
+	74   :   0;
+	75   :   0;
+	76   :   0;
+	77   :   1;
+	78   :   0;
+	79   :   0;
+	80   :   0;
+	81   :   0; -- clk1 counter: Odd Division = 0 (1 bit(s))
+	82   :   0; -- clk1 counter: Low Count = 8 (8 bit(s))
+	83   :   0;
+	84   :   0;
+	85   :   0;
+	86   :   1;
+	87   :   0;
+	88   :   0;
+	89   :   0;
+	90   :   1; -- clk2 counter: Bypass = 1 (1 bit(s))
+	91   :   0; -- clk2 counter: High Count = 0 (8 bit(s))
+	92   :   0;
+	93   :   0;
+	94   :   0;
+	95   :   0;
+	96   :   0;
+	97   :   0;
+	98   :   0;
+	99   :   0; -- clk2 counter: Odd Division = 0 (1 bit(s))
+	100  :   0; -- clk2 counter: Low Count = 0 (8 bit(s))
+	101  :   0;
+	102  :   0;
+	103  :   0;
+	104  :   0;
+	105  :   0;
+	106  :   0;
+	107  :   0;
+	108  :   1; -- clk3 counter: Bypass = 1 (1 bit(s))
+	109  :   0; -- clk3 counter: High Count = 0 (8 bit(s))
+	110  :   0;
+	111  :   0;
+	112  :   0;
+	113  :   0;
+	114  :   0;
+	115  :   0;
+	116  :   0;
+	117  :   0; -- clk3 counter: Odd Division = 0 (1 bit(s))
+	118  :   0; -- clk3 counter: Low Count = 0 (8 bit(s))
+	119  :   0;
+	120  :   0;
+	121  :   0;
+	122  :   0;
+	123  :   0;
+	124  :   0;
+	125  :   0;
+	126  :   1; -- clk4 counter: Bypass = 1 (1 bit(s))
+	127  :   0; -- clk4 counter: High Count = 0 (8 bit(s))
+	128  :   0;
+	129  :   0;
+	130  :   0;
+	131  :   0;
+	132  :   0;
+	133  :   0;
+	134  :   0;
+	135  :   0; -- clk4 counter: Odd Division = 0 (1 bit(s))
+	136  :   0; -- clk4 counter: Low Count = 0 (8 bit(s))
+	137  :   0;
+	138  :   0;
+	139  :   0;
+	140  :   0;
+	141  :   0;
+	142  :   0;
+	143  :   0;
+END;

rtl/scanconverter.v

@@ -33,11 +33,11 @@
 `define V_MULTMODE_4X           3'd3
 `define V_MULTMODE_5X           3'd4
 
-`define PCLK_MUX_1X             3'd0
-`define PCLK_MUX_2X             3'd1
-`define PCLK_MUX_3X             3'd2
-`define PCLK_MUX_4X             3'd3
-`define PCLK_MUX_5X             3'd4
+`define PCLK_MUX_1X             2'd0
+`define PCLK_MUX_2X             2'd2
+`define PCLK_MUX_3X             2'd2
+`define PCLK_MUX_4X             2'd3
+`define PCLK_MUX_5X             2'd3
 
 `define H_MULTMODE_FULLWIDTH    2'h0
 `define H_MULTMODE_ASPECTFIX    2'h1
@@ -52,18 +52,23 @@
 `define VSYNCGEN_GENMID_BIT     0
 `define VSYNCGEN_CHOPMID_BIT    1
 
-`define FID_EVEN                1'b0
-`define FID_ODD                 1'b1
+`define FID_ODD                 1'b0
+`define FID_EVEN                1'b1
 
 `define MIN_VALID_LINES         256     //power of 2 optimization -> ignore lower bits with comparison
 `define DBLFRAME_THOLD          5
-`define FALSE_FIELD             (fpga_vsyncgen[`VSYNCGEN_CHOPMID_BIT] & (FID_in == `FID_ODD))
+`define FALSE_FIELD             (fpga_vsyncgen[`VSYNCGEN_CHOPMID_BIT] & (FID_in == `FID_EVEN))
 
 `define HSYNC_LEADING_EDGE      ((HSYNC_in_L == `HI) & (HSYNC_in == `LO))
 `define VSYNC_LEADING_EDGE      ((VSYNC_in_L == `HI) & (VSYNC_in == `LO))
 
+`define PP_PL_START             1
+`define PP_HS_VS_DE_START       2
+`define PP_ENABLES_START        2
+`define PP_RGB_START            4
+
 //`define PP_RLPF_PL_START_EARLY      // set if start with 2
-`define PP_RLPF_PL_START        3   // minimum 2
+`define PP_RLPF_PL_START        `PP_RGB_START   // minimum 2
 `define PP_RLPF_PL_LENGTH       3   // counted from aquisition
 `define PP_SLGEN_PL_LENGTH      5
 `define PP_LT_BORDER_GEN_LENGTH 1   // lt_box / border_mask gen
@@ -82,42 +87,52 @@ module scanconverter (
     input HSYNC_in,
     input PCLK_in,
     input clk27,
+    input enable_sc,
     input [31:0] h_config,
     input [31:0] h_config2,
     input [31:0] v_config,
     input [31:0] misc_config,
     input [31:0] sl_config,
     input [31:0] sl_config2,
+    output PCLK_out,
     output reg [7:0] R_out,
     output reg [7:0] G_out,
     output reg [7:0] B_out,
     output reg HSYNC_out,
     output reg VSYNC_out,
-    output PCLK_out,
     output reg DE_out,
     output h_unstable,
     output reg [1:0] fpga_vsyncgen,
-    output [1:0] pclk_lock,
-    output [1:0] pll_lock_lost,
+    output pll_lock_lost,
     output reg [10:0] vmax,
     output reg [10:0] vmax_tvp,
     output reg [19:0] pcnt_frame,
     output ilace_flag,
     output vsync_flag,
     input lt_active,
-    input [1:0] lt_mode
+    input [1:0] lt_mode,
+    output reg [10:0] xpos,
+    output reg [10:0] ypos,
+    input pll_areset,
+    input pll_scanclk,
+    input pll_scanclkena,
+    input pll_configupdate,
+    input pll_scandata,
+    output pll_scandone,
+    output pll_activeclock
 );
 
-//clock-related signals
+//clock-related signals and registers
 wire pclk_act;
 wire pclk_1x, pclk_2x, pclk_3x, pclk_4x, pclk_5x;
-wire pclk_2x_lock, pclk_3x_lock;
-wire [2:0] pclk_mux_sel;
+wire [1:0] pclk_mux_sel;
+wire pll_lock;
+reg pll_clkswitch;
 
 //RGB signals&registers: 8 bits per component -> 16.7M colors
 wire [7:0] R_act, G_act, B_act;
 wire [7:0] R_lbuf, G_lbuf, B_lbuf;
-reg [7:0] R_in_L, G_in_L, B_in_L, R_in_LL, G_in_LL, B_in_LL, R_1x, G_1x, B_1x;
+reg [7:0] R_in_L, G_in_L, B_in_L, R_in_LL, G_in_LL, B_in_LL, R_in_LLL, G_in_LLL, B_in_LLL, R_1x, G_1x, B_1x;
 
 //H+V syncs + data enable signals&registers
 wire HSYNC_act, VSYNC_act, DE_act;
@@ -131,9 +146,10 @@ reg FID_cur, FID_last, FID_prev, FID_1x;
 reg frame_change, frame_change_longpulse, line_change;
 
 //H+V counters
-wire [11:0] linebuf_hoffset; //Offset for line (max. 2047 pixels), MSB indicates which line is read/written
+reg [11:0] linebuf_hoffset_pp; //Offset for line (max. 2047 pixels), MSB indicates which line is read/written
+wire [11:0] linebuf_hoffset_act;
 wire [11:0] hcnt_act;
-reg [11:0] hcnt_1x, hcnt_2x, hcnt_3x, hcnt_4x, hcnt_5x, hcnt_4x_aspfix, hcnt_2x_opt, hcnt_3x_opt, hcnt_4x_opt, hcnt_5x_opt, hcnt_5x_hscomp;
+reg [11:0] hcnt_1x, hcnt_2x, hcnt_3x, hcnt_4x, hcnt_5x, hcnt_4x_aspfix, hcnt_2x_opt, hcnt_3x_opt, hcnt_3x_lace_ref, hcnt_4x_opt, hcnt_5x_opt, hcnt_5x_hscomp;
 reg [2:0] hcnt_2x_opt_ctr, hcnt_3x_opt_ctr, hcnt_4x_opt_ctr, hcnt_5x_opt_ctr;
 wire [10:0] vcnt_act;
 reg [10:0] vcnt_tvp, vcnt_1x, vcnt_2x, vcnt_3x, vcnt_4x, vcnt_5x; //max. 2047
@@ -141,10 +157,11 @@ reg [10:0] vcnt_tvp, vcnt_1x, vcnt_2x, vcnt_3x, vcnt_4x, vcnt_5x; //max. 2047
 //other counters
 wire [2:0] line_id_act, col_id_act;
 reg [11:0] hmax[0:1];
+reg [11:0] hmax_3x;
 reg line_idx;
 reg [1:0] line_out_idx_2x, line_out_idx_3x, line_out_idx_4x;
 reg [2:0] line_out_idx_5x;
-reg [23:0] warn_h_unstable, warn_pll_lock_lost, warn_pll_lock_lost_3x;
+reg [23:0] warn_h_unstable, warn_pll_lock_lost;
 
 // post-processing pipeline
 reg HSYNC_pp[1:`PP_PIPELINE_LENGTH] /* synthesis ramstyle = "logic" */;
@@ -173,7 +190,7 @@ reg [2:0] pclk_5x_cnt;
 reg [10:0] H_ACTIVE;    //max. 2047
 reg [9:0] H_AVIDSTART;  //max. 1023
 reg [10:0] V_ACTIVE;    //max. 2047
-reg [6:0] V_AVIDSTART;  //max. 127
+reg [7:0] V_AVIDSTART;  //max. 255
 reg [7:0] H_SYNCLEN;
 reg [2:0] V_SYNCLEN;
 reg [5:0] V_MASK;
@@ -186,8 +203,9 @@ reg [2:0] H_OPT_SAMPLE_MULT;
 reg [2:0] H_OPT_SAMPLE_SEL;
 reg [9:0] H_L5BORDER;
 reg [9:0] H_L3BORDER;
-reg [6:0] H_L3_OPT_SAMPLE_COMP;
+reg [11:0] H_L3_OPT_START;
 reg [3:0] X_MASK_BR;
+reg [2:0] X_MASK_COLOR;
 reg [5:0] X_REV_LPF_STR;
 reg [3:0] SL_L_STR[4:0] /* synthesis ramstyle = "logic" */;
 reg [3:0] SL_C_STR[5:0] /* synthesis ramstyle = "logic" */;
@@ -198,6 +216,7 @@ reg SL_METHOD;
 reg SL_NO_ALTERN;
 reg SL_ALTIV;
 reg X_REV_LPF_ENABLE;
+reg X_PANASONIC_HACK;
 
 // constants for each frame to be calculated off config-registers
 reg CALC_CONSTS;
@@ -209,11 +228,11 @@ reg [7:0] V_AVIDMASK_START;
 reg [10:0] V_AVIDMASK_STOP;
 
 reg [11:0] LT_POS_TOPLEFT_BOX_H_STOP;
-reg [10:0] LT_POS_TOPLEFT_BOX_V_STOP;
+reg [11:0] LT_POS_TOPLEFT_BOX_V_STOP;
 reg [11:0] LT_POS_CENTER_BOX_H_START;
 reg [11:0] LT_POS_CENTER_BOX_H_STOP;
-reg [10:0] LT_POS_CENTER_BOX_V_START;
-reg [10:0] LT_POS_CENTER_BOX_V_STOP;
+reg [11:0] LT_POS_CENTER_BOX_V_START;
+reg [11:0] LT_POS_CENTER_BOX_V_STOP;
 reg [11:0] LT_POS_BOTTOMRIGHT_H_START;
 reg [10:0] LT_POS_BOTTOMRIGHT_V_START;
 
@@ -228,7 +247,6 @@ reg [19:0] pcnt_ctr;
 
 assign pclk_1x = PCLK_in;
 assign PCLK_out = pclk_act;
-assign pclk_lock = {pclk_2x_lock, pclk_3x_lock};
 assign ilace_flag = (FID_cur != FID_last);
 
 //Scanline generation
@@ -357,7 +375,7 @@ case (V_MULTMODE)
         hcnt_act = hcnt_1x;
         vcnt_act = vcnt_1x;
         pclk_mux_sel = `PCLK_MUX_1X;
-        linebuf_hoffset = 0;
+        linebuf_hoffset_act = 0;
         col_id_act = {2'b00, hcnt_1x[0]};
         rlpf_trigger_act = 1'b1;
     end
@@ -374,19 +392,19 @@ case (V_MULTMODE)
         case (H_MULTMODE)
             default: begin //`H_MULTMODE_FULLWIDTH
                 pclk_mux_sel = `PCLK_MUX_2X;
-                linebuf_hoffset = hcnt_2x;
+                linebuf_hoffset_act = hcnt_2x;
                 col_id_act = {2'b00, hcnt_2x[0]};
                 rlpf_trigger_act = 1'b1;
             end
             `H_MULTMODE_OPTIMIZED_1X: begin
                 pclk_mux_sel = `PCLK_MUX_1X;     //special case: pclk bypass to enable 2x native sampling
-                linebuf_hoffset = hcnt_2x_opt;
+                linebuf_hoffset_act = hcnt_2x_opt;
                 col_id_act = {2'b00, hcnt_2x[1]};
                 rlpf_trigger_act = (hcnt_2x_opt_ctr == 0);
             end
             `H_MULTMODE_OPTIMIZED: begin
                 pclk_mux_sel = `PCLK_MUX_2X;
-                linebuf_hoffset = hcnt_2x_opt;
+                linebuf_hoffset_act = hcnt_2x_opt;
                 col_id_act = hcnt_2x_opt_ctr;
                 rlpf_trigger_act = (hcnt_2x_opt_ctr == 0);
              end
@@ -404,21 +422,21 @@ case (V_MULTMODE)
         case (H_MULTMODE)
             default: begin //`H_MULTMODE_FULLWIDTH
                 pclk_mux_sel = `PCLK_MUX_3X;
-                linebuf_hoffset = hcnt_3x;
+                linebuf_hoffset_act = hcnt_3x;
                 hcnt_act = hcnt_3x;
                 col_id_act = {2'b00, hcnt_3x[0]};
                 rlpf_trigger_act = 1'b1;
             end
             `H_MULTMODE_ASPECTFIX: begin
                 pclk_mux_sel = `PCLK_MUX_4X;
-                linebuf_hoffset = hcnt_4x_aspfix;
+                linebuf_hoffset_act = hcnt_4x_aspfix;
                 hcnt_act = hcnt_4x_aspfix;
                 col_id_act = {2'b00, hcnt_4x[0]};
                 rlpf_trigger_act = 1'b1;
             end
             `H_MULTMODE_OPTIMIZED: begin
                 pclk_mux_sel = `PCLK_MUX_3X;
-                linebuf_hoffset = hcnt_3x_opt;
+                linebuf_hoffset_act = hcnt_3x_opt;
                 hcnt_act = hcnt_3x;
                 col_id_act = hcnt_3x_opt_ctr;
                 rlpf_trigger_act = (hcnt_3x_opt_ctr == 0);
@@ -438,12 +456,12 @@ case (V_MULTMODE)
         pclk_mux_sel = `PCLK_MUX_4X;
         case (H_MULTMODE)
             default: begin //`H_MULTMODE_FULLWIDTH
-                linebuf_hoffset = hcnt_4x;
+                linebuf_hoffset_act = hcnt_4x;
                 col_id_act = {2'b00, hcnt_4x[0]};
                 rlpf_trigger_act = 1'b1;
             end
             `H_MULTMODE_OPTIMIZED: begin
-                linebuf_hoffset = hcnt_4x_opt;
+                linebuf_hoffset_act = hcnt_4x_opt;
                 col_id_act = hcnt_4x_opt_ctr;
                 rlpf_trigger_act = (hcnt_4x_opt_ctr == 0);
             end
@@ -462,12 +480,12 @@ case (V_MULTMODE)
         pclk_mux_sel = `PCLK_MUX_5X;
         case (H_MULTMODE)
             default: begin //`H_MULTMODE_FULLWIDTH
-                linebuf_hoffset = hcnt_5x_hscomp;
+                linebuf_hoffset_act = hcnt_5x_hscomp;
                 col_id_act = {2'b00, hcnt_5x[0]};
                 rlpf_trigger_act = 1'b1;
             end
             `H_MULTMODE_OPTIMIZED: begin
-                linebuf_hoffset = hcnt_5x_opt;
+                linebuf_hoffset_act = hcnt_5x_opt;
                 col_id_act = hcnt_5x_opt_ctr;
                 rlpf_trigger_act = (hcnt_5x_opt_ctr == 0);
             end
@@ -475,24 +493,44 @@ case (V_MULTMODE)
     end
 endcase
 
-//TODO: use single PLL and ALTPLL_RECONFIG
-pll_2x pll_linedouble (
-    .areset ( (V_MULTMODE != `V_MULTMODE_2X) & (V_MULTMODE != `V_MULTMODE_5X) ),
-    .inclk0 ( PCLK_in ),
-    .c0 ( pclk_2x ),
-    .c1 ( pclk_5x ),
-    .locked ( pclk_2x_lock )
+pll_2x pll_pclk (
+    .areset(pll_areset),
+    .clkswitch(pll_clkswitch),
+    .configupdate(pll_configupdate),
+    .inclk0(clk27), // set videogen clock to primary (power-on default) since both reference clocks must be running during switchover
+    .inclk1(PCLK_in), // is the secondary input clock fully compensated?
+    .scanclk(pll_scanclk),
+    .scanclkena(pll_scanclkena),
+    .scandata(pll_scandata),
+    .activeclock(pll_activeclock),
+    .c0(pclk_2x), // pclk_3x in secondary config
+    .c1(pclk_5x), // pclk_4x in secondary config
+    .locked(pll_lock),
+    .scandataout(),
+    .scandone(pll_scandone)
 );
 
-pll_3x pll_linetriple (
-    .areset ( (V_MULTMODE != `V_MULTMODE_3X) & (V_MULTMODE != `V_MULTMODE_4X) ),
-    .inclk0 ( PCLK_in ),
-    .c0 ( pclk_3x ),
-    .c1 ( pclk_4x ),
-    .locked ( pclk_3x_lock )
-);
+assign pclk_3x = pclk_2x;
+assign pclk_4x = pclk_5x;
 
-wire [11:0] linebuf_rdaddr = linebuf_hoffset-H_AVIDSTART;
+cycloneive_clkctrl   clkctrl1 ( 
+    .clkselect(enable_sc ? pclk_mux_sel : 2'h2),
+    .ena(1'b1),
+    .inclk({pclk_5x, pclk_2x, 1'b0, pclk_1x}), // fitter forbids using both clk27 and pclk_1x here since they're on opposite sides
+    .outclk(pclk_act)
+// synopsys translate_off
+    ,
+    .devclrn(1'b1),
+    .devpor(1'b1)
+// synopsys translate_on
+);
+defparam
+    clkctrl1.clock_type = "Global Clock",
+    clkctrl1.ena_register_mode = "falling edge",
+    clkctrl1.lpm_type = "cycloneive_clkctrl";
+
+
+wire [11:0] linebuf_rdaddr = linebuf_hoffset_pp-H_AVIDSTART;
 wire [11:0] linebuf_wraddr = hcnt_1x-H_AVIDSTART;
 
 //TODO: add secondary buffers for interlaced signals with alternative field order
@@ -506,15 +544,6 @@ linebuf linebuf_rgb (
     .q ( {R_lbuf, G_lbuf, B_lbuf} )
 );
 
-mux5 mux5_inst (
-    .data0 ( pclk_1x ),
-    .data1 ( pclk_2x ),
-    .data2 ( pclk_3x ),
-    .data3 ( pclk_4x ),
-    .data4 ( pclk_5x ),
-    .sel ( pclk_mux_sel ),
-    .result ( pclk_act )
-);
 
 //Postprocess pipeline
 //
@@ -524,53 +553,55 @@ mux5 mux5_inst (
 // RGB:                             2 cycles
 //
 // Pipeline structure
-// |   1   |   2   |   3   |   4   |   5   |   6   |   7   |   8   |   9   |  10   |  11   |
-// |-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
-// | LBUF  | LBUF  |       |       |       |       |       |       |       |       |       |
-// |       |       | RLPF  | RLPF  | RLPF  |       |       |       |       |       |       |
-// |       |       |       |   Y   |   Y   |       |       |       |       |       |       |
-// |       |       |       |       |       |  SLG  |  SLG  |  SLG  |  SLG  |  SLG  |       |
-// |       |       |       |       |       |       |       |       |       |       | MASK  |
-// |       |       |       |       |       |       |       |       |       |       | LTBOX |
+// |   1   |   2   |   3   |   4   |   5   |   6   |   7   |   8   |   9   |  10   |  11   |  12   |
+// |-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
+// | RADDR |       |       |       |       |       |       |       |       |       |       |       |
+// |       | LBUF  | LBUF  |       |       |       |       |       |       |       |       |       |
+// |       |       |       | RLPF  | RLPF  | RLPF  |       |       |       |       |       |       |
+// |       |       |       |       |   Y   |   Y   |       |       |       |       |       |       |
+// |       |       |       |       |       |       |  SLG  |  SLG  |  SLG  |  SLG  |  SLG  |       |
+// |       |       |       |       |       |       |       |       |       |       |       | MASK  |
+// |       |       |       |       |       |       |       |       |       |       |       | LTBOX |
 integer pp_idx;
 always @(posedge pclk_act)
 begin
-    line_id_pp[1] <= SL_ALTIV ? {2'b00, vcnt_act[0]} : line_id_act;
-    col_id_pp[1] <= col_id_act;
-    for(pp_idx = 2; pp_idx <= `PP_SLGEN_PL_END-5; pp_idx = pp_idx+1) begin
+    line_id_pp[`PP_PL_START] <= SL_ALTIV ? {2'b00, vcnt_act[0]} : line_id_act;
+    col_id_pp[`PP_PL_START] <= col_id_act;
+    for(pp_idx = `PP_PL_START+1; pp_idx <= `PP_SLGEN_PL_END-5; pp_idx = pp_idx+1) begin
         line_id_pp[pp_idx] <= line_id_pp[pp_idx-1];
         col_id_pp[pp_idx] <= col_id_pp[pp_idx-1];
     end
 
     hcnt_pp <= hcnt_act;
     vcnt_pp <= vcnt_act;
-    border_enable_pp[2] <= ((hcnt_pp < H_AVIDMASK_START) | (hcnt_pp >= H_AVIDMASK_STOP) | (vcnt_pp < V_AVIDMASK_START) | (vcnt_pp >= V_AVIDMASK_STOP));
-    for(pp_idx = 3; pp_idx <= `PP_PIPELINE_LENGTH; pp_idx = pp_idx+1) begin
+    linebuf_hoffset_pp <= linebuf_hoffset_act;
+    xpos <= hcnt_pp - H_AVIDSTART;
+    ypos <= vcnt_pp - V_AVIDSTART;
+
+    border_enable_pp[`PP_ENABLES_START] <= ((hcnt_pp < H_AVIDMASK_START) | (hcnt_pp >= H_AVIDMASK_STOP) | (vcnt_pp < V_AVIDMASK_START) | (vcnt_pp >= V_AVIDMASK_STOP));
+    case (lt_mode)
+        default: begin
+            lt_box_enable_pp[`PP_ENABLES_START] <= 0;
+        end
+        `LT_POS_TOPLEFT: begin
+            lt_box_enable_pp[`PP_ENABLES_START] <= ((hcnt_pp < LT_POS_TOPLEFT_BOX_H_STOP) && (vcnt_pp < LT_POS_TOPLEFT_BOX_V_STOP)) ? 1'b1 : 1'b0;
+        end
+        `LT_POS_CENTER: begin
+            lt_box_enable_pp[`PP_ENABLES_START] <= ((hcnt_pp >= LT_POS_CENTER_BOX_H_START) && (hcnt_pp < LT_POS_CENTER_BOX_H_STOP) && (vcnt_pp >= LT_POS_CENTER_BOX_V_START) && (vcnt_pp < LT_POS_CENTER_BOX_V_STOP)) ? 1'b1 : 1'b0;
+        end
+        `LT_POS_BOTTOMRIGHT: begin
+            lt_box_enable_pp[`PP_ENABLES_START] <= ((hcnt_pp >= LT_POS_BOTTOMRIGHT_H_START) && (vcnt_pp >= LT_POS_BOTTOMRIGHT_V_START)) ? 1'b1 : 1'b0;
+        end
+    endcase
+    for(pp_idx = `PP_ENABLES_START+1; pp_idx <= `PP_PIPELINE_LENGTH; pp_idx = pp_idx+1) begin
+        lt_box_enable_pp[pp_idx] <= lt_box_enable_pp[pp_idx-1];
         border_enable_pp[pp_idx] <= border_enable_pp[pp_idx-1];
     end
 
-    case (lt_mode)
-        default: begin
-            lt_box_enable_pp[2] <= 0;
-        end
-        `LT_POS_TOPLEFT: begin
-            lt_box_enable_pp[2] <= ((hcnt_pp < LT_POS_TOPLEFT_BOX_H_STOP) && (vcnt_pp < LT_POS_TOPLEFT_BOX_V_STOP)) ? 1'b1 : 1'b0;
-        end
-        `LT_POS_CENTER: begin
-            lt_box_enable_pp[2] <= ((hcnt_pp >= LT_POS_CENTER_BOX_H_START) && (hcnt_pp < LT_POS_CENTER_BOX_H_STOP) && (vcnt_pp >= LT_POS_CENTER_BOX_V_START) && (vcnt_pp < LT_POS_CENTER_BOX_V_STOP)) ? 1'b1 : 1'b0;
-        end
-        `LT_POS_BOTTOMRIGHT: begin
-            lt_box_enable_pp[2] <= ((hcnt_pp >= LT_POS_BOTTOMRIGHT_H_START) && (vcnt_pp >= LT_POS_BOTTOMRIGHT_V_START)) ? 1'b1 : 1'b0;
-        end
-    endcase
-    for(pp_idx = 3; pp_idx <= `PP_PIPELINE_LENGTH; pp_idx = pp_idx+1) begin
-        lt_box_enable_pp[pp_idx] <= lt_box_enable_pp[pp_idx-1];
-    end
-
-    HSYNC_pp[2] <= HSYNC_act;
-    VSYNC_pp[2] <= VSYNC_act;
-    DE_pp[2] <= DE_act;
-    for(pp_idx = 3; pp_idx <= `PP_PIPELINE_LENGTH; pp_idx = pp_idx+1) begin
+    HSYNC_pp[`PP_HS_VS_DE_START] <= HSYNC_act;
+    VSYNC_pp[`PP_HS_VS_DE_START] <= VSYNC_act;
+    DE_pp[`PP_HS_VS_DE_START] <= DE_act;
+    for(pp_idx = `PP_HS_VS_DE_START+1; pp_idx <= `PP_PIPELINE_LENGTH; pp_idx = pp_idx+1) begin
         HSYNC_pp[pp_idx] <= HSYNC_pp[pp_idx-1];
         VSYNC_pp[pp_idx] <= VSYNC_pp[pp_idx-1];
         DE_pp[pp_idx] <= DE_pp[pp_idx-1];
@@ -580,10 +611,10 @@ begin
     DE_out <= DE_pp[`PP_PIPELINE_LENGTH];
 
     // get RGB and delay it
-    R_pp[3] <= R_act;
-    G_pp[3] <= G_act;
-    B_pp[3] <= B_act;
-    for(pp_idx = 4; pp_idx <= `PP_PIPELINE_LENGTH; pp_idx = pp_idx + 1) begin
+    R_pp[`PP_RGB_START] <= R_act;
+    G_pp[`PP_RGB_START] <= G_act;
+    B_pp[`PP_RGB_START] <= B_act;
+    for(pp_idx = `PP_RGB_START+1; pp_idx <= `PP_PIPELINE_LENGTH; pp_idx = pp_idx + 1) begin
         R_pp[pp_idx] <= R_pp[pp_idx-1];
         G_pp[pp_idx] <= G_pp[pp_idx-1];
         B_pp[pp_idx] <= B_pp[pp_idx-1];
@@ -593,9 +624,9 @@ begin
     B_out <= B_pp[`PP_PIPELINE_LENGTH];
 
     // reverse LPF ...
-    rlpf_trigger_r[1] <= rlpf_trigger_act;
-    for(pp_idx = 2; pp_idx <= `PP_RLPF_PL_START-1; pp_idx = pp_idx + 1)
-        rlpf_trigger_r[`PP_RLPF_PL_START-1] <= rlpf_trigger_r[1];
+    rlpf_trigger_r[`PP_PL_START] <= rlpf_trigger_act;
+    for(pp_idx = `PP_PL_START+1; pp_idx <= `PP_RLPF_PL_START-1; pp_idx = pp_idx + 1)
+        rlpf_trigger_r[pp_idx] <= rlpf_trigger_r[pp_idx-1];
 
     // Optimized modes repeat pixels. Save previous pixel only when linebuffer offset changes.
     if (rlpf_trigger_r[`PP_RLPF_PL_START-1]) begin
@@ -689,9 +720,9 @@ begin
         G_out <= {8{lt_box_enable_pp[`PP_PIPELINE_LENGTH]}};
         B_out <= {8{lt_box_enable_pp[`PP_PIPELINE_LENGTH]}};
     end else if (border_enable_pp[`PP_PIPELINE_LENGTH]) begin
-        R_out <= {2{X_MASK_BR}};
-        G_out <= {2{X_MASK_BR}};
-        B_out <= {2{X_MASK_BR}};
+        R_out <= X_MASK_COLOR[2] ? {2{X_MASK_BR}} : 8'h00;
+        G_out <= X_MASK_COLOR[1] ? {2{X_MASK_BR}} : 8'h00;
+        B_out <= X_MASK_COLOR[0] ? {2{X_MASK_BR}} : 8'h00;
     end
 end
 
@@ -701,31 +732,25 @@ begin
     if (!reset_n) begin
         warn_h_unstable <= 1'b0;
         warn_pll_lock_lost <= 1'b0;
-        warn_pll_lock_lost_3x <= 1'b0;
     end else begin
         if (hmax[0] != hmax[1])
             warn_h_unstable <= 1;
         else if (warn_h_unstable != 0)
             warn_h_unstable <= warn_h_unstable + 1'b1;
     
-        if (((V_MULTMODE == `V_MULTMODE_2X) | (V_MULTMODE == `V_MULTMODE_5X)) & ~pclk_2x_lock)
+        if ((V_MULTMODE > `V_MULTMODE_1X) & ~pll_lock)
             warn_pll_lock_lost <= 1;
         else if (warn_pll_lock_lost != 0)
             warn_pll_lock_lost <= warn_pll_lock_lost + 1'b1;
-            
-        if (((V_MULTMODE == `V_MULTMODE_3X) | (V_MULTMODE == `V_MULTMODE_4X)) & ~pclk_3x_lock)
-            warn_pll_lock_lost_3x <= 1;
-        else if (warn_pll_lock_lost_3x != 0)
-            warn_pll_lock_lost_3x <= warn_pll_lock_lost_3x + 1'b1;
     end
 end
 
 assign h_unstable = (warn_h_unstable != 0);
-assign pll_lock_lost = {(warn_pll_lock_lost != 0), (warn_pll_lock_lost_3x != 0)};
+assign pll_lock_lost = (warn_pll_lock_lost != 0);
 
 //Detect if TVP7002 is skipping VSYNCs. This occurs for interlaced signals fed via digital sync inputs,
-//causing TVP7002 not to regenerate VSYNC for field 1. Moreover, if leading edges of HSYNC and VSYNC are
-//too far from each other for field 0, no VSYNC is regenerated at all. This can be avoided by disabling
+//causing TVP7002 not to regenerate VSYNC for even field. Moreover, if leading edges of HSYNC and VSYNC are
+//too far from each other for odd field, no VSYNC is regenerated at all. This can be avoided by disabling
 //doubled sampling rates ("AV3 interlacefix") and/or minimizing VSYNC delay induced by RC filter on PCB.
 //However, TVP7002 datasheet warns that HSYNC/VSYNC should not change simultaneously, so leaving out the
 //filter may lead to stability issues and is not recommended. A combination of 220ohm resistor and 1nF
@@ -786,6 +811,12 @@ begin
     end
 end
 
+// Control PLL reference clock switchover
+always @(posedge clk27)
+begin
+    pll_clkswitch <= (pll_activeclock != enable_sc);
+end
+
 //Forward status flag to CPU
 assign vsync_flag = ~VSYNC_in_cc_LL;
 
@@ -825,8 +856,8 @@ begin
         end
 
         if (`HSYNC_LEADING_EDGE) begin
-            if (`VSYNC_LEADING_EDGE) begin // non-interlace frame or even field (interlace) start
-                FID_cur <= 1'b0;
+            if (`VSYNC_LEADING_EDGE) begin // non-interlace frame or odd field (interlace) start
+                FID_cur <= `FID_ODD;
                 FID_last <= FID_cur;
                 vcnt_1x <= 0;
                 frame_change <= 1'b1;
@@ -837,9 +868,9 @@ begin
                 vcnt_1x <= vcnt_1x + 1'b1;
                 vcnt_tvp <= vcnt_tvp + 1'b1;
             end
-        end else if (`VSYNC_LEADING_EDGE) begin // odd field (interlace) start
+        end else if (`VSYNC_LEADING_EDGE) begin // even field (interlace) start
             if (!`FALSE_FIELD) begin
-                FID_cur <= 1'b1;
+                FID_cur <= `FID_EVEN;
                 FID_last <= FID_cur;
                 vcnt_1x <= 11'h7ff; // -1 for 11 bit word
                 frame_change <= 1'b1;
@@ -848,7 +879,7 @@ begin
             vcnt_tvp <= 0;
             vmax_tvp <= vcnt_tvp;
         end else if ((fpga_vsyncgen[`VSYNCGEN_GENMID_BIT]) && (vcnt_tvp == (vmax_tvp>>1)) && (hcnt_1x == (hmax[~line_idx]>>1))) begin //VSM=1
-            FID_cur <= 1'b1;
+            FID_cur <= `FID_EVEN;
             FID_last <= FID_cur;
             vcnt_1x <= 11'h7ff; // -1 for 11 bit word
             frame_change <= 1'b1;
@@ -858,11 +889,11 @@ begin
 
         if (`VSYNC_LEADING_EDGE) begin
             FID_prev <= FID_in;
-            // detect non-interlaced signal with odd-odd field signaling (TVP7002 detects it as interlaced with analog sync inputs).
+            // detect non-interlaced signal with consecutive even field signaling (TVP7002 detects it as interlaced with analog sync inputs).
             // FID is updated at leading edge of VSYNC
             if (FID_in == FID_prev)
                 fpga_vsyncgen[`VSYNCGEN_CHOPMID_BIT] <= `FALSE;
-            else if (FID_in == `FID_ODD)   // TVP7002 falsely indicates field change with (vcnt < active_lines)
+            else if (FID_in == `FID_EVEN)   // TVP7002 falsely indicates field change with (vcnt < active_lines)
                 fpga_vsyncgen[`VSYNCGEN_CHOPMID_BIT] <= (vcnt_tvp < `MIN_VALID_LINES);
         end
 
@@ -875,27 +906,29 @@ begin
             H_AVIDSTART <= h_config[19:11] + h_config[27:20];   // Horizontal sync+backporch length (0...1023)
             H_ACTIVE <= h_config[10:0];                       // Horizontal active length (0...2047)
 
-            V_SYNCLEN <= v_config[19:17];                     // Vertical sync length (0...7)
-            V_AVIDSTART <= v_config[16:11] + v_config[19:17];   // Vertical sync+backporch length (0...127)
+            V_SYNCLEN <= v_config[21:19];                     // Vertical sync length (0...7)
+            V_AVIDSTART <= v_config[18:11] + v_config[21:19];   // Vertical sync+backporch length (0...255)
             V_ACTIVE <= v_config[10:0];                       // Vertical active length (0...2047)
 
             H_MASK <= h_config2[29:19];
-            V_MASK <= v_config[25:20];
+            V_MASK <= v_config[27:22];
 
 //            H_L5BORDER <= h_config[29] ? (11'd1920-h_config[10:0])/2 : (11'd1600-h_config[10:0])/2;
             H_L5BORDER <= h_config[29] ? H_L5BORDER_1920_tmp[10:1] : H_L5BORDER_1600_tmp[10:1];
             // For Line3x 240x360
             H_L3BORDER <= h_config[28] ? H_L5BORDER_1920_tmp[10:1] : 10'd0;
 
-            H_L3_OPT_SAMPLE_COMP <= h_config[28] ? 7'd90 : 7'd0;
+            H_L3_OPT_START <= h_config2[15:13] + (h_config[28] ? 7'd90 : 7'd0);
 
             H_OPT_SCALE <= h_config2[18:16];
             H_OPT_SAMPLE_SEL <= h_config2[15:13];
             H_OPT_SAMPLE_MULT <= h_config2[12:10];
             H_OPT_STARTOFF <= h_config2[9:0];
 
-            X_REV_LPF_ENABLE <= (misc_config[8:4] != 5'b00000);
-            X_REV_LPF_STR <= (misc_config[8:4] + 6'd16);
+            X_PANASONIC_HACK <= misc_config[12];
+            X_REV_LPF_ENABLE <= (misc_config[11:7] != 5'b00000);
+            X_REV_LPF_STR <= (misc_config[11:7] + 6'd16);
+            X_MASK_COLOR <= misc_config[6:4];
             X_MASK_BR <= misc_config[3:0];
 
             SL_NO_ALTERN <= sl_config[31];
@@ -952,16 +985,19 @@ begin
         HSYNC_in_L <= HSYNC_in;
         VSYNC_in_L <= VSYNC_in;
 
-        // Add one delay stage to match linebuf delay
+        // Add two delay stages to match linebuf delay
         R_in_LL <= R_in_L;
         G_in_LL <= G_in_L;
         B_in_LL <= B_in_L;
+        R_in_LLL <= R_in_LL;
+        G_in_LLL <= G_in_LL;
+        B_in_LLL <= B_in_LL;
 
-        R_1x <= R_in_LL;
-        G_1x <= G_in_LL;
-        B_1x <= B_in_LL;
+        R_1x <= R_in_LLL;
+        G_1x <= G_in_LLL;
+        B_1x <= B_in_LLL;
         HSYNC_1x <= (hcnt_1x < H_SYNCLEN) ? `HSYNC_POL : ~`HSYNC_POL;
-        if (FID_cur == `FID_EVEN)
+        if (FID_cur == `FID_ODD)
             VSYNC_1x <= (vcnt_1x < V_SYNCLEN) ? `VSYNC_POL : ~`VSYNC_POL;
         else
             VSYNC_1x <= (((vcnt_1x+1'b1) < V_SYNCLEN) | ((vcnt_1x+1'b1 == V_SYNCLEN) & (hcnt_1x <= (hmax[~line_idx]>>1)))) ? `VSYNC_POL : ~`VSYNC_POL;
@@ -985,14 +1021,14 @@ begin
             line_out_idx_2x <= 0;
             if (frame_change)
                 vcnt_2x <= 11'h7ff; // -1 for 11 bit word
-            else if (line_change & (FID_cur == `FID_EVEN))
+            else if (line_change & (FID_cur == `FID_ODD))
                 vcnt_2x <= vcnt_2x + 1'b1;
         end else if (hcnt_2x == hmax[~line_idx]) begin
             hcnt_2x <= 0;
             line_out_idx_2x <= line_out_idx_2x + 1'b1;
             hcnt_2x_opt <= H_OPT_SAMPLE_SEL;
             hcnt_2x_opt_ctr <= 0;
-            if (FID_cur == `FID_ODD)
+            if (FID_cur == `FID_EVEN)
                 vcnt_2x <= vcnt_2x + 1'b1;
         end else begin
             hcnt_2x <= hcnt_2x + 1'b1;
@@ -1007,7 +1043,7 @@ begin
 
         HSYNC_2x <= (hcnt_2x < H_SYNCLEN) ? `HSYNC_POL : ~`HSYNC_POL;
         VSYNC_2x <= (vcnt_2x < V_SYNCLEN) ? `VSYNC_POL : ~`VSYNC_POL;
-        DE_2x <= ((hcnt_2x >= H_AVIDSTART) & (hcnt_2x < H_AVIDSTOP)) & ((vcnt_2x >= V_AVIDSTART) & (vcnt_2x < V_AVIDSTOP));
+        DE_2x <= ((hcnt_2x >= H_AVIDSTART) & (hcnt_2x < ((X_PANASONIC_HACK & (vcnt_2x == V_AVIDSTOP-1'b1) & (line_out_idx_2x==2'h1)) ? (H_AVIDSTOP-12'd98) : H_AVIDSTOP))) & ((vcnt_2x >= V_AVIDSTART) & (vcnt_2x < V_AVIDSTOP));
     end
 end
 
@@ -1019,9 +1055,9 @@ begin
         line_out_idx_3x <= 0;
     end else begin
         if ((pclk_3x_cnt == 0) & (line_change | frame_change)) begin  //aligned with posedge of pclk_1x
-            if (!(frame_change & (FID_cur == `FID_ODD))) begin
+            if (!(frame_change & (FID_cur == `FID_EVEN))) begin
                 hcnt_3x <= 0;
-                hcnt_3x_opt <= H_OPT_SAMPLE_SEL + H_L3_OPT_SAMPLE_COMP;
+                hcnt_3x_opt <= H_L3_OPT_START;
                 hcnt_3x_opt_ctr <= 0;
                 line_out_idx_3x <= 0;
             end
@@ -1029,10 +1065,10 @@ begin
                 vcnt_3x <= -11'b1-FID_cur;
             else if (line_change)
                 vcnt_3x <= vcnt_3x + 1'b1;
-        end else if (hcnt_3x == hmax[~line_idx]) begin
+        end else if (hcnt_3x == hmax_3x) begin
             hcnt_3x <= 0;
             line_out_idx_3x <= line_out_idx_3x + 1'b1;
-            hcnt_3x_opt <= H_OPT_SAMPLE_SEL + H_L3_OPT_SAMPLE_COMP;
+            hcnt_3x_opt <= H_L3_OPT_START;
             hcnt_3x_opt_ctr <= 0;
         end else begin
             hcnt_3x <= hcnt_3x + 1'b1;
@@ -1052,14 +1088,16 @@ begin
             pclk_3x_cnt <= pclk_3x_cnt + 1'b1;
 
         pclk_1x_prev3x <= pclk_1x;
+        hmax_3x <= hmax[~line_idx];
+        hcnt_3x_lace_ref <= (hmax_3x>>1)+1'b1;
 
         HSYNC_3x <= (hcnt_3x < H_SYNCLEN) ? `HSYNC_POL : ~`HSYNC_POL;
-        if (FID_cur == `FID_EVEN)
+        if (FID_cur == `FID_ODD)
             VSYNC_3x <= (vcnt_3x < V_SYNCLEN) ? `VSYNC_POL : ~`VSYNC_POL;
         else begin
-            if ((vcnt_3x+1'b1 == 11'd0) & (line_out_idx_3x == 1) & (hcnt_3x == (hmax[~line_idx]>>1)+1'b1))
+            if ((vcnt_3x+1'b1 == 11'd0) & (line_out_idx_3x == 1) & (hcnt_3x == hcnt_3x_lace_ref))
                 VSYNC_3x <= `VSYNC_POL;
-            else if ((vcnt_3x+1'b1 == V_SYNCLEN) & (line_out_idx_3x == 1) & (hcnt_3x == (hmax[~line_idx]>>1)+1'b1))
+            else if ((vcnt_3x+1'b1 == V_SYNCLEN) & (line_out_idx_3x == 1) & (hcnt_3x == hcnt_3x_lace_ref))
                 VSYNC_3x <= ~`VSYNC_POL;
         end
         
@@ -1090,14 +1128,14 @@ begin
             line_out_idx_4x <= 0;
             if (frame_change)
                 vcnt_4x <= 11'h7ff; // -1 for 11 bit word
-            else if (line_change & (FID_cur == `FID_EVEN))
+            else if (line_change & (FID_cur == `FID_ODD))
                 vcnt_4x <= vcnt_4x + 1'b1;
         end else if (hcnt_4x == hmax[~line_idx]) begin
             hcnt_4x <= 0;
             line_out_idx_4x <= line_out_idx_4x + 1'b1;
             hcnt_4x_opt <= H_OPT_SAMPLE_SEL;
             hcnt_4x_opt_ctr <= 0;
-            if ((FID_cur == `FID_ODD) && (line_out_idx_4x == 1))
+            if ((FID_cur == `FID_EVEN) && (line_out_idx_4x == 1))
                 vcnt_4x <= vcnt_4x + 1'b1;
         end else begin
             hcnt_4x <= hcnt_4x + 1'b1;

rtl/videogen.v

@@ -24,13 +24,14 @@ module videogen (
     input reset_n,
     input lt_active,
     input [1:0] lt_mode,
-    output [7:0] R_out,
-    output [7:0] G_out,
-    output [7:0] B_out,
+    output reg [7:0] R_out,
+    output reg [7:0] G_out,
+    output reg [7:0] B_out,
     output reg HSYNC_out,
     output reg VSYNC_out,
-    output PCLK_out,
-    output reg ENABLE_out
+    output reg DE_out,
+    output reg [9:0] xpos,
+    output reg [9:0] ypos
 );
 
 //Parameters for 720x480@59.94Hz (858px x 525lines, pclk 27MHz -> 59.94Hz)
@@ -63,31 +64,23 @@ parameter   Y_START     =   V_SYNCLEN + V_BACKPORCH;
 reg [9:0] h_cnt; //max. 1024
 reg [9:0] v_cnt; //max. 1024
 
-reg [9:0] xpos;
-reg [9:0] ypos;
-
-assign PCLK_out = clk27;
-
-//R, G and B should be 0 outside of active area
-assign R_out = ENABLE_out ? V_gen : 8'h00;
-assign G_out = ENABLE_out ? V_gen : 8'h00;
-assign B_out = ENABLE_out ? V_gen : 8'h00;
-
-reg [7:0] V_gen;
-
-
 //HSYNC gen (negative polarity)
 always @(posedge clk27 or negedge reset_n)
 begin
     if (!reset_n) begin
         h_cnt <= 0;
+        xpos <= 0;
         HSYNC_out <= 0;
     end else begin
         //Hsync counter
-        if (h_cnt < H_TOTAL-1)
+        if (h_cnt < H_TOTAL-1) begin
             h_cnt <= h_cnt + 1'b1;
-        else
+            if (h_cnt >= X_START)
+                xpos <= xpos + 1'b1;
+        end else begin
             h_cnt <= 0;
+            xpos <= 0;
+        end
 
         //Hsync signal
         HSYNC_out <= (h_cnt < H_SYNCLEN) ? 1'b0 : 1'b1;
@@ -99,14 +92,19 @@ always @(posedge clk27 or negedge reset_n)
 begin
     if (!reset_n) begin
         v_cnt <= 0;
+        ypos <= 0;
         VSYNC_out <= 0;
     end else begin
         //Vsync counter
         if (h_cnt == H_TOTAL-1) begin
-            if (v_cnt < V_TOTAL-1)
+            if (v_cnt < V_TOTAL-1) begin
                 v_cnt <= v_cnt + 1'b1;
-            else
+                if (v_cnt >= Y_START)
+                    ypos <= ypos + 1'b1;
+            end else begin
                 v_cnt <= 0;
+                ypos <= 0;
+            end
         end
 
         //Vsync signal
@@ -118,36 +116,38 @@ end
 always @(posedge clk27 or negedge reset_n)
 begin
     if (!reset_n) begin
-        V_gen <= 8'h00;
-        ENABLE_out <= 1'b0;
+        R_out <= 8'h00;
+        G_out <= 8'h00;
+        B_out <= 8'h00;
+        DE_out <= 1'b0;
     end else begin
         if (lt_active) begin
             case (lt_mode)
                 default: begin
-                    V_gen <= 8'h00;
+                    {R_out, G_out, B_out} <= {3{8'h00}};
                 end
                 `LT_POS_TOPLEFT: begin
-                    V_gen <= ((h_cnt < (X_START+(H_ACTIVE/`LT_WIDTH_DIV))) && (v_cnt < (Y_START+(V_ACTIVE/`LT_HEIGHT_DIV)))) ? 8'hff : 8'h00;
+                    {R_out, G_out, B_out} <= {3{((xpos < (H_ACTIVE/`LT_WIDTH_DIV)) && (ypos < (V_ACTIVE/`LT_HEIGHT_DIV))) ? 8'hff : 8'h00}};
                 end
                 `LT_POS_CENTER: begin
-                    V_gen <= ((h_cnt >= (X_START+(H_ACTIVE/2)-(H_ACTIVE/(`LT_WIDTH_DIV*2)))) && (h_cnt < (X_START+(H_ACTIVE/2)+(H_ACTIVE/(`LT_WIDTH_DIV*2)))) && (v_cnt >= (Y_START+(V_ACTIVE/2)-(V_ACTIVE/(`LT_HEIGHT_DIV*2)))) && (v_cnt < (Y_START+(V_ACTIVE/2)+(V_ACTIVE/(`LT_HEIGHT_DIV*2))))) ? 8'hff : 8'h00;
+                    {R_out, G_out, B_out} <= {3{((xpos >= ((H_ACTIVE/2)-(H_ACTIVE/(`LT_WIDTH_DIV*2)))) && (xpos < ((H_ACTIVE/2)+(H_ACTIVE/(`LT_WIDTH_DIV*2)))) && (ypos >= ((V_ACTIVE/2)-(V_ACTIVE/(`LT_HEIGHT_DIV*2)))) && (ypos < ((V_ACTIVE/2)+(V_ACTIVE/(`LT_HEIGHT_DIV*2))))) ? 8'hff : 8'h00}};
                 end
                 `LT_POS_BOTTOMRIGHT: begin
-                    V_gen <= ((h_cnt >= (X_START+H_ACTIVE-(H_ACTIVE/`LT_WIDTH_DIV))) && (v_cnt >= (Y_START+V_ACTIVE-(V_ACTIVE/`LT_HEIGHT_DIV)))) ? 8'hff : 8'h00;
+                    {R_out, G_out, B_out} <= {3{((xpos >= (H_ACTIVE-(H_ACTIVE/`LT_WIDTH_DIV))) && (ypos >= (V_ACTIVE-(V_ACTIVE/`LT_HEIGHT_DIV)))) ? 8'hff : 8'h00}};
                 end
             endcase
         end else begin
-            if ((h_cnt < X_START+H_OVERSCAN) || (h_cnt >= X_START+H_OVERSCAN+H_AREA) || (v_cnt < Y_START+V_OVERSCAN) || (v_cnt >= Y_START+V_OVERSCAN+V_AREA))
-                V_gen <= (h_cnt[0] ^ v_cnt[0]) ? 8'hff : 8'h00;
-            else if ((h_cnt < X_START+H_OVERSCAN+H_BORDER) || (h_cnt >= X_START+H_OVERSCAN+H_AREA-H_BORDER) || (v_cnt < Y_START+V_OVERSCAN+V_BORDER) || (v_cnt >= Y_START+V_OVERSCAN+V_AREA-V_BORDER))
-                V_gen <= 8'h50;
-            else if (v_cnt >= Y_START+V_OVERSCAN+V_BORDER+V_GRADIENT-V_GRAYRAMP)
-                V_gen <= (((h_cnt - (X_START+H_OVERSCAN+H_BORDER)) >> 4) << 3) + (h_cnt - (X_START+H_OVERSCAN+H_BORDER) >> 6);
+            if ((xpos < H_OVERSCAN) || (xpos >= H_OVERSCAN+H_AREA) || (ypos < V_OVERSCAN) || (ypos >= V_OVERSCAN+V_AREA))
+                {R_out, G_out, B_out} <= {3{(xpos[0] ^ ypos[0]) ? 8'hff : 8'h00}};
+            else if ((xpos < H_OVERSCAN+H_BORDER) || (xpos >= H_OVERSCAN+H_AREA-H_BORDER) || (ypos < V_OVERSCAN+V_BORDER) || (ypos >= V_OVERSCAN+V_AREA-V_BORDER))
+                {R_out, G_out, B_out} <= {3{8'h50}};
+            else if (ypos >= V_OVERSCAN+V_BORDER+V_GRADIENT-V_GRAYRAMP)
+                {R_out, G_out, B_out} <= {3{8'((((xpos - (H_OVERSCAN+H_BORDER)) >> 4) << 3) + (xpos - (H_OVERSCAN+H_BORDER) >> 6))}};
             else
-                V_gen <= (h_cnt - (X_START+H_OVERSCAN+H_BORDER)) >> 1;
+                {R_out, G_out, B_out} <= {3{8'((xpos - (H_OVERSCAN+H_BORDER)) >> 1)}};
         end
 
-        ENABLE_out <= (h_cnt >= X_START && h_cnt < X_START + H_ACTIVE && v_cnt >= Y_START && v_cnt < Y_START + V_ACTIVE);
+        DE_out <= (h_cnt >= X_START && h_cnt < X_START + H_ACTIVE && v_cnt >= Y_START && v_cnt < Y_START + V_ACTIVE);
     end
 end
 

scripts/reprogram.sh

@@ -0,0 +1,7 @@
+#!/bin/sh
+
+make rv-reprogram
+
+if [ $# -eq 1 ] && [ $1 = "jtag_uart" ] && [ $(pgrep -c nios2-terminal) = 0 ]; then
+    nios2-terminal
+fi

software/ossc_sw.project

@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<CodeLite_Project Name="ossc_sw" InternalType="" Version="10.0.0">
+<CodeLite_Project Name="ossc_sw" InternalType="" Version="11000">
   <Plugins>
     <Plugin Name="qmake">
       <![CDATA[00020001N0005Debug0000000000000001N0007Release000000000000]]>
@@ -31,9 +31,9 @@
     <Excludepaths/>
     <Ignorefiles/>
     <Extensions>
-      <![CDATA[cpp;c;h;hpp;xrc;wxcp;fbp]]>
+      <![CDATA[*.cpp;*.c;*.h;*.hpp;*.xrc;*.wxcp;*.fbp]]>
     </Extensions>
-    <Topleveldir>../software</Topleveldir>
+    <Topleveldir>/home/markus/Code/ossc/software</Topleveldir>
   </Reconciliation>
   <VirtualDirectory Name="sys_controller">
     <VirtualDirectory Name="ths7353">
@@ -74,6 +74,8 @@
       <File Name="sys_controller/memory/sdcard.c"/>
     </VirtualDirectory>
     <VirtualDirectory Name="ossc">
+      <File Name="sys_controller/ossc/utils.h"/>
+      <File Name="sys_controller/ossc/utils.c"/>
       <File Name="sys_controller/ossc/menu.c"/>
       <File Name="sys_controller/ossc/menu.h"/>
       <File Name="sys_controller/ossc/sysconfig.h"/>
@@ -121,7 +123,7 @@
       </Compiler>
       <Linker Options="" Required="yes"/>
       <ResourceCompiler Options="" Required="no"/>
-      <General OutputFile="" IntermediateDirectory="./Debug" Command="make rv-reprogram &amp;&amp; nios2-terminal" CommandArguments="" UseSeparateDebugArgs="no" DebugArguments="" WorkingDirectory="$(ProjectPath)/sys_controller" PauseExecWhenProcTerminates="yes" IsGUIProgram="no" IsEnabled="yes"/>
+      <General OutputFile="" IntermediateDirectory="./Debug" Command="../../scripts/reprogram.sh" CommandArguments="jtag_uart" UseSeparateDebugArgs="no" DebugArguments="" WorkingDirectory="$(ProjectPath)/sys_controller" PauseExecWhenProcTerminates="no" IsGUIProgram="no" IsEnabled="yes"/>
       <BuildSystem Name="Default"/>
       <Environment EnvVarSetName="&lt;Use Defaults&gt;" DbgSetName="&lt;Use Defaults&gt;">
         <![CDATA[]]>
@@ -139,7 +141,7 @@
         <Target Name="Ack BSP update">cd ../sys_controller_bsp &amp;&amp; touch bsp_timestamp</Target>
         <RebuildCommand/>
         <CleanCommand>make clean</CleanCommand>
-        <BuildCommand>make APP_CFLAGS_DEBUG_LEVEL="-DDEBUG"</BuildCommand>
+        <BuildCommand>make ENABLE_AUDIO=y APP_CFLAGS_DEBUG_LEVEL="-DDEBUG" generate_hex</BuildCommand>
         <PreprocessFileCommand/>
         <SingleFileCommand/>
         <MakefileGenerationCommand/>
@@ -163,7 +165,7 @@
       </Compiler>
       <Linker Options="-O2" Required="yes"/>
       <ResourceCompiler Options="" Required="no"/>
-      <General OutputFile="" IntermediateDirectory="./Release" Command="make rv-reprogram" CommandArguments="" UseSeparateDebugArgs="no" DebugArguments="" WorkingDirectory="$(ProjectPath)/sys_controller" PauseExecWhenProcTerminates="no" IsGUIProgram="no" IsEnabled="yes"/>
+      <General OutputFile="" IntermediateDirectory="./Release" Command="../../scripts/reprogram.sh" CommandArguments="" UseSeparateDebugArgs="no" DebugArguments="" WorkingDirectory="$(ProjectPath)/sys_controller" PauseExecWhenProcTerminates="no" IsGUIProgram="no" IsEnabled="yes"/>
       <BuildSystem Name="Default"/>
       <Environment EnvVarSetName="&lt;Use Defaults&gt;" DbgSetName="&lt;Use Defaults&gt;">
         <![CDATA[]]>
@@ -185,7 +187,7 @@
         <Target Name="Ack BSP update">cd ../sys_controller_bsp &amp;&amp; touch bsp_timestamp</Target>
         <RebuildCommand/>
         <CleanCommand>make clean</CleanCommand>
-        <BuildCommand>make</BuildCommand>
+        <BuildCommand>make ENABLE_AUDIO=y generate_hex</BuildCommand>
         <PreprocessFileCommand/>
         <SingleFileCommand/>
         <MakefileGenerationCommand/>

software/sys_controller/Makefile

@@ -159,12 +159,17 @@ C_SRCS += ossc/av_controller.c
 C_SRCS += ossc/avconfig.c
 C_SRCS += ossc/controls.c
 C_SRCS += ossc/firmware.c
+C_SRCS += ossc/fat16_export.c
 ifeq ($(OSDLANG),JP)
 C_SRCS += ossc/menu_sjis.c
 else
 C_SRCS += ossc/menu.c
 endif
+ifeq ($(OSDLANG),JP)
+C_SRCS += ossc/userdata_sjis.c
+else
 C_SRCS += ossc/userdata.c
+endif
 C_SRCS += ossc/utils.c
 C_SRCS += ulibSD/sd_io.c
 C_SRCS += ulibSD/spi_io.c
@@ -196,7 +201,7 @@ APP_CFLAGS_UNDEFINED_SYMBOLS :=
 APP_CFLAGS_OPTIMIZATION := -Os
 APP_CFLAGS_DEBUG_LEVEL :=
 APP_CFLAGS_WARNINGS := -Wall -Wno-unused-but-set-variable -Wno-unused-variable -Wno-unused-function -Wno-packed-bitfield-compat
-APP_CFLAGS_USER_FLAGS := -fdata-sections -ffunction-sections -fshort-enums -fgnu89-inline
+APP_CFLAGS_USER_FLAGS := -fdata-sections -ffunction-sections -fshort-enums -fgnu89-inline -flto
 
 APP_ASFLAGS_USER :=
 APP_LDFLAGS_USER := -Wl,--gc-sections
@@ -970,7 +975,7 @@ clean : clean_elf_derived_files
 endif
 
 clean :
-	@$(RM) -r $(ELF) $(OBJDUMP_NAME) $(LINKER_MAP_NAME) $(OBJ_ROOT_DIR) $(RUNTIME_ROOT_DIR) $(FORCE_REBUILD_DEP_LIST) ossc/menu_sjis.c
+	@$(RM) -r $(ELF) $(OBJDUMP_NAME) $(LINKER_MAP_NAME) $(OBJ_ROOT_DIR) $(RUNTIME_ROOT_DIR) $(FORCE_REBUILD_DEP_LIST) ossc/menu_sjis.c ossc/userdata_sjis.c
 	@$(ECHO) [$(APP_NAME) clean complete]
 
 # Clean just the BSP.
@@ -1130,9 +1135,12 @@ print-elf-name:
 ossc/menu_sjis.c: ossc/menu.c
 	iconv -f UTF-8 -t SHIFT-JIS ossc/menu.c > ossc/menu_sjis.c
 
+ossc/userdata_sjis.c: ossc/userdata.c
+	iconv -f UTF-8 -t SHIFT-JIS ossc/userdata.c > ossc/userdata_sjis.c
+
 mem_init/sys_onchip_memory2_0.hex: sys_controller.elf
 	$(RV_OBJCOPY) --change-addresses -0x10000 -O binary --gap-fill 0 $< mem_init/sys_onchip_memory2_0.bin
-	../../tools/bin2hex mem_init/sys_onchip_memory2_0.bin mem_init/sys_onchip_memory2_0.hex
+	../../tools/bin2hex 4 mem_init/sys_onchip_memory2_0.bin mem_init/sys_onchip_memory2_0.hex
 
 .PHONY: mem_init_generate_new
 mem_init_generate_new: mem_init/sys_onchip_memory2_0.hex

software/sys_controller/it6613/HDMI_TX.c

@@ -326,12 +326,16 @@ void HDMITX_SetAudioInfoFrame(BYTE bAudioDwSampling)
     }
 
     AudioInfo.info.AudioChannelCount = 1; // 2 channels
-    AudioInfo.info.AudioCodingType = 1; // PCM
-    AudioInfo.info.SampleSize = 3; // 24bit
-    AudioInfo.info.SampleFreq = bAudioDwSampling ? 3 : 5; //48kHz or 96kHz
-    AudioInfo.info.SpeakerPlacement = 0; // Front left and front right
-    AudioInfo.info.LevelShiftValue = 0;
-    AudioInfo.info.DM_INH = 0; // Down-mix Inhibit Flag; 0=Permitted or no information about any assertion of this
+
+    // HDMI requires that CT, SS and SF fields are set to 0
+    //AudioInfo.info.AudioCodingType = 1; // PCM
+    //AudioInfo.info.SampleSize = 3; // 24bit
+    //AudioInfo.info.SampleFreq = bAudioDwSampling ? 3 : 5; //48kHz or 96kHz
+
+    // default value assignments omitted
+    //AudioInfo.info.SpeakerPlacement = 0; // Front left and front right
+    //AudioInfo.info.LevelShiftValue = 0;
+    //AudioInfo.info.DM_INH = 0; // Down-mix Inhibit Flag; 0=Permitted or no information about any assertion of this
 
     EnableAudioInfoFrame(TRUE, (BYTE *) &AudioInfo);
 }

software/sys_controller/it6613/it6613_sys.c

@@ -220,7 +220,7 @@ HDMITX_ChangeDisplayOption(HDMI_Video_Type OutputVideoTiming, HDMI_OutputColorMo
         aspec = HDMI_16x9 ;
         Colorimetry = HDMI_ITU709 ;
         break ;
-    case HDMI_1080p24:
+/*    case HDMI_1080p24:
         VIC = 32 ;
         VideoPixelClock = 74250000 ;
         pixelrep = 0 ;
@@ -247,7 +247,7 @@ HDMITX_ChangeDisplayOption(HDMI_Video_Type OutputVideoTiming, HDMI_OutputColorMo
         pixelrep = 0 ;
         aspec = HDMI_16x9 ;
         Colorimetry = HDMI_ITU601 ;
-        break ;
+        break ;*/
         
         
     default:

software/sys_controller/it6613/it6613_sys.h

@@ -5,7 +5,7 @@
 ////////////////////////////////////////////////////////////////////////////////
 
 typedef enum tagHDMI_Video_Type {
-    HDMI_Unkown = 0 ,
+    HDMI_Unknown = 0 ,
     HDMI_640x480p60 = 1 ,
     HDMI_480p60,
     HDMI_480p60_16x9,
@@ -13,6 +13,7 @@ typedef enum tagHDMI_Video_Type {
     HDMI_1080i60,
     HDMI_480i60,
     HDMI_480i60_16x9,
+    HDMI_240p60,
     HDMI_1080p60 = 16,
     HDMI_576p50,
     HDMI_576p50_16x9,
@@ -20,11 +21,12 @@ typedef enum tagHDMI_Video_Type {
     HDMI_1080i50,
     HDMI_576i50,
     HDMI_576i50_16x9,
+    HDMI_288p50,
     HDMI_1080p50 = 31,
-    HDMI_1080p24,
+    /*HDMI_1080p24,
     HDMI_1080p25,
     HDMI_1080p30,
-    HDMI_1080i120 = 46, // richard add
+    HDMI_1080i120 = 46,*/ // richard add
 } HDMI_Video_Type ;
 
 typedef enum tagHDMI_Aspec {

software/sys_controller/link.common.ld

@@ -3,7 +3,7 @@ __DYNAMIC  =  0;
 
 MEMORY
 {
-    dataram    : ORIGIN = 0x00010000, LENGTH = 0x9000
+    dataram    : ORIGIN = 0x00010000, LENGTH = 0xa000
 }
 
 /* Stack information variables */

software/sys_controller/memory/flash.c

@@ -23,88 +23,39 @@
 #include "flash.h"
 #include "utils.h"
 
-extern alt_epcq_controller_dev epcq_controller_0;
+// save some code space
+#define SINGLE_FLASH_INSTANCE
 
-alt_epcq_controller_dev *epcq_controller_dev;
+alt_flash_dev *epcq_dev;
 
 
-int check_flash()
+int init_flash()
 {
-    epcq_controller_dev = &epcq_controller_0;
+#ifdef SINGLE_FLASH_INSTANCE
+    extern alt_llist alt_flash_dev_list;
+    epcq_dev = (alt_flash_dev*)alt_flash_dev_list.next;
+#else
+    epcq_dev = alt_flash_open_dev(EPCQ_CONTROLLER2_0_AVL_MEM_NAME);
+#endif
 
-    if ((epcq_controller_dev == NULL) || !(epcq_controller_dev->is_epcs && (epcq_controller_dev->page_size == PAGESIZE)))
-        return -FLASH_DETECT_ERROR;
-
-    printf("Flash size in bytes: %lu\nSector size: %lu (%lu pages)\nPage size: %lu\n",
-            epcq_controller_dev->size_in_bytes, epcq_controller_dev->sector_size, epcq_controller_dev->sector_size/epcq_controller_dev->page_size, epcq_controller_dev->page_size);
-
-    return 0;
-}
-
-int read_flash(alt_u32 offset, alt_u32 length, alt_u8 *dstbuf)
-{
-    int retval, i;
-
-    retval = alt_epcq_controller_read(&epcq_controller_dev->dev, offset, dstbuf, length);
-    if (retval != 0)
-        return -FLASH_READ_ERROR;
-
-    return 0;
-}
-
-int write_flash_page(alt_u8 *pagedata, alt_u32 length, alt_u32 pagenum)
-{
-    int retval, i;
-
-    if ((pagenum % PAGES_PER_SECTOR) == 0) {
-        printf("Erasing sector %u\n", (unsigned)(pagenum/PAGES_PER_SECTOR));
-        retval = alt_epcq_controller_erase_block(&epcq_controller_dev->dev, pagenum*PAGESIZE);
-
-        if (retval != 0) {
-            printf("Flash erase error, sector %u\nRetval %d\n", (unsigned)(pagenum/PAGES_PER_SECTOR), retval);
-            return -FLASH_ERASE_ERROR;
-        }
-    }
-
-    retval = alt_epcq_controller_write_block(&epcq_controller_dev->dev, (pagenum/PAGES_PER_SECTOR)*PAGES_PER_SECTOR*PAGESIZE, pagenum*PAGESIZE, pagedata, length);
-
-    if (retval != 0) {
-        printf("Flash write error, page %u\nRetval %d\n", (unsigned)pagenum, retval);
-        return -FLASH_WRITE_ERROR;
-    }
-
-    return 0;
-}
-
-int write_flash(alt_u8 *buf, alt_u32 length, alt_u32 pagenum)
-{
-    int retval;
-    alt_u32 bytes_to_w;
-
-    while (length > 0) {
-        bytes_to_w = (length > PAGESIZE) ? PAGESIZE : length;
-
-        retval = write_flash_page(buf, bytes_to_w, pagenum);
-        if (retval != 0)
-            return retval;
-
-        buf += bytes_to_w;
-        length -= bytes_to_w;
-        ++pagenum;
-    }
+    if (epcq_dev == NULL)
+        return -1;
 
     return 0;
 }
 
 int verify_flash(alt_u32 offset, alt_u32 length, alt_u32 golden_crc, alt_u8 *tmpbuf)
 {
-    alt_u32 crcval=0, i, bytes_to_read;
+    alt_u32 crcval=0, i, j, bytes_to_read;
     int retval;
 
     for (i=0; i<length; i=i+PAGESIZE) {
         bytes_to_read = ((length-i < PAGESIZE) ? (length-i) : PAGESIZE);
 
-        retval = read_flash(i, bytes_to_read, tmpbuf);
+        //retval = read_flash(i, bytes_to_read, tmpbuf);
+        retval = alt_epcq_controller2_read(epcq_dev, offset+i, tmpbuf, bytes_to_read);
+        for (j=0; j<bytes_to_read; j++)
+            tmpbuf[j] = bitswap8(tmpbuf[j]);
         if (retval != 0)
             return retval;
 

software/sys_controller/memory/flash.h

@@ -22,7 +22,7 @@
 
 #include "alt_types.h"
 #include "sysconfig.h"
-#include "altera_epcq_controller_mod.h"
+#include "altera_epcq_controller2.h"
 
 // EPCS16 pagesize is 256 bytes
 // Flash is split 50-50 to FW and userdata, 1MB each
@@ -32,20 +32,10 @@
 #define USERDATA_OFFSET 0x100000
 #define MAX_USERDATA_ENTRY 15    // 16 sectors for userdata
 
-#define FLASH_DETECT_ERROR      200
-#define FLASH_READ_ERROR        201
-#define FLASH_ERASE_ERROR       202
-#define FLASH_WRITE_ERROR       203
 #define FLASH_VERIFY_ERROR      204
 
-int check_flash();
-
-int read_flash(alt_u32 offset, alt_u32 length, alt_u8 *dstbuf);
-
-int write_flash_page(alt_u8 *pagedata, alt_u32 length, alt_u32 pagenum);
-
-int write_flash(alt_u8 *buf, alt_u32 length, alt_u32 pagenum);
 
+int init_flash();
 int verify_flash(alt_u32 offset, alt_u32 length, alt_u32 golden_crc, alt_u8 *tmpbuf);
 
 #endif /* FLASH_H_ */

software/sys_controller/memory/sdcard.c

@@ -18,11 +18,12 @@
 //
 
 #include <io.h>
+#include <string.h>
 #include "sdcard.h"
 #include "flash.h"
-#include "lcd.h"
+#include "utils.h"
 
-extern char menu_row1[LCD_ROW_LEN+1], menu_row2[LCD_ROW_LEN+1];
+extern alt_flash_dev *epcq_dev;
 
 SD_DEV sdcard_dev;
 
@@ -32,26 +33,35 @@ int check_sdcard(alt_u8 *databuf)
 
     res = SD_Init(&sdcard_dev);
     printf("SD det status: %u\n", res);
-    if (res != SD_OK)
-        return res;
+    if (res == SD_OK)
+        res = SD_Read(&sdcard_dev, databuf, 0, 0, 512);
 
-    return SD_Read(&sdcard_dev, databuf, 0, 0, 512);
+    return -res;
 }
 
 int copy_sd_to_flash(alt_u32 sd_blknum, alt_u32 flash_pagenum, alt_u32 length, alt_u8 *tmpbuf)
 {
-    int retval;
+    SDRESULTS res;
+    int retval, i;
     alt_u32 bytes_to_rw;
 
     while (length > 0) {
         bytes_to_rw = (length < SD_BLK_SIZE) ? length : SD_BLK_SIZE;
-        retval = SD_Read(&sdcard_dev, tmpbuf, sd_blknum, 0, bytes_to_rw);
-        if (retval != 0) {
+        res = SD_Read(&sdcard_dev, tmpbuf, sd_blknum, 0, bytes_to_rw);
+        if (res != SD_OK) {
             printf("Failed to read SD card\n");
-            return -retval;
+            return -res;
         }
 
-        retval = write_flash(tmpbuf, bytes_to_rw, flash_pagenum);
+        if ((flash_pagenum % PAGES_PER_SECTOR) == 0) {
+            retval = alt_epcq_controller2_erase_block(epcq_dev, flash_pagenum*PAGESIZE);
+            if (retval != 0)
+                return retval;
+        }
+
+        for (i=0; i<bytes_to_rw; i++)
+            tmpbuf[i] = bitswap8(tmpbuf[i]);
+        retval = alt_epcq_controller2_write_block(epcq_dev, ((flash_pagenum/PAGES_PER_SECTOR)*SECTORSIZE), flash_pagenum*PAGESIZE, tmpbuf, bytes_to_rw);
         if (retval != 0)
             return retval;
 
@@ -62,3 +72,35 @@ int copy_sd_to_flash(alt_u32 sd_blknum, alt_u32 flash_pagenum, alt_u32 length, a
 
     return 0;
 }
+
+int copy_flash_to_sd(alt_u32 flash_pagenum, alt_u32 sd_blknum, alt_u32 length, alt_u8 *tmpbuf)
+{
+    SDRESULTS res;
+    int retval, i;
+    alt_u32 bytes_to_rw;
+
+    while (length > 0) {
+        bytes_to_rw = (length < SD_BLK_SIZE) ? length : SD_BLK_SIZE;
+        retval = alt_epcq_controller2_read(epcq_dev, flash_pagenum*PAGESIZE, tmpbuf, bytes_to_rw);
+        for (i=0; i<bytes_to_rw; i++)
+            tmpbuf[i] = bitswap8(tmpbuf[i]);
+        if (retval != 0)
+            return retval;
+
+        if (bytes_to_rw < SD_BLK_SIZE)
+            memset(tmpbuf+bytes_to_rw, 0, SD_BLK_SIZE-bytes_to_rw);
+
+        res = SD_Write(&sdcard_dev, tmpbuf, sd_blknum);
+        if (res != SD_OK) {
+            printf("Failed to write to SD card\n");
+            return -res;
+        }
+
+        ++sd_blknum;
+        flash_pagenum += bytes_to_rw/PAGESIZE;
+        length -= bytes_to_rw;
+    }
+
+    return 0;
+
+}

software/sys_controller/memory/sdcard.h

@@ -26,5 +26,6 @@
 
 int check_sdcard(alt_u8 *databuf);
 int copy_sd_to_flash(alt_u32 sd_blknum, alt_u32 flash_pagenum, alt_u32 length, alt_u8 *tmpbuf);
+int copy_flash_to_sd(alt_u32 flash_pagenum, alt_u32 sd_blknum, alt_u32 length, alt_u8 *tmpbuf);
 
 #endif /* SDCARD_H_ */

software/sys_controller/ossc/av_controller.c

@@ -1,5 +1,5 @@
 //
-// Copyright (C) 2015-2019  Markus Hiienkari <mhiienka@niksula.hut.fi>
+// Copyright (C) 2015-2022  Markus Hiienkari <mhiienka@niksula.hut.fi>
 //
 // This file is part of Open Source Scan Converter project.
 //
@@ -65,12 +65,14 @@ extern alt_u8 remote_rpt, remote_rpt_prev;
 extern avconfig_t tc, tc_default;
 extern alt_u8 vm_sel;
 
-alt_u8 target_typemask;
+tvp_input_t target_tvp;
+tvp_sync_input_t target_tvp_sync;
 alt_u8 target_type;
 alt_u8 stable_frames;
 alt_u8 update_cur_vm;
 
 alt_u8 profile_sel, profile_sel_menu, input_profiles[AV_LAST], lt_sel, def_input, profile_link, lcd_bl_timeout;
+alt_u8 osd_enable=1, osd_status_timeout=1;
 alt_u8 auto_input, auto_av1_ypbpr, auto_av2_ypbpr = 1, auto_av3_ypbpr;
 
 char row1[LCD_ROW_LEN+1], row2[LCD_ROW_LEN+1], menu_row1[LCD_ROW_LEN+1], menu_row2[LCD_ROW_LEN+1];
@@ -83,15 +85,59 @@ alt_u8 pcm1862_active;
 alt_u32 pclk_out;
 alt_u32 read_it2(alt_u32 regaddr);
 
-volatile sc_regs *sc = (volatile sc_regs*)SC_CONFIG_0_BASE;
+// Manually (see cyiv-51005.pdf) or automatically (MIF/HEX from PLL megafunction) generated config may not
+// provide fully correct scan chain data (e.g. mismatches in C3) and lead to incorrect PLL configuration.
+// To get correct scan chain data, do the following:
+//   1. Create a ALTPLL_RECONFIG instance with initial value read from your MIF/HEX file
+//   2. Connect ALTPLL_RECONFIG to your PLL and set its reconfig input to something you can control easily (e.g. button)
+//   3. Create a signaltap file and add all PLL signals to capture. Set sample depth to 256 and clock to scanclk
+//   4. Compile the design and program the FPGA
+//   5. Open signaltap and set trigger to scanclkena rising edge
+//   6. Run signaltap and trigger PLL reconfiguration
+//   7. Export VCD file for analysis
+//   8. Compare your MIF/HEX to the captured scan chain and update it accordingly
+//   9. Dump the updated scan chain data to an array like below (last 16 bits are 0)
+//  10. PLL can be then reconfigured with custom pll_reconfig as shown in program_mode()
+const pll_config_t pll_configs[] = { {{0x0d806000, 0x00402010, 0x08040220, 0x00004022, 0x00000000}},    // 1x, 1x (default)
+                                     {{0x0dc06000, 0x00783c11, 0x070180e0, 0x0000180e, 0x00000000}},    // 2x, 5x
+                                     {{0x0d806000, 0x00301804, 0x02014060, 0x00001406, 0x00000000}} };  // 3x, 4x
 
-inline void lcd_write_menu()
+volatile sc_regs *sc = (volatile sc_regs*)SC_CONFIG_0_BASE;
+volatile osd_regs *osd = (volatile osd_regs*)OSD_GENERATOR_0_BASE;
+volatile pll_reconfig_regs *pll_reconfig = (volatile pll_reconfig_regs*)PLL_RECONFIG_0_BASE;
+
+void ui_disp_menu(alt_u8 osd_mode)
 {
+    alt_u8 menu_page;
+
+    if ((osd_mode == 1) || (osd_enable == 2)) {
+        strncpy((char*)osd->osd_array.data[0][0], menu_row1, OSD_CHAR_COLS);
+        strncpy((char*)osd->osd_array.data[1][0], menu_row2, OSD_CHAR_COLS);
+        osd->osd_row_color.mask = 0;
+        osd->osd_sec_enable[0].mask = 3;
+        osd->osd_sec_enable[1].mask = 0;
+    } else if (osd_mode == 2) {
+        menu_page = get_current_menunavi()->mp;
+        strncpy((char*)osd->osd_array.data[menu_page][1], menu_row2, OSD_CHAR_COLS);
+        osd->osd_sec_enable[1].mask |= (1<<menu_page);
+    }
+
     lcd_write((char*)&menu_row1, (char*)&menu_row2);
 }
 
-inline void lcd_write_status() {
-    lcd_write((char*)&row1, (char*)&row2);
+void ui_disp_status(alt_u8 refresh_osd_timer) {
+    if (!menu_active) {
+        if (refresh_osd_timer)
+            osd->osd_config.status_refresh = 1;
+
+        strncpy((char*)osd->osd_array.data[0][0], row1, OSD_CHAR_COLS);
+        strncpy((char*)osd->osd_array.data[1][0], row2, OSD_CHAR_COLS);
+        osd->osd_row_color.mask = 0;
+        osd->osd_sec_enable[0].mask = 3;
+        osd->osd_sec_enable[1].mask = 0;
+
+        lcd_write((char*)&row1, (char*)&row2);
+    }
 }
 
 #ifdef ENABLE_AUDIO
@@ -129,7 +175,7 @@ inline void TX_enable(tx_mode_t mode)
     EnableVideoOutput(cm.hdmitx_pclk_level ? PCLK_HIGH : PCLK_MEDIUM, COLOR_RGB444, (mode == TX_HDMI_YCBCR444) ? COLOR_YUV444 : COLOR_RGB444, (mode != TX_DVI));
 
     if (mode != TX_DVI) {
-        HDMITX_SetAVIInfoFrame(HDMI_Unkown, (mode == TX_HDMI_RGB) ? F_MODE_RGB444 : F_MODE_YUV444, 0, 0, tc.hdmi_itc, cm.hdmitx_pixr_ifr);
+        HDMITX_SetAVIInfoFrame(cm.hdmitx_vic, (mode == TX_HDMI_RGB) ? F_MODE_RGB444 : F_MODE_YUV444, 0, 0, tc.hdmi_itc, cm.hdmitx_pixr_ifr);
         cm.cc.hdmi_itc = tc.hdmi_itc;
     }
 
@@ -141,6 +187,41 @@ inline void TX_enable(tx_mode_t mode)
     SetAVMute(FALSE);
 }
 
+void pll_reconfigure(alt_u8 id)
+{
+    if ((id < sizeof(pll_configs)/sizeof(pll_config_t)) && (id != pll_reconfig->pll_config_status.c_config_id)) {
+        memcpy((void*)pll_reconfig->pll_config_data.data, pll_configs[id].data, sizeof(pll_config_t));
+        pll_reconfig->pll_config_status.t_config_id = id;
+
+        printf("Reconfiguring PLL to config %u\n", id);
+
+        // Try switching to fixed reference clock as otherwise reconfig may hang or corrupt configuration
+        if (cm.avinput != AV_TESTPAT) {
+            sys_ctrl &= ~VIDGEN_OFF;
+            IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, sys_ctrl);
+            usleep(10);
+        }
+
+        // Do not reconfigure if clock switch failed
+        if ((IORD_ALTERA_AVALON_PIO_DATA(PIO_1_BASE) & PLL_ACTIVECLK_MASK) == 0) {
+            // reset state machine if previous reconfigure hanged (should not occur with stable refclk)
+            if (pll_reconfig->pll_config_status.busy) {
+                pll_reconfig->pll_config_status.reset = 1;
+                usleep(1);
+            }
+
+            pll_reconfig->pll_config_status.reset = 0;
+            pll_reconfig->pll_config_status.update = 1;
+            usleep(10);
+        }
+
+        if (cm.avinput != AV_TESTPAT) {
+            sys_ctrl |= VIDGEN_OFF;
+            IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, sys_ctrl);
+        }
+    }
+}
+
 void set_lpf(alt_u8 lpf)
 {
     alt_u32 pclk;
@@ -149,29 +230,35 @@ void set_lpf(alt_u8 lpf)
 
     //Auto
     if (lpf == 0) {
-        switch (target_type) {
-        case VIDEO_PC:
+        if (target_tvp == TVP_INPUT3) {
             tvp_set_lpf((pclk < 30000000) ? 0x0F : 0);
             ths_set_lpf(THS_LPF_BYPASS);
-            break;
-        case VIDEO_HDTV:
+        } else {
             tvp_set_lpf(0);
-            ths_set_lpf((pclk < 80000000) ? THS_LPF_35MHZ : THS_LPF_BYPASS);
-            break;
-        case VIDEO_EDTV:
-            tvp_set_lpf(0);
-            ths_set_lpf(THS_LPF_16MHZ);
-            break;
-        case VIDEO_SDTV:
-        case VIDEO_LDTV:
-        default:
-            tvp_set_lpf(0);
-            ths_set_lpf(THS_LPF_9MHZ);
-            break;
+
+            switch (target_type) {
+            case VIDEO_PC:
+            case VIDEO_HDTV:
+                ths_set_lpf((pclk < 80000000) ? THS_LPF_35MHZ : THS_LPF_BYPASS);
+                break;
+            case VIDEO_EDTV:
+                ths_set_lpf(THS_LPF_16MHZ);
+                break;
+            case VIDEO_SDTV:
+            case VIDEO_LDTV:
+            default:
+                ths_set_lpf(THS_LPF_9MHZ);
+                break;
+            }
         }
     } else {
-        tvp_set_lpf((tc.video_lpf == 2) ? 0x0F : 0);
-        ths_set_lpf((tc.video_lpf > 2) ? (VIDEO_LPF_MAX-tc.video_lpf) : THS_LPF_BYPASS);
+        if (target_tvp == TVP_INPUT3) {
+            tvp_set_lpf((lpf == 2) ? 0x0F : 0);
+            ths_set_lpf(THS_LPF_BYPASS);
+        } else {
+            tvp_set_lpf(0);
+            ths_set_lpf((lpf > 2) ? (VIDEO_LPF_MAX-lpf) : THS_LPF_BYPASS);
+        }
     }
 }
 
@@ -195,7 +282,7 @@ inline int check_linecnt(alt_u8 progressive, alt_u32 totlines) {
 }
 
 // Check if input video status / target configuration has changed
-status_t get_status(tvp_input_t input, video_format format)
+status_t get_status(tvp_sync_input_t syncinput)
 {
     alt_u32 data1, data2;
     alt_u32 totlines, clkcnt;
@@ -221,7 +308,7 @@ status_t get_status(tvp_input_t input, video_format format)
         }
     }
 
-    sync_active = tvp_check_sync(input, format);
+    sync_active = tvp_check_sync(syncinput);
     vsyncmode = cm.sync_active ? sc->sc_status.fpga_vsyncgen : 0;
 
     // Read sync information from TVP7002 status registers
@@ -296,14 +383,22 @@ status_t get_status(tvp_input_t input, video_format format)
             (tc.l5_fmt != cm.cc.l5_fmt) ||
             (tc.tvp_hpll2x != cm.cc.tvp_hpll2x) ||
             (tc.upsample2x != cm.cc.upsample2x) ||
-            (tc.vga_ilace_fix != cm.cc.vga_ilace_fix))
+            (tc.vga_ilace_fix != cm.cc.vga_ilace_fix) ||
+            (tc.default_vic != cm.cc.default_vic) ||
+            (tc.clamp_offset != cm.cc.clamp_offset))
             status = (status < MODE_CHANGE) ? MODE_CHANGE : status;
 
         if ((tc.s480p_mode != cm.cc.s480p_mode) && (video_modes[cm.id].v_total == 525))
             status = (status < MODE_CHANGE) ? MODE_CHANGE : status;
 
+        if ((tc.s400p_mode != cm.cc.s400p_mode) && (video_modes[cm.id].v_total == 449))
+            status = (status < MODE_CHANGE) ? MODE_CHANGE : status;
+
+        if (cm.pll_config != pll_reconfig->pll_config_status.c_config_id)
+            status = (status < MODE_CHANGE) ? MODE_CHANGE : status;
+
         if (update_cur_vm) {
-            cm.h_mult_total = (video_modes[cm.id].h_total*cm.sample_mult) + (video_modes[cm.id].h_total_adj % cm.sample_mult);
+            cm.h_mult_total = (video_modes[cm.id].h_total*cm.sample_mult) + ((cm.sample_mult*video_modes[cm.id].h_total_adj*5 + 50) / 100);
             tvp_setup_hpll(cm.h_mult_total, clkcnt, cm.cc.tvp_hpll2x && (video_modes[cm.id].flags & MODE_PLLDIVBY2));
             cm.sample_sel = tvp_set_hpll_phase(video_modes[cm.id].sampler_phase, cm.sample_mult);
             status = (status < SC_CONFIG_CHANGE) ? SC_CONFIG_CHANGE : status;
@@ -327,8 +422,10 @@ status_t get_status(tvp_input_t input, video_format format)
         (tc.h_mask != cm.cc.h_mask) ||
         (tc.v_mask != cm.cc.v_mask) ||
         (tc.mask_br != cm.cc.mask_br) ||
+        (tc.mask_color != cm.cc.mask_color) ||
         (tc.ar_256col != cm.cc.ar_256col) ||
-        (tc.reverse_lpf != cm.cc.reverse_lpf))
+        (tc.reverse_lpf != cm.cc.reverse_lpf) ||
+        (tc.panasonic_hack != cm.cc.panasonic_hack))
         status = (status < SC_CONFIG_CHANGE) ? SC_CONFIG_CHANGE : status;
 
     if (tc.sync_vth != cm.cc.sync_vth)
@@ -352,6 +449,12 @@ status_t get_status(tvp_input_t input, video_format format)
     if (tc.sync_lpf != cm.cc.sync_lpf)
         tvp_set_sync_lpf(tc.sync_lpf);
 
+    if (tc.stc_lpf != cm.cc.stc_lpf)
+        tvp_set_clp_lpf(tc.stc_lpf);
+
+    if ((tc.alc_h_filter != cm.cc.alc_h_filter) || (tc.alc_v_filter != cm.cc.alc_v_filter))
+        tvp_set_alcfilt(tc.alc_v_filter, tc.alc_h_filter);
+
     if (memcmp(&tc.col, &cm.cc.col, sizeof(color_setup_t)))
         tvp_set_gain_offset(&tc.col);
 
@@ -456,7 +559,6 @@ void update_sc_config()
     }
 
     switch (cm.target_lm) {
-        case MODE_L2_320_COL:
         case MODE_L2_240x360:
             h_opt_scale = 4;
             break;
@@ -472,15 +574,9 @@ void update_sc_config()
         case MODE_L3_240x360:
             h_opt_scale = 6;
             break;
-        case MODE_L4_320_COL:
-            h_opt_scale = 4;
-            break;
         case MODE_L4_256_COL:
             h_opt_scale = 5-cm.cc.ar_256col;
             break;
-        case MODE_L5_320_COL:
-            h_opt_scale = 5;
-            break;
         case MODE_L5_256_COL:
             h_opt_scale = 6-cm.cc.ar_256col;
             break;
@@ -529,6 +625,8 @@ void update_sc_config()
 
     misc_config.rev_lpf_str = cm.cc.reverse_lpf;
     misc_config.mask_br = cm.cc.mask_br;
+    misc_config.mask_color = cm.cc.mask_color;
+    misc_config.panasonic_hack = cm.cc.panasonic_hack;
 
     sl_config.sl_l_str_arr = sl_l_str_arr;
     sl_config.sl_l_overlay = sl_l_overlay;
@@ -551,7 +649,7 @@ void update_sc_config()
 // Configure TVP7002 and scan converter logic based on the video mode
 void program_mode()
 {
-    alt_u8 h_syncinlen, v_syncinlen, hdmitx_pclk_level;
+    alt_u8 h_syncinlen, v_syncinlen, hdmitx_pclk_level, osd_x_size, osd_y_size;
     alt_u32 h_hz, v_hz_x100, h_synclen_px;
 
     // Mark as stable (needed after sync up to avoid unnecessary mode switch)
@@ -572,13 +670,12 @@ void program_mode()
     v_syncinlen = tvp_readreg(TVP_VSINWIDTH);
     printf("Hswidth: %u  Vswidth: %u  Macrovision: %u\n", (unsigned)h_syncinlen, (unsigned)(v_syncinlen & 0x1F), (unsigned)cm.macrovis);
 
-    sniprintf(row1, LCD_ROW_LEN+1, "%s %u%c", avinput_str[cm.avinput], (unsigned)cm.totlines, cm.progressive ? 'p' : 'i');
+    sniprintf(row1, LCD_ROW_LEN+1, "%s %u-%c", avinput_str[cm.avinput], (unsigned)cm.totlines, cm.progressive ? 'p' : 'i');
     sniprintf(row2, LCD_ROW_LEN+1, "%u.%.2ukHz %u.%.2uHz", (unsigned)(h_hz/1000), (unsigned)((h_hz%1000)/10), (unsigned)(v_hz_x100/100), (unsigned)(v_hz_x100%100));
-    if (!menu_active)
-        lcd_write_status();
+    ui_disp_status(1);
 
     //printf ("Get mode id with %u %u %f\n", totlines, progressive, hz);
-    cm.id = get_mode_id(cm.totlines, cm.progressive, v_hz_x100/100, target_typemask);
+    cm.id = get_mode_id(cm.totlines, cm.progressive, v_hz_x100/100, h_syncinlen);
 
     if (cm.id == -1) {
         printf ("Error: no suitable mode found, defaulting to 240p\n");
@@ -586,9 +683,14 @@ void program_mode()
     }
     vm_sel = cm.id;
 
-    cm.h_mult_total = (video_modes[cm.id].h_total*cm.sample_mult) + (video_modes[cm.id].h_total_adj % cm.sample_mult);
+    cm.h_mult_total = (video_modes[cm.id].h_total*cm.sample_mult) + ((cm.sample_mult*video_modes[cm.id].h_total_adj*5 + 50) / 100);
+
+    // Trilevel sync is used with HDTV modes using composite sync
+    if (video_modes[cm.id].type & VIDEO_HDTV)
+        target_type = (target_tvp_sync <= TVP_SOG3) ? VIDEO_HDTV : VIDEO_PC;
+    else
+        target_type = video_modes[cm.id].type;
 
-    target_type = target_typemask & video_modes[cm.id].type;
     h_synclen_px = ((alt_u32)h_syncinlen * (alt_u32)cm.h_mult_total) / cm.clkcnt;
 
     printf("Mode %s selected - hsync width: %upx\n", video_modes[cm.id].name, (unsigned)h_synclen_px);
@@ -597,11 +699,38 @@ void program_mode()
                      cm.h_mult_total,
                      cm.clkcnt,
                      cm.cc.tvp_hpll2x && (video_modes[cm.id].flags & MODE_PLLDIVBY2),
-                     (alt_u8)h_synclen_px);
+                     (alt_u8)h_synclen_px,
+                     (alt_8)(cm.cc.clamp_offset-SIGNED_NUMVAL_ZERO));
     set_lpf(cm.cc.video_lpf);
     set_csc(cm.cc.ypbpr_cs);
     cm.sample_sel = tvp_set_hpll_phase(video_modes[cm.id].sampler_phase, cm.sample_mult);
 
+    pll_reconfig->pll_config_status.reset = (cm.fpga_vmultmode == FPGA_V_MULTMODE_1X);
+
+    switch (cm.fpga_vmultmode) {
+    case FPGA_V_MULTMODE_2X:
+    case FPGA_V_MULTMODE_5X:
+        cm.pll_config = PLL_CONFIG_2X_5X;
+        break;
+    case FPGA_V_MULTMODE_3X:
+    case FPGA_V_MULTMODE_4X:
+        cm.pll_config = PLL_CONFIG_3X_4X;
+        break;
+    default:
+        break;
+    }
+    pll_reconfigure(cm.pll_config);
+
+    if (cm.fpga_vmultmode == FPGA_V_MULTMODE_1X) {
+        osd_y_size = (video_modes[cm.id].v_active > 700) ? 1 : 0;
+        osd_x_size = osd_y_size + !!(video_modes[cm.id].flags & MODE_INTERLACED);
+    } else {
+        osd_x_size = 1 - cm.tx_pixelrep + (cm.fpga_hmultmode == FPGA_H_MULTMODE_OPTIMIZED_1X) + (cm.fpga_vmultmode > FPGA_V_MULTMODE_3X);
+        osd_y_size = 0;
+    }
+    osd->osd_config.x_size = osd_x_size;
+    osd->osd_config.y_size = osd_y_size;
+
     update_sc_config();
 
     TX_SetPixelRepetition(cm.tx_pixelrep, ((cm.cc.tx_mode!=TX_DVI) && (cm.tx_pixelrep == cm.hdmitx_pixr_ifr)) ? 1 : 0);
@@ -626,7 +755,7 @@ void program_mode()
         cm.hdmitx_pclk_level = hdmitx_pclk_level;
         TX_enable(cm.cc.tx_mode);
     } else if (cm.cc.tx_mode!=TX_DVI) {
-        HDMITX_SetAVIInfoFrame(HDMI_Unkown, (cm.cc.tx_mode == TX_HDMI_RGB) ? F_MODE_RGB444 : F_MODE_YUV444, 0, 0, cm.cc.hdmi_itc, cm.hdmitx_pixr_ifr);
+        HDMITX_SetAVIInfoFrame(cm.hdmitx_vic, (cm.cc.tx_mode == TX_HDMI_RGB) ? F_MODE_RGB444 : F_MODE_YUV444, 0, 0, cm.cc.hdmi_itc, cm.hdmitx_pixr_ifr);
 #ifdef ENABLE_AUDIO
 #ifdef MANUAL_CTS
         SetupAudio(cm.cc.tx_mode);
@@ -684,6 +813,10 @@ int init_hw()
     sys_ctrl = AV_RESET_N|LCD_BL|SD_SPI_SS_N|LCD_CS_N|REMOTE_EVENT;
     IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, sys_ctrl);
 
+    // Reload initial PLL config (needed after jtagm_reset_req if config has changed).
+    // Note that test pattern gets restored only if pclk was active before jtagm_reset_req assertion.
+    pll_reconfigure(PLL_CONFIG_VG);
+
     //wait >500ms for SD card interface to be stable
     //over 200ms and LCD may be buggy?
     usleep(200000);
@@ -727,8 +860,8 @@ int init_hw()
     }
 #endif
 
-    if (check_flash() != 0) {
-        printf("Error: incorrect flash type detected\n");
+    if (init_flash() != 0) {
+        printf("Error: could not find flash\n");
         return -1;
     }
 
@@ -741,13 +874,23 @@ int init_hw()
     read_userdata(INIT_CONFIG_SLOT, 0);
     read_userdata(profile_sel, 0);
 
+    // Setup OSD
+    osd->osd_config.x_size = 0;
+    osd->osd_config.y_size = 0;
+    osd->osd_config.x_offset = 3;
+    osd->osd_config.y_offset = 3;
+    osd->osd_config.enable = !!osd_enable;
+    osd->osd_config.status_timeout = osd_status_timeout;
+    osd->osd_config.border_color = 1;
+
+    // init always in HDMI mode (fixes yellow screen bug)
+    cm.hdmitx_vic = HDMI_480p60;
+    TX_enable(TX_HDMI_RGB);
+
     // Setup remote keymap
     if (!(IORD_ALTERA_AVALON_PIO_DATA(PIO_1_BASE) & PB1_BIT))
         setup_rc();
 
-    // init always in HDMI mode (fixes yellow screen bug)
-    TX_enable(TX_HDMI_RGB);
-
     return 0;
 }
 
@@ -760,7 +903,7 @@ int latency_test() {
     sys_ctrl |= LT_ACTIVE|(position<<LT_MODE_OFFS);
     IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, sys_ctrl);
     sniprintf(menu_row2, LCD_ROW_LEN+1, "OK to init");
-    lcd_write_menu();
+    ui_disp_menu(0);
 
     while (1) {
         btn_vec = IORD_ALTERA_AVALON_PIO_DATA(PIO_1_BASE) & RC_MASK;
@@ -770,7 +913,7 @@ int latency_test() {
                 sys_ctrl &= ~(3<<LT_MODE_OFFS);
                 IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, sys_ctrl);
                 menu_row2[0] = 0;
-                lcd_write_menu();
+                ui_disp_menu(0);
                 usleep(400000);
                 sys_ctrl |= LT_ARMED|(position<<LT_MODE_OFFS);
                 IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, sys_ctrl);
@@ -793,7 +936,7 @@ int latency_test() {
                     sniprintf(menu_row2, LCD_ROW_LEN+1, "%u.%.2ums", latency_ms_x100/100, latency_ms_x100%100);
                 else
                     sniprintf(menu_row2, LCD_ROW_LEN+1, "%u.%.2ums/%u.%.2ums", latency_ms_x100/100, latency_ms_x100%100, stb_ms_x100/100, stb_ms_x100%100);
-                lcd_write_menu();
+                ui_disp_menu(0);
             } else if (btn_vec == rc_keymap[RC_BACK]) {
                 break;
             }
@@ -815,10 +958,10 @@ int latency_test() {
 // Enable chip outputs
 void enable_outputs()
 {
-    // program video mode
-    program_mode();
     // enable TVP output
     tvp_enable_output();
+    // program video mode
+    program_mode();
 
     // enable and unmute TX
     TX_enable(tc.tx_mode);
@@ -826,7 +969,6 @@ void enable_outputs()
 
 int main()
 {
-    tvp_input_t target_tvp = 0;
     ths_input_t target_ths = 0;
     pcm_input_t target_pcm = 0;
     video_format target_format = 0;
@@ -849,16 +991,16 @@ int main()
         printf("### DIY VIDEO DIGITIZER / SCANCONVERTER INIT OK ###\n\n");
         sniprintf(row1, LCD_ROW_LEN+1, "OSSC  fw. %u.%.2u" FW_SUFFIX1 FW_SUFFIX2, FW_VER_MAJOR, FW_VER_MINOR);
 #ifndef DEBUG
-        strncpy(row2, "2014-2019  marqs", LCD_ROW_LEN+1);
+        strncpy(row2, "2014-2022  marqs", LCD_ROW_LEN+1);
 #else
         strncpy(row2, "** DEBUG BUILD *", LCD_ROW_LEN+1);
 #endif
-        lcd_write_status();
+        ui_disp_status(1);
         usleep(500000);
     } else {
         sniprintf(row1, LCD_ROW_LEN+1, "Init error  %d", init_stat);
         strncpy(row2, "", LCD_ROW_LEN+1);
-        lcd_write_status();
+        ui_disp_status(1);
         while (1) {}
     }
 
@@ -947,15 +1089,15 @@ int main()
             auto_input_changed = 0;
         }
 
-        if (target_input != cm.avinput) {
+        if ((target_input != cm.avinput) || ((target_tvp_sync >= TVP_HV_A) && ((tc.av3_alt_rgb != cm.cc.av3_alt_rgb)))) {
 
             target_tvp = TVP_INPUT1;
-            target_typemask = VIDEO_LDTV|VIDEO_SDTV|VIDEO_EDTV|VIDEO_HDTV;
+            target_tvp_sync = TVP_SOG1;
 
-            if (target_input <= AV1_YPBPR) {
+            if ((target_input <= AV1_YPBPR) || (tc.av3_alt_rgb==1 && ((target_input == AV3_RGBHV) || (target_input == AV3_RGBs)))) {
                 target_ths = THS_INPUT_B;
                 target_pcm = PCM_INPUT4;
-            } else if (target_input <= AV2_RGsB) {
+            } else if ((target_input <= AV2_RGsB) || (tc.av3_alt_rgb==2 && ((target_input == AV3_RGBHV) || (target_input == AV3_RGBs)))) {
                 target_ths = THS_INPUT_A;
                 target_pcm = PCM_INPUT3;
             } else  { // if (target_input <= AV3_YPBPR) {
@@ -981,7 +1123,24 @@ int main()
                 break;
             case AV3_RGBHV:
                 target_format = FORMAT_RGBHV;
-                target_typemask = VIDEO_PC;
+                break;
+            default:
+                break;
+            }
+
+            switch (target_input) {
+            case AV1_RGBs:
+                target_tvp_sync = TVP_SOG2;
+                break;
+            case AV3_RGBHV:
+                target_tvp_sync = TVP_HV_A;
+                break;
+            case AV3_RGBs:
+                target_tvp_sync = TVP_CS_A;
+                break;
+            case AV3_RGsB:
+            case AV3_YPBPR:
+                target_tvp_sync = TVP_SOG3;
                 break;
             default:
                 break;
@@ -998,12 +1157,11 @@ int main()
             if (pcm1862_active)
                 pcm_source_sel(target_pcm);
 #endif
-            tvp_source_sel(target_tvp, target_format);
+            tvp_source_sel(target_tvp, target_tvp_sync, target_format);
             cm.clkcnt = 0; //TODO: proper invalidate
             strncpy(row1, avinput_str[cm.avinput], LCD_ROW_LEN+1);
             strncpy(row2, "    NO SYNC", LCD_ROW_LEN+1);
-            if (!menu_active)
-                lcd_write_status();
+            ui_disp_status(1);
             if (man_input_change) {
                 // record last input if it was selected manually
                 if (def_input == AV_LAST)
@@ -1016,7 +1174,7 @@ int main()
 
         // Check here to enable regardless of input
         if (tc.tx_mode != cm.cc.tx_mode) {
-            HDMITX_SetAVIInfoFrame(HDMI_Unkown, F_MODE_RGB444, 0, 0, 0, 0);
+            HDMITX_SetAVIInfoFrame(cm.hdmitx_vic, F_MODE_RGB444, 0, 0, 0, 0);
             TX_enable(tc.tx_mode);
             cm.cc.tx_mode = tc.tx_mode;
             cm.clkcnt = 0; //TODO: proper invalidate
@@ -1024,12 +1182,25 @@ int main()
         if ((tc.tx_mode != TX_DVI) && (tc.hdmi_itc != cm.cc.hdmi_itc)) {
             //EnableAVIInfoFrame(FALSE, NULL);
             printf("setting ITC to %d\n", tc.hdmi_itc);
-            HDMITX_SetAVIInfoFrame(HDMI_Unkown, (tc.tx_mode == TX_HDMI_RGB) ? F_MODE_RGB444 : F_MODE_YUV444, 0, 0, tc.hdmi_itc, cm.hdmitx_pixr_ifr);
+            HDMITX_SetAVIInfoFrame(cm.hdmitx_vic, (tc.tx_mode == TX_HDMI_RGB) ? F_MODE_RGB444 : F_MODE_YUV444, 0, 0, tc.hdmi_itc, cm.hdmitx_pixr_ifr);
             cm.cc.hdmi_itc = tc.hdmi_itc;
         }
+        if (tc.av3_alt_rgb != cm.cc.av3_alt_rgb) {
+            printf("Changing AV3 RGB source\n");
+            cm.cc.av3_alt_rgb = tc.av3_alt_rgb;
+        }
+        if ((!!osd_enable != osd->osd_config.enable) || (osd_status_timeout != osd->osd_config.status_timeout)) {
+            osd->osd_config.enable = !!osd_enable;
+            osd->osd_config.status_timeout = osd_status_timeout;
+            if (menu_active) {
+                remote_code = 0;
+                render_osd_page();
+                display_menu(1);
+            }
+        }
 
         if (cm.avinput != AV_TESTPAT) {
-            status = get_status(target_tvp, target_format);
+            status = get_status(target_tvp_sync);
 
             switch (status) {
             case ACTIVITY_CHANGE:
@@ -1045,8 +1216,7 @@ int main()
                     //ths_source_sel(THS_STANDBY, 0);
                     strncpy(row1, avinput_str[cm.avinput], LCD_ROW_LEN+1);
                     strncpy(row2, "    NO SYNC", LCD_ROW_LEN+1);
-                    if (!menu_active)
-                        lcd_write_status();
+                    ui_disp_status(1);
                     alt_timestamp_start();// reset auto input timer
                     auto_input_ctr = 0;
                     auto_input_current_ctr = 0;

software/sys_controller/ossc/av_controller.h

@@ -23,6 +23,8 @@
 #include "avconfig.h"
 #include "sysconfig.h"
 #include "sc_config_regs.h"
+#include "osd_generator_regs.h"
+#include "pll_reconfig_regs.h"
 
 // sys_ctrl bits
 #define LT_ACTIVE                   (1<<15)
@@ -42,6 +44,8 @@
 // HDMI_TX definitions
 #define HDMITX_MODE_MASK            0x00040000
 
+#define PLL_ACTIVECLK_MASK          0x00080000
+
 #define TX_PIXELREP_DISABLE         0
 #define TX_PIXELREP_2X              1
 #define TX_PIXELREP_4X              3
@@ -63,6 +67,10 @@
 #define AUTO_MAX_COUNT            100
 #define AUTO_CURRENT_MAX_COUNT      6
 
+#define PLL_CONFIG_VG               0
+#define PLL_CONFIG_2X_5X            1
+#define PLL_CONFIG_3X_4X            2
+
 // In reverse order of importance
 typedef enum {
     NO_CHANGE           = 0,
@@ -78,6 +86,10 @@ typedef enum {
     TX_DVI              = 2
 } tx_mode_t;
 
+typedef struct {
+    alt_u32 data[5];
+} pll_config_t;
+
 //TODO: transform binary values into flags
 typedef struct {
     alt_u32 totlines;
@@ -91,18 +103,20 @@ typedef struct {
     alt_u8 tx_pixelrep;
     alt_u8 hdmitx_pixr_ifr;
     alt_u8 hdmitx_pclk_level;
+    HDMI_Video_Type hdmitx_vic;
     alt_u8 sample_mult;
     alt_u8 sample_sel;
     alt_u8 hsync_cut;
     alt_u16 h_mult_total;
     mode_flags target_lm;
     avinput_t avinput;
+    alt_u8 pll_config;
     // Current configuration
     avconfig_t cc;
 } avmode_t;
 
-inline void lcd_write_menu();
-inline void lcd_write_status();
+void ui_disp_menu(alt_u8 osd_mode);
+void ui_disp_status(alt_u8 refresh_osd_timer);
 
 int load_profile();
 int save_profile();

software/sys_controller/ossc/avconfig.c

@@ -62,6 +62,9 @@ const avconfig_t tc_default = {
         .c_gain = DEFAULT_COARSE_GAIN,
     },
     .link_av = AV_LAST,
+    .clamp_offset = SIGNED_NUMVAL_ZERO,
+    .alc_h_filter = DEFAULT_ALC_H_FILTER,
+    .alc_v_filter = DEFAULT_ALC_V_FILTER,
 };
 
 int set_default_avconfig()

software/sys_controller/ossc/avconfig.h

@@ -23,6 +23,8 @@
 #include "alt_types.h"
 #include "tvp7002.h"
 
+#define SIGNED_NUMVAL_ZERO  128
+
 #define SCANLINESTR_MAX     15
 #define SL_HYBRIDSTR_MAX    28
 #define H_MASK_MAX          255
@@ -37,6 +39,10 @@
 #define PLL_COAST_MAX       5
 #define REVERSE_LPF_MAX     31
 #define COARSE_GAIN_MAX     15
+#define ALC_H_FILTER_MAX    7
+#define ALC_V_FILTER_MAX    10
+#define CLAMP_OFFSET_MIN    (SIGNED_NUMVAL_ZERO-100)
+#define CLAMP_OFFSET_MAX    (SIGNED_NUMVAL_ZERO+100)
 
 #define SL_MODE_MAX         2
 #define SL_TYPE_MAX         2
@@ -50,7 +56,7 @@
 #define L5FMT_1600x1200     1
 #define L5FMT_1920x1200     2
 
-static const char *avinput_str[] = { "Test pattern", "AV1: RGBS", "AV1: RGsB", "AV1: YPbPr", "AV2: YPbPr", "AV2: RGsB", "AV3: RGBHV", "AV3: RGBS", "AV3: RGsB", "AV3: YPbPr", "Last used" };
+static const char *avinput_str[] = { "Test pattern", "AV1_RGBS", "AV1_RGsB", "AV1_YPbPr", "AV2_YPbPr", "AV2_RGsB", "AV3_RGBHV", "AV3_RGBS", "AV3_RGsB", "AV3_YPbPr", "Last used" };
 
 typedef enum {
     AV_TESTPAT      = 0,
@@ -92,9 +98,11 @@ typedef struct {
     alt_u8 h_mask;
     alt_u8 v_mask;
     alt_u8 mask_br;
+    alt_u8 mask_color;
     alt_u8 tx_mode;
     alt_u8 hdmi_itc;
     alt_u8 s480p_mode;
+    alt_u8 s400p_mode;
     alt_u8 tvp_hpll2x;
     alt_u8 upsample2x;
     alt_u8 ypbpr_cs;
@@ -102,15 +110,22 @@ typedef struct {
     alt_u8 linelen_tol;
     alt_u8 vsync_thold;
     alt_u8 sync_lpf;
+    alt_u8 stc_lpf;
     alt_u8 video_lpf;
     alt_u8 pre_coast;
     alt_u8 post_coast;
     alt_u8 full_tx_setup;
     alt_u8 vga_ilace_fix;
+    alt_u8 av3_alt_rgb;
+    alt_u8 panasonic_hack;
     alt_u8 reverse_lpf;
     alt_u8 audio_dw_sampl;
     alt_u8 audio_swap_lr;
     alt_u8 audio_gain;
+    alt_u8 default_vic;
+    alt_u8 clamp_offset;
+    alt_u8 alc_h_filter;
+    alt_u8 alc_v_filter;
     color_setup_t col;
     avinput_t link_av;
 } __attribute__((packed)) avconfig_t;

software/sys_controller/ossc/controls.c

@@ -25,6 +25,7 @@
 #include "av_controller.h"
 #include "video_modes.h"
 #include "userdata.h"
+#include "firmware.h"
 #include "lcd.h"
 #include "altera_avalon_pio_regs.h"
 
@@ -43,10 +44,15 @@ extern avconfig_t tc;
 extern avinput_t target_input;
 extern alt_u8 menu_active;
 extern alt_u16 sys_ctrl;
+extern alt_u16 tc_sampler_phase;
 extern alt_u8 profile_sel, profile_sel_menu;
 extern alt_u8 lcd_bl_timeout;
-extern alt_u8 update_cur_vm;
+extern alt_u8 update_cur_vm, vm_edit;
 extern volatile sc_regs *sc;
+extern volatile osd_regs *osd;
+
+extern menu_t menu_scanlines, menu_advtiming;
+extern char target_profile_name[PROFILE_NAME_LEN+1];
 
 alt_u32 remote_code;
 alt_u8 remote_rpt, remote_rpt_prev;
@@ -60,7 +66,8 @@ void setup_rc()
     for (i=0; i<REMOTE_MAX_KEYS; i++) {
         strncpy(menu_row1, "Press", LCD_ROW_LEN+1);
         strncpy(menu_row2, rc_keydesc[i], LCD_ROW_LEN+1);
-        lcd_write_menu();
+        osd->osd_config.menu_active = 1;
+        ui_disp_menu(1);
         confirm = 0;
 
         while (1) {
@@ -71,14 +78,14 @@ void setup_rc()
                 if (confirm == 0) {
                     rc_keymap[i] = remote_code;
                     strncpy(menu_row1, "Confirm", LCD_ROW_LEN+1);
-                    lcd_write_menu();
+                    ui_disp_menu(1);
                     confirm = 1;
                 } else {
                     if (remote_code == rc_keymap[i]) {
                         confirm = 2;
                     } else {
                         strncpy(menu_row1, "Mismatch, retry", LCD_ROW_LEN+1);
-                        lcd_write_menu();
+                        ui_disp_menu(1);
                         confirm = 0;
                     }
                 }
@@ -104,12 +111,14 @@ void setup_rc()
         }
     }
     write_userdata(INIT_CONFIG_SLOT);
+
+    osd->osd_config.menu_active = 0;
 }
 
 int parse_control()
 {
-    int i, ret=0;
-    alt_u32 btn_vec;
+    int i, prof_x10=0, ret=0, retval;
+    alt_u32 btn_vec, btn_vec_prev=1;
     alt_u8 pt_only = 0;
     avinput_t man_target_input = AV_LAST;
 
@@ -148,43 +157,100 @@ int parse_control()
         case RC_BTN0: man_target_input = AV3_YPBPR; break;
         case RC_MENU:
             menu_active = !menu_active;
+            osd->osd_config.menu_active = menu_active;
             profile_sel_menu = profile_sel;
 
-            if (menu_active)
+            if (menu_active) {
+                render_osd_page();
                 display_menu(1);
-            else
-                lcd_write_status();
+            } else {
+                ui_disp_status(0);
+            }
 
             break;
         case RC_INFO:
             sc_status = sc->sc_status;
             sc_status2 = sc->sc_status2;
-            sniprintf(menu_row1, LCD_ROW_LEN+1, "Prof.%u %9s", profile_sel, video_modes[cm.id].name);
-            if (cm.sync_active) {
-                //fpga_v_hz_x100 = (100*TVP_EXTCLK_HZ)/IORD_ALTERA_AVALON_PIO_DATA(PIO_8_BASE);
-                /*sniprintf(menu_row2, LCD_ROW_LEN+1, "%4lu%c%c  %3lu.%.2luHz", (((fpga_status & 0x7ff)+1)<<fpga_ilace)+fpga_ilace,
-                                                                              fpga_ilace ? 'i' : 'p',
-                                                                              ((fpga_status >> 16) & 0x3) ? '*' : ' ',
-                                                                              fpga_v_hz_x100/100,
-                                                                              fpga_v_hz_x100%100);*/
-                sniprintf(menu_row2, LCD_ROW_LEN+1, "%4lu%c%c  %lu", (unsigned long)((sc_status.vmax+1)<<sc_status.interlace_flag)+sc_status.interlace_flag,
-                                                                     sc_status.interlace_flag ? 'i' : 'p',
-                                                                     sc_status.fpga_vsyncgen ? '*' : ' ',
-                                                                     (unsigned long)sc_status2.pcnt_frame);
+            fpga_v_hz_x100 = (100*TVP_EXTCLK_HZ)/sc_status2.pcnt_frame;
+
+            if (!menu_active) {
+                memset((void*)osd->osd_array.data, 0, sizeof(osd_char_array));
+                read_userdata(profile_sel, 1);
+                sniprintf((char*)osd->osd_array.data[0][0], OSD_CHAR_COLS, "Profile:");
+                sniprintf((char*)osd->osd_array.data[0][1], OSD_CHAR_COLS, "%u: %s", profile_sel, (target_profile_name[0] == 0) ? "<empty>" : target_profile_name);
+                if (cm.sync_active) {
+                    sniprintf((char*)osd->osd_array.data[1][0], OSD_CHAR_COLS, "Mode preset:");
+                    sniprintf((char*)osd->osd_array.data[1][1], OSD_CHAR_COLS, "%s", video_modes[cm.id].name);
+                    sniprintf((char*)osd->osd_array.data[2][0], OSD_CHAR_COLS, "Imode (FPGA):");
+                    sniprintf((char*)osd->osd_array.data[2][1], OSD_CHAR_COLS, "%lu-%c%c %lu.%.2luHz", (unsigned long)((sc_status.vmax+1)<<sc_status.interlace_flag)+sc_status.interlace_flag,
+                                                                             sc_status.interlace_flag ? 'i' : 'p',
+                                                                             sc_status.fpga_vsyncgen ? '*' : ' ',
+                                                                             fpga_v_hz_x100/100,
+                                                                             fpga_v_hz_x100%100);
+                    sniprintf((char*)osd->osd_array.data[3][0], OSD_CHAR_COLS, "Ccnt / frame:");
+                    sniprintf((char*)osd->osd_array.data[3][1], OSD_CHAR_COLS, "%lu", (unsigned long)sc_status2.pcnt_frame);
+                }
+                sniprintf((char*)osd->osd_array.data[4][0], OSD_CHAR_COLS, "Firmware:");
+                sniprintf((char*)osd->osd_array.data[4][1], OSD_CHAR_COLS, "%u.%.2u" FW_SUFFIX1 FW_SUFFIX2, FW_VER_MAJOR, FW_VER_MINOR);
+                osd->osd_config.status_refresh = 1;
+                osd->osd_row_color.mask = 0;
+                osd->osd_sec_enable[0].mask = 0x1f;
+                osd->osd_sec_enable[1].mask = 0x1f;
             }
-            lcd_write_menu();
             break;
         case RC_LCDBL:
             sys_ctrl ^= LCD_BL;
             break;
-        case RC_SL_MODE: tc.sl_mode = (tc.sl_mode < SL_MODE_MAX) ? (tc.sl_mode + 1) : 0; break;
-        case RC_SL_TYPE: tc.sl_type = (tc.sl_type < SL_TYPE_MAX) ? (tc.sl_type + 1) : 0; break;
-        case RC_SL_MINUS: tc.sl_str = tc.sl_str ? (tc.sl_str - 1) : 0; break;
-        case RC_SL_PLUS: tc.sl_str = (tc.sl_str < SCANLINESTR_MAX) ? (tc.sl_str + 1) : SCANLINESTR_MAX; break;
+        case RC_SL_MODE:
+            tc.sl_mode = (tc.sl_mode < SL_MODE_MAX) ? (tc.sl_mode + 1) : 0;
+            if (!menu_active) {
+                strncpy((char*)osd->osd_array.data[0][0], menu_scanlines.items[0].name, OSD_CHAR_COLS);
+                strncpy((char*)osd->osd_array.data[1][0], menu_scanlines.items[0].sel.setting_str[tc.sl_mode], OSD_CHAR_COLS);
+                osd->osd_config.status_refresh = 1;
+                osd->osd_row_color.mask = 0;
+                osd->osd_sec_enable[0].mask = 3;
+                osd->osd_sec_enable[1].mask = 0;
+            } else if (get_current_menunavi()->m == &menu_scanlines) {
+                render_osd_page();
+            }
+            break;
+        case RC_SL_TYPE:
+            tc.sl_type = (tc.sl_type < SL_TYPE_MAX) ? (tc.sl_type + 1) : 0;
+            if (!menu_active) {
+                strncpy((char*)osd->osd_array.data[0][0], menu_scanlines.items[7].name, OSD_CHAR_COLS);
+                strncpy((char*)osd->osd_array.data[1][0], menu_scanlines.items[7].sel.setting_str[tc.sl_type], OSD_CHAR_COLS);
+                osd->osd_config.status_refresh = 1;
+                osd->osd_row_color.mask = 0;
+                osd->osd_sec_enable[0].mask = 3;
+                osd->osd_sec_enable[1].mask = 0;
+            } else if (get_current_menunavi()->m == &menu_scanlines) {
+                render_osd_page();
+            }
+            break;
+        case RC_SL_MINUS:
+        case RC_SL_PLUS:
+            if (i == RC_SL_MINUS)
+                tc.sl_str = tc.sl_str ? (tc.sl_str - 1) : 0;
+            else
+                tc.sl_str = (tc.sl_str < SCANLINESTR_MAX) ? (tc.sl_str + 1) : SCANLINESTR_MAX;
+
+            if (!menu_active) {
+                strncpy((char*)osd->osd_array.data[0][0], menu_scanlines.items[1].name, OSD_CHAR_COLS);
+                menu_scanlines.items[1].num.df(tc.sl_str);
+                strncpy((char*)osd->osd_array.data[1][0], menu_row2, OSD_CHAR_COLS);
+                osd->osd_config.status_refresh = 1;
+                osd->osd_row_color.mask = 0;
+                osd->osd_sec_enable[0].mask = 3;
+                osd->osd_sec_enable[1].mask = 0;
+            } else if (get_current_menunavi()->m == &menu_scanlines) {
+                render_osd_page();
+            }
+            break;
         case RC_LM_MODE:
             strncpy(menu_row1, "Linemult mode:", LCD_ROW_LEN+1);
             strncpy(menu_row2, "press 1-5", LCD_ROW_LEN+1);
-            lcd_write_menu();
+            osd->osd_config.menu_active = 1;
+            ui_disp_menu(1);
 
             while (1) {
                 btn_vec = IORD_ALTERA_AVALON_PIO_DATA(PIO_1_BASE) & RC_MASK;
@@ -203,7 +269,7 @@ int parse_control()
                         *pmcfg_ptr[video_modes[cm.id].group] = i;
                     } else {
                         sniprintf(menu_row2, LCD_ROW_LEN+1, "%ux unsupported", i+1);
-                        lcd_write_menu();
+                        ui_disp_menu(1);
                         usleep(500000);
                     }
                     break;
@@ -213,35 +279,72 @@ int parse_control()
 
                 usleep(WAITLOOP_SLEEP_US);
             }
-            lcd_write_status();
             menu_active = 0;
+            osd->osd_config.menu_active = 0;
+            ui_disp_status(0);
+            break;
+        case RC_PHASE_MINUS:
+        case RC_PHASE_PLUS:
+            if (i == RC_PHASE_MINUS)
+                video_modes[cm.id].sampler_phase = video_modes[cm.id].sampler_phase ? (video_modes[cm.id].sampler_phase - 1) : SAMPLER_PHASE_MAX;
+            else
+                video_modes[cm.id].sampler_phase = (video_modes[cm.id].sampler_phase < SAMPLER_PHASE_MAX) ? (video_modes[cm.id].sampler_phase + 1) : 0;
+
+            update_cur_vm = 1;
+            if (cm.id == vm_edit)
+                tc_sampler_phase = video_modes[vm_edit].sampler_phase;
+
+            if (!menu_active) {
+                strncpy((char*)osd->osd_array.data[0][0], menu_advtiming.items[8].name, OSD_CHAR_COLS);
+                sniprintf(menu_row2, LCD_ROW_LEN+1, "%d deg", (video_modes[cm.id].sampler_phase*1125)/100);
+                strncpy((char*)osd->osd_array.data[1][0], menu_row2, OSD_CHAR_COLS);
+                osd->osd_config.status_refresh = 1;
+                osd->osd_row_color.mask = 0;
+                osd->osd_sec_enable[0].mask = 3;
+                osd->osd_sec_enable[1].mask = 0;
+            } else if (get_current_menunavi()->m == &menu_advtiming) {
+                render_osd_page();
+            }
             break;
-        case RC_PHASE_PLUS: video_modes[cm.id].sampler_phase = (video_modes[cm.id].sampler_phase < SAMPLER_PHASE_MAX) ? (video_modes[cm.id].sampler_phase + 1) : 0; update_cur_vm = 1; break;
-        case RC_PHASE_MINUS: video_modes[cm.id].sampler_phase = video_modes[cm.id].sampler_phase ? (video_modes[cm.id].sampler_phase - 1) : SAMPLER_PHASE_MAX; update_cur_vm = 1; break;
         case RC_PROF_HOTKEY:
+Prof_Hotkey_Prompt:
             strncpy(menu_row1, "Profile load:", LCD_ROW_LEN+1);
-            strncpy(menu_row2, "press 0-9", LCD_ROW_LEN+1);
-            lcd_write_menu();
+            sniprintf(menu_row2, LCD_ROW_LEN+1, "press %u-%u", prof_x10*10, ((prof_x10*10+9) > MAX_PROFILE) ? MAX_PROFILE : (prof_x10*10+9));
+            osd->osd_config.menu_active = 1;
+            ui_disp_menu(1);
 
             while (1) {
                 btn_vec = IORD_ALTERA_AVALON_PIO_DATA(PIO_1_BASE) & RC_MASK;
-                for (i = RC_BTN1; i < REMOTE_MAX_KEYS; i++) {
-                    if (btn_vec == rc_keymap[i])
+
+                if ((btn_vec_prev == 0) && (btn_vec != 0)) {
+                    for (i = RC_BTN1; i < REMOTE_MAX_KEYS; i++) {
+                        if (btn_vec == rc_keymap[i])
+                            break;
+                    }
+
+                    if ((i == RC_BTN0) || (i < (RC_BTN1 + (prof_x10 == (MAX_PROFILE/10)) ? (MAX_PROFILE%10) : 9))) {
+                        profile_sel_menu = prof_x10*10 + ((i+1)%10);
+                        retval = load_profile();
+                        sniprintf(menu_row2, LCD_ROW_LEN+1, "%s", (retval==0) ? "Done" : "Failed");
+                        ui_disp_menu(1);
+                        usleep(500000);
                         break;
+                    } else if (i == RC_PROF_HOTKEY) {
+                        prof_x10 = (prof_x10+1) % ((MAX_PROFILE/10)+1);
+                        btn_vec_prev = btn_vec;
+                        goto Prof_Hotkey_Prompt;
+                    } else if (i == RC_BACK) {
+                        break;
+                    }
                 }
 
-                if (i <= RC_BTN0) {
-                    profile_sel_menu = (i+1)%10;
-                    load_profile();
-                    break;
-                } else if (i == RC_BACK) {
-                    break;
-                }
-
+                btn_vec_prev = btn_vec;
                 usleep(WAITLOOP_SLEEP_US);
             }
-            lcd_write_status();
+
             menu_active = 0;
+            osd->osd_config.menu_active = 0;
+            ui_disp_status(0);
             break;
         case RC_RIGHT:
             if (!menu_active)

software/sys_controller/ossc/fat16_export.c

@@ -0,0 +1,133 @@
+//
+// Copyright (C) 2020 Ari Sundholm <megari@iki.fi>
+//
+// This file has been contributed to the Open Source Scan Converter project
+// developed by Markus Hiienkari Markus Hiienkari <mhiienka@niksula.hut.fi>
+// and other members of the retro gaming community.
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#include <string.h>
+#include "fat16_export.h"
+
+/*
+ * The beginning of the boot sector, along with the BPB.
+ */
+static const alt_u8 bootsec_beg_bpb_16[27] = {
+    0xeb, 0x00, 0x90,                               /* 0x000: Code (x86 short jump + NOP) */
+    0x4d, 0x53, 0x57, 0x49, 0x4e, 0x34, 0x2e, 0x31, /* 0x003: OS Name */
+    0x00, 0x02, 0x04, 0x80, 0x00, 0x02, 0x00, 0x08, /* 0x00B: Bios Parameter Block */
+    0x00, 0x80, 0xf8, 0x20, 0x00, 0x3f, 0x00, 0xff,
+};
+
+/*
+ * The rest of the boot sector before the boot code and terminator.
+ * Offsets 0x024 to 0x03d, inclusive.
+ */
+static const alt_u8 bootsec_after_bpb_16[26] = {
+    /* Zeros             */ 0x80, 0x00, 0x29, 0xf4, /* 0x024...0x027 */
+    0xcf, 0xc6, 0x04, 0x4f, 0x53, 0x53, 0x43, 0x50, /* 0x028...0x02f */
+    0x52, 0x4f, 0x46, 0x49, 0x4c, 0x53, 0x46, 0x41, /* 0x030...0x037 */
+    0x54, 0x31, 0x36, 0x20, 0x20, 0x20, /* Zeros */ /* 0x038...0x03d */
+};
+
+/*
+ * After this, we have the boot code (448 bytes) and sector terminator
+ * (2 bytes). The former will be left zeroed-out and the latter will
+ * be generated.
+ */
+
+/* Generates a FAT16 boot sector.
+ * buf must be at least FAT16_SECTOR_SIZE bytes long,
+ * and is assumed to be pre-zeroed.
+ */
+void generate_boot_sector_16(alt_u8 *const buf) {
+    /* Initial FAT16 boot sector contents + the BPB. */
+    memcpy(buf, bootsec_beg_bpb_16, sizeof(bootsec_beg_bpb_16));
+
+    /*
+     * Then the rest of the boot sector.
+     *
+     * The boot code is supposed to be 448 bytes filled with 0xf4,
+     * but leave it zeroed out to keep the code smaller. This may
+     * be a deviation from the FAT16 spec, but should be harmless
+     * for our purposes.
+     */
+    memcpy(buf + 36, bootsec_after_bpb_16, sizeof(bootsec_after_bpb_16));
+
+    /* RISC-V is little-endian, so do a 16-bit write instead. */
+    *((alt_u16*)(buf + 510)) = 0xaa55U;
+}
+
+/* The fixed 'preamble' of a FAT on a FAT16 volume. */
+static const alt_u32 fat16_preamble = 0xfffffff8U;
+
+/*
+ * Generate a FAT.
+ * The buffer is assumed to be zeroed out and have a size of at least
+ * FAT16_SECTOR_SIZE bytes.
+ * The number of clusters already written is given as an argument.
+ * The function returns the total number of clusters written so far.
+ *
+ * The intention is to be able to generate and write the FAT in chunks
+ * that do not exhaust all the remaining RAM.
+ */
+alt_u16 generate_fat16(void *const buf, const alt_u16 written) {
+	alt_u16 cur_ofs = 0;
+    const alt_u16 start_cluster = 3U + written;
+    alt_u16 *const fat = buf;
+
+    /*
+     * The total number of FAT entries to write consists of:
+     * 1. The FAT "preamble" (2 entries),
+     * 2. The cluster chain of the file (512 entries).
+     *
+     * The latter needs to contain the chain terminator.
+     */
+    const alt_u16 clusters_remaining = PROF_16_CLUSTER_COUNT - written;
+    const alt_u16 preamble_compensation = written ? 0 : 2U;
+    const alt_u16 clusters_to_write =
+        ((clusters_remaining > FAT16_ENTRIES_PER_SECTOR)
+            ? FAT16_ENTRIES_PER_SECTOR
+            : clusters_remaining) - preamble_compensation;
+    const alt_u16 end_cluster = start_cluster + clusters_to_write;
+    const alt_u16 last_fat_cluster = PROF_16_CLUSTER_COUNT + 2U;
+
+    if (!written) {
+        *((alt_u32*)fat) = fat16_preamble;
+        cur_ofs += sizeof(fat16_preamble)/sizeof(alt_u16);
+    }
+
+    for (alt_u16 cluster = start_cluster; cluster < end_cluster; ++cluster) {
+        alt_u16 *const cur_entry = fat + cur_ofs;
+        /* FAT16 entries are 16-bit little-endian. */
+        if (cluster == last_fat_cluster) {
+            /* At the last cluster, write the chain terminator. */
+            *cur_entry = 0xffffU;
+        }
+        else {
+            *cur_entry = cluster;
+        }
+        ++cur_ofs;
+    }
+
+    return end_cluster - 3U;
+}
+
+const alt_u8 prof_dirent_16[PROF_DIRENT_16_SIZE] = {
+    0x4f, 0x53, 0x53, 0x43, 0x50, 0x52, 0x4f, 0x46, 0x42, 0x49, 0x4e, 0x20,
+    0x00, 0x8e, 0x04, 0xb5, 0x6f, 0x51, 0x6f, 0x51, 0x00, 0x00, 0x17, 0x89,
+    0x6f, 0x51, 0x02, 0x00, 0x00, 0x02, 0x10, 0x00,
+};

software/sys_controller/ossc/fat16_export.h

@@ -0,0 +1,83 @@
+//
+// Copyright (C) 2020 Ari Sundholm <megari@iki.fi>
+//
+// This file has been contributed to the Open Source Scan Converter project
+// developed by Markus Hiienkari Markus Hiienkari <mhiienka@niksula.hut.fi>
+// and other members of the retro gaming community.
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#ifndef FAT16_EXPORT_H_
+#define FAT16_EXPORT_H_
+
+#include "alt_types.h"
+
+/* Use a sector size of 512 bytes. */
+#define FAT16_SECTOR_SIZE 512U
+
+/* This volume has 2048-byte clusters. */
+#define FAT16_CLUSTER_SIZE 2048U
+#define FAT16_SECTORS_PER_CLUSTER (FAT16_CLUSTER_SIZE/FAT16_SECTOR_SIZE)
+
+/* Offsets of the two File Allocation Tables. */
+#define FAT16_1_OFS 0x10000UL
+#define FAT16_2_OFS 0x14000UL
+
+/* Each FAT16 entry is a 16-bit little-endian integer. */
+#define FAT16_ENTRY_SIZE 2U
+#define FAT16_ENTRY_SHIFT 1U
+#define FAT16_ENTRIES_PER_SECTOR (FAT16_SECTOR_SIZE >> FAT16_ENTRY_SHIFT)
+
+/* On this volume, each FAT will be 16 kiB in size. */
+#define FAT16_SIZE 0x04000UL
+
+/* The first sector of the root directory. */
+#define FAT16_ROOT_DIR_FIRST_SECTOR 192U
+
+/* The length of the root directory in sectors. */
+#define FAT16_ROOT_DIR_SECTORS 128U
+
+/*
+ * Define the properties and contents of the directory entry for the
+ * settings file.
+ */
+#define PROF_DIRENT_16_OFS  0x18000UL
+#define PROF_DIRENT_16_SIZE 32U
+
+extern const alt_u8 prof_dirent_16[PROF_DIRENT_16_SIZE];
+
+#define PROF_16_DATA_OFS  0x028000UL
+#define PROF_16_DATA_SIZE 0x100200UL
+#define PROF_16_CLUSTER_COUNT ((PROF_16_DATA_SIZE/FAT16_CLUSTER_SIZE)+!!(PROF_16_DATA_SIZE%FAT16_CLUSTER_SIZE))
+/* Profile file data starts at offset 0x00028000 */
+/* Profile file data  ends  at offset 0x00128200 */
+/* Profile file data is 1049088 bytes long. */
+
+
+/* Generate a FAT16 boot sector.
+ * buf must be at least FAT16_BOOT_SECTOR_SIZE bytes long,
+ * and is assumed to be pre-zeroed.
+ */
+void generate_boot_sector_16(alt_u8 *buf);
+
+/*
+ * Generate a FAT of a FAT16 volume.
+ * The buffer is assumed to be zeroed out and have a size of at least 512 bytes.
+ * The number of clusters already written are given as an argument.
+ * The function returns the total number of clusters written so far.
+ */
+alt_u16 generate_fat16(void *buf, alt_u16 written);
+
+#endif // FAT16_EXPORT_H_

software/sys_controller/ossc/firmware.c

@@ -27,6 +27,7 @@
 #include "av_controller.h"
 #include "lcd.h"
 #include "utils.h"
+#include "menu.h"
 #include "altera_avalon_pio_regs.h"
 
 extern char menu_row1[LCD_ROW_LEN+1], menu_row2[LCD_ROW_LEN+1];
@@ -71,15 +72,14 @@ static int check_fw_header(alt_u8 *databuf, fw_hdr *hdr)
 static int check_fw_image(alt_u32 offset, alt_u32 size, alt_u32 golden_crc, alt_u8 *tmpbuf)
 {
     alt_u32 crcval=0, i, bytes_to_read;
-    int retval;
+    SDRESULTS res;
 
     for (i=0; i<size; i=i+SD_BLK_SIZE) {
         bytes_to_read = ((size-i < SD_BLK_SIZE) ? (size-i) : SD_BLK_SIZE);
-        retval = SD_Read(&sdcard_dev, tmpbuf, (offset+i)/SD_BLK_SIZE, 0, bytes_to_read);
-        //retval = read_sd_block(offset+i, bytes_to_read, tmpbuf);
+        res = SD_Read(&sdcard_dev, tmpbuf, (offset+i)/SD_BLK_SIZE, 0, bytes_to_read);
 
-        if (retval != SD_OK)
-            return retval;
+        if (res != SD_OK)
+            return -res;
 
         crcval = crc32(tmpbuf, bytes_to_read, (i==0));
     }
@@ -106,14 +106,16 @@ int fw_update()
     asm volatile("mov %0, sp" : "=r"(sp));
     sniprintf(menu_row1, LCD_ROW_LEN+1, "Stack size:");
     sniprintf(menu_row2, LCD_ROW_LEN+1, "%lu bytes", (ONCHIP_MEMORY2_0_BASE+ONCHIP_MEMORY2_0_SIZE_VALUE)-sp);
-    lcd_write_menu();
+    ui_disp_menu(1);
     usleep(1000000);
 #endif
 
     retval = check_sdcard(databuf);
     SPI_CS_High();
-    if (retval != 0)
+    if (retval != 0) {
+        retval = -retval;
         goto failure;
+    }
 
     retval = check_fw_header(databuf, &fw_header);
     if (retval != 0)
@@ -121,14 +123,14 @@ int fw_update()
 
     sniprintf(menu_row1, LCD_ROW_LEN+1, "Validating data");
     sniprintf(menu_row2, LCD_ROW_LEN+1, "%u bytes", (unsigned)fw_header.data_len);
-    lcd_write_menu();
+    ui_disp_menu(1);
     retval = check_fw_image(512, fw_header.data_len, fw_header.data_crc, databuf);
     if (retval != 0)
         goto failure;
 
     sniprintf(menu_row1, LCD_ROW_LEN+1, "%u.%.2u%s%s", fw_header.version_major, fw_header.version_minor, (fw_header.version_suffix[0] == 0) ? "" : "-", fw_header.version_suffix);
     strncpy(menu_row2, "Update? 1=Y, 2=N", LCD_ROW_LEN+1);
-    lcd_write_menu();
+    ui_disp_menu(1);
 
     while (1) {
         btn_vec = IORD_ALTERA_AVALON_PIO_DATA(PIO_1_BASE) & RC_MASK;
@@ -152,7 +154,7 @@ int fw_update()
     strncpy(menu_row1, "Updating FW", LCD_ROW_LEN+1);
 update_init:
     strncpy(menu_row2, "please wait...", LCD_ROW_LEN+1);
-    lcd_write_menu();
+    ui_disp_menu(1);
 
     retval = copy_sd_to_flash(512/SD_BLK_SIZE, 0, fw_header.data_len, databuf);
     if (retval != 0)
@@ -160,7 +162,7 @@ update_init:
 
     strncpy(menu_row1, "Verifying flash", LCD_ROW_LEN+1);
     strncpy(menu_row2, "please wait...", LCD_ROW_LEN+1);
-    lcd_write_menu();
+    ui_disp_menu(1);
     retval = verify_flash(0, fw_header.data_len, fw_header.data_crc, databuf);
     if (retval != 0)
         goto failure;
@@ -169,7 +171,7 @@ update_init:
 
     strncpy(menu_row1, "Firmware updated", LCD_ROW_LEN+1);
     strncpy(menu_row2, "please restart", LCD_ROW_LEN+1);
-    lcd_write_menu();
+    ui_disp_menu(1);
     while (1) {}
 
     return 0;
@@ -196,24 +198,15 @@ failure:
         case FW_UPD_CANCELLED:
             errmsg = "Update cancelled";
             break;
-        case -FLASH_READ_ERROR:
-            errmsg = "Flash read err";
-            break;
-        case -FLASH_ERASE_ERROR:
-            errmsg = "Flash erase err";
-            break;
-        case -FLASH_WRITE_ERROR:
-            errmsg = "Flash write err";
-            break;
         case -FLASH_VERIFY_ERROR:
             errmsg = "Flash verif fail";
             break;
         default:
-            errmsg = "Error";
+            errmsg = "SD/Flash error";
             break;
     }
     strncpy(menu_row2, errmsg, LCD_ROW_LEN+1);
-    lcd_write_menu();
+    ui_disp_menu(1);
     usleep(1000000);
 
     // Critical error, retry update
@@ -223,5 +216,6 @@ failure:
         goto update_init;
     }
 
+    render_osd_page();
     return -1;
 }

software/sys_controller/ossc/firmware.h

@@ -1,5 +1,5 @@
 //
-// Copyright (C) 2015-2017  Markus Hiienkari <mhiienka@niksula.hut.fi>
+// Copyright (C) 2015-2022  Markus Hiienkari <mhiienka@niksula.hut.fi>
 //
 // This file is part of Open Source Scan Converter project.
 //
@@ -24,7 +24,13 @@
 #include "sysconfig.h"
 
 #define FW_VER_MAJOR            0
-#define FW_VER_MINOR            83
+#define FW_VER_MINOR            90
+
+#define PROFILE_VER_MAJOR       0
+#define PROFILE_VER_MINOR       88
+
+#define INITCFG_VER_MAJOR       0
+#define INITCFG_VER_MINOR       85
 
 #ifdef ENABLE_AUDIO
 #define FW_SUFFIX1              "a"

software/sys_controller/ossc/menu.c

@@ -29,12 +29,6 @@
 #define OPT_NOWRAP  0
 #define OPT_WRAP    1
 
-#ifdef OSDLANG_JP
-#define LNG(e, j) j
-#else
-#define LNG(e, j) e
-#endif
-
 extern char row1[LCD_ROW_LEN+1], row2[LCD_ROW_LEN+1], menu_row1[LCD_ROW_LEN+1], menu_row2[LCD_ROW_LEN+1];
 extern avmode_t cm;
 extern avconfig_t tc;
@@ -44,27 +38,30 @@ extern alt_u16 rc_keymap[REMOTE_MAX_KEYS];
 extern alt_u8 vm_sel, profile_sel_menu, lt_sel, def_input, profile_link, lcd_bl_timeout;
 extern alt_u8 auto_input, auto_av1_ypbpr, auto_av2_ypbpr, auto_av3_ypbpr;
 extern alt_u8 update_cur_vm;
+extern alt_u8 osd_enable, osd_status_timeout;
 extern char target_profile_name[PROFILE_NAME_LEN+1];
+extern volatile osd_regs *osd;
 
-alt_u16 tc_h_samplerate, tc_h_samplerate_adj, tc_h_synclen, tc_h_bporch, tc_h_active, tc_v_synclen, tc_v_bporch, tc_v_active;
-alt_u8 tc_sampler_phase;
+alt_u16 tc_h_samplerate, tc_h_samplerate_adj, tc_h_synclen, tc_h_bporch, tc_h_active, tc_v_synclen, tc_v_bporch, tc_v_active, tc_sampler_phase;
 alt_u8 menu_active;
 alt_u8 vm_sel, vm_edit;
 
 static const char *off_on_desc[] = { LNG("Off","ｵﾌ"), LNG("On","ｵﾝ") };
 static const char *video_lpf_desc[] = { LNG("Auto","ｵｰﾄ"), LNG("Off","ｵﾌ"), "95MHz (HDTV II)", "35MHz (HDTV I)", "16MHz (EDTV)", "9MHz (SDTV)" };
 static const char *ypbpr_cs_desc[] = { "Rec. 601", "Rec. 709", "Auto" };
-static const char *s480p_mode_desc[] = { LNG("Auto","ｵｰﾄ"), "DTV 480p", "VESA 640x480@60" };
+static const char *s480p_mode_desc[] = { LNG("Auto","ｵｰﾄ"), "DTV 480p", "VESA 640x480@60", "PSP 480x272" };
+static const char *s400p_mode_desc[] = { "VGA 640x400@70", "VGA 720x400@70" };
 static const char *sync_lpf_desc[] = { LNG("2.5MHz (max)","2.5MHz (ｻｲﾀﾞｲ)"), LNG("10MHz (med)","10MHz (ﾁｭｳｲ)"), LNG("33MHz (min)","33MHz (ｻｲｼｮｳ)"), LNG("Off","ｵﾌ") };
-static const char *l3_mode_desc[] = { LNG("Generic 16:9","ｼﾞｪﾈﾘｯｸ 16:9"), LNG("Generic 4:3","ｼﾞｪﾈﾘｯｸ 4:3"), LNG("512x240 optim.","512x240 ｻｲﾃｷｶ."), LNG("320x240 optim.","320x240 ｻｲﾃｷｶ."), LNG("256x240 optim.","256x240 ｻｲﾃｷｶ.") };
-static const char *l2l4l5_mode_desc[] = { LNG("Generic 4:3","ｼﾞｪﾈﾘｯｸ 4:3"), LNG("512x240 optim.","512x240 ｻｲﾃｷｶ."), LNG("320x240 optim.","320x240 ｻｲﾃｷｶ."), LNG("256x240 optim.","256x240 ｻｲﾃｷｶ.") };
+static const char *stc_lpf_desc[] = { "4.8MHz (HDTV/PC)", "0.5MHz (SDTV)", "1.7MHz (EDTV)" };
+static const char *l3_mode_desc[] = { LNG("Generic 16:9","ｼﾞｪﾈﾘｯｸ 16:9"), LNG("Generic 4:3","ｼﾞｪﾈﾘｯｸ 4:3"), LNG("512x240 optim.","512x240 ｻｲﾃｷｶ."), LNG("384x240 optim.","384x240 ｻｲﾃｷｶ."), LNG("320x240 optim.","320x240 ｻｲﾃｷｶ."), LNG("256x240 optim.","256x240 ｻｲﾃｷｶ.") };
+static const char *l2l4l5_mode_desc[] = { LNG("Generic 4:3","ｼﾞｪﾈﾘｯｸ 4:3"), LNG("512x240 optim.","512x240 ｻｲﾃｷｶ."), LNG("384x240 optim.","384x240 ｻｲﾃｷｶ."), LNG("320x240 optim.","320x240 ｻｲﾃｷｶ."), LNG("256x240 optim.","256x240 ｻｲﾃｷｶ.") };
 static const char *l5_fmt_desc[] = { "1920x1080", "1600x1200", "1920x1200" };
 static const char *pm_240p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x", "Line3x", "Line4x", "Line5x" };
 static const char *pm_480i_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x (bob)", "Line3x (laced)", "Line4x (bob)" };
-static const char *pm_384p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x", "Line2x 240x360", "Line3x 240x360" };
+static const char *pm_384p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x", "Line2x 240x360", "Line3x 240x360", "Line3x Generic" };
 static const char *pm_480p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x" };
 static const char *pm_1080i_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x (bob)" };
-static const char *ar_256col_desc[] = { "4:3", "8:7" };
+static const char *ar_256col_desc[] = { "Pseudo 4:3 DAR", "1:1 PAR" };
 static const char *tx_mode_desc[] = { "HDMI (RGB)", "HDMI (YCbCr444)", "DVI" };
 static const char *sl_mode_desc[] = { LNG("Off","ｵﾌ"), LNG("Auto","ｵｰﾄ"), LNG("On","ｵﾝ") };
 static const char *sl_method_desc[] = { LNG("Multiplication","Multiplication"), LNG("Subtraction","Subtraction") };
@@ -73,8 +70,12 @@ static const char *sl_id_desc[] = { LNG("Top","ｳｴ"), LNG("Bottom","ｼﾀ")
 static const char *audio_dw_sampl_desc[] = { LNG("Off (fs = 96kHz)","ｵﾌ (fs = 96kHz)"), "2x  (fs = 48kHz)" };
 static const char *lt_desc[] = { "Top-left", "Center", "Bottom-right" };
 static const char *lcd_bl_timeout_desc[] = { "Off", "3s", "10s", "30s" };
+static const char *osd_enable_desc[] = { "Off", "Full", "Simple" };
+static const char *osd_status_desc[] = { "2s", "5s", "10s", "Off" };
 static const char *rgsb_ypbpr_desc[] = { "RGsB", "YPbPr" };
 static const char *auto_input_desc[] = { "Off", "Current input", "All inputs" };
+static const char *mask_color_desc[] = { "Black", "Blue", "Green", "Cyan", "Red", "Magenta", "Yellow", "White" };
+static const char *av3_alt_rgb_desc[] = { "Off", "AV1", "AV2" };
 
 static void sync_vth_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%d mV", (v*1127)/100); }
 static void intclks_to_time_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%u.%.2u us", (unsigned)(((1000000U*v)/(TVP_INTCLK_HZ/1000))/1000), (unsigned)((((1000000U*v)/(TVP_INTCLK_HZ/1000))%1000)/10)); }
@@ -84,12 +85,15 @@ static void sl_cust_str_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%u
 static void sl_hybr_str_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%u%%", (v*625)/100); }
 static void lines_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, LNG("%u lines","%u ﾗｲﾝ"), v); }
 static void pixels_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, LNG("%u pixels","%u ﾄﾞｯﾄ"), v); }
-static void value_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "    %u", v); }
+static void value_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%u", v); }
+static void signed_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%d", (alt_8)(v-SIGNED_NUMVAL_ZERO)); }
 static void lt_disp(alt_u8 v) { strncpy(menu_row2, lt_desc[v], LCD_ROW_LEN+1); }
 static void aud_db_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%d dB", ((alt_8)v-AUDIO_GAIN_0DB)); }
 static void vm_display_name (alt_u8 v) { strncpy(menu_row2, video_modes[v].name, LCD_ROW_LEN+1); }
 static void link_av_desc (avinput_t v) { strncpy(menu_row2, v == AV_LAST ? "No link" : avinput_str[v], LCD_ROW_LEN+1); }
 static void profile_disp(alt_u8 v) { read_userdata(v, 1); sniprintf(menu_row2, LCD_ROW_LEN+1, "%u: %s", v, (target_profile_name[0] == 0) ? "<empty>" : target_profile_name); }
+static void alc_v_filter_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, LNG("%u lines","%u ﾗｲﾝ"), (1<<v)); }
+static void alc_h_filter_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, LNG("%u pixels","%u ﾄﾞｯﾄ"), (1<<(v+1))); }
 //static void coarse_gain_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%u.%u", ((v*10)+50)/100, (((v*10)+50)%100)/10); }
 
 static const arg_info_t vm_arg_info = {&vm_sel, VIDEO_MODES_CNT-1, vm_display_name};
@@ -99,14 +103,14 @@ static const arg_info_t lt_arg_info = {&lt_sel, (sizeof(lt_desc)/sizeof(char*))-
 
 MENU(menu_advtiming, P99_PROTECT({ \
     { LNG("H. samplerate","H. ｻﾝﾌﾟﾙﾚｰﾄ"),        OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_h_samplerate, H_TOTAL_MIN,   H_TOTAL_MAX, vm_tweak } } },
-    { "H. s.rate adj",                           OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_h_samplerate_adj, 0,  H_TOTAL_ADJ_MAX, vm_tweak } } },
+    { "H. s.rate frac",                           OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_h_samplerate_adj, 0,  H_TOTAL_ADJ_MAX, vm_tweak } } },
     { LNG("H. synclen","H. ﾄﾞｳｷﾅｶﾞｻ"),       OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_h_synclen,    H_SYNCLEN_MIN, H_SYNCLEN_MAX, vm_tweak } } },
     { LNG("H. backporch","H. ﾊﾞｯｸﾎﾟｰﾁ"),        OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_h_bporch,     H_BPORCH_MIN,  H_BPORCH_MAX, vm_tweak } } },
     { LNG("H. active","H. ｱｸﾃｨﾌﾞ"),             OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_h_active,     H_ACTIVE_MIN,  H_ACTIVE_MAX, vm_tweak } } },
     { LNG("V. synclen","V. ﾄﾞｳｷﾅｶﾞｻ"),       OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_v_synclen,    V_SYNCLEN_MIN, V_SYNCLEN_MAX, vm_tweak } } },
     { LNG("V. backporch","V. ﾊﾞｯｸﾎﾟｰﾁ"),       OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_v_bporch,     V_BPORCH_MIN,  V_BPORCH_MAX, vm_tweak } } },
     { LNG("V. active","V. ｱｸﾃｨﾌﾞ"),            OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_v_active,     V_ACTIVE_MIN,  V_ACTIVE_MAX, vm_tweak } } },
-    { LNG("Sampling phase","ｻﾝﾌﾟﾘﾝｸﾞﾌｪｰｽﾞ"),     OPT_AVCONFIG_NUMVALUE,  { .num = { &tc_sampler_phase, OPT_WRAP, 0, SAMPLER_PHASE_MAX, sampler_phase_tweak } } },
+    { LNG("Sampling phase","ｻﾝﾌﾟﾘﾝｸﾞﾌｪｰｽﾞ"),     OPT_AVCONFIG_NUMVAL_U16,  { .num_u16 = { &tc_sampler_phase, 0, SAMPLER_PHASE_MAX, vm_tweak } } },
 }))
 
 MENU(menu_cust_sl, P99_PROTECT({ \
@@ -134,10 +138,14 @@ MENU(menu_vinputproc, P99_PROTECT({ \
     { LNG("G/Y gain","G/Y ｹﾞｲﾝ"),               OPT_AVCONFIG_NUMVALUE,  { .num = { &tc.col.g_f_gain,  OPT_NOWRAP, 0, 0xFF, value_disp } } },
     { LNG("B/Pb gain","B/Pb ｹﾞｲﾝ"),             OPT_AVCONFIG_NUMVALUE,  { .num = { &tc.col.b_f_gain,  OPT_NOWRAP, 0, 0xFF, value_disp } } },
     { LNG("Pre-ADC Gain","Pre-ADC Gain"),       OPT_AVCONFIG_NUMVALUE,  { .num = { &tc.col.c_gain,    OPT_NOWRAP, 0, COARSE_GAIN_MAX, value_disp } } },
+    { "Clamp/ALC offset",                       OPT_AVCONFIG_NUMVALUE,  { .num = { &tc.clamp_offset,  OPT_NOWRAP, CLAMP_OFFSET_MIN, CLAMP_OFFSET_MAX, signed_disp } } },
+    { "ALC V filter",                           OPT_AVCONFIG_NUMVALUE,  { .num = { &tc.alc_v_filter,  OPT_NOWRAP, 0, ALC_V_FILTER_MAX, alc_v_filter_disp } } },
+    { "ALC H filter",                           OPT_AVCONFIG_NUMVALUE,  { .num = { &tc.alc_h_filter,  OPT_NOWRAP, 0, ALC_H_FILTER_MAX, alc_h_filter_disp } } },
 }))
 
 MENU(menu_sampling, P99_PROTECT({ \
     { LNG("480p in sampler","ｻﾝﾌﾟﾗｰﾃﾞ480p"),     OPT_AVCONFIG_SELECTION, { .sel = { &tc.s480p_mode,    OPT_WRAP, SETTING_ITEM(s480p_mode_desc) } } },
+    { LNG("400p in sampler","ｻﾝﾌﾟﾗｰﾃﾞ400p"),     OPT_AVCONFIG_SELECTION, { .sel = { &tc.s400p_mode,    OPT_WRAP, SETTING_ITEM(s400p_mode_desc) } } },
     { LNG("Allow TVP HPLL2x","TVP HPLL2xｷｮﾖｳ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.tvp_hpll2x,   OPT_WRAP, SETTING_ITEM(off_on_desc) } } },
     { LNG("Allow upsample2x","ｱｯﾌﾟｻﾝﾌﾟﾙ2xｷｮﾖｳ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.upsample2x,   OPT_WRAP, SETTING_ITEM(off_on_desc) } } },
     { LNG("<Adv. timing   >","<ｶｸｼｭﾀｲﾐﾝｸﾞ>"),    OPT_SUBMENU,            { .sub = { &menu_advtiming, &vm_arg_info, vm_select } } },
@@ -145,6 +153,7 @@ MENU(menu_sampling, P99_PROTECT({ \
 
 MENU(menu_sync, P99_PROTECT({ \
     { LNG("Analog sync LPF","ｱﾅﾛｸﾞﾄﾞｳｷ LPF"),    OPT_AVCONFIG_SELECTION, { .sel = { &tc.sync_lpf,    OPT_WRAP,   SETTING_ITEM(sync_lpf_desc) } } },
+    { "Analog STC LPF",                         OPT_AVCONFIG_SELECTION, { .sel = { &tc.stc_lpf,    OPT_WRAP,   SETTING_ITEM(stc_lpf_desc) } } },
     { LNG("Analog sync Vth","ｱﾅﾛｸﾞﾄﾞｳｷ Vth"),    OPT_AVCONFIG_NUMVALUE,  { .num = { &tc.sync_vth,    OPT_NOWRAP, 0, SYNC_VTH_MAX, sync_vth_disp } } },
     { LNG("Hsync tolerance","Hsyncｺｳｻ"),        OPT_AVCONFIG_NUMVALUE,  { .num = { &tc.linelen_tol, OPT_NOWRAP, 0, 0xFF, intclks_to_time_disp } } },
     { LNG("Vsync threshold","Vsyncｼｷｲﾁ"),       OPT_AVCONFIG_NUMVALUE,  { .num = { &tc.vsync_thold, OPT_NOWRAP, VSYNC_THOLD_MIN, VSYNC_THOLD_MAX, intclks_to_time_disp } } },
@@ -154,7 +163,7 @@ MENU(menu_sync, P99_PROTECT({ \
 
 MENU(menu_output, P99_PROTECT({ \
     { LNG("240p/288p proc","240p/288pｼｮﾘ"),     OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_240p,         OPT_WRAP, SETTING_ITEM(pm_240p_desc) } } },
-    { LNG("384p proc","384pｼｮﾘ"),               OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_384p,         OPT_WRAP, SETTING_ITEM(pm_384p_desc) } } },
+    { LNG("384p/400p proc","384p/400pｼｮﾘ"),     OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_384p,         OPT_WRAP, SETTING_ITEM(pm_384p_desc) } } },
     { LNG("480i/576i proc","480i/576iｼｮﾘ"),     OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_480i,         OPT_WRAP, SETTING_ITEM(pm_480i_desc) } } },
     { LNG("480p/576p proc","480p/576pｼｮﾘ"),     OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_480p,         OPT_WRAP, SETTING_ITEM(pm_480p_desc) } } },
     { LNG("960i/1080i proc","960i/1080iｼｮﾘ"),   OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_1080i,        OPT_WRAP, SETTING_ITEM(pm_1080i_desc) } } },
@@ -183,6 +192,7 @@ MENU(menu_scanlines, P99_PROTECT({ \
 MENU(menu_postproc, P99_PROTECT({ \
     { LNG("Horizontal mask","ｽｲﾍｲﾏｽｸ"),           OPT_AVCONFIG_NUMVALUE,  { .num = { &tc.h_mask,      OPT_NOWRAP, 0, H_MASK_MAX, pixels_disp } } },
     { LNG("Vertical mask","ｽｲﾁｮｸﾏｽｸ"),            OPT_AVCONFIG_NUMVALUE,  { .num = { &tc.v_mask,      OPT_NOWRAP, 0, V_MASK_MAX, pixels_disp } } },
+    { "Mask color",                              OPT_AVCONFIG_SELECTION, { .sel = { &tc.mask_color,  OPT_NOWRAP,   SETTING_ITEM(mask_color_desc) } } },
     { LNG("Mask brightness","ﾏｽｸｱｶﾙｻ"),           OPT_AVCONFIG_NUMVALUE,  { .num = { &tc.mask_br,     OPT_NOWRAP, 0, HV_MASK_MAX_BR, value_disp } } },
     { LNG("Reverse LPF","ｷﾞｬｸLPF"),              OPT_AVCONFIG_NUMVALUE,  { .num = { &tc.reverse_lpf, OPT_NOWRAP, 0, REVERSE_LPF_MAX, value_disp } } },
     { LNG("<DIY lat. test>","DIYﾁｴﾝﾃｽﾄ"),         OPT_FUNC_CALL,          { .fun = { latency_test, &lt_arg_info } } },
@@ -191,6 +201,9 @@ MENU(menu_postproc, P99_PROTECT({ \
 MENU(menu_compatibility, P99_PROTECT({ \
     { LNG("Full TX setup","ﾌﾙTXｾｯﾄｱｯﾌﾟ"),         OPT_AVCONFIG_SELECTION, { .sel = { &tc.full_tx_setup,    OPT_WRAP, SETTING_ITEM(off_on_desc) } } },
     { LNG("AV3 interlacefix","AV3ｲﾝﾀｰﾚｰｽｼｭｳｾｲ"),  OPT_AVCONFIG_SELECTION, { .sel = { &tc.vga_ilace_fix,   OPT_WRAP, SETTING_ITEM(off_on_desc) } } },
+    { "AV3 use alt. RGB",                        OPT_AVCONFIG_SELECTION, { .sel = { &tc.av3_alt_rgb,     OPT_WRAP, SETTING_ITEM(av3_alt_rgb_desc) } } },
+    { "Default HDMI VIC",                       OPT_AVCONFIG_NUMVALUE,  { .num = { &tc.default_vic,     OPT_NOWRAP, 0, HDMI_1080p50, value_disp } } },
+    { "Panasonic hack",                        OPT_AVCONFIG_SELECTION, { .sel = { &tc.panasonic_hack,   OPT_WRAP, SETTING_ITEM(off_on_desc) } } },
 }))
 
 #ifdef ENABLE_AUDIO
@@ -207,7 +220,7 @@ MENU(menu_audio, P99_PROTECT({ \
 MENU(menu_settings, P99_PROTECT({ \
     { LNG("<Load profile >","<ﾌﾟﾛﾌｧｲﾙﾛｰﾄﾞ    >"),   OPT_FUNC_CALL,         { .fun = { load_profile, &profile_arg_info } } },
     { LNG("<Save profile >","<ﾌﾟﾛﾌｧｲﾙｾｰﾌﾞ    >"),  OPT_FUNC_CALL,          { .fun = { save_profile, &profile_arg_info } } },
-    { LNG("<Reset settings>","<ｾｯﾃｲｵｼｮｷｶ    >"),  OPT_FUNC_CALL,          { .fun = { set_default_avconfig, NULL } } },
+    { LNG("<Reset settings>","<ｾｯﾃｲｦｼｮｷｶ    >"),  OPT_FUNC_CALL,          { .fun = { set_default_avconfig, NULL } } },
     { LNG("Link prof->input","Link prof->input"), OPT_AVCONFIG_NUMVALUE,  { .num = { &tc.link_av,  OPT_WRAP, AV1_RGBs, AV_LAST, link_av_desc } } },
     { LNG("Link input->prof","Link input->prof"),   OPT_AVCONFIG_SELECTION, { .sel = { &profile_link,  OPT_WRAP, SETTING_ITEM(off_on_desc) } } },
     { LNG("Initial input","ｼｮｷﾆｭｳﾘｮｸ"),          OPT_AVCONFIG_SELECTION, { .sel = { &def_input,       OPT_WRAP, SETTING_ITEM(avinput_str) } } },
@@ -216,9 +229,12 @@ MENU(menu_settings, P99_PROTECT({ \
     { "Auto AV2 Y/Gs",                          OPT_AVCONFIG_SELECTION, { .sel = { &auto_av2_ypbpr,     OPT_WRAP, SETTING_ITEM(rgsb_ypbpr_desc) } } },
     { "Auto AV3 Y/Gs",                          OPT_AVCONFIG_SELECTION, { .sel = { &auto_av3_ypbpr,     OPT_WRAP, SETTING_ITEM(rgsb_ypbpr_desc) } } },
     { "LCD BL timeout",                         OPT_AVCONFIG_SELECTION, { .sel = { &lcd_bl_timeout,  OPT_WRAP, SETTING_ITEM(lcd_bl_timeout_desc) } } },
+    { "OSD",                                    OPT_AVCONFIG_SELECTION, { .sel = { &osd_enable,   OPT_WRAP,   SETTING_ITEM(osd_enable_desc) } } },
+    { "OSD status disp.",                       OPT_AVCONFIG_SELECTION, { .sel = { &osd_status_timeout,   OPT_WRAP,   SETTING_ITEM(osd_status_desc) } } },
 #ifndef DEBUG
-    {     "<Import sett.  >",                     OPT_FUNC_CALL,        { .fun = { import_userdata, NULL } } },
-    { LNG("<Fw. update    >","<ﾌｧｰﾑｳｪｱｱｯﾌﾟﾃﾞｰﾄ>"), OPT_FUNC_CALL,          { .fun = { fw_update, NULL } } },
+    { LNG("<Import sett.  >","<ｾｯﾃｲﾖﾐｺﾐ      >"), OPT_FUNC_CALL,        { .fun = { import_userdata, NULL } } },
+    { LNG("<Export sett.  >","<ｾｯﾃｲｶｷｺﾐ      >"), OPT_FUNC_CALL,        { .fun = { export_userdata, NULL } } },
+    { LNG("<Fw. update    >","<ﾌｧｰﾑｳｪｱｱｯﾌﾟﾃﾞｰﾄ>"), OPT_FUNC_CALL,        { .fun = { fw_update, NULL } } },
 #endif
 }))
 
@@ -230,9 +246,9 @@ MENU(menu_main, P99_PROTECT({ \
     { LNG("Output opt.    >","ｼｭﾂﾘｮｸｵﾌﾟｼｮﾝ  >"),  OPT_SUBMENU,            { .sub = { &menu_output, NULL, NULL } } },
     { LNG("Scanline opt.  >","ｽｷｬﾝﾗｲﾝｵﾌﾟｼｮﾝ >"),  OPT_SUBMENU,            { .sub = { &menu_scanlines, NULL, NULL } } },
     { LNG("Post-proc.     >","ｱﾄｼｮﾘ         >"),  OPT_SUBMENU,            { .sub = { &menu_postproc, NULL, NULL } } },
-    { LNG("Compatibility  >","ｺﾞｶﾝｾｲ        >"), OPT_SUBMENU,             { .sub = { &menu_compatibility, NULL, NULL } } },
+    { LNG("Compatibility  >","ｺﾞｶﾝｾｲ        >"),  OPT_SUBMENU,            { .sub = { &menu_compatibility, NULL, NULL } } },
     AUDIO_MENU
-    { "Settings opt   >",                       OPT_SUBMENU,             { .sub = { &menu_settings, NULL, NULL } } },
+    { LNG("Settings opt   >","ｾｯﾃｲｶﾝﾘ       >"),  OPT_SUBMENU,            { .sub = { &menu_settings, NULL, NULL } } },
 }))
 
 // Max 3 levels currently
@@ -240,12 +256,75 @@ menunavi navi[] = {{&menu_main, 0}, {NULL, 0}, {NULL, 0}};
 alt_u8 navlvl = 0;
 
 
+menunavi* get_current_menunavi() {
+    return &navi[navlvl];
+}
+
+void write_option_value(menuitem_t *item, int func_called, int retval)
+{
+    switch (item->type) {
+        case OPT_AVCONFIG_SELECTION:
+            strncpy(menu_row2, item->sel.setting_str[*(item->sel.data)], LCD_ROW_LEN+1);
+            break;
+        case OPT_AVCONFIG_NUMVALUE:
+            item->num.df(*(item->num.data));
+            break;
+        case OPT_AVCONFIG_NUMVAL_U16:
+            item->num_u16.df(item->num_u16.data);
+            break;
+        case OPT_SUBMENU:
+            if (item->sub.arg_info)
+                item->sub.arg_info->df(*item->sub.arg_info->data);
+            else
+                menu_row2[0] = 0;
+            break;
+        case OPT_FUNC_CALL:
+            if (func_called) {
+                if (retval == 0)
+                    strncpy(menu_row2, "Done", LCD_ROW_LEN+1);
+                else if (retval < 0)
+                    sniprintf(menu_row2, LCD_ROW_LEN+1, "Failed (%d)", retval);
+            } else if (item->fun.arg_info) {
+                item->fun.arg_info->df(*item->fun.arg_info->data);
+            } else {
+                menu_row2[0] = 0;
+            }
+            break;
+        default:
+            break;
+    }
+}
+
+void render_osd_page() {
+    int i;
+    menuitem_t *item;
+    uint32_t row_mask[2] = {0, 0};
+
+    if (!menu_active || (osd_enable != 1))
+        return;
+
+    for (i=0; i < navi[navlvl].m->num_items; i++) {
+        item = &navi[navlvl].m->items[i];
+        strncpy((char*)osd->osd_array.data[i][0], item->name, OSD_CHAR_COLS);
+        row_mask[0] |= (1<<i);
+
+        if ((item->type != OPT_SUBMENU) && (item->type != OPT_FUNC_CALL)) {
+            write_option_value(item, 0, 0);
+            strncpy((char*)osd->osd_array.data[i][1], menu_row2, OSD_CHAR_COLS);
+            row_mask[1] |= (1<<i);
+        }
+    }
+
+    osd->osd_sec_enable[0].mask = row_mask[0];
+    osd->osd_sec_enable[1].mask = row_mask[1];
+}
+
 void display_menu(alt_u8 forcedisp)
 {
     menucode_id code = NO_ACTION;
-    menuitem_type type;
+    menuitem_t *item;
     alt_u8 *val, val_wrap, val_min, val_max;
-    alt_u16 *val_u16;
+    alt_u16 *val_u16, val_u16_min, val_u16_max;
     int i, func_called = 0, retval = 0;
 
     for (i=RC_OK; i < RC_INFO; i++) {
@@ -258,39 +337,46 @@ void display_menu(alt_u8 forcedisp)
     if (!forcedisp && !remote_code)
         return;
 
-    type = navi[navlvl].m->items[navi[navlvl].mp].type;
+    item = &navi[navlvl].m->items[navi[navlvl].mp];
 
     // Parse menu control
     switch (code) {
     case PREV_PAGE:
-        navi[navlvl].mp = (navi[navlvl].mp == 0) ? navi[navlvl].m->num_items-1 : (navi[navlvl].mp-1);
-        break;
     case NEXT_PAGE:
-        navi[navlvl].mp = (navi[navlvl].mp+1) % navi[navlvl].m->num_items;
+        if ((item->type == OPT_FUNC_CALL) || (item->type == OPT_SUBMENU))
+            osd->osd_sec_enable[1].mask &= ~(1<<navi[navlvl].mp);
+
+        if (code == PREV_PAGE)
+            navi[navlvl].mp = (navi[navlvl].mp == 0) ? navi[navlvl].m->num_items-1 : (navi[navlvl].mp-1);
+        else
+            navi[navlvl].mp = (navi[navlvl].mp+1) % navi[navlvl].m->num_items;
         break;
     case PREV_MENU:
         if (navlvl > 0) {
             navlvl--;
+            render_osd_page();
         } else {
             menu_active = 0;
-            lcd_write_status();
+            osd->osd_config.menu_active = 0;
+            ui_disp_status(0);
             return;
         }
         break;
     case OPT_SELECT:
-        switch (navi[navlvl].m->items[navi[navlvl].mp].type) {
+        switch (item->type) {
             case OPT_SUBMENU:
-                if (navi[navlvl].m->items[navi[navlvl].mp].sub.arg_f)
-                    navi[navlvl].m->items[navi[navlvl].mp].sub.arg_f();
+                if (item->sub.arg_f)
+                    item->sub.arg_f();
 
-                if (navi[navlvl+1].m != navi[navlvl].m->items[navi[navlvl].mp].sub.menu)
+                if (navi[navlvl+1].m != item->sub.menu)
                     navi[navlvl+1].mp = 0;
-                navi[navlvl+1].m = navi[navlvl].m->items[navi[navlvl].mp].sub.menu;
+                navi[navlvl+1].m = item->sub.menu;
                 navlvl++;
+                render_osd_page();
 
                 break;
             case OPT_FUNC_CALL:
-                retval = navi[navlvl].m->items[navi[navlvl].mp].fun.f();
+                retval = item->fun.f();
                 func_called = 1;
                 break;
             default:
@@ -299,13 +385,13 @@ void display_menu(alt_u8 forcedisp)
         break;
     case VAL_MINUS:
     case VAL_PLUS:
-        switch (navi[navlvl].m->items[navi[navlvl].mp].type) {
+        switch (item->type) {
             case OPT_AVCONFIG_SELECTION:
             case OPT_AVCONFIG_NUMVALUE:
-                val = navi[navlvl].m->items[navi[navlvl].mp].sel.data;
-                val_wrap = navi[navlvl].m->items[navi[navlvl].mp].sel.wrap_cfg;
-                val_min = navi[navlvl].m->items[navi[navlvl].mp].sel.min;
-                val_max = navi[navlvl].m->items[navi[navlvl].mp].sel.max;
+                val = item->sel.data;
+                val_wrap = item->sel.wrap_cfg;
+                val_min = item->sel.min;
+                val_max = item->sel.max;
 
                 if (code == VAL_MINUS)
                     *val = (*val > val_min) ? (*val-1) : (val_wrap ? val_max : val_min);
@@ -313,17 +399,20 @@ void display_menu(alt_u8 forcedisp)
                     *val = (*val < val_max) ? (*val+1) : (val_wrap ? val_min : val_max);
                 break;
             case OPT_AVCONFIG_NUMVAL_U16:
-                val_u16 = navi[navlvl].m->items[navi[navlvl].mp].num_u16.data;
+                val_u16 = item->num_u16.data;
+                val_u16_min = item->num_u16.min;
+                val_u16_max = item->num_u16.max;
+                val_wrap = (val_u16_min == 0);
                 if (code == VAL_MINUS)
-                    *val_u16 = (*val_u16 > navi[navlvl].m->items[navi[navlvl].mp].num_u16.min) ? (*val_u16-1) : *val_u16;
+                    *val_u16 = (*val_u16 > val_u16_min) ? (*val_u16-1) : (val_wrap ? val_u16_max : val_u16_min);
                 else
-                    *val_u16 = (*val_u16 < navi[navlvl].m->items[navi[navlvl].mp].num_u16.max) ? (*val_u16+1) : *val_u16;
+                    *val_u16 = (*val_u16 < val_u16_max) ? (*val_u16+1) : (val_wrap ? val_u16_min : val_u16_max);
                 break;
             case OPT_SUBMENU:
-                val = navi[navlvl].m->items[navi[navlvl].mp].sub.arg_info->data;
-                val_max = navi[navlvl].m->items[navi[navlvl].mp].sub.arg_info->max;
+                val = item->sub.arg_info->data;
+                val_max = item->sub.arg_info->max;
 
-                if (navi[navlvl].m->items[navi[navlvl].mp].sub.arg_info) {
+                if (item->sub.arg_info) {
                     if (code == VAL_MINUS)
                         *val = (*val > 0) ? (*val-1) : 0;
                     else
@@ -331,10 +420,10 @@ void display_menu(alt_u8 forcedisp)
                 }
                 break;
             case OPT_FUNC_CALL:
-                val = navi[navlvl].m->items[navi[navlvl].mp].fun.arg_info->data;
-                val_max = navi[navlvl].m->items[navi[navlvl].mp].fun.arg_info->max;
+                val = item->fun.arg_info->data;
+                val_max = item->fun.arg_info->max;
 
-                if (navi[navlvl].m->items[navi[navlvl].mp].fun.arg_info) {
+                if (item->fun.arg_info) {
                     if (code == VAL_MINUS)
                         *val = (*val > 0) ? (*val-1) : 0;
                     else
@@ -350,37 +439,15 @@ void display_menu(alt_u8 forcedisp)
     }
 
     // Generate menu text
-    type = navi[navlvl].m->items[navi[navlvl].mp].type;
-    strncpy(menu_row1, navi[navlvl].m->items[navi[navlvl].mp].name, LCD_ROW_LEN+1);
-    switch (navi[navlvl].m->items[navi[navlvl].mp].type) {
-        case OPT_AVCONFIG_SELECTION:
-            strncpy(menu_row2, navi[navlvl].m->items[navi[navlvl].mp].sel.setting_str[*(navi[navlvl].m->items[navi[navlvl].mp].sel.data)], LCD_ROW_LEN+1);
-            break;
-        case OPT_AVCONFIG_NUMVALUE:
-            navi[navlvl].m->items[navi[navlvl].mp].num.df(*(navi[navlvl].m->items[navi[navlvl].mp].num.data));
-            break;
-        case OPT_AVCONFIG_NUMVAL_U16:
-            navi[navlvl].m->items[navi[navlvl].mp].num_u16.df(*(navi[navlvl].m->items[navi[navlvl].mp].num_u16.data));
-            break;
-        case OPT_SUBMENU:
-            if (navi[navlvl].m->items[navi[navlvl].mp].sub.arg_info)
-                navi[navlvl].m->items[navi[navlvl].mp].sub.arg_info->df(*navi[navlvl].m->items[navi[navlvl].mp].sub.arg_info->data);
-            else
-                menu_row2[0] = 0;
-            break;
-        case OPT_FUNC_CALL:
-            if (func_called)
-                sniprintf(menu_row2, LCD_ROW_LEN+1, "%s", (retval==0) ? "Done" : "Failed");
-            else if (navi[navlvl].m->items[navi[navlvl].mp].fun.arg_info)
-                navi[navlvl].m->items[navi[navlvl].mp].fun.arg_info->df(*navi[navlvl].m->items[navi[navlvl].mp].fun.arg_info->data);
-            else
-                menu_row2[0] = 0;
-            break;
-        default:
-            break;
-    }
+    item = &navi[navlvl].m->items[navi[navlvl].mp];
+    strncpy(menu_row1, item->name, LCD_ROW_LEN+1);
+    write_option_value(item, func_called, retval);
+    strncpy((char*)osd->osd_array.data[navi[navlvl].mp][1], menu_row2, OSD_CHAR_COLS);
+    osd->osd_row_color.mask = (1<<navi[navlvl].mp);
+    if (func_called || ((item->type == OPT_FUNC_CALL) && item->fun.arg_info != NULL) || ((item->type == OPT_SUBMENU) && item->sub.arg_info != NULL))
+        osd->osd_sec_enable[1].mask |= (1<<navi[navlvl].mp);
 
-    lcd_write_menu();
+    ui_disp_menu(0);
 }
 
 static void vm_select() {
@@ -396,7 +463,7 @@ static void vm_select() {
     tc_sampler_phase = video_modes[vm_edit].sampler_phase;
 }
 
-static void vm_tweak(alt_u16 v) {
+static void vm_tweak(alt_u16 *v) {
     if (cm.sync_active && (cm.id == vm_edit)) {
         if ((video_modes[cm.id].h_total != tc_h_samplerate) ||
             (video_modes[cm.id].h_total_adj != (alt_u8)tc_h_samplerate_adj) ||
@@ -405,7 +472,8 @@ static void vm_tweak(alt_u16 v) {
             (video_modes[cm.id].h_active != tc_h_active) ||
             (video_modes[cm.id].v_synclen != tc_v_synclen) ||
             (video_modes[cm.id].v_backporch != (alt_u8)tc_v_bporch) ||
-            (video_modes[cm.id].v_active != tc_v_active))
+            (video_modes[cm.id].v_active != tc_v_active) ||
+            (video_modes[cm.id].sampler_phase != tc_sampler_phase))
             update_cur_vm = 1;
     }
     video_modes[vm_edit].h_total = tc_h_samplerate;
@@ -416,14 +484,14 @@ static void vm_tweak(alt_u16 v) {
     video_modes[vm_edit].v_synclen = (alt_u8)tc_v_synclen;
     video_modes[vm_edit].v_backporch = (alt_u8)tc_v_bporch;
     video_modes[vm_edit].v_active = tc_v_active;
-
-    sniprintf(menu_row2, LCD_ROW_LEN+1, "%u", v);
-}
-
-static void sampler_phase_tweak(alt_u8 v) {
-    if (cm.sync_active && (cm.id == vm_edit) && (video_modes[cm.id].sampler_phase != tc_sampler_phase))
-        update_cur_vm = 1;
-
     video_modes[vm_edit].sampler_phase = tc_sampler_phase;
-    sniprintf(menu_row2, LCD_ROW_LEN+1, LNG("%d deg","%d ﾄﾞ"), (v*1125)/100);
+
+    if (v == &tc_sampler_phase)
+        sniprintf(menu_row2, LCD_ROW_LEN+1, LNG("%d deg","%d ﾄﾞ"), ((*v)*1125)/100);
+    else if (v == &tc_h_samplerate)
+        sniprintf(menu_row2, LCD_ROW_LEN+1, "%u", video_modes[vm_edit].h_total);
+    else if (v == &tc_h_samplerate_adj)
+        sniprintf(menu_row2, LCD_ROW_LEN+1, ".%.2u", video_modes[vm_edit].h_total_adj*5);
+    else
+        sniprintf(menu_row2, LCD_ROW_LEN+1, "%u", *v);
 }

software/sys_controller/ossc/menu.h

@@ -23,6 +23,12 @@
 #include "alt_types.h"
 #include "controls.h"
 
+#ifdef OSDLANG_JP
+#define LNG(e, j) j
+#else
+#define LNG(e, j) e
+#endif
+
 typedef enum {
     OPT_AVCONFIG_SELECTION,
     OPT_AVCONFIG_NUMVALUE,
@@ -34,7 +40,7 @@ typedef enum {
 typedef int (*func_call)(void);
 typedef void (*arg_func)(void);
 typedef void (*disp_func)(alt_u8);
-typedef void (*disp_func_u16)(alt_u16);
+typedef void (*disp_func_u16)(alt_u16*);
 
 typedef struct {
     alt_u8 *data;
@@ -114,9 +120,11 @@ typedef struct {
     alt_u8 mp;
 } menunavi;
 
+menunavi* get_current_menunavi();
+void render_osd_page();
 void display_menu(alt_u8 forcedisp);
 static void vm_select();
-static void vm_tweak(alt_u16 v);
+static void vm_tweak(alt_u16 *v);
 static void sampler_phase_tweak(alt_u8 v);
 
 #endif

software/sys_controller/ossc/userdata.c

@@ -17,15 +17,19 @@
 // along with this program.  If not, see <http://www.gnu.org/licenses/>.
 //
 
+#include <errno.h>
 #include <string.h>
 #include <unistd.h>
 #include "userdata.h"
+#include "fat16_export.h"
 #include "flash.h"
 #include "sdcard.h"
 #include "firmware.h"
 #include "lcd.h"
 #include "controls.h"
 #include "av_controller.h"
+#include "menu.h"
+#include "utils.h"
 #include "altera_avalon_pio_regs.h"
 
 extern alt_u16 rc_keymap[REMOTE_MAX_KEYS];
@@ -39,7 +43,9 @@ extern alt_u8 profile_sel;
 extern alt_u8 def_input, profile_link;
 extern alt_u8 lcd_bl_timeout;
 extern alt_u8 auto_input, auto_av1_ypbpr, auto_av2_ypbpr, auto_av3_ypbpr;
+extern alt_u8 osd_enable, osd_status_timeout;
 extern SD_DEV sdcard_dev;
+extern alt_flash_dev *epcq_dev;
 extern char menu_row1[LCD_ROW_LEN+1], menu_row2[LCD_ROW_LEN+1];
 
 char target_profile_name[PROFILE_NAME_LEN+1];
@@ -51,7 +57,7 @@ int write_userdata(alt_u8 entry)
     alt_u16 pageoffset, srcoffset;
     alt_u8 pageno;
     alt_u32 bytes_to_w;
-    int retval;
+    int retval, i;
 
     if (entry > MAX_USERDATA_ENTRY) {
         printf("invalid entry\n");
@@ -59,12 +65,12 @@ int write_userdata(alt_u8 entry)
     }
 
     strncpy(((ude_hdr*)databuf)->userdata_key, "USRDATA", 8);
-    ((ude_hdr*)databuf)->version_major = FW_VER_MAJOR;
-    ((ude_hdr*)databuf)->version_minor = FW_VER_MINOR;
     ((ude_hdr*)databuf)->type = (entry > MAX_PROFILE) ? UDE_INITCFG : UDE_PROFILE;
 
     switch (((ude_hdr*)databuf)->type) {
     case UDE_INITCFG:
+        ((ude_hdr*)databuf)->version_major = INITCFG_VER_MAJOR;
+        ((ude_hdr*)databuf)->version_minor = INITCFG_VER_MINOR;
         ((ude_initcfg*)databuf)->data_len = sizeof(ude_initcfg) - offsetof(ude_initcfg, last_profile);
         memcpy(((ude_initcfg*)databuf)->last_profile, input_profiles, sizeof(input_profiles));
         ((ude_initcfg*)databuf)->last_input = target_input;
@@ -75,14 +81,20 @@ int write_userdata(alt_u8 entry)
         ((ude_initcfg*)databuf)->auto_av1_ypbpr = auto_av1_ypbpr;
         ((ude_initcfg*)databuf)->auto_av2_ypbpr = auto_av2_ypbpr;
         ((ude_initcfg*)databuf)->auto_av3_ypbpr = auto_av3_ypbpr;
+        ((ude_initcfg*)databuf)->osd_enable = osd_enable;
+        ((ude_initcfg*)databuf)->osd_status_timeout = osd_status_timeout;
         memcpy(((ude_initcfg*)databuf)->keys, rc_keymap, sizeof(rc_keymap));
-        retval = write_flash_page(databuf, sizeof(ude_initcfg), (USERDATA_OFFSET+entry*SECTORSIZE)/PAGESIZE);
+        for (i=0; i<sizeof(ude_initcfg); i++)
+            databuf[i] = bitswap8(databuf[i]);
+        retval = alt_epcq_controller2_write(epcq_dev, (USERDATA_OFFSET+entry*SECTORSIZE), databuf, sizeof(ude_initcfg));
         if (retval != 0)
-            return -1;
+            return retval;
 
         printf("Initconfig data written (%u bytes)\n", sizeof(ude_initcfg) - offsetof(ude_initcfg, last_profile));
         break;
     case UDE_PROFILE:
+        ((ude_hdr*)databuf)->version_major = PROFILE_VER_MAJOR;
+        ((ude_hdr*)databuf)->version_minor = PROFILE_VER_MINOR;
         vm_to_write = VIDEO_MODES_SIZE;
         ((ude_profile*)databuf)->avc_data_len = sizeof(avconfig_t);
         ((ude_profile*)databuf)->vm_data_len = vm_to_write;
@@ -98,15 +110,30 @@ int write_userdata(alt_u8 entry)
         memcpy(databuf+pageoffset, &tc, sizeof(avconfig_t));
         pageoffset += sizeof(avconfig_t);
 
-        // write a full page first
+        // erase sector and write a full page first, assume sizeof(video_modes) >> PAGESIZE
         memcpy(databuf+pageoffset, (char*)video_modes, PAGESIZE-pageoffset);
         srcoffset = PAGESIZE-pageoffset;
         vm_to_write -= PAGESIZE-pageoffset;
-        write_flash_page(databuf, PAGESIZE, ((USERDATA_OFFSET+entry*SECTORSIZE)/PAGESIZE));
+        for (i=0; i<PAGESIZE; i++)
+            databuf[i] = bitswap8(databuf[i]);
+        retval = alt_epcq_controller2_write(epcq_dev, (USERDATA_OFFSET+entry*SECTORSIZE), databuf, PAGESIZE);
+        if (retval != 0)
+            return retval;
 
-        // then write the rest
-        if (vm_to_write > 0)
-            write_flash((alt_u8*)video_modes+srcoffset, vm_to_write, ((USERDATA_OFFSET+entry*SECTORSIZE)/PAGESIZE) + 1);
+        // then write the rest page by page
+        pageno = 1;
+        while (vm_to_write > 0) {
+            memcpy(databuf, (char*)video_modes+srcoffset, (vm_to_write > PAGESIZE) ? PAGESIZE : vm_to_write);
+            for (i=0; i<PAGESIZE; i++)
+                databuf[i] = bitswap8(databuf[i]);
+            retval = alt_epcq_controller2_write_block(epcq_dev, (USERDATA_OFFSET+entry*SECTORSIZE), (USERDATA_OFFSET+entry*SECTORSIZE+pageno*PAGESIZE), databuf, (vm_to_write > PAGESIZE) ? PAGESIZE : vm_to_write);
+            if (retval != 0)
+                return retval;
+
+            srcoffset += PAGESIZE;
+            vm_to_write = (vm_to_write < PAGESIZE) ? 0 : (vm_to_write - PAGESIZE);
+            pageno++;
+        }
 
         printf("Profile %u data written (%u bytes)\n", entry, sizeof(avconfig_t)+VIDEO_MODES_SIZE);
         break;
@@ -132,24 +159,23 @@ int read_userdata(alt_u8 entry, int dry_run)
         return -1;
     }
 
-    retval = read_flash(USERDATA_OFFSET+(entry*SECTORSIZE), PAGESIZE, databuf);
-    if (retval != 0) {
-        printf("Flash read error\n");
-        return -1;
-    }
+    retval = alt_epcq_controller2_read(epcq_dev, (USERDATA_OFFSET+entry*SECTORSIZE), databuf, PAGESIZE);
+    for (i=0; i<PAGESIZE; i++)
+        databuf[i] = bitswap8(databuf[i]);
+    if (retval != 0)
+        return retval;
 
     if (strncmp(((ude_hdr*)databuf)->userdata_key, "USRDATA", 8)) {
         printf("No userdata found on entry %u\n", entry);
         return 1;
     }
 
-    if ((((ude_hdr*)databuf)->version_major != FW_VER_MAJOR) || (((ude_hdr*)databuf)->version_minor != FW_VER_MINOR)) {
-        printf("Data version %u.%u does not match fw\n", ((ude_hdr*)databuf)->version_major, ((ude_hdr*)databuf)->version_minor);
-        return 2;
-    }
-
     switch (((ude_hdr*)databuf)->type) {
     case UDE_INITCFG:
+        if ((((ude_hdr*)databuf)->version_major != INITCFG_VER_MAJOR) || (((ude_hdr*)databuf)->version_minor != INITCFG_VER_MINOR)) {
+            printf("Initconfig version %u.%u does not match current one\n", ((ude_hdr*)databuf)->version_major, ((ude_hdr*)databuf)->version_minor);
+            return 2;
+        }
         if (((ude_initcfg*)databuf)->data_len == sizeof(ude_initcfg) - offsetof(ude_initcfg, last_profile)) {
             if (dry_run)
                 return 0;
@@ -166,6 +192,8 @@ int read_userdata(alt_u8 entry, int dry_run)
             auto_av1_ypbpr = ((ude_initcfg*)databuf)->auto_av1_ypbpr;
             auto_av2_ypbpr = ((ude_initcfg*)databuf)->auto_av2_ypbpr;
             auto_av3_ypbpr = ((ude_initcfg*)databuf)->auto_av3_ypbpr;
+            osd_enable = ((ude_initcfg*)databuf)->osd_enable;
+            osd_status_timeout = ((ude_initcfg*)databuf)->osd_status_timeout;
             profile_link = ((ude_initcfg*)databuf)->profile_link;
             profile_sel = input_profiles[AV_TESTPAT]; // Global profile
             lcd_bl_timeout = ((ude_initcfg*)databuf)->lcd_bl_timeout;
@@ -174,6 +202,10 @@ int read_userdata(alt_u8 entry, int dry_run)
         }
         break;
     case UDE_PROFILE:
+        if ((((ude_hdr*)databuf)->version_major != PROFILE_VER_MAJOR) || (((ude_hdr*)databuf)->version_minor != PROFILE_VER_MINOR)) {
+            printf("Profile version %u.%u does not match current one\n", ((ude_hdr*)databuf)->version_major, ((ude_hdr*)databuf)->version_minor);
+            return 2;
+        }
         if ((((ude_profile*)databuf)->avc_data_len == sizeof(avconfig_t)) && (((ude_profile*)databuf)->vm_data_len == VIDEO_MODES_SIZE)) {
             strncpy(target_profile_name, ((ude_profile*)databuf)->name, PROFILE_NAME_LEN+1);
             if (dry_run)
@@ -197,7 +229,11 @@ int read_userdata(alt_u8 entry, int dry_run)
                     pageoffset = 0;
                     pageno++;
                     // check
-                    read_flash(USERDATA_OFFSET+(entry*SECTORSIZE)+pageno*PAGESIZE, PAGESIZE, databuf);
+                    retval = alt_epcq_controller2_read(epcq_dev, (USERDATA_OFFSET+entry*SECTORSIZE+pageno*PAGESIZE), databuf, PAGESIZE);
+                    for (i=0; i<PAGESIZE; i++)
+                        databuf[i] = bitswap8(databuf[i]);
+                    if (retval != 0)
+                        return retval;
                 } else {
                     memcpy((char*)video_modes+dstoffset, databuf+pageoffset, vm_to_read);
                     pageoffset += vm_to_read;
@@ -219,6 +255,7 @@ int read_userdata(alt_u8 entry, int dry_run)
 
 int import_userdata()
 {
+    SDRESULTS res;
     int retval;
     int n, entries_imported=0;
     char *errmsg;
@@ -229,11 +266,10 @@ int import_userdata()
     retval = check_sdcard(databuf);
     SPI_CS_High();
     if (retval != 0)
-        goto failure;
+        goto sd_disable;
 
-    strncpy(menu_row1, "Import? 1=Y, 2=N", LCD_ROW_LEN+1);
-    *menu_row2 = '\0';
-    lcd_write_menu();
+    strncpy(menu_row2, "Import? 1=Y, 2=N", LCD_ROW_LEN+1);
+    ui_disp_menu(2);
 
     while (1) {
         btn_vec = IORD_ALTERA_AVALON_PIO_DATA(PIO_1_BASE) & RC_MASK;
@@ -242,23 +278,23 @@ int import_userdata()
             break;
         } else if (btn_vec == rc_keymap[RC_BTN2]) {
             retval = UDATA_IMPT_CANCELLED;
-            goto failure;
+            strncpy(menu_row2, "Cancelled", LCD_ROW_LEN+1);
+            goto sd_disable;
         }
 
         usleep(WAITLOOP_SLEEP_US);
     }
 
-    strncpy(menu_row1, "Loading settings", LCD_ROW_LEN+1);
-    strncpy(menu_row2, "please wait...", LCD_ROW_LEN+1);
-    lcd_write_menu();
+    strncpy(menu_row2, "Loading...", LCD_ROW_LEN+1);
+    ui_disp_menu(2);
 
     // Import the userdata
     for (n=0; n<=MAX_USERDATA_ENTRY; ++n) {
-        retval = SD_Read(&sdcard_dev, &header, (512+n*SECTORSIZE)/SD_BLK_SIZE, 0, sizeof(header));
-        if (retval != 0) {
+        res = SD_Read(&sdcard_dev, &header, (512+n*SECTORSIZE)/SD_BLK_SIZE, 0, sizeof(header));
+        if (res != SD_OK) {
             printf("Failed to read SD card\n");
-            retval = -retval;
-            goto failure;
+            retval = -res;
+            goto sd_disable;
         }
 
         if (strncmp(header.userdata_key, "USRDATA", 8)) {
@@ -266,12 +302,13 @@ int import_userdata()
             continue;
         }
 
-        if ((header.version_major != FW_VER_MAJOR) || (header.version_minor != FW_VER_MINOR)) {
-            printf("Data version %u.%u does not match fw\n", header.version_major, header.version_minor);
+        if ((header.type == UDE_PROFILE) && ((header.version_major != PROFILE_VER_MAJOR) || (header.version_minor != PROFILE_VER_MINOR))) {
+            printf("Profile version %u.%u does not match current one\n", header.version_major, header.version_minor);
             continue;
-        }
-
-        if (header.type > UDE_PROFILE) {
+        } else if ((header.type == UDE_INITCFG) && ((header.version_major != INITCFG_VER_MAJOR) || (header.version_minor != INITCFG_VER_MINOR))) {
+            printf("Initconfig version %u.%u does not match current one\n", header.version_major, header.version_minor);
+            continue;
+        } else if (header.type > UDE_PROFILE) {
             printf("Unknown userdata entry type %u\n", header.type);
             continue;
         }
@@ -281,27 +318,213 @@ int import_userdata()
             (header.type == UDE_PROFILE) ? sizeof(ude_profile) : sizeof(ude_initcfg), databuf);
         if (retval != 0) {
             printf("Copy from SD to flash failed (error %d)\n", retval);
-            goto failure;
+            goto sd_disable;
         }
 
         entries_imported++;
     }
 
-    SPI_CS_High();
+    // flash read immediately after write might fail, add some delay
+    usleep(1000);
 
     read_userdata(INIT_CONFIG_SLOT, 0);
     profile_sel = input_profiles[target_input];
     read_userdata(profile_sel, 0);
 
-    sniprintf(menu_row1, LCD_ROW_LEN+1, "%d entries", entries_imported);
-    strncpy(menu_row2, "imported", LCD_ROW_LEN+1);
-    lcd_write_menu();
-    usleep(1000000);
+    sniprintf(menu_row2, LCD_ROW_LEN+1, "%d slots loaded", entries_imported);
+    retval = 1;
 
-    return 0;
-
-failure:
+sd_disable:
     SPI_CS_High();
 
-    return -1;
+    return retval;
+}
+
+static alt_u8 poll_yesno(const useconds_t useconds, alt_u32 *const btn_vec_out)
+{
+    alt_u32 btn_vec;
+    alt_u8 ret = 0U;
+
+    for (alt_u32 i = 0; i < (useconds/WAITLOOP_SLEEP_US); ++i) {
+        btn_vec = IORD_ALTERA_AVALON_PIO_DATA(PIO_1_BASE) & RC_MASK;
+
+        for (alt_u32 j = RC_BTN1; j < (REMOTE_MAX_KEYS - 1); ++j) {
+            if (btn_vec == rc_keymap[j]) {
+                ret = 1U;
+                break;
+            }
+        }
+
+        if (ret)
+            break;
+
+        usleep(WAITLOOP_SLEEP_US);
+    }
+
+    if (ret)
+        *btn_vec_out = btn_vec;
+
+    return ret;
+}
+
+int export_userdata()
+{
+    int retval;
+    const char *msg;
+    alt_u8 databuf[SD_BLK_SIZE];
+    alt_u8 prompt_state = 0;
+    useconds_t prompt_delay;
+    const alt_u8 prompt_transitions[] = { 1, 2, 0, 0, };
+    const alt_u8 prompt_ofs[] = { 0, 16, 31, LNG(48, 47), };
+    const char *prompt_msgs =
+        LNG(
+        "SD CARD WILL BE" "\0" // [ 0..15]
+        "OVERWRITTEN!!!"  "\0" // [16..30]
+        "Export? 1=Y, 2=N""\0" // [31..47]
+        "Press 1 or 2",        // [48..60]
+        "SDｶｰﾄﾞｦｳﾜｶﾞｷｼﾏｽ" "\0" // [ 0..15]
+        "ｺﾞﾁｭｳｲｸﾀﾞｻｲ!!!"  "\0" // [16..30]
+        "1=ｼﾞｯｺｳｽﾙ 2=ﾔﾒﾙ" "\0" // [31..46]
+        "ﾄﾞﾁﾗｶｴﾗﾝﾃﾞｸﾀﾞｻｲ"      // [47..60]
+        );
+    alt_u32 btn_vec, sd_block_offset;
+
+    _Static_assert(SD_BLK_SIZE == FAT16_SECTOR_SIZE, "Sector size mismatch");
+
+    retval = check_sdcard(databuf);
+    SPI_CS_High();
+    if (retval != 0) {
+        retval = -retval;
+        goto out;
+    }
+
+    usleep(100000U);
+    while (1) {
+        msg = &prompt_msgs[prompt_ofs[prompt_state]];
+        prompt_delay = (prompt_state == 2) ? 2000000U
+            : ((prompt_state == 3) ? 300000U : 1000000U);
+        prompt_state = prompt_transitions[prompt_state];
+
+        strncpy(menu_row2, msg, LCD_ROW_LEN+1);
+        ui_disp_menu(2);
+        if (poll_yesno(prompt_delay, &btn_vec))
+            goto eval_button;
+
+        continue;
+eval_button:
+        if (btn_vec == rc_keymap[RC_BTN1]) {
+            break;
+        } else if (btn_vec == rc_keymap[RC_BTN2] ||
+            btn_vec == rc_keymap[RC_BACK])
+        {
+            retval = UDATA_EXPT_CANCELLED;
+            goto out;
+        }
+        prompt_state = 3;
+    }
+
+    usleep(100000U);
+    strncpy(menu_row1,"SD Format", LCD_ROW_LEN+1);
+    strncpy(menu_row2,"1=FAT16, 2=RAW", LCD_ROW_LEN+1);
+    ui_disp_menu(2);
+    if ((!poll_yesno(5000000U, &btn_vec)) || ((btn_vec != rc_keymap[RC_BTN1]) && (btn_vec != rc_keymap[RC_BTN2])))  {
+        retval = UDATA_EXPT_CANCELLED;
+        goto out;
+    }
+    sd_block_offset = (btn_vec == rc_keymap[RC_BTN1]) ? (PROF_16_DATA_OFS/SD_BLK_SIZE) : 0;
+
+    strncpy(menu_row2, LNG("Exporting...", "ｵﾏﾁｸﾀﾞｻｲ"), LCD_ROW_LEN+1);
+    ui_disp_menu(2);
+
+    // RAW copy
+    if (btn_vec == rc_keymap[RC_BTN2])
+        goto copy_start;
+
+    /* Zero out the boot sector, FATs and root directory. */
+    memset(databuf, 0, SD_BLK_SIZE);
+    for (alt_u32 sector = 0;
+        sector < (FAT16_ROOT_DIR_FIRST_SECTOR + FAT16_ROOT_DIR_SECTORS);
+        ++sector)
+    {
+        retval = SD_Write(&sdcard_dev, databuf, sector);
+        if (retval)
+            goto out;
+    }
+
+    /* Generate and write the boot sector. */
+    generate_boot_sector_16(databuf);
+    retval = SD_Write(&sdcard_dev, databuf, 0);
+    if (retval)
+        goto out;
+
+    /* Generate and write the file allocation tables. */
+    for (alt_u16 clusters_written = 0, sd_blk_idx = 0;
+        clusters_written < (PROF_16_DATA_SIZE/FAT16_CLUSTER_SIZE);)
+    {
+        memset(databuf, 0, SD_BLK_SIZE);
+        clusters_written = generate_fat16(databuf, clusters_written);
+        retval = SD_Write(&sdcard_dev, databuf,
+            (FAT16_1_OFS/SD_BLK_SIZE) + sd_blk_idx);
+        if (retval)
+            goto out;
+
+        retval = SD_Write(&sdcard_dev, databuf,
+            (FAT16_2_OFS/SD_BLK_SIZE) + sd_blk_idx);
+        if (retval)
+            goto out;
+
+        ++sd_blk_idx;
+    }
+
+    /* Write the directory entry of the settings file. */
+    memset(databuf, 0, SD_BLK_SIZE);
+    memcpy(databuf, prof_dirent_16, PROF_DIRENT_16_SIZE);
+    retval = SD_Write(&sdcard_dev, databuf, PROF_DIRENT_16_OFS/SD_BLK_SIZE);
+    if (retval)
+        goto out;
+
+copy_start:
+    // Zero out first 512 bytes (1 SD block) of the file
+    memset(databuf, 0, SD_BLK_SIZE);
+    retval = SD_Write(&sdcard_dev, databuf, sd_block_offset++);
+    if (retval)
+        goto out;
+
+    /* This may wear the SD card a bit more than necessary... */
+    retval = copy_flash_to_sd(USERDATA_OFFSET/PAGESIZE,
+        sd_block_offset,
+        (MAX_USERDATA_ENTRY + 1) * SECTORSIZE,
+        databuf);
+
+out:
+    SPI_CS_High();
+
+    switch (retval) {
+        case 0:
+            msg = LNG("Success", "ｶﾝﾘｮｳｼﾏｼﾀ"); // Alternative: "ｶﾝﾘｮｳｲﾀｼﾏｼﾀ"
+            break;
+        case SD_NOINIT:
+            msg = LNG("No SD card det.", "SDｶｰﾄﾞｶﾞﾐﾂｶﾘﾏｾﾝ");
+            break;
+        case -EINVAL:
+            msg = LNG("Invalid params.", "ﾊﾟﾗﾒｰﾀｶﾞﾑｺｳﾃﾞｽ");
+            break;
+        case UDATA_EXPT_CANCELLED:
+            msg = LNG("Cancelled", "ｷｬﾝｾﾙｻﾚﾏｼﾀ"); // Alternative: "ｷｬﾝｾﾙｻｾﾃｲﾀﾀﾞｷﾏｽ"
+            break;
+        default:
+            msg = LNG("SD/Flash error", "SDｶFLASHﾉｴﾗｰ"); // ﾌﾗｯｼｭ would be NG.
+            break;
+    }
+    strncpy(menu_row2, msg, LCD_ROW_LEN+1);
+
+    if (!retval) {
+        return 1;
+    } else {
+        /*
+         * We want the message above to remain on screen, so return a
+         * positive value which nevertheless stands out when debugging.
+         */
+        return 0x0dead;
+    }
 }

software/sys_controller/ossc/userdata.h

@@ -34,6 +34,7 @@
 #define INIT_CONFIG_SLOT MAX_USERDATA_ENTRY
 
 #define UDATA_IMPT_CANCELLED 104
+#define UDATA_EXPT_CANCELLED 105
 
 typedef enum {
     UDE_INITCFG  = 0,
@@ -59,6 +60,8 @@ typedef struct {
     alt_u8 auto_av1_ypbpr;
     alt_u8 auto_av2_ypbpr;
     alt_u8 auto_av3_ypbpr;
+    alt_u8 osd_enable;
+    alt_u8 osd_status_timeout;
     alt_u16 keys[REMOTE_MAX_KEYS];
 } __attribute__((packed, __may_alias__)) ude_initcfg;
 
@@ -74,5 +77,6 @@ typedef struct {
 int write_userdata(alt_u8 entry);
 int read_userdata(alt_u8 entry, int dry_run);
 int import_userdata();
+int export_userdata();
 
 #endif

software/sys_controller/ossc/utils.c

@@ -25,6 +25,12 @@
 #include "sysconfig.h"
 #include "io.h"
 
+inline unsigned char bitswap8(unsigned char v)
+{
+    return ((v * 0x0802LU & 0x22110LU) |
+            (v * 0x8020LU & 0x88440LU)) * 0x10101LU >> 16;
+}
+
 alt_u32 bswap32(alt_u32 w)
 {
     return (((w << 24) & 0xff000000) |

software/sys_controller/ossc/utils.h

@@ -24,7 +24,7 @@
 
 #define PRINTF_BUFSIZE 512
 
-unsigned char bitswap8(unsigned char v);
+inline unsigned char bitswap8(unsigned char v);
 
 alt_u32 bswap32(alt_u32 w);
 

software/sys_controller/pcm1862/pcm1862.c

@@ -44,8 +44,8 @@ inline void pcm1862_writereg(alt_u8 regaddr, alt_u8 data)
 void pcm_source_sel(pcm_input_t input) {
     alt_u8 adc_ch = 1<<input;
 
-    pcm1862_writereg(PCM1862_ADC1L, adc_ch);
-    pcm1862_writereg(PCM1862_ADC1R, adc_ch);
+    pcm1862_writereg(PCM1862_ADC1L, (1<<6)|adc_ch);
+    pcm1862_writereg(PCM1862_ADC1R, (1<<6)|adc_ch);
 }
 
 void pcm_set_gain(alt_8 db_gain) {
@@ -60,6 +60,8 @@ int pcm1862_init()
     if (pcm1862_readreg(0x05) != 0x86)
         return 0;
 
+    pcm1862_writereg(PCM1862_PWR_CTRL, 0x75);
+
     //pcm1862_writereg(0x00, 0xff);
     pcm1862_writereg(PCM1862_CLKCONFIG, 0x90);
 
@@ -67,7 +69,9 @@ int pcm1862_init()
     pcm1862_writereg(PCM1862_DSP2_CLKDIV, 0x00);
     pcm1862_writereg(PCM1862_ADC_CLKDIV,  0x03);
     pcm1862_writereg(PCM1862_PLLCONFIG, 0x00);
-    pcm1862_writereg(PCM1862_DSP_CTRL, 0x30);
+    pcm1862_writereg(PCM1862_DSP_CTRL, 0xB0);
+
+    pcm1862_writereg(PCM1862_PWR_CTRL, 0x70);
 
     return 1;
 }

software/sys_controller/pcm1862/pcm1862_regs.h

@@ -53,6 +53,7 @@
 
 #define PCM1862_PLLCONFIG       0x28
 
+#define PCM1862_PWR_CTRL        0x70
 #define PCM1862_DSP_CTRL        0x71
 
 #endif /* PCM1862_REGS_H_ */

software/sys_controller/spi_charlcd/lcd.c

@@ -67,6 +67,7 @@ void lcd_write(char *row1, char *row2)
     IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, sys_ctrl);
 
     lcd_cmd(0x01,CLEARDELAY); // clear display
+    usleep(400); // additional delay for copycat lcd module
 
     // Set RS to enter data write mode
     sys_ctrl |= LCD_RS;

software/sys_controller/tvp7002/tvp7002.c

@@ -25,7 +25,6 @@
 #include "tvp7002.h"
 
 //#define SYNCBYPASS    // Bypass VGA syncs (for debug - needed for interlace?)
-//#define EXTADCCLK     // Use external ADC clock (external osc)
 //#define ADCPOWERDOWN  // Power-down ADCs
 //#define PLLPOSTDIV    // Double-rate PLL with div-by-2 (decrease jitter?)
 
@@ -41,7 +40,7 @@ const ypbpr_to_rgb_csc_t csc_coeffs[] = {
 static const alt_u8 Kvco[] = {75, 85, 150, 200};
 static const char *Kvco_str[] = { "Ultra low", "Low", "Medium", "High" };
 
-static void tvp_set_clamp(video_format fmt)
+static void tvp_set_clamp_type(video_format fmt)
 {
     alt_u8 status = tvp_readreg(TVP_SOGTHOLD) & 0xF8;
 
@@ -60,25 +59,64 @@ static void tvp_set_clamp(video_format fmt)
     tvp_writereg(TVP_SOGTHOLD, status);
 }
 
-static void tvp_set_clamp_position(video_type type, alt_u8 h_syncinlen)
+static void tvp_set_clamp_alc(video_type type, alt_u8 clamp_ref_offset, alt_8 clamp_user_offset, alt_u8 en_alc)
 {
+    alt_16 clamp_pos = clamp_ref_offset + clamp_user_offset;
+    alt_u8 clamp_width, alc_offset;
+
     switch (type) {
     case VIDEO_LDTV:
-        tvp_writereg(TVP_CLAMPSTART, h_syncinlen+0x2);
-        tvp_writereg(TVP_CLAMPWIDTH, 0x6);
+        clamp_pos += 2;
+        clamp_width = 6;
+        alc_offset = 1;
         break;
     case VIDEO_HDTV:
-        tvp_writereg(TVP_CLAMPSTART, h_syncinlen+0x32);
-        tvp_writereg(TVP_CLAMPWIDTH, 0x20);
+        clamp_pos += 50;
+        clamp_width = 32;
+        alc_offset = 8;
         break;
     case VIDEO_SDTV:
     case VIDEO_EDTV:
     case VIDEO_PC:
     default:
-        tvp_writereg(TVP_CLAMPSTART, h_syncinlen+0x6);
-        tvp_writereg(TVP_CLAMPWIDTH, 0x10);
+        clamp_pos += 6;
+        clamp_width = 16;
+        alc_offset = 2;
         break;
     }
+
+    // Make sure clamp and ALC positions are within 8bit range
+    if (clamp_pos < 0)
+        clamp_pos = 0;
+    else if (clamp_pos + clamp_width + alc_offset > 255)
+        clamp_pos = 255 - alc_offset - clamp_width;
+
+    tvp_writereg(TVP_CLAMPSTART, (alt_u8)clamp_pos);
+    tvp_writereg(TVP_CLAMPWIDTH, clamp_width);
+
+    if (en_alc) {
+        tvp_writereg(TVP_ALCEN, 0x80); //enable ALC
+        tvp_writereg(TVP_ALCPLACE, clamp_pos+clamp_width+alc_offset);
+    } else {
+        tvp_writereg(TVP_ALCEN, 0x00); //disable ALC
+    }
+}
+
+static void tvp_sel_clk(tvp_refclk_t refclk, alt_u8 ext_pclk)
+{
+    alt_u8 status = tvp_readreg(TVP_INPMUX2) & 0xF5;
+
+    //TODO: set SOG and CLP LPF based on mode
+    if (refclk == REFCLK_EXT27) {
+        status |= 0x8;
+
+        if (!ext_pclk)
+            status |= 0x2;
+    } else {
+        status |= 0x2;
+    }
+
+    tvp_writereg(TVP_INPMUX2, status);
 }
 
 inline alt_u32 tvp_readreg(alt_u32 regaddr)
@@ -159,8 +197,8 @@ void tvp_init()
 
     // Set default configuration (skip those which match register reset values)
 
-    // Configure external refclk
-    tvp_sel_clk(REFCLK_EXT27);
+    // Configure external refclk, HPLL generated pclk
+    tvp_sel_clk(REFCLK_EXT27, 0);
 
     // Hsync input->output delay (horizontal shift)
     // Default is 13, which maintains alignment of RGB and hsync at output
@@ -261,22 +299,6 @@ void tvp_setup_hpll(alt_u16 h_samplerate, alt_u16 refclks_per_line, alt_u8 plldi
     tvp_writereg(TVP_HPLLCTRL, ((vco_range << 6) | (cp_current << 3)));
 }
 
-void tvp_sel_clk(tvp_refclk_t refclk)
-{
-    alt_u8 status = tvp_readreg(TVP_INPMUX2) & 0xFA;
-
-    //TODO: set SOG and CLP LPF based on mode
-    if (refclk == REFCLK_INTCLK) {
-        tvp_writereg(TVP_INPMUX2, status|0x2);
-    } else {
-#ifdef EXTADCCLK
-        tvp_writereg(TVP_INPMUX2, status|0x8);
-#else
-        tvp_writereg(TVP_INPMUX2, status|0xA);
-#endif
-    }
-}
-
 void tvp_sel_csc(const ypbpr_to_rgb_csc_t *csc)
 {
     tvp_writereg(TVP_CSC1HI, (csc->G_Y >> 8));
@@ -315,6 +337,13 @@ void tvp_set_sync_lpf(alt_u8 val)
     printf("Sync LPF value set to 0x%x\n", val);
 }
 
+void tvp_set_clp_lpf(alt_u8 val)
+{
+    alt_u8 status = tvp_readreg(TVP_INPMUX2) & 0xCF;
+    tvp_writereg(TVP_INPMUX2, status|(val<<4));
+    printf("CLP LPF value set to 0x%x\n", val);
+}
+
 alt_u8 tvp_set_hpll_phase(alt_u8 val, alt_u8 sample_mult)
 {
     alt_u8 sample_sel;
@@ -335,36 +364,17 @@ void tvp_set_sog_thold(alt_u8 val)
     printf("SOG thold set to 0x%x\n", val);
 }
 
-void tvp_set_alc(alt_u8 en_alc, video_type type, alt_u8 h_syncinlen)
-{
-    if (en_alc) {
-        tvp_writereg(TVP_ALCEN, 0x80); //enable ALC
-
-        //select ALC placement
-        switch (type) {
-        case VIDEO_LDTV:
-            tvp_writereg(TVP_ALCPLACE, h_syncinlen+0x9);
-            break;
-        case VIDEO_HDTV:
-            tvp_writereg(TVP_ALCPLACE, h_syncinlen+0x5A);
-            break;
-        case VIDEO_SDTV:
-        case VIDEO_EDTV:
-        case VIDEO_PC:
-        default:
-            tvp_writereg(TVP_ALCPLACE, h_syncinlen+0x18);
-            break;
-        }
-    } else {
-        tvp_writereg(TVP_ALCEN, 0x00); //disable ALC
-    }
+void tvp_set_alcfilt(alt_u8 nsv, alt_u8 nsh) {
+    tvp_writereg(TVP_ALCFILT, (nsv<<3)|nsh);
 }
 
-void tvp_source_setup(video_type type, alt_u16 h_samplerate, alt_u16 refclks_per_line, alt_u8 plldivby2, alt_u8 h_syncinlen)
+void tvp_source_setup(video_type type, alt_u16 h_samplerate, alt_u16 refclks_per_line, alt_u8 plldivby2, alt_u8 h_synclen_px, alt_8 clamp_user_offset)
 {
-    // Clamp position and ALC
-    tvp_set_clamp_position(type, h_syncinlen);
-    tvp_set_alc(1, type, h_syncinlen);
+    // Due to short MVS width, clamp reference starts prematurely (at the end of MVS window). Adjust offset so that reference moves back to hsync trailing edge.
+    alt_u8 clamp_ref_offset = h_synclen_px - (((30*h_samplerate)/refclks_per_line)+5)/10;
+
+    // Clamp and ALC
+    tvp_set_clamp_alc(type, clamp_ref_offset, clamp_user_offset, 1);
 
     // Setup Macrovision stripper and H-PLL coast signal.
     // Coast needs to be enabled when HSYNC is missing during VSYNC. RGBHV mode cannot use it, so turn off the internal signal for this mode.
@@ -385,27 +395,19 @@ void tvp_source_setup(video_type type, alt_u16 h_samplerate, alt_u16 refclks_per
     tvp_setup_hpll(h_samplerate, refclks_per_line, plldivby2);
 }
 
-void tvp_source_sel(tvp_input_t input, video_format fmt)
+void tvp_source_sel(tvp_input_t input, tvp_sync_input_t syncinput, video_format fmt)
 {
     alt_u8 sync_status;
-    alt_u8 sog_ch;
-
-    if ((fmt == FORMAT_RGsB) || (fmt == FORMAT_YPbPr))
-        sog_ch = (input == TVP_INPUT3) ? 2 : 0;
-    else if ((input == TVP_INPUT1) && (fmt == FORMAT_RGBS))
-        sog_ch = 1;
-    else
-        sog_ch = 2;
 
     // RGB+SOG input select
-    tvp_writereg(TVP_INPMUX1, (sog_ch<<6) | (input<<4) | (input<<2) | input);
+    tvp_writereg(TVP_INPMUX1, (((syncinput <= TVP_SOG3) ? syncinput : 0)<<6) | (input<<4) | (input<<2) | input);
 
     // Clamp setup
-    tvp_set_clamp(fmt);
+    tvp_set_clamp_type(fmt);
 
     // HV/SOG sync select
-    if ((input == TVP_INPUT3) && ((fmt == FORMAT_RGBHV) || (fmt == FORMAT_RGBS))) {
-        if (fmt == FORMAT_RGBHV)
+    if (syncinput > TVP_SOG3) {
+        if (syncinput < TVP_CS_A)
             tvp_writereg(TVP_SYNCCTRL1, 0x52);
         else // RGBS
             tvp_writereg(TVP_SYNCCTRL1, 0x53);
@@ -444,16 +446,16 @@ void tvp_source_sel(tvp_input_t input, video_format fmt)
     printf("\n");
 }
 
-alt_u8 tvp_check_sync(tvp_input_t input, video_format fmt)
+alt_u8 tvp_check_sync(tvp_sync_input_t syncinput)
 {
     alt_u8 sync_status;
 
     sync_status = tvp_readreg(TVP_SYNCSTAT);
 
-    if ((input == TVP_INPUT3) && (fmt == FORMAT_RGBHV))
-        return ((sync_status & 0x90) == 0x90);
-    else if ((input == TVP_INPUT3) && (fmt == FORMAT_RGBS))
+    if (syncinput >= TVP_CS_A)
         return ((sync_status & 0x88) == 0x88);
+    else if (syncinput >= TVP_HV_A)
+        return ((sync_status & 0x90) == 0x90);
     else
         return !!(sync_status & (1<<1));
 }

software/sys_controller/tvp7002/tvp7002.h

@@ -34,6 +34,8 @@
 #define DEFAULT_FINE_GAIN       26
 #define DEFAULT_FINE_OFFSET     0x80
 #define DEFAULT_COARSE_GAIN     0x8
+#define DEFAULT_ALC_H_FILTER    0x3
+#define DEFAULT_ALC_V_FILTER    0x9
 
 #define TVP_INTCLK_HZ           6500000UL
 #define TVP_EXTCLK_HZ           27000000UL
@@ -44,6 +46,16 @@ typedef enum {
     TVP_INPUT3 = 2
 } tvp_input_t;
 
+typedef enum {
+    TVP_SOG1 = 0,
+    TVP_SOG2 = 1,
+    TVP_SOG3 = 2,
+    TVP_HV_A = 3,
+    TVP_HV_B = 4,
+    TVP_CS_A = 5,
+    TVP_CS_B = 6
+} tvp_sync_input_t;
+
 typedef enum {
     REFCLK_EXT27    = 0,
     REFCLK_INTCLK   = 1
@@ -95,24 +107,24 @@ void tvp_set_gain_offset(color_setup_t *col);
 
 void tvp_setup_hpll(alt_u16 h_samplerate, alt_u16 refclks_per_line, alt_u8 plldivby2);
 
-void tvp_sel_clk(tvp_refclk_t refclk);
-
 void tvp_sel_csc(const ypbpr_to_rgb_csc_t *csc);
 
 void tvp_set_lpf(alt_u8 val);
 
 void tvp_set_sync_lpf(alt_u8 val);
 
+void tvp_set_clp_lpf(alt_u8 val);
+
 alt_u8 tvp_set_hpll_phase(alt_u8 val, alt_u8 sample_mult);
 
 void tvp_set_sog_thold(alt_u8 val);
 
-void tvp_set_alc(alt_u8 en_alc, video_type type, alt_u8 h_syncinlen);
+void tvp_set_alcfilt(alt_u8 nsv, alt_u8 nsh);
 
-void tvp_source_setup(video_type type, alt_u16 h_samplerate, alt_u16 refclks_per_line, alt_u8 plldivby2, alt_u8 h_syncinlen);
+void tvp_source_setup(video_type type, alt_u16 h_samplerate, alt_u16 refclks_per_line, alt_u8 plldivby2, alt_u8 h_synclen_px, alt_8 clamp_user_offset);
 
-void tvp_source_sel(tvp_input_t input, video_format fmt);
+void tvp_source_sel(tvp_input_t input, tvp_sync_input_t syncinput, video_format fmt);
 
-alt_u8 tvp_check_sync(tvp_input_t input, video_format fmt);
+alt_u8 tvp_check_sync(tvp_sync_input_t syncinput);
 
 #endif /* TVP7002_H_ */

software/sys_controller/tvp7002/video_modes.c

@@ -19,6 +19,7 @@
 
 #include <stdio.h>
 #include <unistd.h>
+#include <string.h>
 #include "system.h"
 #include "av_controller.h"
 #include "video_modes.h"
@@ -31,11 +32,10 @@ const mode_data_t video_modes_default[] = VIDEO_MODES_DEF;
 mode_data_t video_modes[VIDEO_MODES_CNT];
 
 /* TODO: rewrite, check hz etc. */
-alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type typemask)
+alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, alt_u8 h_syncinlen)
 {
     alt_8 i;
     alt_u8 num_modes = sizeof(video_modes)/sizeof(mode_data_t);
-    video_type mode_type;
     mode_flags valid_lm[] = { MODE_PT, (MODE_L2 | (MODE_L2<<cm.cc.l2_mode)), (MODE_L3_GEN_16_9<<cm.cc.l3_mode), (MODE_L4_GEN_4_3<<cm.cc.l4_mode), (MODE_L5_GEN_4_3<<cm.cc.l5_mode) };
     mode_flags target_lm;
     alt_u8 pt_only = 0;
@@ -44,16 +44,21 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
     alt_u8* group_ptr[] = { &pt_only, &cm.cc.pm_240p, &cm.cc.pm_384p, &cm.cc.pm_480i, &cm.cc.pm_480p, &cm.cc.pm_1080i };
 
     for (i=0; i<num_modes; i++) {
-        mode_type = video_modes[i].type;
-
         switch (video_modes[i].group) {
-            case GROUP_NONE:
-            case GROUP_240P:
-                break;
             case GROUP_384P:
                 //fixed Line2x/3x mode for 240x360p
                 valid_lm[2] = MODE_L2_240x360;
                 valid_lm[3] = MODE_L3_240x360;
+                valid_lm[4] = MODE_L3_GEN_16_9;
+                if (video_modes[i].v_total == 449) {
+                    if (!strncmp(video_modes[i].name, "720x400", 7)) {
+                        if (cm.cc.s400p_mode == 0)
+                            continue;
+                    } else if (!strncmp(video_modes[i].name, "640x400", 7)) {
+                        if (cm.cc.s400p_mode == 1)
+                            continue;
+                    }
+                }
                 break;
             case GROUP_480I:
                 //fixed Line3x/4x mode for 480i
@@ -61,35 +66,58 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
                 valid_lm[3] = MODE_L4_GEN_4_3;
                 break;
             case GROUP_480P:
-                if (video_modes[i].v_total == 525) {
-                    if (video_modes[i-1].group == GROUP_480I) { // hit "480p" on the list
-                        if (cm.cc.s480p_mode == 0) // Auto
-                            mode_type &= ~VIDEO_PC;
-                        else if (cm.cc.s480p_mode == 2) // VESA 640x480@60
+                if (video_modes[i].vic == HDMI_480p60) {
+                    switch (cm.cc.s480p_mode) {
+                        case 0: // Auto
+                            if (h_syncinlen > 82)
+                                continue;
+                            break;
+                        case 1: // DTV 480p
+                            break;
+                        default:
                             continue;
-                    } else { // "640x480" on the list
-                        if (cm.cc.s480p_mode == 0) // Auto
-                            mode_type &= ~VIDEO_EDTV;
-                        else if (cm.cc.s480p_mode == 1) // DTV 480p
+                    }
+                } else if (video_modes[i].flags & MODE_L2_480x272) { // hit "480x272" on the list
+                    switch (cm.cc.s480p_mode) {
+                        case 3: // PSP 480x272
+                            // force optimized Line2x mode for 480x272
+                            valid_lm[1] = MODE_L2_480x272;
+                            break;
+                        default:
+                            continue;
+                    }
+                } else if (video_modes[i].vic == HDMI_640x480p60) {
+                    switch (cm.cc.s480p_mode) {
+                        case 0: // Auto
+                        case 2: // VESA 640x480@60
+                            break;
+                        default:
                             continue;
                     }
                 }
                 break;
-            case GROUP_1080I:
-                break;
             default:
-                printf("WARNING: Corrupted mode (id %d)\n", i);
-                continue;
                 break;
         }
 
+        // Skip potentially conflicting 50Hz presets if refresh rate is much higher
+        if ((video_modes[i].vic == HDMI_576p50) ||
+            (video_modes[i].vic == HDMI_720p50) ||
+            (video_modes[i].vic == HDMI_1080i50) ||
+            (video_modes[i].vic == HDMI_1080p50))
+        {
+            if (hz >= 55)
+                continue;
+        }
+
         target_lm = valid_lm[*group_ptr[video_modes[i].group]];
 
-        if ((typemask & mode_type) && (target_lm & video_modes[i].flags) && (progressive == !(video_modes[i].flags & MODE_INTERLACED)) && (totlines <= (video_modes[i].v_total+LINECNT_MAX_TOLERANCE))) {
+        if ((target_lm & video_modes[i].flags) && (progressive == !(video_modes[i].flags & MODE_INTERLACED)) && (totlines <= (video_modes[i].v_total+LINECNT_MAX_TOLERANCE))) {
 
             // defaults
             cm.tx_pixelrep = TX_PIXELREP_DISABLE;
             cm.hdmitx_pixr_ifr = 0;
+            cm.hdmitx_vic = HDMI_Unknown;
             cm.sample_mult = 1;
             cm.hsync_cut = 0;
             cm.target_lm = target_lm & video_modes[i].flags;    //ensure L2 mode uniqueness
@@ -98,8 +126,9 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
                 case MODE_PT:
                     cm.fpga_vmultmode = FPGA_V_MULTMODE_1X;
                     cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;
-                    // Upsample / pixel-repeat horizontal resolution of 240p/480i modes to fulfill min. 25MHz TMDS clock requirement
-                    if ((video_modes[i].group == GROUP_240P) || (video_modes[i].group == GROUP_480I)) {
+                    cm.hdmitx_vic = video_modes[i].vic;
+                    // Upsample / pixel-repeat horizontal resolution of 240p/480i/384p modes to fulfill min. 25MHz TMDS clock requirement
+                    if ((video_modes[i].group == GROUP_240P) || (video_modes[i].group == GROUP_480I) || ((video_modes[i].group == GROUP_384P) && (video_modes[i].flags & MODE_PLLDIVBY2))) {
                         if (cm.cc.upsample2x)
                             cm.sample_mult = 2;
                         else
@@ -127,6 +156,7 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
                     }
                     break;
                 case MODE_L2_512_COL:
+                case MODE_L2_480x272:
                     cm.fpga_vmultmode = FPGA_V_MULTMODE_2X;
                     cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
                     cm.sample_mult = 2;
@@ -137,6 +167,7 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
                     cm.sample_mult = 6;
                     break;
                 case MODE_L2_320_COL:
+                case MODE_L2_384_COL:
                     cm.fpga_vmultmode = FPGA_V_MULTMODE_2X;
                     cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED_1X;
                     cm.sample_mult = 4;
@@ -166,6 +197,11 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
                     cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
                     cm.sample_mult = 2;
                     break;
+                case MODE_L3_384_COL:
+                    cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
+                    cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
+                    cm.sample_mult = 3;
+                    break;
                 case MODE_L3_320_COL:
                     cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
                     cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
@@ -198,6 +234,11 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
                     cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
                     cm.sample_mult = 2;
                     break;
+                case MODE_L4_384_COL:
+                    cm.fpga_vmultmode = FPGA_V_MULTMODE_4X;
+                    cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
+                    cm.sample_mult = 3;
+                    break;
                 case MODE_L4_320_COL:
                     cm.fpga_vmultmode = FPGA_V_MULTMODE_4X;
                     cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
@@ -219,6 +260,12 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
                     cm.sample_mult = 3;
                     cm.hsync_cut = 40;
                     break;
+                case MODE_L5_384_COL:
+                    cm.fpga_vmultmode = FPGA_V_MULTMODE_5X;
+                    cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
+                    cm.sample_mult = 4;
+                    cm.hsync_cut = 30;
+                    break;
                 case MODE_L5_320_COL:
                     cm.fpga_vmultmode = FPGA_V_MULTMODE_5X;
                     cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
@@ -237,6 +284,9 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
                     break;
             }
 
+            if (cm.hdmitx_vic == HDMI_Unknown)
+                cm.hdmitx_vic = cm.cc.default_vic;
+
             return i;
         }
     }

software/sys_controller/tvp7002/video_modes.h

@@ -22,10 +22,11 @@
 
 #include <alt_types.h>
 #include "sysconfig.h"
+#include "it6613_sys.h"
 
 #define H_TOTAL_MIN 300
 #define H_TOTAL_MAX 2800
-#define H_TOTAL_ADJ_MAX 5
+#define H_TOTAL_ADJ_MAX 19
 #define H_SYNCLEN_MIN 10
 #define H_SYNCLEN_MAX 255
 #define H_BPORCH_MIN 1
@@ -35,7 +36,7 @@
 #define V_SYNCLEN_MIN 1
 #define V_SYNCLEN_MAX 7
 #define V_BPORCH_MIN 1
-#define V_BPORCH_MAX 63
+#define V_BPORCH_MAX 236  // 255 - 12 for L5FMT_1920x1080 - 7 for V_SYNCLEN_MAX
 #define V_ACTIVE_MIN 160
 #define V_ACTIVE_MAX 1200
 
@@ -70,32 +71,38 @@ typedef enum {
     MODE_PT             = (1<<2),
     MODE_L2             = (1<<3),
     MODE_L2_512_COL     = (1<<4),
-    MODE_L2_320_COL     = (1<<5),
-    MODE_L2_256_COL     = (1<<6),
-    MODE_L2_240x360     = (1<<7),
-    MODE_L3_GEN_16_9    = (1<<8),
-    MODE_L3_GEN_4_3     = (1<<9),
-    MODE_L3_512_COL     = (1<<10),
-    MODE_L3_320_COL     = (1<<11),
-    MODE_L3_256_COL     = (1<<12),
-    MODE_L3_240x360     = (1<<13),
-    MODE_L4_GEN_4_3     = (1<<14),
-    MODE_L4_512_COL     = (1<<15),
-    MODE_L4_320_COL     = (1<<16),
-    MODE_L4_256_COL     = (1<<17),
-    MODE_L5_GEN_4_3     = (1<<18),
-    MODE_L5_512_COL     = (1<<19),
-    MODE_L5_320_COL     = (1<<20),
-    MODE_L5_256_COL     = (1<<21),
+    MODE_L2_384_COL     = (1<<5),
+    MODE_L2_320_COL     = (1<<6),
+    MODE_L2_256_COL     = (1<<7),
+    MODE_L2_240x360     = (1<<8),
+    MODE_L2_480x272     = (1<<9),
+    MODE_L3_GEN_16_9    = (1<<10),
+    MODE_L3_GEN_4_3     = (1<<11),
+    MODE_L3_512_COL     = (1<<12),
+    MODE_L3_384_COL     = (1<<13),
+    MODE_L3_320_COL     = (1<<14),
+    MODE_L3_256_COL     = (1<<15),
+    MODE_L3_240x360     = (1<<16),
+    MODE_L4_GEN_4_3     = (1<<17),
+    MODE_L4_512_COL     = (1<<18),
+    MODE_L4_384_COL     = (1<<19),
+    MODE_L4_320_COL     = (1<<20),
+    MODE_L4_256_COL     = (1<<21),
+    MODE_L5_GEN_4_3     = (1<<22),
+    MODE_L5_512_COL     = (1<<23),
+    MODE_L5_384_COL     = (1<<24),
+    MODE_L5_320_COL     = (1<<25),
+    MODE_L5_256_COL     = (1<<26),
 } mode_flags;
 
 typedef struct {
     char name[10];
-    alt_u16 h_active;
+    HDMI_Video_Type vic:5;
+    alt_u16 h_active:11;
     alt_u16 v_active;
-    alt_u16 h_total:12;
-    alt_u8  h_total_adj:4;
-    alt_u16 v_total;
+    alt_u16 h_total;
+    alt_u8  h_total_adj:5;
+    alt_u16 v_total:11;
     alt_u8 h_backporch;
     alt_u8 v_backporch;
     alt_u8 h_synclen;
@@ -109,57 +116,68 @@ typedef struct {
 
 #define VIDEO_MODES_DEF { \
     /* 240p modes */ \
-    { "1600x240",   1600,  240,  2046, 0, 262,  202, 15,  150, 3,  DEFAULT_SAMPLER_PHASE, (VIDEO_SDTV | VIDEO_PC),   GROUP_240P,     (MODE_L5_GEN_4_3 | MODE_PLLDIVBY2) },                                                           \
-    { "1280x240",   1280,  240,  1560, 0, 262,  170, 15,   72, 3,  DEFAULT_SAMPLER_PHASE, (VIDEO_SDTV | VIDEO_PC),   GROUP_240P,     (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) },                                        \
-    { "960x240",     960,  240,  1170, 0, 262,  128, 15,   54, 3,  DEFAULT_SAMPLER_PHASE, (VIDEO_SDTV | VIDEO_PC),   GROUP_240P,     (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) },                                                           \
-    { "512x240",     512,  240,   682, 0, 262,   77, 14,   50, 3,  DEFAULT_SAMPLER_PHASE, (VIDEO_SDTV | VIDEO_PC),   GROUP_240P,     (MODE_L2_512_COL | MODE_L3_512_COL | MODE_L4_512_COL | MODE_L5_512_COL) },                      \
-    { "320x240",     320,  240,   426, 0, 262,   49, 14,   31, 3,  DEFAULT_SAMPLER_PHASE, (VIDEO_SDTV | VIDEO_PC),   GROUP_240P,     (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL) },                      \
-    { "256x240",     256,  240,   341, 0, 262,   39, 14,   25, 3,  DEFAULT_SAMPLER_PHASE, (VIDEO_SDTV | VIDEO_PC),   GROUP_240P,     (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL) },                      \
-    { "240p",        720,  240,   858, 0, 262,   57, 15,   62, 3,  DEFAULT_SAMPLER_PHASE, (VIDEO_SDTV | VIDEO_PC),   GROUP_240P,     (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) },                                                         \
+    { "1600x240",  HDMI_Unknown,     1600,  240,  2046, 0,  262,  202, 15,  150, 3,  DEFAULT_SAMPLER_PHASE, VIDEO_SDTV,                 GROUP_240P,     (MODE_L5_GEN_4_3 | MODE_PLLDIVBY2) },                                                           \
+    { "1280x240",  HDMI_Unknown,     1280,  240,  1560, 0,  262,  170, 15,   72, 3,  DEFAULT_SAMPLER_PHASE, VIDEO_SDTV,                 GROUP_240P,     (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) },                                        \
+    { "960x240",   HDMI_Unknown,      960,  240,  1170, 0,  262,  128, 15,   54, 3,  DEFAULT_SAMPLER_PHASE, VIDEO_SDTV,                 GROUP_240P,     (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) },                                                           \
+    { "512x240",   HDMI_Unknown,      512,  240,   682, 0,  262,   77, 14,   50, 3,  DEFAULT_SAMPLER_PHASE, VIDEO_SDTV,                 GROUP_240P,     (MODE_L2_512_COL | MODE_L3_512_COL | MODE_L4_512_COL | MODE_L5_512_COL) },                      \
+    { "384x240",   HDMI_Unknown,      384,  240,   512, 0,  262,   59, 14,   37, 3,  DEFAULT_SAMPLER_PHASE, VIDEO_SDTV,                 GROUP_240P,     (MODE_L2_384_COL | MODE_L3_384_COL | MODE_L4_384_COL | MODE_L5_384_COL) },                      \
+    { "320x240",   HDMI_Unknown,      320,  240,   426, 0,  262,   49, 14,   31, 3,  DEFAULT_SAMPLER_PHASE, VIDEO_SDTV,                 GROUP_240P,     (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL) },                      \
+    { "256x240",   HDMI_Unknown,      256,  240,   341, 0,  262,   39, 14,   25, 3,  DEFAULT_SAMPLER_PHASE, VIDEO_SDTV,                 GROUP_240P,     (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL) },                      \
+    { "240p",      HDMI_240p60,       720,  240,   858, 0,  262,   57, 15,   62, 3,  DEFAULT_SAMPLER_PHASE, VIDEO_SDTV,                 GROUP_240P,     (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) },                                                         \
     /* 288p modes */ \
-    { "1600x240L",  1600,  240,  2046, 0, 312,  202, 41,  150, 3,  DEFAULT_SAMPLER_PHASE, (VIDEO_SDTV | VIDEO_PC),   GROUP_240P,     (MODE_L5_GEN_4_3 | MODE_PLLDIVBY2) },                                                           \
-    { "1280x288",   1280,  288,  1560, 0, 312,  170, 15,   72, 3,  DEFAULT_SAMPLER_PHASE, (VIDEO_SDTV | VIDEO_PC),   GROUP_240P,     (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) },                                        \
-    { "960x288",     960,  288,  1170, 0, 312,  128, 15,   54, 3,  DEFAULT_SAMPLER_PHASE, (VIDEO_SDTV | VIDEO_PC),   GROUP_240P,     (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) },                                                           \
-    { "512x240LB",   512,  240,   682, 0, 312,   77, 41,   50, 3,  DEFAULT_SAMPLER_PHASE, (VIDEO_SDTV | VIDEO_PC),   GROUP_240P,     (MODE_L2_512_COL | MODE_L3_512_COL | MODE_L4_512_COL | MODE_L5_512_COL) },                      \
-    { "320x240LB",   320,  240,   426, 0, 312,   49, 41,   31, 3,  DEFAULT_SAMPLER_PHASE, (VIDEO_SDTV | VIDEO_PC),   GROUP_240P,     (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL) },                      \
-    { "256x240LB",   256,  240,   341, 0, 312,   39, 41,   25, 3,  DEFAULT_SAMPLER_PHASE, (VIDEO_SDTV | VIDEO_PC),   GROUP_240P,     (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL) },                      \
-    { "288p",        720,  288,   864, 0, 312,   69, 19,   63, 3,  DEFAULT_SAMPLER_PHASE, (VIDEO_SDTV | VIDEO_PC),   GROUP_240P,     (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) },                                                         \
+    { "1600x240L", HDMI_Unknown,     1600,  240,  2046, 0,  312,  202, 41,  150, 3,  DEFAULT_SAMPLER_PHASE, VIDEO_SDTV,                 GROUP_240P,     (MODE_L5_GEN_4_3 | MODE_PLLDIVBY2) },                                                           \
+    { "1280x288",  HDMI_Unknown,     1280,  288,  1560, 0,  312,  170, 15,   72, 3,  DEFAULT_SAMPLER_PHASE, VIDEO_SDTV,                 GROUP_240P,     (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) },                                        \
+    { "960x288",   HDMI_Unknown,      960,  288,  1170, 0,  312,  128, 15,   54, 3,  DEFAULT_SAMPLER_PHASE, VIDEO_SDTV,                 GROUP_240P,     (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) },                                                           \
+    { "512x240LB", HDMI_Unknown,      512,  240,   682, 0,  312,   77, 41,   50, 3,  DEFAULT_SAMPLER_PHASE, VIDEO_SDTV,                 GROUP_240P,     (MODE_L2_512_COL | MODE_L3_512_COL | MODE_L4_512_COL | MODE_L5_512_COL) },                      \
+    { "384x240LB", HDMI_Unknown,      384,  240,   512, 0,  312,   59, 41,   37, 3,  DEFAULT_SAMPLER_PHASE, VIDEO_SDTV,                 GROUP_240P,     (MODE_L2_384_COL | MODE_L3_384_COL | MODE_L4_384_COL | MODE_L5_384_COL) },                      \
+    { "320x240LB", HDMI_Unknown,      320,  240,   426, 0,  312,   49, 41,   31, 3,  DEFAULT_SAMPLER_PHASE, VIDEO_SDTV,                 GROUP_240P,     (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL) },                      \
+    { "256x240LB", HDMI_Unknown,      256,  240,   341, 0,  312,   39, 41,   25, 3,  DEFAULT_SAMPLER_PHASE, VIDEO_SDTV,                 GROUP_240P,     (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL) },                      \
+    { "288p",      HDMI_288p50,       720,  288,   864, 0,  312,   69, 19,   63, 3,  DEFAULT_SAMPLER_PHASE, VIDEO_SDTV,                 GROUP_240P,     (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) },                                                         \
     /* 360p: GBI */ \
-    { "480x360",     480,  360,   600, 0, 375,   63, 10,   38, 3,  DEFAULT_SAMPLER_PHASE, (VIDEO_EDTV),              GROUP_384P,     (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) },                                                         \
-    { "240x360",     256,  360,   300, 0, 375,   24, 10,   18, 3,  DEFAULT_SAMPLER_PHASE, (VIDEO_EDTV),              GROUP_384P,     (MODE_L2_240x360 | MODE_L3_240x360) },                                                          \
-    /* 384p: Sega Model 2 */ \
-    { "384p",        496,  384,   640, 0, 423,   50, 29,   62, 3,  DEFAULT_SAMPLER_PHASE, (VIDEO_EDTV),              GROUP_384P,     (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) },                                                         \
-    /* 640x400, VGA Mode 13h */ \
-    { "640x400",     640,  400,   800, 0, 449,   48, 36,   96, 2,  DEFAULT_SAMPLER_PHASE, VIDEO_PC,                  GROUP_384P,     (MODE_PT | MODE_L2) },                                                                          \
+    { "480x360",   HDMI_Unknown,      480,  360,   600, 0,  375,   63, 10,   38, 3,  DEFAULT_SAMPLER_PHASE, VIDEO_EDTV,                 GROUP_384P,     (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) },                                                         \
+    { "240x360",   HDMI_Unknown,      256,  360,   300, 0,  375,   24, 10,   18, 3,  DEFAULT_SAMPLER_PHASE, VIDEO_EDTV,                 GROUP_384P,     (MODE_L2_240x360 | MODE_L3_240x360) },                                                          \
+    /* 384p: Sega Model 2 (real vtotal=423, avoid collision with PC88/98 and VGA400p) */ \
+    { "384p",      HDMI_Unknown,      496,  384,   640, 0,  408,   50, 29,   62, 3,  DEFAULT_SAMPLER_PHASE, VIDEO_EDTV,                 GROUP_384P,     (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) },                                                         \
+    /* 400p line3x */ \
+    { "1600x400",  HDMI_Unknown,     1600,  400,  2000, 0,  449,  120, 34,  240, 2,  DEFAULT_SAMPLER_PHASE, VIDEO_PC,                   GROUP_384P,     (MODE_L3_GEN_16_9) },                                                                           \
+    /* 720x400@70Hz, VGA Mode 3+/7+ */ \
+    { "720x400",   HDMI_Unknown,      720,  400,   900, 0,  449,   64, 34,   96, 2,  DEFAULT_SAMPLER_PHASE, VIDEO_PC,                   GROUP_384P,     (MODE_PT | MODE_L2) },                                                                          \
+    /* 640x400@70Hz, VGA Mode 13h */ \
+    { "640x400",   HDMI_Unknown,      640,  400,   800, 0,  449,   48, 34,   96, 2,  DEFAULT_SAMPLER_PHASE, VIDEO_PC,                   GROUP_384P,     (MODE_PT | MODE_L2) },                                                                          \
     /* 384p: X68k @ 24kHz */ \
-    { "640x384",     640,  384,   800, 0, 492,   48, 63,   96, 2,  DEFAULT_SAMPLER_PHASE, VIDEO_PC,                  GROUP_384P,     (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) },                                                         \
+    { "640x384",   HDMI_Unknown,      640,  384,   800, 0,  492,   48, 63,   96, 2,  DEFAULT_SAMPLER_PHASE, VIDEO_PC,                   GROUP_384P,     (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) },                                                         \
     /* ~525-line modes */ \
-    { "480i",        720,  240,   858, 0, 525,   57, 15,   62, 3,  DEFAULT_SAMPLER_PHASE, (VIDEO_SDTV | VIDEO_PC),   GROUP_480I,     (MODE_PT | MODE_L2 | MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2 | MODE_INTERLACED) },  \
-    { "480p",        720,  480,   858, 0, 525,   60, 30,   62, 6,  DEFAULT_SAMPLER_PHASE, (VIDEO_EDTV | VIDEO_PC),   GROUP_480P,     (MODE_PT | MODE_L2) },                                                                          \
-    { "640x480",     640,  480,   800, 0, 525,   48, 33,   96, 2,  DEFAULT_SAMPLER_PHASE, (VIDEO_PC | VIDEO_EDTV),   GROUP_480P,     (MODE_PT | MODE_L2) },                                                                          \
+    { "480i",      HDMI_480i60,       720,  240,   858, 0,  525,   57, 15,   62, 3,  DEFAULT_SAMPLER_PHASE, VIDEO_SDTV,                 GROUP_480I,     (MODE_PT | MODE_L2 | MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2 | MODE_INTERLACED) },  \
+    { "480p",      HDMI_480p60,       720,  480,   858, 0,  525,   60, 30,   62, 6,  DEFAULT_SAMPLER_PHASE, VIDEO_EDTV,                 GROUP_480P,     (MODE_PT | MODE_L2) },                                                                          \
+    /* 480p PSP in-game */ \
+    { "480x272",   HDMI_480p60_16x9,  480,  272,   858, 0,  525,  177,134,   62, 6,  DEFAULT_SAMPLER_PHASE, VIDEO_EDTV,                 GROUP_480P,     (MODE_PT | MODE_L2_480x272) },                                                                  \
+    { "640x480",   HDMI_640x480p60,   640,  480,   800, 0,  525,   48, 33,   96, 2,  DEFAULT_SAMPLER_PHASE, VIDEO_PC,                   GROUP_480P,     (MODE_PT | MODE_L2) },                                                                          \
     /* X68k @ 31kHz */ \
-    { "640x512",     640,  512,   800, 0, 568,   48, 28,   96, 2,  DEFAULT_SAMPLER_PHASE, (VIDEO_PC | VIDEO_EDTV),   GROUP_480P,     (MODE_PT | MODE_L2) },                                                                          \
+    { "640x512",   HDMI_Unknown,      640,  512,   800, 0,  568,   48, 28,   96, 2,  DEFAULT_SAMPLER_PHASE, VIDEO_PC,                   GROUP_480P,     (MODE_PT | MODE_L2) },                                                                          \
     /* ~625-line modes */ \
-    { "576i",        720,  288,   864, 0, 625,   69, 19,   63, 3,  DEFAULT_SAMPLER_PHASE, (VIDEO_SDTV | VIDEO_PC),   GROUP_480I,     (MODE_PT | MODE_L2 | MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2 | MODE_INTERLACED) },  \
-    { "576p",        720,  576,   864, 0, 625,   68, 39,   64, 5,  DEFAULT_SAMPLER_PHASE, VIDEO_EDTV,                GROUP_480P,     (MODE_PT | MODE_L2) },                                                                          \
-    { "800x600",     800,  600,  1056, 0, 628,   88, 23,  128, 4,  DEFAULT_SAMPLER_PHASE, VIDEO_PC,                  GROUP_NONE,     MODE_PT },                                                                                      \
+    { "576i",      HDMI_576i50,       720,  288,   864, 0,  625,   69, 19,   63, 3,  DEFAULT_SAMPLER_PHASE, VIDEO_SDTV,                 GROUP_480I,     (MODE_PT | MODE_L2 | MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2 | MODE_INTERLACED) },  \
+    { "576p",      HDMI_576p50,       720,  576,   864, 0,  625,   68, 39,   64, 5,  DEFAULT_SAMPLER_PHASE, VIDEO_EDTV,                 GROUP_480P,     (MODE_PT | MODE_L2) },                                                                          \
+    { "800x600",   HDMI_Unknown,      800,  600,  1056, 0,  628,   88, 23,  128, 4,  DEFAULT_SAMPLER_PHASE, VIDEO_PC,                   GROUP_NONE,     MODE_PT },                                                                                      \
     /* 720p modes */ \
-    { "720p",       1280,  720,  1650, 0, 750,  220, 20,   40, 5,  DEFAULT_SAMPLER_PHASE, (VIDEO_HDTV | VIDEO_PC),   GROUP_NONE,     MODE_PT },                                                                                      \
+    { "720p_50",   HDMI_720p50,      1280,  720,  1980, 0,  750,  220, 20,   40, 5,  DEFAULT_SAMPLER_PHASE, (VIDEO_HDTV | VIDEO_PC),    GROUP_NONE,     MODE_PT },                                                                                      \
+    { "720p_60",   HDMI_720p60,      1280,  720,  1650, 0,  750,  220, 20,   40, 5,  DEFAULT_SAMPLER_PHASE, (VIDEO_HDTV | VIDEO_PC),    GROUP_NONE,     MODE_PT },                                                                                      \
     /* VESA XGA and SXGA modes */ \
-    { "1024x768",   1024,  768,  1344, 0,  806,  160, 29,  136, 6,  DEFAULT_SAMPLER_PHASE, VIDEO_PC,                  GROUP_NONE,     MODE_PT },                                                                                      \
-    { "1280x1024",  1280, 1024,  1688, 0, 1066,  248, 38,  112, 3,  DEFAULT_SAMPLER_PHASE, VIDEO_PC,                  GROUP_NONE,     MODE_PT },                                                                                      \
+    { "1024x768",  HDMI_Unknown,     1024,  768,  1344, 0,  806,  160, 29,  136, 6,  DEFAULT_SAMPLER_PHASE, VIDEO_PC,                   GROUP_NONE,     MODE_PT },                                                                                      \
+    { "1280x1024", HDMI_Unknown,     1280, 1024,  1688, 0, 1066,  248, 38,  112, 3,  DEFAULT_SAMPLER_PHASE, VIDEO_PC,                   GROUP_NONE,     MODE_PT },                                                                                      \
     /* PS2 GSM 960i mode */ \
-    { "640x960i",    640,  480,   800, 0, 1050,   48, 33,   96, 2,  DEFAULT_SAMPLER_PHASE, (VIDEO_EDTV | VIDEO_PC),   GROUP_1080I,    (MODE_PT | MODE_L2 | MODE_INTERLACED) },                                                        \
+    { "640x960i",  HDMI_Unknown,      640,  480,   800, 0, 1050,   48, 33,   96, 2,  DEFAULT_SAMPLER_PHASE, VIDEO_EDTV,                 GROUP_1080I,    (MODE_PT | MODE_L2 | MODE_INTERLACED) },                                                        \
     /* 1080i/p modes */ \
-    { "1080i",      1920,  540,  2200, 0, 1125,  148, 16,   44, 5,  DEFAULT_SAMPLER_PHASE, (VIDEO_HDTV | VIDEO_PC),   GROUP_1080I,    (MODE_PT | MODE_L2 | MODE_INTERLACED) },                                                        \
-    { "1080p",      1920, 1080,  2200, 0, 1125,  148, 36,   44, 5,  DEFAULT_SAMPLER_PHASE, (VIDEO_HDTV | VIDEO_PC),   GROUP_NONE,     MODE_PT },                                                                                      \
+    { "1080i_50",  HDMI_1080i50,     1920,  540,  2640, 0, 1125,  148, 15,   44, 5,  DEFAULT_SAMPLER_PHASE, (VIDEO_HDTV | VIDEO_PC),    GROUP_1080I,    (MODE_PT | MODE_L2 | MODE_INTERLACED) },                                                        \
+    { "1080i_60",  HDMI_1080i60,     1920,  540,  2200, 0, 1125,  148, 16,   44, 5,  DEFAULT_SAMPLER_PHASE, (VIDEO_HDTV | VIDEO_PC),    GROUP_1080I,    (MODE_PT | MODE_L2 | MODE_INTERLACED) },                                                        \
+    { "1080p_50",  HDMI_1080p50,     1920, 1080,  2640, 0, 1125,  148, 36,   44, 5,  DEFAULT_SAMPLER_PHASE, (VIDEO_HDTV | VIDEO_PC),    GROUP_NONE,     MODE_PT },                                                                                      \
+    { "1080p_60",  HDMI_1080p60,     1920, 1080,  2200, 0, 1125,  148, 36,   44, 5,  DEFAULT_SAMPLER_PHASE, (VIDEO_HDTV | VIDEO_PC),    GROUP_NONE,     MODE_PT },                                                                                      \
     /* VESA UXGA with 49 H.backporch cycles exchanged for H.synclen */ \
-    { "1600x1200",  1600, 1200,  2160, 0, 1250,  255, 46,  241, 3,  DEFAULT_SAMPLER_PHASE, VIDEO_PC,                  GROUP_NONE,     MODE_PT },                                                                                      \
+    { "1600x1200", HDMI_Unknown,     1600, 1200,  2160, 0, 1250,  255, 46,  241, 3,  DEFAULT_SAMPLER_PHASE, VIDEO_PC,                   GROUP_NONE,     MODE_PT },                                                                                      \
 }
 
 #define VIDEO_MODES_SIZE (sizeof((mode_data_t[])VIDEO_MODES_DEF))
 #define VIDEO_MODES_CNT (sizeof((mode_data_t[])VIDEO_MODES_DEF)/sizeof(mode_data_t))
 
-alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type typemask);
+alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, alt_u8 h_syncinlen);
 
 #endif /* VIDEO_MODES_H_ */

software/sys_controller/ulibSD/sd_io.c

@@ -32,7 +32,7 @@ DWORD __SD_Sectors (SD_DEV *dev)
         return (((DWORD)(ftell(dev->fp)))/((DWORD)512)-1);
     }
 }
-#else   // For use with uControllers   
+#else   // For use with uControllers
 /******************************************************************************
  Private Methods Prototypes - Direct work with SD card
 ******************************************************************************/
@@ -160,15 +160,15 @@ SDRESULTS __SD_Write_Block(SD_DEV *dev, void *dat, BYTE token)
     WORD idx;
     BYTE line;
     // Send token (single or multiple)
-    SPI_RW(token);
+    SPI_WW(token);
     // Single block write?
     if(token != 0xFD)
     {
         // Send block data
-        for(idx=0; idx!=SD_BLK_SIZE; idx++) SPI_RW(*((BYTE*)dat + idx));
+        for(idx=0; idx!=SD_BLK_SIZE; idx++) SPI_WW(*((BYTE*)dat + idx));
         /* Dummy CRC */
-        SPI_RW(0xFF);
-        SPI_RW(0xFF);
+        SPI_WW(0xFF);
+        SPI_WW(0xFF);
         // If not accepted, returns the reject error
         if((SPI_RW(0xFF) & 0x1F) != 0x05) return(SD_REJECT);
     }
@@ -201,7 +201,7 @@ DWORD __SD_Sectors (SD_DEV *dev)
     BYTE READ_BL_LEN = 0;
     int timer_set;
 
-    if(__SD_Send_Cmd(CMD9, 0)==0) 
+    if(__SD_Send_Cmd(CMD9, 0)==0)
     {
         // Wait for response
         timer_set = SPI_Timer_On(5);  // Wait for data packet (timeout of 5ms)
@@ -262,7 +262,7 @@ DWORD __SD_Sectors (SD_DEV *dev)
 SDRESULTS SD_Init(SD_DEV *dev)
 {
     BYTE initdata[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-#if defined(_M_IX86)    // x86 
+#if defined(_M_IX86)    // x86
     dev->fp = fopen(dev->fn, "r+");
     if (dev->fp == NULL)
         return (SD_ERROR);
@@ -400,7 +400,7 @@ SDRESULTS SD_Read(SD_DEV *dev, void *dat, DWORD sector, WORD ofs, WORD cnt)
         } while((tkn==0xFF)&&(SPI_Timer_Status()==TRUE));
         SPI_Timer_Off();
         // Token of single block?
-        if(tkn==0xFE) { 
+        if(tkn==0xFE) {
             // Size block (512 bytes) + CRC (2 bytes) - offset - bytes to count
             remaining = SD_BLK_SIZE + 2 - ofs - cnt;
             // Skip offset
@@ -447,9 +447,13 @@ SDRESULTS SD_Write(SD_DEV *dev, void *dat, DWORD sector)
 #else   // uControllers
     // Query ok?
     if(sector > dev->last_sector) return(SD_PARERR);
+    // Convert sector number to byte address (sector * SD_BLK_SIZE) for SDC1
+    if (!(dev->cardtype & SDCT_BLOCK))
+        sector *= SD_BLK_SIZE;
+
     // Single block write (token <- 0xFE)
     // Convert sector number to bytes address (sector * SD_BLK_SIZE)
-    if(__SD_Send_Cmd(CMD24, sector * SD_BLK_SIZE)==0)
+    if(__SD_Send_Cmd(CMD24, sector)==0)
         return(__SD_Write_Block(dev, dat, 0xFE));
     else
         return(SD_ERROR);

software/sys_controller/ulibSD/spi_io.c

@@ -15,7 +15,7 @@ void SPI_Init (void) {
     I2C_init(SD_SPI_BASE,ALT_CPU_FREQ,400000);
 }
 
-void SPI_W(BYTE *wd, int len) {
+void SPI_W(const BYTE *wd, int len) {
     SPI_write(SD_SPI_BASE, wd, len);
 }
 
@@ -23,6 +23,10 @@ void SPI_R(BYTE *rd, int len) {
     SPI_read(SD_SPI_BASE, rd, len);
 }
 
+void SPI_WW(BYTE d) {
+    SPI_W(&d, 1);
+}
+
 BYTE SPI_RW (BYTE d) {
     BYTE w;
     SPI_R(&w, 1);

software/sys_controller/ulibSD/spi_io.h

@@ -33,15 +33,21 @@ void SPI_R (BYTE *rd, int len);
     \param *wd Pointer to array which holds the bytes.
     \param len Length of the array.
  */
-void SPI_W (BYTE *wd, int len);
+void SPI_W (const BYTE *wd, int len);
 
 /**
-    \brief Read/Write a single byte.
-    \param d Byte to send.
+    \brief Read a single byte.
+    \param d Byte. Ignored.
     \return Byte that arrived.
  */
 BYTE SPI_RW (BYTE d);
 
+/**
+    \brief Write a single byte.
+    \param d Byte to write.
+ */
+void SPI_WW(BYTE d);
+
 /**
     \brief Flush of SPI buffer.
  */

software/sys_controller_bsp/Makefile

@@ -225,12 +225,12 @@ altera_avalon_timer_driver_C_LIB_SRCS := \
 	$(altera_avalon_timer_driver_SRCS_ROOT)/src/altera_avalon_timer_ts.c \
 	$(altera_avalon_timer_driver_SRCS_ROOT)/src/altera_avalon_timer_vars.c
 
-# altera_epcq_controller_mod_driver sources root 
-altera_epcq_controller_mod_driver_SRCS_ROOT := drivers
+# altera_epcq_controller2_driver sources root
+altera_epcq_controller2_driver_SRCS_ROOT := drivers
 
-# altera_epcq_controller_mod_driver sources 
-altera_epcq_controller_mod_driver_C_LIB_SRCS := \
-	$(altera_epcq_controller_mod_driver_SRCS_ROOT)/src/altera_epcq_controller_mod.c
+# altera_epcq_controller2_driver sources
+altera_epcq_controller2_driver_C_LIB_SRCS := \
+	$(altera_epcq_controller2_driver_SRCS_ROOT)/src/altera_epcq_controller2.c
 
 # altera_nios2_gen2_hal_driver sources root 
 altera_nios2_gen2_hal_driver_SRCS_ROOT := HAL
@@ -276,7 +276,7 @@ nios2_hw_crc32_driver_SRCS_ROOT := drivers
 COMPONENT_C_LIB_SRCS += \
 	$(altera_avalon_jtag_uart_driver_C_LIB_SRCS) \
 	$(altera_avalon_timer_driver_C_LIB_SRCS) \
-	$(altera_epcq_controller_mod_driver_C_LIB_SRCS) \
+	$(altera_epcq_controller2_driver_C_LIB_SRCS) \
 	$(altera_nios2_gen2_hal_driver_C_LIB_SRCS) \
 	$(hal_C_LIB_SRCS) \
 	$(i2c_opencores_driver_C_LIB_SRCS) \

software/sys_controller_bsp/alt_sys_init.c

@@ -61,7 +61,7 @@
 //#include "altera_nios2_gen2_irq.h"
 #include "altera_avalon_jtag_uart.h"
 #include "altera_avalon_timer.h"
-#include "altera_epcq_controller_mod.h"
+#include "altera_epcq_controller2.h"
 #include "i2c_opencores.h"
 
 /*
@@ -71,7 +71,7 @@
 //ALTERA_NIOS2_GEN2_IRQ_INSTANCE ( NIOS2_QSYS_0, nios2_qsys_0);
 ALTERA_AVALON_JTAG_UART_INSTANCE ( JTAG_UART_0, jtag_uart_0);
 ALTERA_AVALON_TIMER_INSTANCE ( TIMER_0, timer_0);
-ALTERA_EPCQ_CONTROLLER_MOD_AVL_MEM_AVL_CSR_INSTANCE ( EPCQ_CONTROLLER_0, EPCQ_CONTROLLER_0_AVL_MEM, EPCQ_CONTROLLER_0_AVL_CSR, epcq_controller_0);
+ALTERA_EPCQ_CONTROLLER2_AVL_MEM_AVL_CSR_INSTANCE ( EPCQ_CONTROLLER2_0, EPCQ_CONTROLLER2_0_AVL_MEM, EPCQ_CONTROLLER2_0_AVL_CSR, epcq_controller2_0);
 I2C_OPENCORES_INSTANCE ( I2C_OPENCORES_0, i2c_opencores_0);
 I2C_OPENCORES_INSTANCE ( I2C_OPENCORES_1, i2c_opencores_1);
 
@@ -98,7 +98,7 @@ void alt_sys_init( void )
 {
     ALTERA_AVALON_TIMER_INIT ( TIMER_0, timer_0);
     ALTERA_AVALON_JTAG_UART_INIT ( JTAG_UART_0, jtag_uart_0);
-    ALTERA_EPCQ_CONTROLLER_MOD_INIT ( EPCQ_CONTROLLER_0, epcq_controller_0);
+    ALTERA_EPCQ_CONTROLLER2_INIT ( EPCQ_CONTROLLER2_0, epcq_controller2_0);
     I2C_OPENCORES_INIT ( I2C_OPENCORES_0, i2c_opencores_0);
     I2C_OPENCORES_INIT ( I2C_OPENCORES_1, i2c_opencores_1);
 }

software/sys_controller_bsp/drivers/inc/altera_epcq_controller2.h

@@ -28,8 +28,8 @@
 *                                                                             *
 ******************************************************************************/
 
-#ifndef __ALT_EPCQ_CONTROLLER_H__
-#define __ALT_EPCQ_CONTROLLER_H__
+#ifndef __ALT_EPCQ_CONTROLLER2_H__
+#define __ALT_EPCQ_CONTROLLER2_H__
 
 #include "alt_types.h"
 #include "sys/alt_flash_dev.h"
@@ -43,7 +43,7 @@ extern "C"
 /**
  *  Description of the EPCQ controller
  */
-typedef struct alt_epcq_controller_dev
+typedef struct alt_epcq_controller2_dev
 {
     alt_flash_dev dev;
 
@@ -56,25 +56,25 @@ typedef struct alt_epcq_controller_dev
     alt_u32 sector_size; /** size of each flash sector */
     alt_u32 page_size; /** page size */
     alt_u32 silicon_id; /** ID of silicon used with EPCQ IP */
-} alt_epcq_controller_dev;
+} alt_epcq_controller2_dev;
 
 /**
 *   Macros used by alt_sys_init.c to create data storage for driver instance
 */
-#define ALTERA_EPCQ_CONTROLLER_MOD_AVL_MEM_AVL_CSR_INSTANCE(epcq_name, avl_mem, avl_csr, epcq_dev) \
-alt_epcq_controller_dev epcq_dev =                                                       \
+#define ALTERA_EPCQ_CONTROLLER2_AVL_MEM_AVL_CSR_INSTANCE(epcq_name, avl_mem, avl_csr, epcq_dev) \
+static alt_epcq_controller2_dev epcq_dev =                                                       \
 {                                                                                               \
   .dev = {                                                                                      \
             .llist = ALT_LLIST_ENTRY,                                                           \
             .name = avl_mem##_NAME,                                                             \
-            .write = alt_epcq_controller_write,                                                 \
-            .read = alt_epcq_controller_read,                                                   \
-            .get_info = alt_epcq_controller_get_info,                                           \
-            .erase_block = alt_epcq_controller_erase_block,                                     \
-            .write_block = alt_epcq_controller_write_block,                                     \
+            .write = alt_epcq_controller2_write,                                                 \
+            .read = alt_epcq_controller2_read,                                                   \
+            .get_info = alt_epcq_controller2_get_info,                                           \
+            .erase_block = alt_epcq_controller2_erase_block,                                     \
+            .write_block = alt_epcq_controller2_write_block,                                     \
             .base_addr = ((void*)(avl_mem##_BASE)),                                             \
             .length = ((int)(avl_mem##_SPAN)),                                                  \
-            .lock = alt_epcq_controller_lock ,                                                  \
+            .lock = alt_epcq_controller2_lock ,                                                  \
          },                                                                                     \
   .data_base = ((alt_u32)(avl_mem##_BASE)),   							\
   .data_end = ((alt_u32)(avl_mem##_BASE) + (alt_u32)(avl_mem##_SPAN)),	                        \
@@ -94,33 +94,33 @@ alt_epcq_controller_dev epcq_dev =
     of the Nios II Software Developer's Handbook.
 
 */
-int alt_epcq_controller_read(alt_flash_dev *flash_info, int offset, void *dest_addr, int length);
+int alt_epcq_controller2_read(alt_flash_dev *flash_info, int offset, void *dest_addr, int length);
 
-int alt_epcq_controller_get_info(alt_flash_fd *fd, flash_region **info, int *number_of_regions);
+int alt_epcq_controller2_get_info(alt_flash_fd *fd, flash_region **info, int *number_of_regions);
 
-int alt_epcq_controller_erase_block(alt_flash_dev *flash_info, int block_offset);
+int alt_epcq_controller2_erase_block(alt_flash_dev *flash_info, int block_offset);
 
-int alt_epcq_controller_write_block(alt_flash_dev *flash_info, int block_offset, int data_offset, const void *data, int length);
+int alt_epcq_controller2_write_block(alt_flash_dev *flash_info, int block_offset, int data_offset, const void *data, int length);
 
-int alt_epcq_controller_write(alt_flash_dev *flash_info, int offset, const void *src_addr, int length);
+int alt_epcq_controller2_write(alt_flash_dev *flash_info, int offset, const void *src_addr, int length);
 
-int alt_epcq_controller_lock(alt_flash_dev *flash_info, alt_u32 sectors_to_lock);
+int alt_epcq_controller2_lock(alt_flash_dev *flash_info, alt_u32 sectors_to_lock);
 
 
 /*
  * Initialization function
  */
-extern alt_32 altera_epcq_controller_init(alt_epcq_controller_dev *dev);
+extern alt_32 altera_epcq_controller2_init(alt_epcq_controller2_dev *dev);
 
 /*
  * alt_sys_init.c will call this macro automatically initialize the driver instance
  */
-#define ALTERA_EPCQ_CONTROLLER_MOD_INIT(name, dev) 	\
-		altera_epcq_controller_init(&dev);
+#define ALTERA_EPCQ_CONTROLLER2_INIT(name, dev) 	\
+		altera_epcq_controller2_init(&dev);
 
 
 #ifdef __cplusplus
 }
 #endif /* __cplusplus */
 
-#endif /* __ALT_EPCQ_CONTROLLER_H__ */
+#endif /* __ALT_EPCQ_CONTROLLER2_H__ */

software/sys_controller_bsp/drivers/inc/altera_epcq_controller2_regs.h

@@ -28,8 +28,8 @@
 *                                                                             *
 ******************************************************************************/
 
-#ifndef __ALTERA_EPCQ_CONTROLLER_REGS_H__
-#define __ALTERA_EPCQ_CONTROLLER_REGS_H__
+#ifndef __ALTERA_EPCQ_CONTROLLER2_REGS_H__
+#define __ALTERA_EPCQ_CONTROLLER2_REGS_H__
 
 #include <io.h>
 
@@ -41,31 +41,31 @@
  * data sheet,
  *
  */
-#define ALTERA_EPCQ_CONTROLLER_STATUS_REG                       (0x0)
+#define ALTERA_EPCQ_CONTROLLER2_STATUS_REG                       (0x0)
 
 /*
  * EPCQ_RD_STATUS register access macros
  */
-#define IOADDR_ALTERA_EPCQ_CONTROLLER_STATUS(base) \
-    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_STATUS_REG)
+#define IOADDR_ALTERA_EPCQ_CONTROLLER2_STATUS(base) \
+    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER2_STATUS_REG)
 
-#define IORD_ALTERA_EPCQ_CONTROLLER_STATUS(base) \
-    IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_STATUS_REG)
+#define IORD_ALTERA_EPCQ_CONTROLLER2_STATUS(base) \
+    IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_STATUS_REG)
 
-#define IOWR_ALTERA_EPCQ_CONTROLLER_STATUS(base, data) \
-    IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_STATUS_REG, data)
+#define IOWR_ALTERA_EPCQ_CONTROLLER2_STATUS(base, data) \
+    IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_STATUS_REG, data)
 
 /*
  * EPCQ_RD_STATUS register description macros
  */
 
 /** Write in progress bit */
-#define ALTERA_EPCQ_CONTROLLER_STATUS_WIP_MASK                  (0x00000001)
-#define ALTERA_EPCQ_CONTROLLER_STATUS_WIP_AVAILABLE             (0x00000000)
-#define ALTERA_EPCQ_CONTROLLER_STATUS_WIP_BUSY                  (0x00000001)
+#define ALTERA_EPCQ_CONTROLLER2_STATUS_WIP_MASK                  (0x00000001)
+#define ALTERA_EPCQ_CONTROLLER2_STATUS_WIP_AVAILABLE             (0x00000000)
+#define ALTERA_EPCQ_CONTROLLER2_STATUS_WIP_BUSY                  (0x00000001)
 /** When to time out a poll of the write in progress bit */
 /* 0.7 sec time out */
-#define ALTERA_EPCQ_CONTROLLER_1US_TIMEOUT_VALUE    		    700000 
+#define ALTERA_EPCQ_CONTROLLER2_1US_TIMEOUT_VALUE                700000 
 
 /*
  * EPCQ_RD_SID register offset
@@ -77,19 +77,19 @@
  * This register is valid only if the device is an EPCS.
  *
  */
-#define ALTERA_EPCQ_CONTROLLER_SID_REG                          (0x4)
+#define ALTERA_EPCQ_CONTROLLER2_SID_REG                          (0x4)
 
 /*
  * EPCQ_RD_SID register access macros
  */
-#define IOADDR_ALTERA_EPCQ_CONTROLLER_SID(base) \
-    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_SID_REG)
+#define IOADDR_ALTERA_EPCQ_CONTROLLER2_SID(base) \
+    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER2_SID_REG)
 
-#define IORD_ALTERA_EPCQ_CONTROLLER_SID(base) \
-    IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_SID_REG)
+#define IORD_ALTERA_EPCQ_CONTROLLER2_SID(base) \
+    IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_SID_REG)
 
-#define IOWR_ALTERA_EPCQ_CONTROLLER_SID(base, data) \
-    IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_SID_REG, data)
+#define IOWR_ALTERA_EPCQ_CONTROLLER2_SID(base, data) \
+    IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_SID_REG, data)
 
 /*
  * EPCQ_RD_SID register description macros
@@ -97,10 +97,10 @@
  * Specific device values obtained from Table 14 of: 
  * "Serial Configuration (EPCS) Devices Datasheet"
  */
-#define ALTERA_EPCQ_CONTROLLER_SID_MASK                         (0x000000FF)
-#define ALTERA_EPCQ_CONTROLLER_SID_EPCS16                       (0x00000014)
-#define ALTERA_EPCQ_CONTROLLER_SID_EPCS64                       (0x00000016)
-#define ALTERA_EPCQ_CONTROLLER_SID_EPCS128                      (0x00000018)
+#define ALTERA_EPCQ_CONTROLLER2_SID_MASK                         (0x000000FF)
+#define ALTERA_EPCQ_CONTROLLER2_SID_EPCS16                       (0x00000014)
+#define ALTERA_EPCQ_CONTROLLER2_SID_EPCS64                       (0x00000016)
+#define ALTERA_EPCQ_CONTROLLER2_SID_EPCS128                      (0x00000018)
 
 /*
  * EPCQ_RD_RDID register offset
@@ -112,19 +112,19 @@
  * This register is only valid if the device is an EPCQ.
  *
  */
-#define ALTERA_EPCQ_CONTROLLER_RDID_REG                         (0x8)
+#define ALTERA_EPCQ_CONTROLLER2_RDID_REG                         (0x8)
 
 /*
  * EPCQ_RD_RDID register access macros
  */
-#define IOADDR_ALTERA_EPCQ_CONTROLLER_RDID(base) \
-    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_RDID_REG)
+#define IOADDR_ALTERA_EPCQ_CONTROLLER2_RDID(base) \
+    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER2_RDID_REG)
 
-#define IORD_ALTERA_EPCQ_CONTROLLER_RDID(base) \
-    IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_RDID_REG)
+#define IORD_ALTERA_EPCQ_CONTROLLER2_RDID(base) \
+    IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_RDID_REG)
 
-#define IOWR_ALTERA_EPCQ_CONTROLLER_RDID(base, data) \
-    IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_RDID_REG, data)
+#define IOWR_ALTERA_EPCQ_CONTROLLER2_RDID(base, data) \
+    IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_RDID_REG, data)
 
 /*
  * EPCQ_RD_RDID register description macros
@@ -133,14 +133,14 @@
  *  "Quad-Serial Configuration (EPCQ (www.altera.com/literature/hb/cfg/cfg_cf52012.pdf))
  *  Devices Datasheet"
  */
-#define ALTERA_EPCQ_CONTROLLER_RDID_MASK                         (0x000000FF)
-#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ16                       (0x00000015)
-#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ32                       (0x00000016)
-#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ64                       (0x00000017)
-#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ128                      (0x00000018)
-#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ256                      (0x00000019)
-#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ512                      (0x00000020)
-#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ1024                     (0x00000021)
+#define ALTERA_EPCQ_CONTROLLER2_RDID_MASK                         (0x000000FF)
+#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ16                       (0x00000015)
+#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ32                       (0x00000016)
+#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ64                       (0x00000017)
+#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ128                      (0x00000018)
+#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ256                      (0x00000019)
+#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ512                      (0x00000020)
+#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ1024                     (0x00000021)
 
 /*
  * EPCQ_MEM_OP register offset
@@ -148,30 +148,31 @@
  * The EPCQ_MEM_OP register is used to do memory protect and erase operations
  *
  */
-#define ALTERA_EPCQ_CONTROLLER_MEM_OP_REG                       (0xC)
+#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_REG                       (0xC)
 
 /*
  * EPCQ_MEM_OP register access macros
  */
-#define IOADDR_ALTERA_EPCQ_CONTROLLER_MEM_OP(base) \
-    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_MEM_OP_REG)
+#define IOADDR_ALTERA_EPCQ_CONTROLLER2_MEM_OP(base) \
+    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER2_MEM_OP_REG)
 
-#define IORD_ALTERA_EPCQ_CONTROLLER_MEM_OP(base) \
-    IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_MEM_OP_REG)
+#define IORD_ALTERA_EPCQ_CONTROLLER2_MEM_OP(base) \
+    IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_MEM_OP_REG)
 
-#define IOWR_ALTERA_EPCQ_CONTROLLER_MEM_OP(base, data) \
-    IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_MEM_OP_REG, data)
+#define IOWR_ALTERA_EPCQ_CONTROLLER2_MEM_OP(base, data) \
+    IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_MEM_OP_REG, data)
 
 /*
  * EPCQ_MEM_OP register description macros
  */
-#define ALTERA_EPCQ_CONTROLLER_MEM_OP_CMD_MASK                  (0x00000003)
-#define ALTERA_EPCQ_CONTROLLER_MEM_OP_BULK_ERASE_CMD            (0x00000001)
-#define ALTERA_EPCQ_CONTROLLER_MEM_OP_SECTOR_ERASE_CMD          (0x00000002)
-#define ALTERA_EPCQ_CONTROLLER_MEM_OP_SECTOR_PROTECT_CMD        (0x00000003)
+#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_CMD_MASK                  (0x00000003)
+#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_BULK_ERASE_CMD            (0x00000001)
+#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_ERASE_CMD          (0x00000002)
+#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_PROTECT_CMD        (0x00000003)
+#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_WRITE_ENABLE_CMD          (0x00000004)
 
 /** see datasheet for sector values */
-#define ALTERA_EPCQ_CONTROLLER_MEM_OP_SECTOR_VALUE_MASK         (0x00FFFF00)
+#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_VALUE_MASK         (0x00FFFF00)
 
 /*
  * EPCQ_ISR register offset
@@ -180,28 +181,28 @@
  * operation triggered an interrupt
  *
  */
-#define ALTERA_EPCQ_CONTROLLER_ISR_REG                          (0x10)
+#define ALTERA_EPCQ_CONTROLLER2_ISR_REG                          (0x10)
 
 /*
  * EPCQ_ISR register access macros
  */
-#define IOADDR_ALTERA_EPCQ_CONTROLLER_ISR(base) \
-    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_ISR_REG)
+#define IOADDR_ALTERA_EPCQ_CONTROLLER2_ISR(base) \
+    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER2_ISR_REG)
 
-#define IORD_ALTERA_EPCQ_CONTROLLER_ISR(base) \
-    IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_ISR_REG)
+#define IORD_ALTERA_EPCQ_CONTROLLER2_ISR(base) \
+    IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_ISR_REG)
 
-#define IOWR_ALTERA_EPCQ_CONTROLLER_ISR(base, data) \
-    IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_ISR_REG, data)
+#define IOWR_ALTERA_EPCQ_CONTROLLER2_ISR(base, data) \
+    IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_ISR_REG, data)
 
 /*
  * EPCQ_ISR register description macros
  */
-#define ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_ERASE_MASK           (0x00000001)
-#define ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_ERASE_ACTIVE         (0x00000001)
+#define ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_ERASE_MASK           (0x00000001)
+#define ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_ERASE_ACTIVE         (0x00000001)
 
-#define ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_WRITE_MASK           (0x00000002)
-#define ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_WRITE_ACTIVE         (0x00000002)
+#define ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_WRITE_MASK           (0x00000002)
+#define ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_WRITE_ACTIVE         (0x00000002)
 
 
 /*
@@ -211,28 +212,28 @@
  * interrupts.
  *
  */
-#define ALTERA_EPCQ_CONTROLLER_IMR_REG                          (0x14)
+#define ALTERA_EPCQ_CONTROLLER2_IMR_REG                          (0x14)
 
 /*
  * EPCQ_IMR register access macros
  */
-#define IOADDR_ALTERA_EPCQ_CONTROLLER_IMR(base) \
-    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_IMR_REG)
+#define IOADDR_ALTERA_EPCQ_CONTROLLER2_IMR(base) \
+    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER2_IMR_REG)
 
-#define IORD_ALTERA_EPCQ_CONTROLLER_IMR(base) \
-    IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_IMR_REG)
+#define IORD_ALTERA_EPCQ_CONTROLLER2_IMR(base) \
+    IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_IMR_REG)
 
-#define IOWR_ALTERA_EPCQ_CONTROLLER_IMR(base, data) \
-    IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_IMR_REG, data)
+#define IOWR_ALTERA_EPCQ_CONTROLLER2_IMR(base, data) \
+    IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_IMR_REG, data)
 
 /*
  * EPCQ_IMR register description macros
  */
-#define ALTERA_EPCQ_CONTROLLER_IMR_ILLEGAL_ERASE_MASK           (0x00000001)
-#define ALTERA_EPCQ_CONTROLLER_IMR_ILLEGAL_ERASE_ENABLED        (0x00000001)
+#define ALTERA_EPCQ_CONTROLLER2_IMR_ILLEGAL_ERASE_MASK           (0x00000001)
+#define ALTERA_EPCQ_CONTROLLER2_IMR_ILLEGAL_ERASE_ENABLED        (0x00000001)
 
-#define ALTERA_EPCQ_CONTROLLER_IMR_ILLEGAL_WRITE_MASK           (0x00000002)
-#define ALTERA_EPCQ_CONTROLLER_IMR_ILLEGAL_WRITE_ENABLED        (0x00000002)
+#define ALTERA_EPCQ_CONTROLLER2_IMR_ILLEGAL_WRITE_MASK           (0x00000002)
+#define ALTERA_EPCQ_CONTROLLER2_IMR_ILLEGAL_WRITE_ENABLED        (0x00000002)
 
 /*
  * EPCQ_CHIP_SELECT register offset
@@ -257,4 +258,4 @@
 #define ALTERA_EPCQ_CHIP2_SELECT        (0x00000002)
 #define ALTERA_EPCQ_CHIP3_SELECT        (0x00000003)
 
-#endif /* __ALTERA_EPCQ_CONTROLLER_REGS_H__ */
+#endif /* __ALTERA_EPCQ_CONTROLLER2_REGS_H__ */

software/sys_controller_bsp/drivers/inc/altera_epcq_controller_mod.h

@@ -1,126 +0,0 @@
-/******************************************************************************
-*                                                                             *
-* License Agreement                                                           *
-*                                                                             *
-* Copyright (c) 2015 Altera Corporation, San Jose, California, USA.           *
-* All rights reserved.                                                        *
-*                                                                             *
-* Permission is hereby granted, free of charge, to any person obtaining a     *
-* copy of this software and associated documentation files (the "Software"),  *
-* to deal in the Software without restriction, including without limitation   *
-* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
-* and/or sell copies of the Software, and to permit persons to whom the       *
-* Software is furnished to do so, subject to the following conditions:        *
-*                                                                             *
-* The above copyright notice and this permission notice shall be included in  *
-* all copies or substantial portions of the Software.                         *
-*                                                                             *
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
-* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
-* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
-* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
-* DEALINGS IN THE SOFTWARE.                                                   *
-*                                                                             *
-* This agreement shall be governed in all respects by the laws of the State   *
-* of California and by the laws of the United States of America.              *
-*                                                                             *
-******************************************************************************/
-
-#ifndef __ALT_EPCQ_CONTROLLER_H__
-#define __ALT_EPCQ_CONTROLLER_H__
-
-#include "alt_types.h"
-#include "sys/alt_flash_dev.h"
-#include "sys/alt_llist.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif /* __cplusplus */
-
-/**
- *  Description of the EPCQ controller
- */
-typedef struct alt_epcq_controller_dev
-{
-    alt_flash_dev dev;
-
-    alt_u32 data_base; /** base address of data slave */
-    alt_u32 data_end; /** end address of data slave (not inclusive) */
-    alt_u32 csr_base; /** base address of CSR slave */
-    alt_u32 size_in_bytes; /** size of memory in bytes */
-    alt_u32 is_epcs; /** 1 if device is an EPCS device */
-    alt_u32 number_of_sectors; /** number of flash sectors */
-    alt_u32 sector_size; /** size of each flash sector */
-    alt_u32 page_size; /** page size */
-    alt_u32 silicon_id; /** ID of silicon used with EPCQ IP */
-} alt_epcq_controller_dev;
-
-/**
-*   Macros used by alt_sys_init.c to create data storage for driver instance
-*/
-#define ALTERA_EPCQ_CONTROLLER_MOD_AVL_MEM_AVL_CSR_INSTANCE(epcq_name, avl_mem, avl_csr, epcq_dev) \
-alt_epcq_controller_dev epcq_dev =                                                       \
-{                                                                                               \
-  .dev = {                                                                                      \
-            .llist = ALT_LLIST_ENTRY,                                                           \
-            .name = avl_mem##_NAME,                                                             \
-            .write = alt_epcq_controller_write,                                                 \
-            .read = alt_epcq_controller_read,                                                   \
-            .get_info = alt_epcq_controller_get_info,                                           \
-            .erase_block = alt_epcq_controller_erase_block,                                     \
-            .write_block = alt_epcq_controller_write_block,                                     \
-            .base_addr = ((void*)(avl_mem##_BASE)),                                             \
-            .length = ((int)(avl_mem##_SPAN)),                                                  \
-            .lock = alt_epcq_controller_lock ,                                                  \
-         },                                                                                     \
-  .data_base = ((alt_u32)(avl_mem##_BASE)),   							\
-  .data_end = ((alt_u32)(avl_mem##_BASE) + (alt_u32)(avl_mem##_SPAN)),	                        \
-  .csr_base = ((alt_u32)(avl_csr##_BASE)),   							\
-  .size_in_bytes = ((alt_u32)(avl_mem##_SPAN)),         				        \
-  .is_epcs = ((alt_u32)(avl_mem##_IS_EPCS)),							\
-  .number_of_sectors = ((alt_u32)(avl_mem##_NUMBER_OF_SECTORS)),			        \
-  .sector_size = ((alt_u32)(avl_mem##_SECTOR_SIZE)),						\
-  .page_size = ((alt_u32)(avl_mem##_PAGE_SIZE))	,						\
-}
-
-/*
-    Public API
-
-    Refer to Using Flash Devices in the
-    Developing Programs Using the Hardware Abstraction Layer chapter
-    of the Nios II Software Developer's Handbook.
-
-*/
-int alt_epcq_controller_read(alt_flash_dev *flash_info, int offset, void *dest_addr, int length);
-
-int alt_epcq_controller_get_info(alt_flash_fd *fd, flash_region **info, int *number_of_regions);
-
-int alt_epcq_controller_erase_block(alt_flash_dev *flash_info, int block_offset);
-
-int alt_epcq_controller_write_block(alt_flash_dev *flash_info, int block_offset, int data_offset, const void *data, int length);
-
-int alt_epcq_controller_write(alt_flash_dev *flash_info, int offset, const void *src_addr, int length);
-
-int alt_epcq_controller_lock(alt_flash_dev *flash_info, alt_u32 sectors_to_lock);
-
-
-/*
- * Initialization function
- */
-extern alt_32 altera_epcq_controller_init(alt_epcq_controller_dev *dev);
-
-/*
- * alt_sys_init.c will call this macro automatically initialize the driver instance
- */
-#define ALTERA_EPCQ_CONTROLLER_MOD_INIT(name, dev) 	\
-		altera_epcq_controller_init(&dev);
-
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __ALT_EPCQ_CONTROLLER_H__ */

software/sys_controller_bsp/drivers/inc/i2c_opencores.h

@@ -1,33 +0,0 @@
-#ifndef __I2C_OPENCORES_H__
-#define __I2C_OPENCORES_H__
-
-
-#include "alt_types.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif /* __cplusplus */
-
-#define SCL_MIN_CLKDIV 10
-
-
-void I2C_init(alt_u32 base,alt_u32 clk,alt_u32 speed);
-int I2C_start(alt_u32 base, alt_u32 add, alt_u32 read);
-alt_u32 I2C_read(alt_u32 base,alt_u32 last);
-alt_u32 I2C_write(alt_u32 base,alt_u8 data, alt_u32 last);
-void SPI_read(alt_u32 base, alt_u8 *rdata, int len);
-void SPI_write(alt_u32 base, alt_u8 *wdata, int len);
-#define I2C_OK (0)
-#define I2C_ACK (0)
-#define I2C_NOACK (1)
-#define I2C_ABITRATION_LOST (2)
-
-#define I2C_OPENCORES_INSTANCE(name, dev) extern int alt_no_storage
-#define I2C_OPENCORES_INIT(name, dev) while (0)
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __I2C_OPENCORES_H__ */

software/sys_controller_bsp/drivers/inc/i2c_opencores.h

@@ -0,0 +1 @@
+../../../../ip/i2c_opencores/HAL/inc/i2c_opencores.h

software/sys_controller_bsp/drivers/inc/i2c_opencores_regs.h

@@ -1,77 +0,0 @@
-
-
-#ifndef __I2C_OPENCORES_REGS_H__
-#define __I2C_OPENCORES_REGS_H__
-
-#include <io.h>
-/* prescal   clock/(5*desired_SCL) */
-/* all registers are 8 bits wide but on 32 bit address boundaries.*/
-/* reg definitions take from i2c_specs.pdf in the docs folder */
-
-#define IOADDR_I2C_OPENCORES_PRERLO(base)           __IO_CALC_ADDRESS_NATIVE(base, 0)
-#define IORD_I2C_OPENCORES_PRERLO(base)             IORD(base, 0)
-#define IOWR_I2C_OPENCORES_PRERLO(base, data)       IOWR(base, 0, data)
-
-
-#define IOADDR_I2C_OPENCORES_PRERHI(base)           __IO_CALC_ADDRESS_NATIVE(base, 0)
-#define IORD_I2C_OPENCORES_PRERHI(base)             IORD(base, 1)
-#define IOWR_I2C_OPENCORES_PRERHI(base, data)       IOWR(base, 1, data)
-
-
-#define IOADDR_I2C_OPENCORES_CTR(base)      __IO_CALC_ADDRESS_NATIVE(base, 2)
-#define IORD_I2C_OPENCORES_CTR(base)        IORD(base, 2)
-#define IOWR_I2C_OPENCORES_CTR(base, data)  IOWR(base, 2, data)
-/* bit definitions*/
-#define I2C_OPENCORES_CTR_EN_MSK             (0x80)
-#define I2C_OPENCORES_CTR_EN_OFST            (7)
-#define I2C_OPENCORES_CTR_IEN_MSK            (0x40)
-#define I2C_OPENCORES_CTR_IEN_OFST           (6)
-
-
-#define IOADDR_I2C_OPENCORES_TXR(base)       __IO_CALC_ADDRESS_NATIVE(base, 3)
-#define IOWR_I2C_OPENCORES_TXR(base, data)   IOWR(base, 3, data)
-/* bit definitions*/
-#define I2C_OPENCORES_TXR_RD_MSK             (0x1)
-#define I2C_OPENCORES_TXR_RD_OFST            (0)
-#define I2C_OPENCORES_TXR_WR_MSK             (0x0)
-#define I2C_OPENCORES_TXR_WR_OFST            (0)
-
-
-#define IOADDR_I2C_OPENCORES_RXR(base)       __IO_CALC_ADDRESS_NATIVE(base, 3)
-#define IORD_I2C_OPENCORES_RXR(base)         IORD(base, 3)
-
-
-#define IOADDR_I2C_OPENCORES_CR(base)       __IO_CALC_ADDRESS_NATIVE(base, 4)
-#define IOWR_I2C_OPENCORES_CR(base, data)   IOWR(base, 4, data)
-/* bit definitions*/
-#define I2C_OPENCORES_CR_STA_MSK             (0x80)
-#define I2C_OPENCORES_CR_STA_OFST            (7)
-#define I2C_OPENCORES_CR_STO_MSK             (0x40)
-#define I2C_OPENCORES_CR_STO_OFST            (6)
-#define I2C_OPENCORES_CR_RD_MSK              (0x20)
-#define I2C_OPENCORES_CR_RD_OFST             (5)
-#define I2C_OPENCORES_CR_WR_MSK              (0x10)
-#define I2C_OPENCORES_CR_WR_OFST             (4)
-#define I2C_OPENCORES_CR_NACK_MSK             (0x8)
-#define I2C_OPENCORES_CR_NACK_OFST            (3)
-#define I2C_OPENCORES_CR_SPIM_MSK             (0x4)
-#define I2C_OPENCORES_CR_SPIM_OFST            (2)
-#define I2C_OPENCORES_CR_IACK_MSK            (0x1)
-#define I2C_OPENCORES_CR_IACK_OFST           (0)
-
-
-#define IOADDR_I2C_OPENCORES_SR(base)       __IO_CALC_ADDRESS_NATIVE(base, 4)
-#define IORD_I2C_OPENCORES_SR(base)         IORD(base, 4)
-/* bit definitions*/
-#define I2C_OPENCORES_SR_RXNACK_MSK           (0x80)
-#define I2C_OPENCORES_SR_RXNACK_OFST          (7)
-#define I2C_OPENCORES_SR_BUSY_MSK            (0x40)
-#define I2C_OPENCORES_SR_BUSY_OFST           (6)
-#define I2C_OPENCORES_SR_AL_MSK              (0x20)
-#define I2C_OPENCORES_SR_AL_OFST             (5)
-#define I2C_OPENCORES_SR_TIP_MSK             (0x2)
-#define I2C_OPENCORES_SR_TIP_OFST            (1)
-#define I2C_OPENCORES_SR_IF_MSK              (0x1)
-#define I2C_OPENCORES_SR_IF_OFST             (0)
-
-#endif /* __I2C_OPENCORES_REGS_H__ */

software/sys_controller_bsp/drivers/inc/i2c_opencores_regs.h

@@ -0,0 +1 @@
+../../../../ip/i2c_opencores/inc/i2c_opencores_regs.h