Florian Reitz
|
c93b63a92c
|
Skip boot added
|
2017-11-30 16:25:11 +01:00 |
|
Florian Reitz
|
331b84cc17
|
Change in makefile and folder structure
|
2017-11-30 13:00:06 +01:00 |
|
Unknown
|
2df245675d
|
Schematic updated
|
2017-11-30 12:14:54 +01:00 |
|
Florian Reitz
|
ab87f81ba8
|
Boot verified for IIgs, IIe 128k and IIe 64k
|
2017-11-29 01:20:44 +01:00 |
|
Florian Reitz
|
741624f3b5
|
IIgs boot working!!!
|
2017-11-26 21:26:15 +01:00 |
|
Florian Reitz
|
4feea40b5d
|
VS2015 project added
|
2017-11-26 00:19:35 +01:00 |
|
Florian Reitz
|
0f92b7cf03
|
Source updated for CC65
|
2017-11-25 23:23:25 +01:00 |
|
freitz85
|
505fe10434
|
SDHC flag added to CPLD
|
2017-11-25 19:42:33 +01:00 |
|
Florian Reitz
|
6517f86ce3
|
Load block 0 and 1 on boot
|
2017-11-20 19:13:16 +01:00 |
|
freitz85
|
9aa65960c4
|
SPI Mode 3
|
2017-11-01 16:50:56 +01:00 |
|
Florian Reitz
|
e9bd383d2e
|
Save and restore ZP locations
Shorter read write loops
|
2017-11-01 16:22:35 +01:00 |
|
freitz85
|
cf98c54e77
|
Linear addressing from Cn00
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2017-10-23 22:42:27 +02:00 |
|
Florian Reitz
|
b0df142692
|
Linear addressing from C700, test code added to ram
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2017-10-22 20:50:14 +02:00 |
|
Florian Reitz
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9e674fe0c6
|
Hex file for new address mapping
|
2017-10-17 00:06:33 +02:00 |
|
freitz85
|
c5945ff0ec
|
New address decoding
|
2017-10-16 22:53:41 +02:00 |
|
freitz85
|
b37df65a45
|
Test for old AddressDecoder
|
2017-10-16 22:01:41 +02:00 |
|
Unknown
|
f2314f838d
|
IRQ Pin removed, A11 added
|
2017-10-16 21:42:57 +02:00 |
|
freitz85
|
70def47cf2
|
More VDHL tests added
|
2017-10-15 20:58:33 +02:00 |
|
Florian Reitz
|
f20a1d529d
|
Test routine added
|
2017-10-15 16:48:13 +02:00 |
|
freitz85
|
723406657e
|
Fixes according to IIgs Tech Note #68
|
2017-10-13 23:04:38 +02:00 |
|
freitz85
|
eeb0b14725
|
AddressDecoder testbench
|
2017-10-12 20:37:37 +02:00 |
|
freitz85
|
819904bea2
|
Spi simulation working
|
2017-10-10 23:37:21 +02:00 |
|
freitz85
|
cc9d9d21db
|
Rename files
|
2017-10-10 22:57:47 +02:00 |
|
freitz85
|
7e2414c1bf
|
AddressDecoder in VHDL
|
2017-10-10 22:36:48 +02:00 |
|
freitz85
|
74c6b83b4e
|
Synthesis guards for debug signals
|
2017-10-10 21:58:22 +02:00 |
|
freitz85
|
2e4ebd9ac0
|
Test bench worst and best case timings
|
2017-10-10 21:22:18 +02:00 |
|
freitz85
|
8a6e7e647e
|
Test bench
|
2017-10-10 02:53:21 +02:00 |
|
freitz85
|
797993500e
|
Test bench added
|
2017-10-10 01:35:18 +02:00 |
|
freitz85
|
c03bc37834
|
Test bench
|
2017-10-10 00:41:31 +02:00 |
|
freitz85
|
caa40196d7
|
Removed BUFG constraint warnings
|
2017-10-09 23:35:52 +02:00 |
|
freitz85
|
b888590d11
|
Top level in VHDL
|
2017-10-09 22:35:47 +02:00 |
|
freitz85
|
c41ff87f8f
|
Merge remote-tracking branch 'origin/devel' into devel
|
2017-10-09 22:30:03 +02:00 |
|
Unknown
|
4f3dca7cc9
|
Timing diagram added
|
2017-10-09 08:49:22 +02:00 |
|
freitz85
|
84cfbdde92
|
test with clocked input buffers
|
2017-10-08 21:48:07 +02:00 |
|
Florian Reitz
|
ff074dc995
|
Merge remote-tracking branch 'origin/devel' into devel
|
2017-10-05 23:12:47 +02:00 |
|
Florian Reitz
|
763a99022c
|
Merge branch 'master' into devel
|
2017-10-05 23:05:31 +02:00 |
|
Florian Reitz
|
75b50c96ce
|
Check for init failure
|
2017-10-05 23:03:31 +02:00 |
|
Florian Reitz
|
d0a9254893
|
several fixes tried
|
2017-10-05 22:57:38 +02:00 |
|
Unknown
|
a15abda39b
|
PLCC44 Socket Pinout
|
2017-10-05 19:30:21 +02:00 |
|
Florian Reitz
|
c438775789
|
Check for init failure
|
2017-10-03 17:46:50 +02:00 |
|
freitz85
|
9c3b1c33ff
|
Reset inited on card remove
|
2017-09-10 14:07:23 +02:00 |
|
freitz85
|
04e26f32da
|
Update to ISE 14.7
|
2017-09-10 13:41:13 +02:00 |
|
Florian Reitz
|
2a06e1ba5d
|
Support for second partition, card detect and write protect added
|
2017-09-09 20:34:24 +02:00 |
|
Florian Reitz
|
b845ad2cc9
|
Merge remote-tracking branch 'origin/master'
|
2017-09-05 20:03:46 +02:00 |
|
freitz85
|
8b8e22c796
|
misc datasheets added
|
2017-09-05 18:09:19 +02:00 |
|
freitz85
|
7425ad32fc
|
formatting
|
2017-09-03 14:51:09 +02:00 |
|
freitz85
|
63313fd7fa
|
inited flag is removed when card is ejected
|
2017-08-31 01:07:34 +02:00 |
|
Florian Reitz
|
30f6b89f2b
|
inited flag in fpga
|
2017-08-27 15:02:58 +02:00 |
|
freitz85
|
19632c05dc
|
inited signal added to cpld
|
2017-08-27 12:21:26 +02:00 |
|
Florian Reitz
|
f3751b90fb
|
7MHz clock used, read/write improved
reverted to Merlin-8
|
2017-08-27 00:37:54 +02:00 |