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793 Commits

Author SHA1 Message Date
Thomas Harte
e12e8fc616 Incorporates ASR tests, and fixes ASR (xxx).w. 
... which was re-injecting the wrong bit to preserve sign.
 2019-06-25 18:44:31 -04:00
Thomas Harte
1fbbf32cd2 Adds ASL tests, and corrects ASL (xxx).w. 
Overflow is wrong on other ASLs though, I think.
 2019-06-25 18:09:01 -04:00
Thomas Harte
31edb15369 Reduces 68000 startup costs a little further. 2019-06-25 17:41:13 -04:00
Thomas Harte
e830d23533 Incorporates TRAPV tests. 2019-06-24 21:21:35 -04:00
Thomas Harte
9a666fb8cc Imports NEG tests and fixes NEG.l Dn timing. 2019-06-24 19:43:30 -04:00
Thomas Harte
0e208ed432 Fixes cycle counting in the test machine. 2019-06-24 17:55:09 -04:00
Thomas Harte
c8b769de8a Completes import of LSL tests and fixes various LSL issues. 
Including LSL (xxx).w actually being LSR, and the carry flag generally being questionable.
 2019-06-24 17:45:38 -04:00
Thomas Harte
c447655047 Resolves assumption that shifts greater than the bit count of the relevant int are well-defined in C. 2019-06-24 16:51:43 -04:00
Thomas Harte
3ec9a1d869 Incorporates JMP tests, fixes JSR (xxx).l timing. 2019-06-24 15:36:33 -04:00
Thomas Harte
faef917cbd Improves resizeable microcycle test. 2019-06-24 10:55:22 -04:00
Thomas Harte
d27ba90c07 Attempts to introduce more rigour to variable-length instruction handling. 2019-06-24 10:43:28 -04:00
Thomas Harte
db4ca746e3 Introduces BSET tests, fixes BSET timing. 2019-06-23 22:53:37 -04:00
Thomas Harte
d50fbfb506 Imports EXG and PEA tests, and fixes EXG timing. 2019-06-23 22:21:25 -04:00
Thomas Harte
86fdc75feb Incorporates RTR test, adding a ProcessorState helper. 2019-06-23 18:37:32 -04:00
Thomas Harte
b63231523a Completes import of ROL tests. 2019-06-23 17:33:12 -04:00
Thomas Harte
70e296674d Starts import of ROL tests. 
Including time tests, this time.
 2019-06-22 22:42:57 -04:00
Thomas Harte
8c8493bc9d Ensures proper loading of the SP at reset. 2019-06-21 18:20:26 -04:00
Thomas Harte
ccfe1b13cb Imports DIVS, MULS and MOVE from SR tests. 
Not all passing.
 2019-06-21 16:03:11 -04:00
Thomas Harte
0c1c10bc66 Introduces a test that proves that DIVS' attempt to set proper timing isn't working. 2019-06-20 19:29:02 -04:00
Thomas Harte
fafd1801fe Introduces first DIVS test, and associated fixes. 2019-06-20 19:02:03 -04:00
Thomas Harte
79d8d27b4c Reintroduces use of locations_by_bus_step_ to decrease 68000 construction time. 2019-06-20 15:10:11 -04:00
Thomas Harte
440f52c943 Incorporates TRAP test. 2019-06-19 21:18:30 -04:00
Thomas Harte
91ced056d2 Adds tests for ADD. No failures. 2019-06-19 18:56:21 -04:00
Thomas Harte
8dace34e63 Imports third-party tests for ABCD, and thereby fixes ABCD. 2019-06-19 18:13:06 -04:00
Thomas Harte
8182b0363f Adds enum to help with status decoding. 2019-06-19 17:01:49 -04:00
Thomas Harte
c5b036fedf Ensures aborted decodes don't overwrite prior correct ones. 2019-06-19 17:00:44 -04:00
Thomas Harte
e26ddd0ed5 Corrects address fetches for CMPI.l #, (xxx).w. 2019-06-19 13:52:56 -04:00
Thomas Harte
ca83431e54 Fixed: Scc is a byte operation. 
It was, until now, post-incrementing and pre-decrementing registers other than A7 incorrectly.
 2019-06-19 13:15:12 -04:00
Thomas Harte
00c32e4b59 Further miscellaneous changes to debug logging. All temporary. 2019-06-18 10:34:31 -04:00
Thomas Harte
877b46d2c1 Advances IWM/drive emulation very close to the point of 'Welcome to Macintosh'. 2019-06-15 16:08:54 -04:00
Thomas Harte
bde975a3b9 Possibly mights the tiniest bit of headway with 'the IWM'. 
I'm now pretty sure that my 3.5" drive, which for now is implemented in the IWM (yuck) is just responding to queries incorrectly.
 2019-06-13 22:38:09 -04:00
Thomas Harte
f6f9024631 Corrects Macintosh aspect ratio (and framing). 2019-06-13 18:41:38 -04:00
Thomas Harte
59a94943aa Resolves final set of build warnings. 2019-06-13 10:55:29 -04:00
Thomas Harte
bf4889f238 Reduces warnings to 6. 2019-06-13 10:43:00 -04:00
Thomas Harte
7cc5afd798 Eliminates another couple of implicit type conversion warnings. 2019-06-13 10:30:26 -04:00
Thomas Harte
11ab021672 Further reduces implicit conversion warnings, to 17. 2019-06-13 10:27:49 -04:00
Thomas Harte
feafd4bdae Eliminates further type conversion warnings. 2019-06-13 10:20:17 -04:00
Thomas Harte
d6150645c0 By hook or by crook, mouse input now works. 2019-06-12 22:19:25 -04:00
Thomas Harte
ec5701459c Makes various temporary logging changes. 2019-06-11 19:54:07 -04:00
Thomas Harte
697e094a4e Sketches out the absolute basics of an SCC interface. 2019-06-08 18:47:11 -04:00
Thomas Harte
e9d0676e75 Fiddles further with the tachometer. 2019-06-06 21:36:19 -04:00
Thomas Harte
7591906777 Numerous IWM fixes: the machine now seems to be trying to measure the tachometer. 2019-06-06 18:32:11 -04:00
Thomas Harte
058fe3e986 Fixes some other low-hanging warning fruit. 2019-06-04 16:47:10 -04:00
Thomas Harte
51ee83a427 Resolves a further 11 conversion errors. 2019-06-04 16:34:45 -04:00
Thomas Harte
5b21da7874 Reduces number of warnings to 70. 2019-06-04 16:27:09 -04:00
Thomas Harte
bd7f00bd9c Resolves a further handful of implicit type conversion warnings. 2019-06-04 15:43:44 -04:00
Thomas Harte
4d4ddded6d Fixes register-relative JMP and JSR. 2019-06-03 15:29:50 -04:00
Thomas Harte
881feb1bd3 Adds preliminary parsing of the Disk Copy 4.2 format. 2019-06-02 13:39:25 -04:00
Thomas Harte
035f07877c Reduces conversions to vector. 2019-05-30 12:08:35 -04:00
Thomas Harte
b3d2b4cd37 Fixes the interrupt return address. 2019-05-29 20:27:46 -04:00
Thomas Harte
c86fe9ada9 Ensures replace_write_values works in release builds. 2019-05-29 19:00:53 -04:00
Thomas Harte
ecf93b7822 Eliminates some type conversion warnings. 2019-05-29 14:56:50 -04:00
Thomas Harte
541b75ee6e Further fixes PEA, and OR/AND/EOR Dn, (An). 2019-05-29 14:37:15 -04:00
Thomas Harte
77b08febdb Corrects PEA and adds an additional debugging aid. 2019-05-29 12:47:17 -04:00
Thomas Harte
fcda376f33 Removes three further type conversion warnings. 2019-05-28 21:56:49 -04:00
Thomas Harte
0848fc7e03 Ensures the Mac uses auto vectored interrupts. 2019-05-28 16:24:41 -04:00
Thomas Harte
3bb8d6717f Ensures A7 is correct at end of an UNLINK. 2019-05-28 16:02:42 -04:00
Thomas Harte
5e2496d59c Simplifies and corrects MOVE logic. 2019-05-28 15:17:03 -04:00
Thomas Harte
c52da9d802 Adds some logging preparatory to a MOVE change. 2019-05-28 15:05:42 -04:00
Thomas Harte
0b999ce0e4 Attempts to fix register-relative JSRs. 2019-05-09 06:43:07 -04:00
Thomas Harte
b04bd7069d Corrects Scc and DBcc (xxx).l and (xxx).w. 2019-05-09 06:28:55 -04:00
Thomas Harte
249b0fbb32 Corrects PC on stack after an illegal instruction. 
Also fixed LOG_TRACE functionality.
 2019-05-08 22:36:25 -04:00
Thomas Harte
d8ed8b66f3 Improves carry/extend for ROXL and ROXR. 2019-05-06 21:14:16 -04:00
Thomas Harte
e6ed50383c Corrects PEA and MOVE.l (An)[+], (xxx).L; also adds an extra test that caught the latter. 2019-05-05 22:47:54 -04:00
Thomas Harte
417a3e1540 Adds missing call to flush. 2019-05-03 23:31:12 -04:00
Thomas Harte
fa8c804d47 Makes explicit a few implicit type conversions. 
There's plenty more down this well, alas.
 2019-05-03 23:26:03 -04:00
Thomas Harte
2c9a1f7b16 Restores vector. 2019-05-03 14:50:07 -04:00
Thomas Harte
0ea4c1ac80 Evicts #includes from my namespace. 2019-05-03 14:48:39 -04:00
Thomas Harte
a873ec97eb Also previously missing: vector.h. 2019-05-03 14:43:31 -04:00
Thomas Harte
cc8a65780e Adds further missing includes. 2019-05-03 14:42:36 -04:00
Thomas Harte
c117deb43b Introduces a couple of missing #includes. 2019-05-03 14:37:05 -04:00
Thomas Harte
a0eb20ff1f Tweaks divide-by-zero timing. 2019-05-03 14:29:36 -04:00
Thomas Harte
34fe9981e4 Added necessary mea culpas. 2019-05-03 14:25:25 -04:00
Thomas Harte
291e91375f Takes a shot at the synchronous bus. 2019-05-03 14:20:59 -04:00
Thomas Harte
857f74b320 Fixed: the accepted interrupt level now appears on the bus. 2019-05-02 15:47:12 -04:00
Thomas Harte
1d9608efc7 Alters the order of interrupt bus activity, to bring it into line with a real 68000. 2019-05-02 15:25:43 -04:00
Thomas Harte
93616a4903 Completes test of a vectored interrupt. 
Correcting issues uncovered.
 2019-05-02 00:00:09 -04:00
Thomas Harte
bb07206c55 Corrects internet response to work as currently implemented. 
Also makes corrections to the bus error and address error exceptions.
 2019-05-01 21:59:06 -04:00
Thomas Harte
2e5c0811e7 Makes some effort at getting into interrupt processing. 2019-05-01 15:26:36 -04:00
Thomas Harte
f6ac407e4d Takes further steps towards supporting interrupts. 
Specifically:
* introduces the necessary bus signalling; and
* adds corresponding functional steps.

Still to figure out: getting into and out of an interrupt cycle.
 2019-05-01 15:19:24 -04:00
Thomas Harte
078c3135df The 5/3 split of microcycles appears not accurately to model when lines are tested. 
Therefore I've reverted to a more normative 4:4 form.
 2019-04-30 22:09:13 -04:00
Thomas Harte
92568c90c8 Adds support for HALT as an input, and puts some effort into how to calculate E. 2019-04-30 22:07:48 -04:00
Thomas Harte
f1879c5fbc Corrects interrupt level test within STOP. 2019-04-30 19:32:35 -04:00
Thomas Harte
31bb770fdd Implement STOPpages, waits for DTack, and bus and address error exceptions. 2019-04-30 19:24:22 -04:00
Thomas Harte
e430f2658f Adds a test and by that means fixes divide-by-zero exception return addresses. 2019-04-29 23:09:50 -04:00
Thomas Harte
3060175ff5 Eliminates constructions of std::tuple for performance reasons. 
Specifically: reduces 68000 construction time from 10+ seconds to more like 2.8.
 2019-04-29 22:43:15 -04:00
Thomas Harte
eb4233e2fd Joins some commonalities, shaving about 150 lines of code. 2019-04-29 22:37:23 -04:00
Thomas Harte
6b4c656849 Reverses order of instruction instantiation, reducing total bus step heft by about 11%. 
... since that means inserting more complicated instructions before simpler ones in general, making subset finds more likely.
 2019-04-29 22:20:18 -04:00
Thomas Harte
1b8fada6aa Restores accidentally-cropped functionality. 2019-04-29 22:10:00 -04:00
Thomas Harte
977f9ee831 Takes a run at divide-by-zero exceptions and starts looking towards ways to improve startup time. 2019-04-29 22:08:16 -04:00
Thomas Harte
16fb3b49a5 It leads to a TODO, but implemented decoding and initial setup of STOPpages. 2019-04-29 19:30:00 -04:00
Thomas Harte
3da1b3bf9b Introduces storage for various bus inputs. 2019-04-29 19:22:05 -04:00
Thomas Harte
bc00856c05 Removed TODO; it appears this is just the standard stack frame. 2019-04-29 19:09:20 -04:00
Thomas Harte
52e3dece81 Improves exposition. 2019-04-29 19:07:14 -04:00
Thomas Harte
2c1d8fa18a Adds a check for instruction privilege violation, albeit that I think I need different bus steps. 2019-04-29 19:06:10 -04:00
Thomas Harte
3e34ae67f6 Implements support for the trace flag. 2019-04-29 19:02:59 -04:00
Thomas Harte
ceebecec8d Corrects zero and negative flags for EXT.w. 2019-04-29 17:54:33 -04:00
Thomas Harte
05d1eda422 Fixes crossed-over decoding of EORI and ORI. 2019-04-29 17:45:52 -04:00
Thomas Harte
31f318ad43 Fixes MOVE.bw #, (xxx).w. 2019-04-29 17:41:46 -04:00
Thomas Harte
270f46e147 Normalises CMPl. 2019-04-29 17:27:56 -04:00
Thomas Harte
8564945713 Corrects vector nomination for unrecognised opcodes. 2019-04-29 17:10:33 -04:00
Thomas Harte
7bd7f3fb73 Sign-extends (xxx).w addresses. 2019-04-29 16:55:43 -04:00
Thomas Harte
c466b6f9e7 Factors out the [unit testing] stuff of being a trace-checking 68000 bus handler. 2019-04-29 16:11:01 -04:00
Thomas Harte
d9071ee9f1 Starts sketching out the asynchronous bus. 2019-04-29 13:45:53 -04:00
Thomas Harte
97e118abfa Corrects accidental exclusion of MOVE.bw (xxx).w, [(xxx).w/(xxx).l]. 2019-04-28 23:25:46 -04:00
Thomas Harte
412f091d76 Implements a missing form of BTST. 2019-04-28 23:20:50 -04:00
Thomas Harte
ca1f669e64 Implements MOVEP. 
371 is now the alleged number of missing opcodes. But I'd dare imagine it's more like three or four.
 2019-04-28 22:52:54 -04:00
Thomas Harte
0298b1b3b7 Implements LINK and UNLINK. 
Also starts excluding opcodes that I can't determine the mapping of from the list of those tested against.

Due to those two things together, the latter incomplete: 627 opcodes outstanding. But only STOP and MOVEP remain on my list of things to implement prior to exceptions.
 2019-04-28 17:12:31 -04:00
Thomas Harte
4b1324de77 Takes a run at TRAPV. 
... to leave 1466 as the unimplemented count.
 2019-04-28 15:52:58 -04:00
Thomas Harte
8e8dce9bec Attempts an implementation of CHK. 
1467 is now the official count of things to implement, though I'm starting to get suspicious.
 2019-04-28 15:47:21 -04:00
Thomas Harte
f4350522bf Implements NBCD. 
Now outstanding: 1891.
 2019-04-27 21:29:50 -04:00
Thomas Harte
e2abb66a11 Adds missing addressing modes for ADDA and SUBA. 
... reducing missing opcodes to 1941.
 2019-04-27 17:22:26 -04:00
Thomas Harte
ab5fcab9bf Attempts an implementation of ADDX and SUBX. 
Leaving 2005 non-[A/F]-line instructions.
 2019-04-27 16:57:47 -04:00
Thomas Harte
e75b386f7d Attempts DIVU and DIVS. 
Reportedly leaving 10965 operations now unimplemented.
 2019-04-26 22:22:35 -04:00
Thomas Harte
796203859f Implements PEA. 
This decreases the unimplemented count by 28 from 11841 to 11813.
 2019-04-26 13:49:59 -04:00
Thomas Harte
40b2fe7339 Merge branch 'master' into 68000 2019-04-26 00:02:35 -04:00
Thomas Harte
a3b6d2d16e Corrects test and resolves all instances of opcodes that are valid but shouldn't be. 
The converse case will require implementation of the remaining instructions.
 2019-04-25 22:54:58 -04:00
Thomas Harte
3983f8303f Introduces failing test of 68000 opcode coverage. 2019-04-25 22:06:05 -04:00
Thomas Harte
dab9bb6575 Implements EXT. 2019-04-25 18:22:19 -04:00
Thomas Harte
c132bda01c Implements MOVE from SR. 2019-04-25 14:39:32 -04:00
Thomas Harte
4e25bcfcdc Corrects decoding of AND/OR x, Dn. 2019-04-25 14:19:13 -04:00
Thomas Harte
ea463549c7 Corrects overflow flag for LSL and LSR. 2019-04-25 13:59:10 -04:00
Thomas Harte
723acb31b3 Corrects various flag issues with ADD, SUB and NEG. 2019-04-25 13:53:23 -04:00
Thomas Harte
5725db9234 Corrects calculated-address TAS. 2019-04-25 12:42:05 -04:00
Thomas Harte
8557e563bc Takes a run at TAS, clarifying bus cycles. 2019-04-25 12:19:40 -04:00
Thomas Harte
d2491633ce Ensures MOVEM to M .w correctly updates A7. 2019-04-24 23:21:15 -04:00
Thomas Harte
002796e5f5 Takes a run at BSET and BCHG. 2019-04-24 23:01:32 -04:00
Thomas Harte
fa0accf251 Attempts to correct flags for ASL, ASR, LSL, LSR. 2019-04-24 21:04:47 -04:00
Thomas Harte
dcb8176d90 Corrects potential failure properly to set stack pointer state. 2019-04-24 17:58:27 -04:00
Thomas Harte
be32b1a198 Fixes JSR (An) return address [again]. 2019-04-24 17:50:38 -04:00
Thomas Harte
582e4acc11 Implements ANDI/ORI/EOR to SR/CCR. 2019-04-24 17:38:59 -04:00
Thomas Harte
10f75acf71 Causes EXG to function. 2019-04-24 16:32:16 -04:00
Thomas Harte
b9933f512f Fixed: the word/long-word bit works the other way around. 2019-04-24 16:30:15 -04:00
Thomas Harte
75a7f7ab22 Inserts missing program fetch for CMPI.bw #, (d8/16...). 2019-04-24 14:45:24 -04:00
Thomas Harte
e214584c76 SWAP should clear overflow and carry. 2019-04-24 13:19:56 -04:00
Thomas Harte
0bb6b498ce Simplifies and fixes post-inc MOVE behaviour. 2019-04-24 13:14:25 -04:00
Thomas Harte
958d44a20d Causes SWAP actually to perform. 2019-04-24 13:06:12 -04:00
Thomas Harte
bb9424d944 Corrects byte increment/decrement actions for A7. 2019-04-24 13:01:08 -04:00
Thomas Harte
11bf706aa2 Attempts to fix LT and LTE conditions. 2019-04-24 10:07:17 -04:00
Thomas Harte
033b8e6b36 ADD/SUBQ #, An shouldn't set flags. 
Also, temporarily at least, adds a new means for observing CPU behaviour.
 2019-04-24 09:59:54 -04:00
Thomas Harte
7c3ea7b2ea Resolves additional byte accesses being signalled as word. 2019-04-23 21:23:20 -04:00
Thomas Harte
a08043ae88 Ensures that MOVE.b #, (xxx).l writes only a byte. 
Also rearranges some of the temporary logging functionality.
 2019-04-23 19:01:58 -04:00
Thomas Harte
7c132a3ed5 Ensures 16-bit values of Xn for (d8, An, Xn) are sign extended. 2019-04-22 22:13:02 -04:00
Thomas Harte
20e774be1e Corrects return address of JSR (An). 2019-04-22 21:11:49 -04:00
Thomas Harte
6d6046757d Fixes predecrementing MOVEM to leave the proper address in the relevant register. 2019-04-22 15:41:09 -04:00
Thomas Harte
55073b0a52 Corrects a bunch of MOVEs to (d8/16, PC/An, [Xn]). 2019-04-21 22:55:23 -04:00
Thomas Harte
44eb4e51ed Ensures DBcc properly signals program fetches. 2019-04-21 22:54:20 -04:00
Thomas Harte
3cb042a49d Corrects the carry and extend flags for various long-word operations. 2019-04-21 22:08:18 -04:00
Thomas Harte
b78ea7d24c Further simplifies CMPA. 2019-04-20 21:23:36 -04:00
Thomas Harte
c66728dce2 Corrects decoding of CMPA. 2019-04-20 21:21:33 -04:00
Thomas Harte
0be9a0cb88 Corrects Scc (and other conditionals) for complex addressing modes. 2019-04-20 18:35:19 -04:00
Thomas Harte
a90f12dab7 Corrects return address for TRAP. 2019-04-20 15:49:32 -04:00
Thomas Harte
ef33b004f9 Corrects word access order of MOVEM.l. 2019-04-20 15:13:12 -04:00
Thomas Harte
2cac4b0d74 Corrects EA usage for ADDA and SUBA. 2019-04-19 23:02:41 -04:00
Thomas Harte
a49f516265 Corrects direction of MOVE [to/from] USP. 2019-04-19 22:41:06 -04:00
Raphaël Zumer
71ac26944d Correct typos in Z80.hpp 2019-04-19 17:44:52 -04:00
Thomas Harte
2d97fc1f59 Beefs up documentation and developer support. 2019-04-19 13:29:35 -04:00
Thomas Harte
9ef7743205 Attempts to unify type decoding a little further. 2019-04-19 13:29:20 -04:00
Thomas Harte
ee7ae11e90 Implements EXG and SWAP. 2019-04-19 11:27:43 -04:00
Thomas Harte
f67d7f1db5 Adds the final (!) set of missing MOVEs. 2019-04-19 11:11:38 -04:00
Thomas Harte
99981751a2 Adds the official NOP. 
Which is a freebie.
 2019-04-18 23:46:01 -04:00
Thomas Harte
ffdf02c5df Adds MOVE XXX.lw, -(An) 2019-04-18 23:40:54 -04:00
Thomas Harte
27c7d00a05 Commutes final missing MOVEs to TODOs. 2019-04-18 23:35:32 -04:00
Thomas Harte
64c4137e5b Begins a cleanup procedure on MOVE. 2019-04-18 23:25:19 -04:00
Thomas Harte
8c26d0c6e6 Makes an attempt at RTE and RTR. 2019-04-18 20:50:58 -04:00
Thomas Harte
81dcfd9f85 Implements AND, OR and EOR. 
As well as introducing a little more nuance to the double-decoding test.
 2019-04-18 16:34:48 -04:00
Thomas Harte
9334557fbf Added important TODO. 2019-04-17 23:12:32 -04:00
Thomas Harte
b09de8efce Attempts to fill in the rest of MOVE x, -(An). 2019-04-17 23:05:16 -04:00
Thomas Harte
5a50eb56dd Marginally increases coverage of MOVE x, -(An). 2019-04-17 22:30:07 -04:00
Thomas Harte
e49b257e94 Takes a run at TRAP. 2019-04-17 22:21:56 -04:00
Thomas Harte
b8a0f4e831 Implements MOVE to/from USP. 2019-04-17 16:58:59 -04:00
Thomas Harte
29f8dcfb40 Fixes a bunch of (d16, An)-type MOVEs and implements MOVE (XXX).wl, (d16,An)/etc. 2019-04-17 16:13:35 -04:00
Thomas Harte
0c05983617 Shortens impact of MULU on the instruction stream to correct parsing. 
I need to look into this.
 2019-04-17 15:15:48 -04:00
Thomas Harte
0bd653708c Corrects MOVE.bw Dn, (An)[+]. 2019-04-17 14:31:20 -04:00
Thomas Harte
41d800cb63 Fixes ADD/SUB Dn,x to use the proper destination value. 2019-04-17 10:23:47 -04:00
Thomas Harte
cadc0bd509 Mental delusion lifted: JSR doesn't look enough like BSR. 2019-04-17 10:02:14 -04:00
Thomas Harte
b64da2710a Corrects a few MOVE #s. 2019-04-17 10:00:14 -04:00
Thomas Harte
82b08d0e3a Corrects addressing behaviour of nRd[+-]. 2019-04-17 08:53:34 -04:00
Thomas Harte
8f77d1831b Implements MULU and MULS. 2019-04-16 22:16:43 -04:00
Thomas Harte
be722143e1 Completes addressing modes for ADDI/etc/etc. 2019-04-16 21:34:16 -04:00
Thomas Harte
d8d974e2d7 Consolidates JSR and BSR preparation. 2019-04-16 21:29:37 -04:00
Thomas Harte
9b7ca6f271 Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. 
Also corrects the BSR return address.
 2019-04-16 19:50:10 -04:00
Thomas Harte
8ce018dbab Adds the necessary runtime support for AND, EOR and OR. 2019-04-16 15:17:40 -04:00
Thomas Harte
180062c58c Finishes fleshing out [ADD/SUB]Q. 2019-04-16 14:28:31 -04:00
Thomas Harte
37656f14d8 Adds basic addressing modes for [ADD/SUB]Q. 2019-04-16 11:19:45 -04:00
Thomas Harte
dec5535e54 Implements (arguably: fixes) BSR. 2019-04-15 23:20:36 -04:00
Thomas Harte
1f0e3b157a Corrects a couple of JSR and JMP addressing modes. 2019-04-15 22:37:11 -04:00
Thomas Harte
d802e83f49 Fills in further MOVEs. 2019-04-15 22:25:22 -04:00
Thomas Harte
ebcae25762 Adjusts JSR behaviour and further extends MOVE. 2019-04-15 22:02:52 -04:00
Thomas Harte
5330267d16 Implements BCLR. 2019-04-15 18:11:02 -04:00
Thomas Harte
892476973b Attempts RO{X}[L/R]. 2019-04-15 17:31:58 -04:00
Thomas Harte
84f4a25bc9 Completes TST. 2019-04-15 16:28:20 -04:00
Thomas Harte
1460a88bb3 Takes a run at JSR and RTS. 2019-04-15 15:14:38 -04:00
Thomas Harte
d25ab35d58 Finally gets setw usage correct. 2019-04-15 12:41:56 -04:00
Thomas Harte
a223cd90a1 Adds predecrement TSTs, increases QL running time, reduces logging. 2019-04-15 12:36:08 -04:00
Thomas Harte
aef92ba29c Corrects immediate shift count. 2019-04-15 12:25:45 -04:00
Thomas Harte
328d297490 Implements the first few addressing modes for TST. 2019-04-15 10:03:52 -04:00
Thomas Harte
3d240f3f18 Corrects decoding of DBcc. 2019-04-15 09:49:23 -04:00
Thomas Harte
45f35236a7 Corrects decoding of ADDA and SUBA. 2019-04-15 09:44:06 -04:00
Thomas Harte
fba210f7ce Corrects MOVE.l Dn, (An)[+]. 2019-04-15 09:30:49 -04:00