6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-11 08:07:22 +00:00
Code Issues Projects Releases Wiki Activity
95,182 Commits 39 Branches 0 Tags 277 MiB
0323d4b169
Commit Graph

138 Commits

Author SHA1 Message Date
Akira Hatanaka
cbaf6d0cc3 [mips] Rename HIRegs and LORegs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188341 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-14 00:47:08 +00:00
Akira Hatanaka
491d04969d [mips] Rename accumulator register classes and FP register operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188020 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-08 21:54:26 +00:00
Akira Hatanaka
94a88c49b0 [mips] Delete register class HWRegs64. 
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188016 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-08 21:37:32 +00:00
Akira Hatanaka
1858786285 [mips] Rename register classes CPURegs and CPU64Regs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187832 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-06 23:08:38 +00:00
Akira Hatanaka
6b034bb3ae [mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of 
instructions defined in MipsInstrInfo.td as codegen-only instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187828 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-06 23:01:10 +00:00
Akira Hatanaka
014096e4d5 [mips] Delete unnecessary InstAliases. Also, clear some of the InstAlias' 
EmitAlias flag and have MipsInstPrinter::printAlias print the aliases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187824 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-06 22:35:29 +00:00
Akira Hatanaka
a1fe9ef62e [mips] Replace usages of register classes with register operands. Also, remove 
unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print
jalr InstAliases in MipsInstPrinter::printAlias.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187821 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-06 22:20:40 +00:00
Akira Hatanaka
ddbdeefa28 [mips] Make load/store accumulator pseudo instructions codeGenOnly. Also, 
remove lines that are setting DecoderNamespace for pseudo atomic instructions.

No intended functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187632 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-01 23:14:16 +00:00
Akira Hatanaka
782638aa0d [mips] Rename instruction DANDi to ANDi64. 
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187469 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-31 00:57:41 +00:00
Akira Hatanaka
52b7321a48 [mips] Define instruction itineraries IIArith and IILogic. 
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187468 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-31 00:55:34 +00:00
Akira Hatanaka
0b92642767 [mips] Use ADDu instead of OR to copy general purpose registers. Also, delete 
the InstAlias pattern which maps "move" to OR to resolve ambiguity in
MatchTable.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186855 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-22 18:52:22 +00:00
Akira Hatanaka
ae24f7d3c6 [mips] Add instruction itinerary classes for mult, seb and slt instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186222 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-12 22:43:20 +00:00
Akira Hatanaka
a66aacf6d7 [mips] Add new InstrItinClasses for move from/to coprocessor instructions and 
floating point loads and stores.

No changes in functionality.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185399 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-02 00:00:02 +00:00
Akira Hatanaka
1d4d32398d [mips] Add instruction selection patterns for blez and bgez. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182396 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-21 17:13:47 +00:00
Akira Hatanaka
f894199a14 [mips] Trap on integer division by zero. 
By default, a teq instruction is inserted after integer divide. No divide-by-zero
checks are performed if option "-mnocheck-zero-division" is used.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182306 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-20 18:07:43 +00:00
Jack Carter
3209baefd4 Mips assembler: Add branch macro definitions 
This patch adds bnez and beqz instructions which represent alias definitions for bne and beq instructions as follows:
bnez $rs,$imm => bne $rs,$zero,$imm
beqz $rs,$imm => beq $rs,$zero,$imm

The corresponding test cases are added.

Patch by Vladimir Medic


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182040 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-16 19:40:19 +00:00
Akira Hatanaka
c147c1b994 [mips] Fix handling of instructions which copy to/from accumulator registers. 
Expand copy instructions between two accumulator registers before callee-saved
scan is done. Handle copies between integer GPR and hi/lo registers in
MipsSEInstrInfo::copyPhysReg. Delete pseudo-copy instructions that are not
needed.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180827 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-30 23:22:09 +00:00
Akira Hatanaka
f5926fd844 [mips] Fix definitions of multiply, multiply-add/sub and divide instructions. 
The new instructions have explicit register output operands and use table-gen
patterns instead of C++ code to do instruction selection.

Mips16's instructions are unaffected by this change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178403 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-30 01:36:35 +00:00
Akira Hatanaka
2cd7d3f9ce [mips] Define pseudo instructions for spilling and copying accumulator 
registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178390 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-30 00:54:52 +00:00
Jack Carter
af7da5cb99 [Mips Assembler] Add support for OR macro with imediate opperand 
Mips assembler supports macros that allows the OR instruction 
to have an immediate parameter. This patch adds an instruction 
alias that converts this macro into a Mips ORI instruction. 

Contributer: Vladimir Medic


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178316 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-28 23:45:13 +00:00
Jack Carter
94fcfaf3a9 [Mips Assembler] Add alias definitions for jal 
Mips assembler allows following to be used as aliased instructions:
jal $rs for jalr $rs
jal $rd,$rd for jalr $rd,$rs

This patch provides alias definitions in td files and test cases to show the usage.

Contributer: Vladimir Medic


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178304 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-28 23:02:21 +00:00
Akira Hatanaka
1ae08e0077 [mips] Print move instructions. 
"move $4, $5" is printed instead of "or $4, $5, $zero".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176455 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-04 22:25:01 +00:00
Akira Hatanaka
0c66403efd [mips] Add definition of JALR instruction which has two register operands. Change the 
original JALR instruction with one register operand to be a pseudo-instruction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174657 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-07 19:48:00 +00:00
Jack Carter
37ef65b9c1 This patch that sets the EmitAlias flag in td files 
and enables the instruction printer to print aliased 
instructions. 

Due to usage of RegisterOperands a change in common 
code (utils/TableGen/AsmWriterEmitter.cpp) is required 
to get the correct register value if it is a RegisterOperand.

Contributer: Vladimir Medic
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174358 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-05 08:32:10 +00:00
Jack Carter
e72fac60e3 This is a resubmittal. For some reason it broke the bots yesterday 
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.

Removal of redundant code and formatting fixes.

Contributers: Jack Carter/Vladimir Medic
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172842 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-18 20:15:06 +00:00
Jack Carter
ec3199f675 This patch tackles the problem of parsing Mips 
register names in the standalone assembler llvm-mc.

Registers such as $A1 can represent either a 32 or
64 bit register based on the instruction using it.
In addition, based on the abi, $T0 can represent different
32 bit registers.


The problem is resolved by the Mips specific AsmParser 
td definitions changing to work together. Many cases of
RegisterClass parameters are now RegisterOperand.


Contributer: Vladimir Medic


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172284 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-12 01:03:14 +00:00
Craig Topper
71ab7a79a7 Remove # from the beginning and end of def names. The # is a paste operator and should only be used with something to paste on either side. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171697 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-07 05:45:56 +00:00
Akira Hatanaka
1ebe5fce8e [mips] 80 columns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171515 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-04 19:38:05 +00:00
Akira Hatanaka
f53b78f5bf [mips] Reorder template parameters. Remove class shift_rotate_imm32 and 
shift_rotate_imm64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171513 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-04 19:25:46 +00:00
Akira Hatanaka
5f560bb2eb [mips] Refactor instructions which move data from or to coprocessors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171510 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-04 19:13:49 +00:00
Akira Hatanaka
dbf51ee459 [mips] Refactor subword-swap, EXT/INS, load-effective-address and read-hardware 
instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170956 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-21 23:21:32 +00:00
Akira Hatanaka
e8bc10b902 [mips] Refactor SYNC and multiply/divide instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170955 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-21 23:17:36 +00:00
Akira Hatanaka
6a8309e62a [mips] Refactor jump, jump register, jump-and-link and nop instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170952 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-21 23:03:50 +00:00
Akira Hatanaka
0a57dc1d14 [mips] Refactor load/store left/right and load-link and store-conditional 
instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170950 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-21 23:01:24 +00:00
Akira Hatanaka
16164657d8 [mips] Refactor load/store instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170948 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-21 22:58:55 +00:00
Akira Hatanaka
8e719fac46 [mips] Refactor LUI instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170944 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-21 22:46:07 +00:00
Akira Hatanaka
35242e27c5 [mips] Refactor count leading zero or one instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170942 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-21 22:43:58 +00:00
Akira Hatanaka
8aaed99a99 [mips] Refactor sign-extension-in-register instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170940 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-21 22:41:52 +00:00
Akira Hatanaka
7de001b97e [mips] Refactor instructions which copy from and to HI/LO registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170939 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-21 22:39:17 +00:00
Akira Hatanaka
2a732ec272 [mips] Refactor logical NOR instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170937 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-21 22:35:47 +00:00
Akira Hatanaka
9bf571fe2c [mips] Refactor SLT (set on less than) instructions. Separate encoding 
information from the rest. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170664 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-20 04:27:52 +00:00
Akira Hatanaka
1e7739f614 [mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass 
parameter.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170661 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-20 04:20:09 +00:00
Akira Hatanaka
5c54025645 [mips] Refactor conditional branch instructions with one register operand. 
Separate encoding information from the rest.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170659 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-20 04:13:23 +00:00
Akira Hatanaka
c488901355 [mips] Refactor conditional branch instructions with two register operands. 
Separate encoding information from the rest.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170657 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-20 04:10:13 +00:00
Akira Hatanaka
2427773f2f [mips] Change the order of template parameters. Move the default parameters to 
the end. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170651 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-20 03:52:08 +00:00
Akira Hatanaka
cdc0c59d1e [mips] Refactor shift instructions with register operands. Separate encoding 
information from the rest.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170650 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-20 03:48:24 +00:00
Akira Hatanaka
0dad34a9bf [mips] Refactor shift immediate instructions. Separate encoding information 
from the rest.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170649 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-20 03:44:41 +00:00
Akira Hatanaka
ab48c503e2 [mips] Refactor arithmetic and logic instructions with immediate operands. 
Separate encoding information from the rest.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170648 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-20 03:40:03 +00:00
Akira Hatanaka
23a3da0113 [mips] Refactor arithmetic and logic instructions. Separate encoding 
information from the rest.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170647 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-20 03:34:05 +00:00
Akira Hatanaka
c9e30ea42c [mips] Delete ArithOverflowR and ArithOverflow and use ArithLogicR and 
ArithLogicI as the instruction base classes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170642 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-20 03:00:16 +00:00