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Author SHA1 Message Date
Craig Topper 052d754ccb [X86] Add another test case for the bug fixed in r229642. With the bug a vpsrldq was emitted instead of pslldq. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229643 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-18 07:45:43 +00:00
Craig Topper f781855732 [X86] Remove AVX512 pslldq/psrldq shift intrinsics. They aren't implemented yet and when they are they should be done with shuffles like SSE2 and AVX2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229641 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-18 06:24:49 +00:00
Craig Topper ed42dcef75 [X86] Remove AVX2 and SSE2 pslldq and psrldq intrinsics. We can represent them in IR with vector shuffles now. All their uses have been removed from clang in favor of shuffles. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229640 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-18 06:24:44 +00:00
Craig Topper 4031c08c87 [X86] Remove the multiply by 8 that goes into the shift constant for X86ISD::VSHLDQ and X86ISD::VSRLDQ. This simplifies the pattern matching in isel and allows these nodes to become the patterns embedded in the instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229431 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-16 20:52:07 +00:00
Craig Topper e124dc723b [X86] Remove x86.avx2.psll.dq.bs and x86.avx2.psrl.dq.bs intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229430 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-16 20:51:59 +00:00
Craig Topper 74b9ad3485 [X86] Add support for lowering shuffles to 256-bit PALIGNR instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229359 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-16 06:29:06 +00:00
Craig Topper abdf58f7f9 [X86] Remove some hard tab characters from tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229358 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-16 06:29:02 +00:00
Craig Topper 60db969913 [X86] Remove gcc builtins for AVX2 psll_dq and psrl_dq intrinsics. Clang no longer needs them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229347 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-16 00:42:36 +00:00
Craig Topper 9bb36ed8d8 [X86] Add assembly parser support for mnemonic aliases for AVX-512 vpcmp instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229287 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-15 07:13:48 +00:00
Craig Topper 09ea4e976b [X86] Add assembler predicates for the rest of the AVX512 feature flags. This makes the assembly matching consistent across all AVX512 instructions. Without this we were allowing some AVX512 instructions to be parsed always, but not the foundation instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229280 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-15 04:54:55 +00:00
Craig Topper e2f7231e45 [X86] Add the remaining 11 possible exact ModRM formats. This makes their encodings linear which can then be used to simplify some other code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229279 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-15 04:16:44 +00:00
Craig Topper 32f60795f5 [X86] Improve parsing support AVX/SSE floating point compare instruction mnemonic aliases. They'll now print with the alias the parser received instead of converting to the explicit immediate form. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229266 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-14 21:54:03 +00:00
Craig Topper f3455f13a2 [X86] Add support for parsing and printing the mnemonic aliases for the XOP VPCOM instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229078 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-13 07:42:25 +00:00
Craig Topper 0d3c686ffd [X86] Fix XOP vpcom intrinsic autoupgrade to map 'true' and 'false' to the correct immediates. Seems they were swapped. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229077 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-13 07:42:15 +00:00
Craig Topper c5222f156f Fix a typo in a comment. NFC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229071 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-13 06:07:29 +00:00
Craig Topper d4f1c60bf5 Fix probable typo in test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229070 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-13 06:07:27 +00:00
Craig Topper db9343fb40 [X86] Remove int_x86_sse2_psll_dq_bs and int_x86_sse2_psrl_dq_bs intrinsics. The builtins aren't used by clang. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229069 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-13 06:07:24 +00:00
Craig Topper 972211d539 [X86] Remove references to builtin names that have been removed from clang. Hope to remove the intrinsics themselves soon. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229068 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-13 06:07:14 +00:00
Craig Topper 77b557430c [X86] Preserve mem refs on newly created 'Store' node instead of 'Load' node when handling store unfolding. 
Bug spotted by Steve King.

I have no idea how to test this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228672 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-10 06:29:28 +00:00
Craig Topper 5fc4b96e62 [X86] Remove unnecessary alignment checks from the load folding tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228671 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-10 05:10:50 +00:00
Craig Topper cc5e6d56fc [X86] Remove 256-bit and 512-bit memop pattern fragments. They are no longer used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228563 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-09 04:04:53 +00:00
Craig Topper bd477dfbbf [X86] Remove 'memop' uses from AVX512. Use 'load' instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228562 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-09 04:04:50 +00:00
Craig Topper 3824fd3a25 [X86] Remove the remaining uses of memop from AVX and AVX2 instruction patterns. AVX and AVX2 can handle unaligned loads being folded so we can just use 'load' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228551 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-08 22:38:25 +00:00
Craig Topper 3e7edda4aa [X86] Add register use/def for wrmsr and rdmsr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228515 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-07 23:36:51 +00:00
Craig Topper e15d286e83 [X86] Add GETSEC instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228514 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-07 23:36:36 +00:00
Craig Topper 0d18b852e0 [X86] Add assembler and disassembler test cases for clflushopt, clwb, pcommit, xsaves, xrstors, xsavec 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228385 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-06 06:19:28 +00:00
Craig Topper aaf239845a [X86] Remove a ton of duplicate test cases for the assembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228383 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-06 05:50:50 +00:00
Craig Topper 20d15157e4 [X86] Add xrstors/xsavec/xsaves/clflushopt/clwb/pcommit instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228283 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-05 08:51:06 +00:00
Craig Topper b8fa51de42 [X86] Remove two feature flags that covered sets of instructions that have no patterns or intrinsics. Since we don't check feature flags in the assembler parser for any instruction sets, these flags don't provide any value. This frees up 2 of the fully utilized feature flags. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228282 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-05 08:51:02 +00:00
Craig Topper 97494e9718 [X86] Make fxsave64/fxrstor64/xsave64/xsrstor64/xsaveopt64 parseable in AT&T syntax. Also make them the default output. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227963 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-03 11:03:57 +00:00
Craig Topper c7f2036c2b [X86] Add Requires[In64BitMode] around MOVSX64rr32/MOVSX64rm32. This makes it more strictly mutexed with the ARPL instruction 32-bit mode. Helps with some disassembler changes I'm experimenting with. Should be NFC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227962 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-03 11:03:43 +00:00
Craig Topper 270f7a2669 [X86] Add a few target specific nodes to 'getTargetNodeName' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227720 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-01 10:00:37 +00:00
Craig Topper aef361807e [X86] Teach disassembler to handle illegal immediates on AVX512 integer compare instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227302 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-28 10:09:56 +00:00
Craig Topper f3a2214da8 [X86] Merge printSSECC and printAVXCC. They only differed by an assertion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227301 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-28 10:09:52 +00:00
Craig Topper 1656cc8ddb [X86] Change comparision immediate type to i8 in test cases for AVX512 floating point comparisons. The type was already changed in the definitions and was being auto upgraded to the new type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227064 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-25 23:26:12 +00:00
Craig Topper fd176682b9 [X86] Use i8 immediate for comparison type on AVX512 packed integer instructions. This matches floating point equivalents. Includes autoupgrade support to convert old code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227063 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-25 23:26:02 +00:00
Craig Topper ff763041d2 [X86] Give scalar VRNDSCALE instructions priority in AVX512 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227039 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-25 08:49:22 +00:00
Craig Topper e3792c042d Simplify a multiclass. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227038 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-25 08:49:19 +00:00
Craig Topper e237954ed8 Remove tab characters. NFC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227036 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-25 08:45:32 +00:00
Craig Topper 896c1e9b70 [X86] Replace i32i8imm on SSE/AVX instructions with i32u8imm which will make the assembler bounds check them. It will also make them print as unsigned. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227032 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-25 02:21:16 +00:00
Craig Topper 046047ccc3 [X86] Use u8imm in several places that used i32i8imm that don't require an i32 type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227031 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-25 02:21:13 +00:00
Craig Topper a92d03bb7a Remove tab characters. NFC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227030 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-25 02:21:11 +00:00
Craig Topper d05a6aa4e6 [x86] Change u8imm operands to always print as unsigned. This makes shuffle masks and the like make way more sense. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226902 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-23 08:00:59 +00:00
Craig Topper 70b58044ef Fix 80 column violation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226898 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-23 06:18:35 +00:00
Craig Topper c3942c9623 [X86] Add IntrNoMem to the AVX512 conflict intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226897 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-23 06:11:45 +00:00
Craig Topper deb2e51099 Revert r226798. Guess I missed the patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226802 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-22 09:01:20 +00:00
Craig Topper efad370a06 Use u8imm instead of i32i8imm on a couple instructions that have no patterns and thus no reason to use a larger operand size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226798 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-22 08:53:11 +00:00
Craig Topper 6660dcedd3 [X86] Remove some unused multiclasses from AVX512 instruction file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226797 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-22 08:53:08 +00:00
Craig Topper 74670deb21 [x86] Remove some unnecessary and slightly confusing typecasts from some patterns. I think it actually went i32->iPtr->i32 in some of these cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226647 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-21 08:43:57 +00:00
Craig Topper 51da87a580 [X86] Convert all the i8imm used by AVX512 and MMX instructions to u8imm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226646 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-21 08:43:49 +00:00
Craig Topper 951d088ae7 [X86] Convert all the i8imm used by SSE and AVX instructions to u8imm. 
This makes the assembler check their size and removes a hack from the disassembler to avoid sign extending the immediate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226645 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-21 08:15:54 +00:00
Craig Topper f81b1f346a [x86] Add assembly parser bounds checking to the immediate value for cmpss/cmpsd/cmpps/cmppd. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226642 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-21 06:07:53 +00:00
Craig Topper d624796bc6 [x86] Add some mayLoad/hasSideEffects flags. Remove one that was already covered by a pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226562 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-20 12:15:30 +00:00
Craig Topper 6f91bd79f3 [x86] Change AVX512 intrinsics to take a 8-bit immediate for the comparision kind instead of a 32-bit immediate. This better aligns with the emitted instruction. It also matches SSE and AVX1 equivalents. Also add auto upgrade support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226430 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-19 06:07:27 +00:00
Craig Topper 06185e7f6b Hide some redundant AVX512 instructions from the asm parser, but force them to show up in the disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226155 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-15 09:37:15 +00:00
Craig Topper cb964a5c58 Fix test case I missed in r225432. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225434 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-08 07:57:27 +00:00
Craig Topper 367b67df3e [X86] Don't print 'dword ptr' or 'qword ptr' on the operand to some of the LEA variants in Intel syntax. The memory operand is inherently unsized. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225432 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-08 07:41:30 +00:00
Craig Topper 76bdb26595 [X86] Merge a switch statement inside a default case of another switch statement on the same variable. There was no additional code in the default so this should be no functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225345 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-07 08:10:38 +00:00
Craig Topper ebddeaee40 [X86] Don't mark the shift by 1 instructions as isConvertibleToThreeAddress. There is no handling for them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225344 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-07 08:10:36 +00:00
Craig Topper decea4d6a6 [X86] Remove some unused TYPE enums from the disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225343 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-07 07:47:52 +00:00
Craig Topper f6145affbf [X86] Add OpSize32 to XBEGIN_4. Add XBEGIN_2 with OpSize16. 
Requires new AsmParserOperand types that detect 16-bit and 32/64-bit mode so that we choose the right instruction based on default sizing without predicates. This is necessary since predicates mess up the disassembler table building.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225256 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-06 08:59:30 +00:00
Craig Topper 88dc6cd5c9 [X86] Make isel select the 2-byte register form of INC/DEC even in non-64-bit mode. Convert to the 1-byte form in non-64-bit mode as part of MCInst lowering. 
Overall this seems simpler. It reduces duplication of patterns between both modes and it simplifies the memory folding/unfolding tables as they don't need to create fake instructions just to keep track of 64-bitness.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225252 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-06 07:35:50 +00:00
Craig Topper e16c86e524 [X86] Remove 16-bit and 32-bit offset jump instructions from the AsmParser. We always select the 8-bit size and let the assembler backend relax to the larger size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225243 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-06 04:23:57 +00:00
Craig Topper 1299ae2403 [X86] Make isel select the shorter form of jump instructions instead of the long form. 
The assembler backend will relax to the long form if necessary. This removes a swap from long form to short form in the MCInstLowering code. Selecting the long form used to be required by the old JIT.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225242 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-06 04:23:53 +00:00
Craig Topper 9bf73516cb Replace several 'assert(false' with 'llvm_unreachable' or fold a condition into the assert. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225160 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-05 10:15:49 +00:00
Craig Topper a5ba79effa [X86] Remove the predicates from the register forms of the 2-byte inc and dec instructions. Remove the 32-bit mode only versions that existed for the disassembler. Move the patterns out of the instructions so they can still be qualified with predicates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225157 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-05 08:19:12 +00:00
Craig Topper 34f96b9cc3 [X86] Simplify code a little by just summing flags instead of conditionally incrementing. NFC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225156 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-05 08:19:10 +00:00
Craig Topper a481b50d75 [X86] Remove unnecessary redeclaration of a variable with the same assignment as the beginning of the function. NFC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225155 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-05 08:19:07 +00:00
Craig Topper d571fdb20b [X86] Remove a strange fixme referring to a hack that doesn't seem to exist since the code is in a comment. Can't figure out what the body of the 'if' was supposed to be anyway. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225154 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-05 08:19:05 +00:00
Craig Topper 1d8d3b62ad [x86] Reduce text duplication for similar operand class declarations in tablegen instruction info. No functional change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225153 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-05 08:19:03 +00:00
Craig Topper 68f83ee530 [X86] Fix the immediate size to match the address size in the operand types for the move to/from absolute memory instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225152 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-05 08:18:59 +00:00
Craig Topper 3249372d83 [X86] Remove unused operand type from disassembler handling. NFC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225151 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-05 08:18:52 +00:00
Craig Topper 00d70e98f0 Minor cleanup to all the switches after MatchInstructionImpl in all the AsmParsers. 
Make sure they all have llvm_unreachable on the default path out of the switch. Remove unnecessary "default: break". Remove a 'return' after unreachable. Fix some indentation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225114 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-03 08:16:34 +00:00
Craig Topper 2717b066cc Fix some formatting in tablegen output. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225113 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-03 08:16:29 +00:00
Craig Topper 577a76839b Replace some 'unreachable' comments with llvm_unreachable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225112 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-03 08:16:14 +00:00
Craig Topper 01c99892ca [X86] Disassembler support for move to/from %rax with a 32-bit memory offset is REX.W and AdSize prefix are both present. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225099 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-03 00:00:20 +00:00
Craig Topper e3c96460b2 [X86] Use 32-bit sign extended immediate for 64-bit LOCK_ArithBinOp with sign extended immediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225098 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-03 00:00:14 +00:00
Craig Topper 8ae0fd2bb3 [X86] Bring some better consistency to the naming of the move to/from %al/ax/eax/rax with memory offset. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225078 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-02 07:36:23 +00:00
Craig Topper 71fc42dbf6 [X86] Make the instructions that use AdSize16/32/64 co-exist together without using mode predicates. 
This is necessary to allow the disassembler to be able to handle AdSize32 instructions in 64-bit mode when address size prefix is used.

Eventually we should probably also support 'addr32' and 'addr16' in the assembler to override the address size on some of these instructions. But for now we'll just use special operand types that will lookup the current mode size to select the right instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225075 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-02 07:02:25 +00:00
Craig Topper c602b726a8 [X86] Update disassembler tests for absolute move instructions to check the encodings. This provides testing for r225036. 64-bit mode is still broken. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225037 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-31 07:24:23 +00:00
Craig Topper 51f423ff30 [X86] Fix disassembly of absolute moves to work correctly in 16 and 32-bit modes with all 4 combinations of OpSize and AdSize prefixes being present or not. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225036 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-31 07:07:31 +00:00
Craig Topper e8ffd99e4e [x86] Simplify detection of jcxz/jecxz/jrcxz in disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225035 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-31 07:07:11 +00:00
Craig Topper f8207ac705 Testcases for r224939. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224976 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-30 02:35:56 +00:00
Craig Topper d52bd88fad [X86] Fix some cases where some 8-bit instructions were marked as being convertible to three address instructions, but aren't really. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224940 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-29 16:25:26 +00:00
Craig Topper 67044e9a6a [X86] Add the 0x82 instructions to the disassebmler. They are identical in functionality to the 0x80 opcode instructions, but are not valid in 64-bit mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224939 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-29 16:25:23 +00:00
Craig Topper 702d11e595 [x86] Refactor some tablegen instruction info classes slightly to prepare for another change. NFC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224938 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-29 16:25:22 +00:00
Craig Topper b96ee8810f [x86] Remove unused classes from tablegen instruction info. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224937 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-29 16:25:19 +00:00
Craig Topper 04c853b269 [x86] Prevent instruction selection of AVX512 cmp.ps/pd/ss/sd intrinsics with illegal immediates. Correctly this time. I did the wrong patterns the first time. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224891 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-27 20:08:45 +00:00
Craig Topper d840bf4ba9 [x86] Prevent instruction selection of AVX512 cmp.ps/pd/ss/sd intrinsics with illegal immediates. Forgot to do this when I did SSE/SSE2/AVX/AVX2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224887 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-27 18:51:06 +00:00
Craig Topper 3e9bf4c0d0 [x86] Assert on invalid immediates in the instruction printer for cmp.ps/pd/ss/sd instead of truncating the immediate. The assembly parser and instruction selection shouldn't generate invalid immediates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224886 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-27 18:11:00 +00:00
Craig Topper 6ba84e58da [x86] Prevent llvm.x86.cmp.ps/pd/ss/sd from being selected with bad immediates. The frontend now checks this when the builtin is used. This will allow the instruction printer to not have to deal with invalid immediates on these instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224885 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-27 18:10:56 +00:00
Craig Topper a996db696b [X86] Add the debug registers DR8-DR15 so we can assemble and disassemble references to them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224862 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-26 18:20:05 +00:00
Craig Topper 6eb3e3ce10 [X86] Don't fail disassembly if REX.R/REX.B is used on an MMX register. Similar fix to not fail to disassembler CR9-CR15 references. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224861 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-26 18:19:44 +00:00
Craig Topper 654a66dbd3 Teach disassembler to handle illegal immediates on (v)cmpps/pd/ss/sd instructions. Instead of rejecting we'll just generate the _alt forms that don't try to alter the mnemonic. While I'm here, merge some common code in the Instruction printers for the condition code replacement and fix the mask on SSE to be 3-bits instead of 4. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224846 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-26 06:36:28 +00:00
Craig Topper 50d894e4d3 Use MCPhysReg for table of register encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224845 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-26 06:36:23 +00:00
Craig Topper 3bc4397f1f [X86] Remove the single AdSize indicator and replace it with separate AdSize16/32/64 flags. 
This removes a hardcoded list of instructions in the CodeEmitter. Eventually I intend to remove the predicates on the affected instructions since in any given mode two of them are valid if we supported addr32/addr16 prefixes in the assembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224809 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-24 06:05:22 +00:00
Craig Topper b10afb51d6 [X86] Add hasSideEffects = 0 to CALLpcrel16. This matches what is inferred from patterns for the 32-bit version. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224692 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-21 20:05:06 +00:00
Craig Topper b8f8f2dbed [X86] Swap operand order in Intel syntax on a bunch of aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224687 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-20 23:05:59 +00:00
Craig Topper a9bae8c3da [X86] Swap operand order of imul aliases in Intel syntax. Also disable printing of the alias instead of the real instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224686 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-20 23:05:57 +00:00
Craig Topper 0c8f0f0403 [X86] Remove '*' from asm strings in far call/jump aliases for Intel syntax. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224685 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-20 23:05:55 +00:00