Evan Cheng
5981fc6788
Fix IIC_iEXTAr itinerary class of Cortex-A9.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114784 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-25 01:09:28 +00:00
Evan Cheng
27fdcd1c95
Remove a unused instruction itinerary class.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114782 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-25 01:06:02 +00:00
Evan Cheng
576a3968a2
Fix zero and sign extension instructions scheduling itineraries.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114780 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-25 00:49:35 +00:00
Evan Cheng
bd30ce4311
More pseudo instruction scheduling itinerary fixes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114768 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-24 22:41:41 +00:00
Evan Cheng
5be3922321
Fix scheduling itinerary for pseudo mov immediate instructions which expand into two real instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114766 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-24 22:03:46 +00:00
Jim Grosbach
433a5785cc
Add ARM explicit MCInst lowering for the Thumb eh.sjlj.setjmp sequence.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114758 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-24 20:47:58 +00:00
Evan Cheng
fff606d7b2
Enable code placement optimization pass for ARM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-24 19:07:23 +00:00
Dale Johannesen
c451051157
We can't return SSE/MMX vectors if SSE is disabled.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114745 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-24 19:05:48 +00:00
Evan Cheng
de0e11c8f3
Fix a potential null dereference bug.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114723 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-24 05:18:35 +00:00
Owen Anderson
f523e476c2
Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further
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reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114710 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 23:45:25 +00:00
Bob Wilson
2a6e616142
Set alignment operand for NEON VST instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114709 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 23:42:37 +00:00
Jim Grosbach
453900814e
ARM-mode eh.sjlj.setjmp pseudo MC-inst lowering expansion
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114707 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 23:33:56 +00:00
Jim Grosbach
b327e13740
#+4 --> #4 for consistency with other asm output
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114706 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 23:32:38 +00:00
Jim Grosbach
45d6c1777c
Fix formatting of output .s code
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114705 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 23:03:26 +00:00
Owen Anderson
71e416ac3a
Add isConditionalMove bits to X86 and ARM instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114703 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 22:57:01 +00:00
Bob Wilson
40ff01a030
Set alignment operand for NEON VLD instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114696 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 21:43:54 +00:00
Jim Grosbach
b2dda4bd34
never mind. I can't read, apparently
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114689 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 19:42:17 +00:00
Evan Cheng
676e258366
Fix r114632. Return if the only terminator is an unconditional branch after the redundant ones are deleted.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114688 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 19:42:03 +00:00
Jim Grosbach
24e6f2f802
Fix opcode value for the 'trap' instruction, keeping the type suffix on the
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constant. Hopefully the non-Darwin bots will like it...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114687 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 19:32:40 +00:00
Jim Grosbach
5c49b69609
explicit 'unsigned long' on constant value. Hopefully make bots happier.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114686 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 19:08:04 +00:00
Benjamin Kramer
c8ab9eb066
Unbreak build. Jim, please review.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114684 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 18:57:26 +00:00
Jim Grosbach
2e6ae13bf6
Clean up the 'trap' instruction printing a bit. Non-Darwin assemblers don't
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(yet) recognize the 'trap' mnemonic, so we use .short/.long to emit the
opcode directly. On Darwin, however, we do want the mnemonic for more
readable assembly code and better disassembly.
Adjust the .td file to use the 'trap' mnemonic and handle using the binutils
workaround in the assembly printer. Also tweak the formatting of the opcode
values to make them consistent between the MC printer and the old printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114679 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 18:05:37 +00:00
Jim Grosbach
16c9a64c28
nuke unused var
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114676 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 17:58:00 +00:00
Evan Cheng
108c872466
If there are multiple unconditional branches terminating a block, eliminate all
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but the first one. Those will never be executed. There was logic to do this
but it was faulty.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114632 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 06:54:40 +00:00
Jim Grosbach
637d89fe0e
Add support for ELF PLT references for ARM MC asm printing. Adding a
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new VariantKind to the MCSymbolExpr seems like overkill, but I'm not sure
there's a more straightforward way to get the printing difference captured.
(i.e., x86 uses @PLT, ARM uses (PLT)).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114613 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 23:27:36 +00:00
Jim Grosbach
b6ec8cae3c
Enable a few additional asserts in MC instruction lowering.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114601 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 23:01:28 +00:00
Cameron Esfahani
4af1eaee70
Fix PR8201: Update the code to call via X86::CALL64pcrel32 in the 64-bit case.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114597 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 22:35:21 +00:00
Bob Wilson
b68987e4bf
Change VDUPLANE DAG combiner to just return the result instead of calling
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CombineTo to avoid putting the result on the worklist. I don't think it makes
much difference for now, but it might help someday as we add more DAG
combine optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114595 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 22:27:30 +00:00
Bob Wilson
0b8ccb8252
Combine both VMOVDRR(VMOVRRD) and VMOVRRD(VMOVDRR), instead of just doing one
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of those. Refactor to share code for handling BUILD_VECTOR(VMOVRRD).
I don't have a testcase that exercises this, but it seems like an obvious
good thing to do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114589 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 22:09:21 +00:00
Jim Grosbach
f0633e48eb
add FIXME
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114578 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 20:55:15 +00:00
Eric Christopher
56a8b817b1
Temporarily work around new address lowering while I figure out what
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needs to happen for darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114577 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 20:42:08 +00:00
Jim Grosbach
bfbe187593
Remove a few commented out bits
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114576 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 20:32:34 +00:00
Jim Grosbach
00d01f1a42
Add PrintSpecial() handling for in ARM MC instruction printer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114563 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 18:37:14 +00:00
Jim Grosbach
a2244cb387
Add MC instruction printer support for ARM and Thumb1 jump tables.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114555 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 17:39:48 +00:00
Bob Wilson
eafca4e2b2
Attempt to fix llvm-gcc build. It was crashing when building gcov.o for an
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ARM cross-compiler on x86, because the MMO size did not match the type size.
This fixes the MMO size and also the size of the stack object to match the
type size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114554 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 17:35:14 +00:00
Jim Grosbach
205a5fa8e4
Add MC instruction printer support for TB[BH] style thumb2 jump tables.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114553 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 17:15:35 +00:00
Jim Grosbach
1b935a3d2e
Clean up comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114550 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 16:45:13 +00:00
Chris Lattner
2c5291b563
fix rdar://8456371 - Handle commutable instructions written backward.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114536 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 06:26:39 +00:00
Chris Lattner
1eb1b68e3a
Fix an inconsistency in the x86 backend that led it to reject "calll foo" on
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x86-32: 32-bit calls were named "call" not "calll". 64-bit calls were correctly
named "callq", so this only impacted x86-32.
This fixes rdar://8456370 - llvm-mc rejects 'calll'
This also exposes that mingw/64 is generating a 32-bit call instead of a 64-bit call,
I will file a bugzilla.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114534 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 05:49:14 +00:00
Chris Lattner
bc57c6db4a
fix rdar://8456412 - llvm-mc crash in encoder on "mov %rdx, %cr8"
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Teaching the code generator about CR8-15, how to rex them up, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114533 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 05:29:50 +00:00
Chris Lattner
c2b942acf6
add the missing aliases for fp stack cmovs, rdar://8456391
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114531 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 04:56:20 +00:00
Chris Lattner
f93b90c5df
reimplement elf TLS support in terms of addressing modes, eliminating SegmentBaseAddress.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114529 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 04:39:11 +00:00
Chris Lattner
33d60d5e56
Fix rdar://8456364 - llvm-mc rejects '%CS'
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114528 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 04:11:10 +00:00
Chris Lattner
0c289c140e
fix rdar://8456389 - llvm-mc mismatch with 'as' on 'fstp'
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-This line, and those below, will be ignored--
M test/MC/AsmParser/X86/x86_instructions.s
M lib/Target/X86/AsmParser/X86AsmParser.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114527 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 04:04:03 +00:00
Chris Lattner
61129252e4
fix rdar://8456361 - llvm-mc rejects 'rep movsd'
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114526 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 03:50:32 +00:00
Chris Lattner
492a43e6f6
convert the last 4 X86ISD nodes that should have memoperands to have them.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114523 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 01:28:21 +00:00
Chris Lattner
2156b79c49
give X86ISD::FNSTCW16m a memoperand, since it touches memory. It only
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can access the stack due to how it is generated though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114522 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 01:11:26 +00:00
Chris Lattner
0729093cd7
give FP_TO_INT16_IN_MEM and friends a memoperand. They are only
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used with stack slots, but hey, lets be safe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114521 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 01:05:16 +00:00
Chris Lattner
8864155a35
give VZEXT_LOAD a memory operand, it now works with segment registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114515 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 00:34:38 +00:00
Chris Lattner
0b79cfee15
revert r114386 now that address modes work correctly, we get a nice
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call through gs-relative memory now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114510 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 00:11:31 +00:00
Chris Lattner
93c4a5bef7
give LCMPXCHG_DAG[8] a memory operand, allowing it to work with addrspace 256/257
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114508 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 23:59:42 +00:00
Evan Cheng
691e64a54c
OptimizeCompareInstr should avoid iterating pass the beginning of the MBB when the 'and' instruction is after the comparison.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114506 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 23:49:07 +00:00
Jim Grosbach
882ef2b76a
Add start of support for MC instruction printer of ARM jump tables. Filling in
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the rest of it is next up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114500 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 23:28:16 +00:00
Owen Anderson
8614167572
Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that this makes
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irrelevant, but add a new test for the new, improved functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114494 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 22:51:46 +00:00
Chris Lattner
b86faa17a4
reimplement support for GS and FS relative address space matching
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by having X86DAGToDAGISel::SelectAddr get passed in the parent node
of the operand match (the load/store/atomic op) and having it get
the address space from that, instead of having special FS/GS addr
mode operations that require duplicating the entire instruction set
to support.
This makes FS and GS relative accesses *far* more predictable and
work much better. It also simplifies the X86 backend a bit, more
to come.
There is still a pending issue with nodes like ISD::PREFETCH and
X86ISD::FLD, which really should be MemSDNode's but aren't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114491 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 22:07:31 +00:00
Owen Anderson
bc146b0a4d
Reimplement r114460 in target-independent DAGCombine rather than target-dependent, by using
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the predicate to discover the number of sign bits. Enhance X86's target lowering to provide
a useful response to this query.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114473 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 20:42:50 +00:00
Chris Lattner
52a261b3c1
fix a long standing wart: all the ComplexPattern's were being
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passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel
like detangling). Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114471 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 20:31:19 +00:00
Chris Lattner
701cd62297
even though I'm about to rip it out, simplify the address mode stuff
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114468 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 19:41:58 +00:00
Chris Lattner
fc448ff89b
convert a couple more places to use the new getStore()
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114463 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 18:51:21 +00:00
Chris Lattner
6229d0acb8
update a bunch of code to use the MachinePointerInfo version of getStore.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114461 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 18:41:36 +00:00
Owen Anderson
c004eec71b
When adding the carry bit to another value on X86, exploit the fact that the carry-materialization
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(sbbl x, x) sets the registers to 0 or ~0. Combined with two's complement arithmetic, we can fold
the intermediate AND and the ADD into a single SUB.
This fixes <rdar://problem/8449754>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114460 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 18:41:19 +00:00
Bob Wilson
65ffec49f7
Define the TargetLowering::getTgtMemIntrinsic hook for ARM so that NEON load
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and store intrinsics are represented with MemIntrinsicSDNodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114454 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 17:56:22 +00:00
Chris Lattner
8026a9d3ee
eliminate some uses of the getStore overload.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114453 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 17:50:43 +00:00
Chris Lattner
da2d8e1032
eliminate an old SelectionDAG::getTruncStore method, propagating
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MachinePointerInfo around more.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114452 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 17:42:31 +00:00
Chris Lattner
3d6ccfba31
propagate MachinePointerInfo through various uses of the old
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SelectionDAG::getExtLoad overload, and eliminate it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114446 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 17:04:51 +00:00
Jim Grosbach
532baa5d53
Fix errant printing of [v]ldm instructions that aren't a pop
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114445 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 16:45:31 +00:00
Gabor Greif
8ff9bb189c
Fix buglet when the TST instruction directly uses the AND result.
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I am unable to write a test for this case, help is solicited, though...
What I did is to tickle the code in the debugger and verify that we do the right thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114430 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 13:30:57 +00:00
Gabor Greif
04ac81d5db
Move the search for the appropriate AND instruction
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into OptimizeCompareInstr.
This necessitates the passing of CmpValue around,
so widen the virtual functions to accomodate.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114428 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 12:01:15 +00:00
Chris Lattner
d1c24ed81c
convert the targets off the non-MachinePointerInfo of getLoad.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114410 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 06:44:06 +00:00
Chris Lattner
e8639036b1
it's more elegant to put the "getConstantPool" and
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"getFixedStack" on the MachinePointerInfo class. While
this isn't the problem I'm setting out to solve, it is the
right way to eliminate PseudoSourceValue, so lets go with it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114406 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 06:22:23 +00:00
Chris Lattner
51abfe490b
update the X86 backend to use the MachinePointerInfo version of one
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of the getLoad methods. This fixes at least one bug where an incorrect
svoffset is passed in (a potential combiner-aa miscompile).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114404 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 06:02:19 +00:00
Chris Lattner
e54b482d1c
Fix a bug where the x86 backend would lower memcpy/memset of segment relative operations
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into non-segment-relative copies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114402 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 05:43:34 +00:00
Chris Lattner
e72f2027e9
reimplement memcpy/memmove/memset lowering to use MachinePointerInfo
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instead of srcvalue/offset pairs. This corrects SV info for mem
operations whose size is > 32-bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114401 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 05:40:29 +00:00
Chris Lattner
59db5496f4
convert targets to the new MF.getMachineMemOperand interface.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114391 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 04:39:43 +00:00
Chris Lattner
08bad54baf
fix rdar://8453210, a crash handling a call through a GS relative load.
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For now, just disable folding the load into the call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114386 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 03:37:00 +00:00
Jim Grosbach
1dc335a79f
Simplify ARM callee-saved register handling by removing the distinction
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between the high and low registers for prologue/epilogue code. This was
a Darwin-only thing that wasn't providing a realistic benefit anymore.
Combining the save areas simplifies the compiler code and results in better
ARM/Thumb2 codegen.
For example, previously we would generate code like:
push {r4, r5, r6, r7, lr}
add r7, sp, #12
stmdb sp!, {r8, r10, r11}
With this change, we combine the register saves and generate:
push {r4, r5, r6, r7, r8, r10, r11, lr}
add r7, sp, #12
rdar://8445635
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114340 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-20 19:32:20 +00:00
Chris Lattner
313a94c3d0
idiom recognition should catch this.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114304 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-19 00:37:34 +00:00
Chris Lattner
702917d4e8
add a readme.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114303 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-19 00:34:58 +00:00
NAKAMURA Takumi
cd458be047
X86Subtarget.h: Fix Cygwin's TD.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114297 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 19:50:42 +00:00
Eric Christopher
50880d08ec
Add the exit instruction to the PTX target.
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Patch by Che-Liang Chiou <clchiou@gmail.com>!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114294 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 18:52:28 +00:00
Michael J. Spencer
895dda6fb5
Fix build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114292 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 17:54:37 +00:00
Eric Christopher
c109556a0a
Thumb opcodes for thumb calls.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114263 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 02:32:38 +00:00
Eric Christopher
6dab137b88
Add addrmode5 fp load support. Swap float/thumb operand adding to handle
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thumb with floating point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114256 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 01:59:37 +00:00
Eric Christopher
b74558ad3e
Floating point stores have a 3rd addressing mode type.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114254 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 01:23:38 +00:00
Jim Grosbach
988ce097b7
factor out a simple helper function to create a label for PC-relative
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instructions (PICADD, PICLDR, et.al.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 00:05:05 +00:00
Jim Grosbach
d30cfde935
PC-relative pseudo instructions are lowered and printed directly. Any encounter
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with one in the generic printing code is an error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114242 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 00:04:53 +00:00
Benjamin Kramer
92aa1f7123
Fix vmov.f64 disassembly on targets where sizeof(long) != 8.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114240 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 23:48:07 +00:00
Jim Grosbach
fbd1873041
Add MC-inst handling for tPICADD
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114237 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 23:41:53 +00:00
Bob Wilson
75f0288b7d
Add target-specific DAG combiner for BUILD_VECTOR and VMOVRRD. An i64
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value should be in GPRs when it's going to be used as a scalar, and we use
VMOVRRD to make that happen, but if the value is converted back to a vector
we need to fold to a simple bit_convert. Radar 8407927.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114233 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 22:59:05 +00:00
Jim Grosbach
e6be85e9ff
Teach the (non-MC) instruction printer to use the cannonical names for push/pop,
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and shift instructions on ARM. Update the tests to match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114230 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 22:36:38 +00:00
Eric Christopher
a5b1e68107
Rework arm fast isel branch and compare code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114226 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 22:28:18 +00:00
Jim Grosbach
74d7e6c64e
Hook up verbose asm comment printing for SOImm operands in MC printer
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114215 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 21:33:25 +00:00
Jim Grosbach
196b48b708
trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114212 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 21:25:10 +00:00
Dan Gohman
d8c0a51362
Avoid emitting a PIC base register if no PIC addresses are needed.
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This fixes rdar://8396318.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114201 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 20:24:24 +00:00
Jim Grosbach
568eeedea7
Add skeleton infrastructure for the ARMMCCodeEmitter class. Patch by Jason Kim!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114195 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 18:46:17 +00:00
Jim Grosbach
c686e33d12
handle the upper16/lower16 target operand flags on symbol references for MC
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instruction lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114191 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 18:25:25 +00:00
Chris Lattner
40cc3f8783
fix rdar://8444631 - encoder crash on 'enter'
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What a weird instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114190 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 18:02:29 +00:00
Jim Grosbach
a28abbe245
expand PICLDR MC lowering to handle other PICLDR and PICSTR versions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114183 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 16:25:52 +00:00
NAKAMURA Takumi
cdd7fb7853
AlphaSchedule.td: 7bit-ize.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114173 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 09:56:43 +00:00
Chris Lattner
35aa94b229
fix rdar://8438816 - unrecognized 'fildq' instruction
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114116 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 20:46:38 +00:00
Jim Grosbach
b74ca9d631
MC-ization of the PICLDR pseudo. Next up, adding the other variants
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(PICLDRB, et. al.) and PICSTR*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114098 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 17:43:25 +00:00
Jim Grosbach
1d51c41a45
Make sure to promote single precision floats to double before extracting them
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from the APFloat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114096 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 17:37:30 +00:00
Kalle Raiskila
1cd1b0b283
Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction.
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This cleans up after the mess r108567 left in the CellSPU backend.
ORCvt-instruction were used to reinterpret registers, and the ORs were then
removed by isMoveInstr(). This patch now removes 350 instrucions of format:
or $3, $3, $3
(from the 52 testcases in CodeGen/CellSPU). One case of a nonexistant or is
checked for.
Some moves of the form 'ori $., $., 0' and 'ai $., $., 0' still remain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114074 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 12:29:33 +00:00
Bob Wilson
de0ae8f83d
Remove support for "dregpair" operand modifier, now that it is no longer being
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used for anything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114067 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 04:55:00 +00:00
Bob Wilson
823611bfba
When expanding ARM pseudo registers, copy the existing predicate operands
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instead of using default predicates on the expanded instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114066 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 04:25:37 +00:00
Jim Grosbach
a8e47b3319
store MC FP immediates as a double instead of as an APFloat, thus avoiding an
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unnecessary dtor for MCOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 03:45:21 +00:00
Bob Wilson
ea606bb76b
Add missing break.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114048 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 00:31:32 +00:00
Bob Wilson
9d4ebc0eb8
Change VLDMQ and VSTMQ to be pseudo instructions. They are expanded after
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register allocation to VLDMD and VSTMD respectively. This avoids using the
dregpair operand modifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114047 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 00:31:02 +00:00
Jim Grosbach
765c4d9477
Add support for the 'lane' modifier on vdup operands
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114030 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 22:13:23 +00:00
Jakob Stoklund Olesen
06f264e504
Remember VLDMQ.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114026 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 21:40:11 +00:00
Jakob Stoklund Olesen
31bbc51ac9
Add missing break.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114025 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 21:40:09 +00:00
Jim Grosbach
60396975be
Teach the MC disassembler to handle vmov.f32 and vmov.f64 immediate to register
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moves. Previously, the immediate was printed as the encoded integer value,
which is incorrect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114021 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 21:04:54 +00:00
Jim Grosbach
a4c3c8f28d
move getRegisterNumbering() to out of ARMBaseRegisterInfo into the helper
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functions in ARMBaseInfo.h so it can be used in the MC library as well.
For anything bigger than this, we may want a means to have a small support
library for shared helper functions like this. Cross that bridge when we
come to it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114016 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 20:26:25 +00:00
Jim Grosbach
f1c3eb37ae
simplify getRegisterNumbering(). Remove the unused isSPVFP argument and
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merge the common cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114013 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 19:52:17 +00:00
Jim Grosbach
7e2c04fd05
Refactor uses of getRegisterNumbering() to not need the isSPVFP argument. Check
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if the register is a member of the SPR register class directly instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114012 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 19:44:57 +00:00
Jim Grosbach
d8be410d4b
Reduce dependencies in the ARM MC instruction printer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114009 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 19:27:50 +00:00
Jim Grosbach
8b7fa198c3
Fix spelling typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114008 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 19:26:50 +00:00
Jim Grosbach
754578b565
Factor out basic enums and hleper functions from ARM.h for cleaner sharing
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between the compiler back end and the MC libraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114007 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 19:26:06 +00:00
Jim Grosbach
26edbcb8d5
Add support for floating point immediates to MC instruction printing. ARM
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VFP instructions use it for loading some constants, so implement that
handling.
Not thrilled with adding a member to MCOperand, but not sure there's much of
a better option that's not pretty fragile (like putting a double in the
union instead and just assuming that's good enough). Suggestions welcome...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113996 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 18:47:08 +00:00
Jakob Stoklund Olesen
d64816a8d0
Recognize VST1q64Pseudo and VSTMQ as stack slot stores.
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Recognize VLD1q64Pseudo as a stack slot load.
Reject these if they are loading or storing a subregister. The API (and
VirtRegRewriter) doesn't know how to deal with that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113985 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 17:27:09 +00:00
Bob Wilson
3a951829fe
Reapply Gabor's 113839, 113840, and 113876 with a fix for a problem
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encountered while building llvm-gcc for arm. This is probably the same issue
that the ppc buildbot hit. llvm::prior works on a MachineBasicBlock::iterator,
not a plain MachineInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113983 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 17:12:08 +00:00
Gabor Greif
7602993f2d
the darwin9-powerpc buildbot keeps consistently crashing,
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backing out following to get it back to green,
so I can investigate in peace:
svn merge -c -113840 llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll
svn merge -c -113876 -c -113839 llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113980 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 16:53:07 +00:00
Jakob Stoklund Olesen
34327856d9
Move ARM is{LoadFrom,StoreTo}StackSlot closer to their siblings so they won't be
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forgotten in the future.
Coalesce identical cases in switch.
No functional changes intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113979 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 16:36:26 +00:00
Bob Wilson
064312de86
Spelling fix.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113978 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 16:28:21 +00:00
Chris Lattner
d0bcc9a015
lcall and ljmp always default to lcalll and ljmpl. This finally
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wraps up r8418316
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113949 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 05:30:20 +00:00
Chris Lattner
cbb442640f
apparently jmpl $1,$2 is an alias for ljmpl, similiarly
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for call. Add this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113948 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 05:25:21 +00:00
Chris Lattner
250b948f21
Disambiguate lcall/ljmp to the 32-bit version. This happens
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even in 64-bit mode apparently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113945 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 05:14:54 +00:00
Chris Lattner
6c1b3b1e32
fix the encoding of sldt GR16 to have the 0x66 prefix, and
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add sldt GR32, which isn't documented in the intel manual
but which gas accepts. Part of rdar://8418316
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113938 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 04:45:10 +00:00
Chris Lattner
cfad564043
implement aliases for shld/shrd, part of rdar://8418316
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113937 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 04:37:18 +00:00
Chris Lattner
e9e16a36d9
fix rdar://8431880 - rcl/rcr with no shift amount not recognized
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113936 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 04:33:27 +00:00
Chris Lattner
84f362d891
add various broken forms of fnstsw. I didn't add the %rax
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version because it adds a prefix and makes even less sense
than the other broken forms. This wraps up rdar://8431422
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113932 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 04:15:16 +00:00
Chris Lattner
8f777a205e
add some aliases for f[u]comi, part of rdar://8431422
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113930 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 04:08:38 +00:00
Chris Lattner
2d592d10a5
add a bunch of aliases for fp operations with no operand,
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rdar://8431422
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113929 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 04:04:33 +00:00
Chris Lattner
f884012c93
Diagnose invalid instructions like "incl" with "too few operands for instruction"
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instead of crashing. This fixes:
rdar://8431815 - crash when invalid operand is one that isn't present
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113921 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 03:50:11 +00:00
Bob Wilson
168f382dc6
Use VLD1/VST1 pseudo instructions for loadRegFromStackSlot and
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storeRegToStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113918 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 01:48:05 +00:00
Jim Grosbach
22854b777e
trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113915 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 01:01:45 +00:00
Dale Johannesen
29fc6f35a5
Add x86MMX a few more places.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113914 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 00:52:23 +00:00
Jim Grosbach
05ae0c6026
Reapply r113875 with additional cleanups.
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"The register specified for a dregpair is the corresponding Q register, so to
get the pair, we need to look up the sub-regs based on the qreg. Create a
lookup function since we don't have access to TargetRegisterInfo here to
be able to use getSubReg(ARM::dsub_[01])."
Additionaly, fix the NEON VLD1* and VST1* instruction patterns not to use
the dregpair modifier for the 2xdreg versions. Explicitly specifying the two
registers as operands is more correct and more consistent with the other
instruction patterns. This enables further cleanup of special case code in the
disassembler as a nice side-effect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14 23:54:06 +00:00
Chris Lattner
ef63c9a9b6
add a terrible hack to allow out with dx is parens, a gas bug.
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This fixes PR8114
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113894 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14 23:34:29 +00:00
Eric Christopher
bb3e5dad66
Emit libcalls for SDIV, this requires some call infrastructure
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that needs to be shared a bit more widely around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113886 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14 23:03:37 +00:00
Jim Grosbach
684193928c
revert 113875 momentarilly. Need to fix the MC disassembler to handle the
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change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113878 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14 22:38:39 +00:00
Jim Grosbach
15d78984d5
trailing whitespace cleanup
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113877 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14 22:27:15 +00:00
Gabor Greif
308f64a7c8
an attempt to salvage the darwin9-powerpc buildbot, which could be miscompiling this line
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113876 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14 22:25:16 +00:00
Jim Grosbach
fe125557dd
The register specified for a dregpair is the corresponding Q register, so to
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get the pair, we need to look up the sub-regs based on the qreg. Create a
lookup function since we don't have access to TargetRegisterInfo here to
be able to use getSubReg(ARM::dsub_[01]).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113875 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14 22:20:33 +00:00
Gabor Greif
f7d10f5c12
set isCompare for another three Thumb1 instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113867 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14 22:00:50 +00:00
Jim Grosbach
5b46d62c44
Add predicate and 's' bit operands to PICADD instruction lowering.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113860 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14 21:28:17 +00:00
Bob Wilson
fe3ac088ee
Avoid warnings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113857 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14 21:12:05 +00:00
Jim Grosbach
f3f09527e6
fix comment typo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113856 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14 21:05:34 +00:00
Bob Wilson
9d84fb3c91
Make NEON ld/st pseudo instruction classes take the instruction itinerary as
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an argument, so that we can distinguish instructions with the same register
classes but different numbers of registers (e.g., vld3 and vld4). Fix some
of the non-pseudo NEON ld/st instruction itineraries to reflect the number
of registers loaded or stored, not just the opcode name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14 20:59:49 +00:00
Gabor Greif
007248b478
set comparable for a bunch of Thumb instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113849 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14 20:47:43 +00:00
Jim Grosbach
1685caffed
Don't ignore the CPSR implicit def when lowering a MachineInstruction to an MCInst.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113847 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14 20:41:27 +00:00
Jim Grosbach
9854f197f3
Clarify comment
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113846 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14 20:35:46 +00:00
Gabor Greif
de90bfd14a
Eliminate a 'tst' that immediately follows an 'and'
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by morphing the 'and' to its recording form 'andS'.
This is basically a test commit into this area, to
see whether the bots like me. Several generalizations
can be applied and various avenues of code simplification
are open. I'll introduce those as I go.
I am aware of stylistic input from Bill Wendling, about
where put the analysis complexity, but I am positive
that we can move things around easily and will find a
satisfactory solution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113839 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14 09:23:22 +00:00
Eric Christopher
23da0b23a3
Fix QOpcode assignment to Opc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113837 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14 08:31:25 +00:00
Michael J. Spencer
08047f6169
CBackend: Fix MSVC build.
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This may produce warnings on MSVS, but it's better than failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113834 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14 04:27:38 +00:00
Michael J. Spencer
bcf4b830b9
CBackend: Cleanup whitespace before I do this next commit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113833 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14 04:27:26 +00:00
Michael J. Spencer
3a210e2d30
Revert "CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally."
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This reverts commit r113632
Conflicts:
cmake/modules/AddLLVM.cmake
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113819 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-13 23:59:48 +00:00
Bob Wilson
bd916c54b7
Convert some VTBL and VTBX instructions to use pseudo instructions prior to
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register allocation. Remove the NEONPreAllocPass, which is no longer needed.
Yeah!!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113818 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-13 23:55:10 +00:00
Bob Wilson
8466fa1842
Switch all the NEON vld-lane and vst-lane instructions over to the new
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pseudo-instruction approach. Change ARMExpandPseudoInsts to use a table
to record all the NEON load/store information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113812 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-13 23:01:35 +00:00
Dale Johannesen
e5db19ebd5
Fix typos. 128-bit PSHUFB takes 128-bit memory op.
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v8i16 is not an MMX type; put it where it belongs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113785 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-13 21:15:43 +00:00
Jim Grosbach
fc16a8950c
trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113768 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-13 18:25:42 +00:00
John Thompson
eac6e1d0c7
Added skeleton for inline asm multiple alternative constraint support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113766 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-13 18:15:37 +00:00
Michael J. Spencer
86e05af491
CMake: Fix MSVS build. Although I don't know why this didn't break other build systems...
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This problem is unrelated to the recent dependency tracking change. It
seems like noone noticed the problem because I don't think anyone compiles
any target other than X86 on windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113727 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-12 18:32:57 +00:00
Michael J. Spencer
d4b8333d62
CMake: Fix mingw32 build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113712 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-12 03:47:31 +00:00
Chris Lattner
0989d29d09
add a missed cmov alias, part of rdar://8416805
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113693 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-11 17:08:22 +00:00
Chris Lattner
697d37a436
add support for all the setCC aliases. Part of rdar://8416805
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113692 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-11 17:06:05 +00:00
Chris Lattner
dfa3c9d982
add support for pushfd/popfd which are aliases for pushfl/popfl.
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This fixes rdar://8408129 - pushfd and popfd get invalid instruction mnemonic errors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113690 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-11 16:39:16 +00:00
Chris Lattner
ee211d0ed6
implement rdar://8407928 - support for in/out with a missing "a" register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113689 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-11 16:32:12 +00:00
Chris Lattner
cbf8a98c7c
fix the asmparser so that the target is responsible for skipping to
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the end of the line on a parser error, allowing skipping to happen
for syntactic errors but not for semantic errors. Before we would
miss emitting a diagnostic about the second line, because we skipped
it due to the semantic error on the first line:
foo %eax
bar %al
This fixes rdar://8414033 - llvm-mc ignores lines after an invalid instruction mnemonic errors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113688 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-11 16:18:25 +00:00
Bill Wendling
a65568676d
Rename ConvertToSetZeroFlag to something more general.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113670 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-11 00:13:50 +00:00
Bill Wendling
3665661a57
No need to recompute the SrcReg and CmpValue.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113666 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 23:46:12 +00:00
Bill Wendling
92ad57f066
Move some of the decision logic for converting an instruction into one that sets
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the 'zero' bit down into the back-end. There are other cases where this logic
isn't sufficient, so they should be handled separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113665 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 23:34:19 +00:00
Eric Christopher
d10cd7b314
Start sketching out ARM fast-isel calls.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113662 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 23:18:12 +00:00
Eric Christopher
44bff903e2
For consistency.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113659 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 23:10:30 +00:00
Eric Christopher
09b2171d7e
Newline at end of file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113654 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 22:46:03 +00:00
Eric Christopher
6f2ccefdc0
Split out some of the calling convention bits so that they can be
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used for fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113652 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 22:42:06 +00:00
Bill Wendling
220e240bdf
Modify the comparison optimizations in the peephole optimizer to update the
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iterator when an optimization took place. This allows us to do more insane
things with the code than just remove an instruction or two.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113640 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 21:55:43 +00:00
Jim Grosbach
51f5b67395
Add a missing case to duplicateCPV() for LSDA constants. Add a FIXME. rdar://8302157
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113637 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 21:38:22 +00:00
Michael J. Spencer
4e9c939312
CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113632 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 21:14:25 +00:00
Dale Johannesen
bb811a2445
Add X86 MMX type to bitcode and Type.
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(The Ada bindings probably need it too, but all the
obvious places to change say "do not edit this file".)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113618 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 20:55:01 +00:00
Bill Wendling
1ec2ee6526
Reapply r113585. The msvc machine is mercurial.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113610 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 20:20:28 +00:00
Bill Wendling
b28f579200
r113585 was causing clang-i686-xp-msvc9 to fail in mysterious ways that I can't
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understand (the log file was no help).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113605 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 19:20:47 +00:00
Bob Wilson
979927ab26
Calculate the number of VLDM/VSTM registers by subtracting the number of
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fixed operands from the total number of operands (including the variadic ones).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113597 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 18:25:35 +00:00
Bill Wendling
81781ed939
Mark the sse_load_f32 and sse_load_f64 load patterns as having memoperands so
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that the memoperands are properly set after DAG building and general mucking
about.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113585 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 10:34:22 +00:00
Bill Wendling
c8714bb144
Reword since this may not be a bug but intended behavior.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113584 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 10:31:11 +00:00
Bob Wilson
efe7d9a12f
Fix merging base-updates for VLDM/VSTM: Before I switched these instructions
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to use AddrMode4, there was a count of the registers stored in one of the
operands. I changed that to just count the operands but forgot to adjust for
the size of D registers. This was noticed by Evan as a performance problem
but it is a potential correctness bug as well, since it is possible that this
could merge a base update with a non-matching immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113576 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 05:15:04 +00:00
Evan Cheng
3ef1c8759a
Teach if-converter to be more careful with predicating instructions that would
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take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 01:29:16 +00:00
Eric Christopher
920a2089d9
Fix build error.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113566 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 00:35:09 +00:00
Eric Christopher
db12b2ba9c
Update comments, reorganize some code, rename variables to be
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more clear. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113565 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 00:34:35 +00:00
Eric Christopher
238bb16251
64-bit fp loads can come straight out of the constant pool, not as
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bad as I'd thought.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113561 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 23:50:00 +00:00
Eric Christopher
9ee4ce2f91
SIToFP and FPToSI conversions work only on fp-reg to fp-reg. Move
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some data around and implement a couple of move routines to do this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113546 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 21:44:45 +00:00
Eric Christopher
aa3ace10c1
New "move to fp reg" routine. Use it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113537 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 20:49:25 +00:00
Eric Christopher
ef2fdd2141
"Strike that, reverse it." -- Mr. Wonka.
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Truncate when truncating, extend when extending.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113536 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 20:36:19 +00:00
Eric Christopher
ce07b5458d
Add FPTrunc, fix some bugs where I forgot to update the value map.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113533 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 20:26:31 +00:00
Eric Christopher
9a040492f7
Basic FP->Int, Int->FP conversions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113523 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 18:54:59 +00:00
Bruno Cardoso Lopes
ae4f7421c0
Add one more pattern to fallback movddup
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113522 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 18:48:34 +00:00
Evan Cheng
5f54ce3473
For each instruction itinerary class, specify the number of micro-ops each
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instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.
This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 18:18:55 +00:00
Roman Divacky
5baf79edc0
Make ELF OS ABI dependent on the OS from target triple.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113508 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 17:57:50 +00:00
Dale Johannesen
f73c5587fa
Move remaining MMX instructions from SSE to MMX.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113501 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 17:13:07 +00:00
Kalle Raiskila
bb7d33a253
Silence compiler warning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113478 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 07:30:15 +00:00