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9626 Commits

Author SHA1 Message Date
Dan Gohman
f58cb6d224 Fix X86FastISel's shift and select code to reject illegal types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55857 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 21:27:34 +00:00
Dan Gohman
31d26912cc Fix the opcodes used by X86FastISel for shifts and conditional moves. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55855 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 21:13:04 +00:00
Evan Cheng
0de588fd89 Factor out code that emits load and store instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55854 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 21:00:03 +00:00
Owen Anderson
9c7216f984 Rename method. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55853 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 20:49:33 +00:00
Dan Gohman
c39f4dba1c X86FastISel support for shifts and conditional moves. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55844 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 18:30:08 +00:00
Evan Cheng
e2471a9169 If SSE2 is available, x86 should pass first 3 f32/f64 arguments in XMM registers for fastcc calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55840 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 17:24:07 +00:00
Dan Gohman
4f22bb0676 Check a comparion's operand type for legality before 
expanding its operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55820 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 01:33:56 +00:00
Dan Gohman
f52550b50e Fix X86FastISel code for comparisons and conditional branches 
to check the result of getRegForValue before using it, and
to check for illegal operand types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55819 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 01:15:35 +00:00
Dan Gohman
d89ae99ec8 X86FastISel support for conditional branches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55816 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 01:06:14 +00:00
Owen Anderson
95267a1e67 Add initial support for selecting constant materializations that require constant 
pool loads on X86 in fast isel.  This isn't actually used yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55814 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 00:06:23 +00:00
Dan Gohman
6e3f05f5ce X86FastISel support for ICmpInst and FCmpInst. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55811 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-04 23:26:51 +00:00
Evan Cheng
4a03775777 For whatever the reason, x86 CallingConv::Fast (i.e. fastcc) was not passing scalar arguments in registers. This patch defines a new fastcc CC which is slightly different from the FastCall CC. In addition to passing integer arguments in ECX and EDX, it also specify doubles are passed in 8-byte slots which are 8-byte aligned (instead of 4-byte aligned). This avoids a potential performance hazard where doubles span cacheline boundaries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55807 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-04 22:59:58 +00:00
Devang Patel
db10033d7c If function notes say optimize for size, then adjust alignment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55794 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-04 21:03:41 +00:00
Dan Gohman
ae73dc1448 Tidy up several unbeseeming casts from pointer to intptr_t. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55779 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-04 17:05:41 +00:00
Owen Anderson
79924eb6f5 Fix the ordering of operands to the store (inverted relative to LLVM IR), and fix the testcase. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55777 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-04 16:48:33 +00:00
Dan Gohman
6448d91ad1 Clean up uses of TargetLowering::getTargetMachine. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55769 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-04 15:39:15 +00:00
Owen Anderson
a3971dfbfe Add a first attempt at implementing stores for X86 fast isel using target hooks. 
Dan or Evan, please review.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55764 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-04 07:08:58 +00:00
Evan Cheng
373d50af1d Load from GV stub should be locally CSE'd. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55763 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-04 06:18:33 +00:00
Evan Cheng
c2feb5c262 Remove code that pad number of bytes to pop for X86_FastCall CC. The code doesn't do the "aligning" for Cygwin, Mingw, and Windows. But aligning it on Darwin and Linux breaks gcc compatibility. That ruled out all the platforms we support! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55756 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-04 01:04:15 +00:00
Dale Johannesen
7794f2a3a7 Add intrinsics for log, log2, log10, exp, exp2. 
No functional change (and no FE change to generate them).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55753 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-04 00:47:13 +00:00
Dan Gohman
3df24e667f Create HandlePHINodesInSuccessorBlocksFast, a version of 
HandlePHINodesInSuccessorBlocks that works FastISel-style. This
allows PHI nodes to be updated correctly while using FastISel.

This also involves some code reorganization; ValueMap and
MBBMap are now members of the FastISel class, so they needn't
be passed around explicitly anymore. Also, SelectInstructions
is changed to SelectInstruction, and only does one instruction
at a time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55746 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-03 23:12:08 +00:00
Evan Cheng
8b19e56051 Add X86 target hook to implement load (even from GlobalAddress). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55693 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-03 06:44:39 +00:00
Ted Kremenek
b388eb82fb Fix capitalization in #include of FastISel.h. This unbreaks the build on case-sensitive filesystems. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55687 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-03 02:54:11 +00:00
Evan Cheng
88e3041ca6 Unbreak fast isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55685 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-03 01:04:47 +00:00
Evan Cheng
c3f44b0d63 Let tblgen only generate fastisel routines, not the class definition. This makes it easier for targets to define its own fastisel class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55679 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-03 00:03:49 +00:00
Dale Johannesen
a619d012c1 Fix some bugs in the code sequences for atomics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55643 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-02 20:30:23 +00:00
Evan Cheng
95ce1178e4 Add Mac OS X compatible JIT callback routine. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55625 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-02 07:49:03 +00:00
Evan Cheng
7602e11c32 Revamp ARM JIT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55624 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-02 06:52:38 +00:00
Evan Cheng
acff339e39 Change getBinaryCodeForInstr prototype. First operand MachineInstr& should be const. Make corresponding changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55623 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-02 06:51:36 +00:00
Evan Cheng
3aac788365 Control flow instruction encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55601 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-01 08:25:56 +00:00
Evan Cheng
3c2ee4939b ldm / stm instruction encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55599 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-01 07:48:18 +00:00
Evan Cheng
5d2c1cf74d AXI2 and AXI3 instruction encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55598 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-01 07:34:13 +00:00
Evan Cheng
4bbd5f8a9c Reorganize instruction formats again; AXI1 encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55597 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-01 07:19:00 +00:00
Evan Cheng
840917be2c addrmode3 instruction encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55596 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-01 07:00:14 +00:00
Evan Cheng
0d14fc8cd5 Reorganize some instruction format definitions. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55594 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-01 01:51:14 +00:00
Evan Cheng
93912739c9 Rest of addrmode2 instruction encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55593 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-01 01:27:33 +00:00
Evan Cheng
17222df0ec Addr2 word / byte load encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55591 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-31 19:02:21 +00:00
Evan Cheng
b7880ac470 Addr1 instructions opcodes are encoded in bits 21-24; encode S bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55590 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-31 18:32:16 +00:00
Gabor Greif
93c53e5583 fix a bunch of 80-col violations 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55588 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-31 15:37:04 +00:00
Bill Wendling
9440e35b98 Revert the "XFAIL" for the rotate_ops.ll testcase. Instead, mark ISD::ROTR 
instructions in CellSPU as "Expand" so that they won't be generated. I added a
"FIXME" so that this hack can be addressed and reverted once ISD::ROTR is
supported in the .td files.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55582 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-31 02:59:23 +00:00
Bill Wendling
3156b62855 Expand for ROTR with MVT::i64. 
Dale, Could you please review this?


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55581 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-31 02:53:19 +00:00
Gabor Greif
92362680c1 fix some 80-col violations 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55565 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-30 10:09:02 +00:00
Evan Cheng
b18ae3cb63 For now, can't mark XOR64rr isAsCheapAsAMove. It's technically correct. But various passes cannot handle remating these. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55562 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-30 08:54:22 +00:00
Evan Cheng
eb9f89287e Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55558 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-30 02:03:58 +00:00
Dale Johannesen
ea9eedb787 Add ppc partial-word ATOMIC_CMP_SWAP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55554 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-30 00:08:53 +00:00
Evan Cheng
456704476f Swap fp comparison operands and change predicate to allow load folding (safely this time). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55553 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-29 23:22:12 +00:00
Evan Cheng
97af60b3ae Use static_cast instead of C style cast. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55552 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-29 23:21:31 +00:00
Evan Cheng
94a50da93c Backing out 55521. Not safe. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55548 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-29 22:13:21 +00:00
Dale Johannesen
0e55f0678c Add partial word version of ATOMIC_SWAP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55546 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-29 18:29:46 +00:00
Owen Anderson
667d8f7607 Add initial support for fast isel of instructions that have inputs pinned to physical registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55545 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-29 17:45:56 +00:00
Evan Cheng
ba705f62b1 TableGen'ing instruction encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55533 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-29 07:42:03 +00:00
Evan Cheng
612b79edc9 addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 encode the opcode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55531 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-29 07:40:52 +00:00
Evan Cheng
3924f78a96 MVN is addrmode1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55530 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-29 07:36:24 +00:00
Evan Cheng
130966411f More refactoring. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55528 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-29 06:41:12 +00:00
Evan Cheng
4d46d0af58 Swap fp comparison operands and change predicate to allow load folding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55521 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 23:48:31 +00:00
Evan Cheng
37f25d989a Refactor ARM instruction format definitions into a separate file. No functionality changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55518 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 23:39:26 +00:00
Dan Gohman
99b218218c Add a target callback for FastISel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55512 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 23:21:34 +00:00
Gabor Greif
327ef031ed remove tabs, fix > 80 cols 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55511 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 23:19:51 +00:00
Gabor Greif
ba36cb5242 erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55504 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 21:40:38 +00:00
Mon P Wang
5ad0bf658a In lowering SELECT_CC, removed cases where we can't flip the true and false when the compare value has a NaN 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55499 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 21:04:05 +00:00
Rafael Espindola
833a990c26 Use resize instead of reserve. Reserve doesn't change size(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55486 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 18:32:53 +00:00
Dale Johannesen
97efa36586 Implement partial-word binary atomics on ppc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55478 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 17:53:09 +00:00
Evan Cheng
66e13153bd FsFLD0S{S|D} and V_SETALLONES are as cheap as moves. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55466 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 07:52:25 +00:00
Dale Johannesen
e00a8a2a2e Split the ATOMIC NodeType's to include the size, e.g. 
ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD.
Increased the Hardcoded Constant OpActionsCapacity to match.
Large but boring; no functional change.

This is to support partial-word atomics on ppc; i8 is
not a valid type there, so by the time we get to lowering, the
ATOMIC_LOAD nodes looks the same whether the type was i8 or i32.
The information can be added to the AtomicSDNode, but that is the
largest SDNode; I don't fully understand the SDNode allocation,
but it is sensitive to the largest node size, so increasing
that must be bad.  This is the alternative.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55457 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 02:44:49 +00:00
Bill Wendling
1dd0086b06 Make "movdq2q" and "movq2dq" dependent upon having SSE2 because they use the 
SSE2 registers as well as the MMX registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55436 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-27 21:32:04 +00:00
Dan Gohman
7deb17108f Reinstate the x86-64 portion of r55190. When doing extloads into 
64-bit registers from 16-bit and smaller memory locations, prefer
instructions that define the entire 64-bit register, to avoid
partial-register updates.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55422 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-27 17:33:15 +00:00
Gabor Greif
99a6cb92d1 disallow direct access to SDValue::ResNo, provide a getter instead 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55394 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-26 22:36:50 +00:00
Owen Anderson
a317767f0e These assertions should be return false's instead, allowing the client to detect the failure. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55377 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-26 18:50:40 +00:00
Owen Anderson
940f83e772 Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested 
was inserted or not.  This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55375 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-26 18:03:31 +00:00
Chris Lattner
6ba50a9252 If an xmm register is referenced explicitly in an inline asm, make sure to 
assign it to a version of the xmm register with the regclass that matches its
type.  This fixes PR2715, a bug handling some crazy xpcom case in mozilla.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55358 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-26 06:19:02 +00:00
Evan Cheng
b09c25ebf0 This is done. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55348 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-26 01:13:44 +00:00
Dale Johannesen
bdab93a2ef Implement 32 & 64 bit versions of PPC atomic 
binary primitives.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55343 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-25 22:34:37 +00:00
Evan Cheng
bdf7b5da47 80 col. violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55341 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-25 21:58:43 +00:00
Evan Cheng
ab6c3bb44d Try approach to moving call address load inside of callseq_start. Now it's done during the preprocess of x86 isel. callseq_start's chain is changed to load's chain node; while load's chain is the last of callseq_start or the loads or copytoreg nodes inserted to move arguments to the right spot. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55338 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-25 21:27:18 +00:00
Dale Johannesen
140a8bb006 Remove PPC-specific lowering for atomics; the 
generic stuff works fine.

Mark rewritten cmp-and-swap as not using CR1.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55336 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-25 21:09:52 +00:00
Dale Johannesen
65e3973dff It's important for the cmp-and-swap to balance 
loads and stores but it's even more important for
it to store the right value.:(



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55319 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-25 18:53:26 +00:00
Bill Wendling
cb3c51a4ae Nevermind. This broke the bootstrap (?!). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55318 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-25 18:32:39 +00:00
Bill Wendling
51e05e7a99 MOVQ2DQ and MOVQ2DQ use SSE2. We should conditionalize the use of these 
instructions on having SSE2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55317 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-25 18:20:52 +00:00
Evan Cheng
e7321441ac Fix asm printing of MOVSDto64mr and MOV64toSDrm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55300 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-25 04:11:42 +00:00
Bill Wendling
59b63e4a18 Temporarily reverting r55292. It's causing a bootstraping failure: 
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc ... src/libiberty/make-temp-file.c -o make-temp-file.o
Assertion failed: (Node2Index[SU->NodeNum] > Node2Index[I->Dep->NodeNum] && "Wrong topological sorting"), function InitDAGTopologicalSorting, file /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp, line 508.
../../../../llvm-gcc.src/libiberty/hashtab.c:955: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter> for instructions.
make[4]: *** [hashtab.o] Error 1
make[4]: *** Waiting for unfinished jobs....
make[3]: *** [multi-do] Error 1
make[2]: *** [all] Error 2
make[1]: *** [all-target-libiberty] Error 2
make: *** [all] Error 2



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55295 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-24 21:45:30 +00:00
Evan Cheng
32c727cd95 Move callseq_start above the call address load to allow load to be folded into the call node. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55292 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-24 19:19:55 +00:00
Cedric Venet
d85f51abd4 Use additionnal include directory instead of ../ in #include. 
Suggested by aKor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55282 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-24 12:30:46 +00:00
Chris Lattner
944fac71e0 Switch the asmprinter (.ll) and all the stuff it requires over to 
use raw_ostream instead of std::ostream.  Among other goodness,
this speeds up llvm-dis of kc++ with a release build from 0.85s
to 0.49s (88% faster).

Other interesting changes:
 1) This makes Value::print be non-virtual.
 2) AP[S]Int and ConstantRange can no longer print to ostream directly, 
    use raw_ostream instead.
 3) This fixes a bug in raw_os_ostream where it didn't flush itself 
    when destroyed.
 4) This adds a new SDNode::print method, instead of only allowing "dump".


A lot of APIs have both std::ostream and raw_ostream versions, it would
be useful to go through and systematically anihilate the std::ostream 
versions.

This passes dejagnu, but there may be minor fallout, plz let me know if
so and I'll fix it.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55263 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-23 22:23:09 +00:00
Anton Korobeynikov
017c260944 Provide a 64 bit variant of mmx.maskmovq intrinsic lowering. 
Is there way to avoid explicit target check?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55238 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-23 15:53:19 +00:00
Dan Gohman
f350b277f3 Move the point at which FastISel taps into the SelectionDAGISel 
process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.

Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.

To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55219 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-23 02:25:05 +00:00
Anton Korobeynikov
70f24c62ad Make option variables static, so they won't cause nameclash 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55203 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-22 21:27:49 +00:00
Bill Wendling
449416deb6 Reverting r55190, r55191, and r55192. They broke the build with this error message: 
{standard input}:17:bad register name `%sil'
make[4]: *** [libgcc/./_addvsi3.o] Error 1
make[4]: *** Waiting for unfinished jobs....
{standard input}:23:bad register name `%dil'
{standard input}:28:bad register name `%dil'
make[4]: *** [libgcc/./_addvdi3.o] Error 1
{standard input}:18:bad register name `%sil'
make[4]: *** [libgcc/./_subvsi3.o] Error 1



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55200 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-22 20:51:05 +00:00
Dan Gohman
b4ae2da7e4 Anyext tweaks for x86. When extloading a value to i32 or i64, choose 
instructions that define the full 32 or 64-bit value. When anyexting
from i8 to i16 or i32, it's not necessary to zero out the high
portion of the register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55190 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-22 19:19:31 +00:00
Dale Johannesen
f87d6c02f5 Implement __sync_synchronize on ppc32. Patch by Gary Benson. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55186 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-22 17:20:54 +00:00
Dale Johannesen
5f0cfa299d Rewrite ppc code generated for __sync_{bool|val}_compare_and_swap 
so that lwarx and stwcx are always executed the same number of times.
This is important for performance, I'm told.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55163 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-22 03:49:10 +00:00
Dan Gohman
22bb31103d Factor out the predicate check code from DAGISelEmitter.cpp 
and use it in FastISelEmitter.cpp, and make FastISel
subtarget aware. Among other things, this lets it work
properly on x86 targets that don't have SSE, where it
successfully selects x87 instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55156 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-22 00:20:26 +00:00
Bill Wendling
ae0218c914 If part of the mask is "undef", then ignore it as we don't care what goes into it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55147 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-21 22:36:36 +00:00
Bill Wendling
e85dc49e13 Fix whitespace. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55146 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-21 22:35:37 +00:00
Evan Cheng
1887c1c2f9 Fix a number of byval / memcpy / memset related codegen issues. 
1. x86-64 byval alignment should be max of 8 and alignment of type. Previously the code was not doing what the commit message was saying.
2. Do not use byte repeat move and store operations. These are slow.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55139 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-21 21:00:15 +00:00
Mon P Wang
7e66510a2e Treat floating point ST1 the same as ST0 when lowering for a call result 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55135 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-21 19:54:16 +00:00
Dan Gohman
509e84fa71 Add libm-oriented ISD opcodes for rounding operations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55130 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-21 17:55:02 +00:00
Anton Korobeynikov
62990bafa3 Allow inline asm nodes with empty bodies inside JIT. 
This unbreaks explicit reg vars inside JIT, which are
implemented in such hacky way :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55128 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-21 17:33:01 +00:00
Dan Gohman
ad3460c3c9 Simplify SelectRoot's interface, and factor out some common code 
from all targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55124 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-21 16:36:34 +00:00
Bill Wendling
3b32a23a90 Clean up whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55117 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-21 08:38:54 +00:00
Chris Lattner
1f0f37a742 unbreak the CBE on treeadd an many others. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55112 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-21 05:51:43 +00:00
Owen Anderson
cb37188323 Use raw_ostream throughout the AsmPrinter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55092 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-21 00:14:44 +00:00
Dan Gohman
0bfa1bfbff Move the handling of ANY_EXTEND, SIGN_EXTEND_INREG, and TRUNCATE 
out of X86ISelDAGToDAG.cpp C++ code and into tablegen code.
Among other things, using tablegen for these things makes them
friendlier to FastISel.

Tablegen can handle the case of i8 subregs on x86-32, but currently
the C++ code for that case uses MVT::Flag in a tricky way, and it
happens to schedule better in some cases. So for now, leave the
C++ code in place to handle the i8 case on x86-32.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55078 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-20 21:27:32 +00:00
Dan Gohman
bb466331e7 Simplify FastISel's constructor argument list, make the FastISel 
class hold a MachineRegisterInfo member, and make the
MachineBasicBlock be passed in to SelectInstructions rather
than the FastISel constructor.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55076 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-20 21:05:57 +00:00
Dan Gohman
cb0fe7c226 Clean up a dead return missed in r55055. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55057 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-20 15:54:46 +00:00
Dan Gohman
67ca6be16a Tablegen generated code already tests the opcode value, so it's not 
necessary to use dyn_cast in these predicates.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55055 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-20 15:24:22 +00:00
Dan Gohman
d8ed2a7184 Use cast instead of dyn_cast. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55052 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-20 14:50:24 +00:00
Dan Gohman
1e684cf1ef Fix comment spacing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55047 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-20 13:46:21 +00:00
Dale Johannesen
a99e38495f Add remaining 64-bit atomic patterns for x86-64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55029 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-20 00:48:50 +00:00
Bill Wendling
5bf1b4eacd Revert r55018 and apply the correct "fix" for the 64-bit sub_and_fetch atomic. 
Just expand it like the other X-bit sub_and_fetches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55023 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-20 00:28:16 +00:00
Bill Wendling
108ecf3975 Add support for the __sync_sub_and_fetch atomics and friends for X86. The code 
was already present, but not hooked up to anything.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55018 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-19 23:09:18 +00:00
Dan Gohman
1adf1b03af Instantiate FastISel for X86. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55011 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-19 21:45:35 +00:00
Dan Gohman
d9f3c480a7 The X86 target will soon have an implementation of createFastISel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55010 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-19 21:32:53 +00:00
Dale Johannesen
140be2dfb7 Add support for 8 and 16 bit forms of __sync 
builtins on X86.

Change "lock" instructions to be on a separate line.
This is needed to work around a bug in the Darwin
assembler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54999 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-19 18:47:28 +00:00
Chris Lattner
23f35bc3ae add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54985 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-19 06:22:16 +00:00
Chris Lattner
fa7e17d379 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54964 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-19 00:41:02 +00:00
Chris Lattner
cd7ab05c37 remove empty file 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54950 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-18 21:27:19 +00:00
Anton Korobeynikov
70053c340e Unbreak cpp backend: upgrade output due to change in APInt API 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54942 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-18 20:03:45 +00:00
Evan Cheng
6aa3898730 ARM asm printer can't handle dwarf info yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54913 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-18 08:52:48 +00:00
Evan Cheng
0ac3fc2a61 Fix a (u)comiss intrinsic lowering bug. It was using anyext which can return junk in higher bits. Patch by Nate Begeman. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54903 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-17 19:22:34 +00:00
Gordon Henriksen
8715367182 Don't require Registry specializations to define random static variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54902 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-17 19:08:34 +00:00
Gordon Henriksen
5eca075b74 Rename some GC classes so that their roll will hopefully be clearer. 
In particular, Collector was confusing to implementors. Several
thought that this compile-time class was the place to implement
their runtime GC heap. Of course, it doesn't even exist at runtime.
Specifically, the renames are:

  Collector               -> GCStrategy
  CollectorMetadata       -> GCFunctionInfo
  CollectorModuleMetadata -> GCModuleInfo
  CollectorRegistry       -> GCRegistry
  Function::getCollector  -> getGC (setGC, hasGC, clearGC)

Several accessors and nested types have also been renamed to be
consistent. These changes should be obvious.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54899 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-17 18:44:35 +00:00
Cedric Venet
94fb5f2a70 Make it compile on VC2005: 
- update VC projects.
- Add an overload to llvm::Stream for <<, since std::hex and std::dec have type std::ios_base& (*)(std::ios_base&) in VC++. (templating the function don't work, due to ambiguities)
- add ../ on several include in X86/AsmPrinter/

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54898 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-17 18:24:26 +00:00
Anton Korobeynikov
0bd89712c0 Move ARM to pluggable asmprinter 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54889 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-17 13:55:10 +00:00
Anton Korobeynikov
676fa7df9c Use correct name for PPC codegen library 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54888 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-17 13:54:44 +00:00
Anton Korobeynikov
06be997654 Factor out asmprinter out of ppc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54887 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-17 13:54:28 +00:00
Anton Korobeynikov
3c3bc48d33 Move X86 assembler printers into separate directory. This allows JIT-only users not to link it in (use 'x86codegen' llvm-config arg for this) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54886 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-17 13:53:59 +00:00
Chris Lattner
fad86b003a Rework the routines that convert AP[S]Int into a string. Now, instead of 
returning an std::string by value, it fills in a SmallString/SmallVector
passed in.  This significantly reduces string thrashing in some cases.

More specifically, this:
 - Adds an operator<< and a print method for APInt that allows you to 
   directly send them to an ostream.
 - Reimplements APInt::toString to be much simpler and more efficient
   algorithmically in addition to not thrashing strings quite as much.

This speeds up llvm-dis on kc++ by 7%, and may also slightly speed up the
asmprinter.  This also fixes a bug I introduced into the asmwriter in a
previous patch w.r.t. alias printing.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54873 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-17 07:19:36 +00:00
Anton Korobeynikov
afc20ae0e5 PPC/Linux normally uses named section for bss 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54847 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-16 12:59:02 +00:00
Anton Korobeynikov
888839e5ed Use proper strings section name for PPC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54846 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-16 12:58:46 +00:00
Anton Korobeynikov
d97f29531c Use correct name for TLS address resolution routine on x86-64 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54845 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-16 12:58:29 +00:00
Anton Korobeynikov
328da65bd1 Add interface for section override. Use this for Sparc, since it should use named BSS section. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54844 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-16 12:58:12 +00:00
Anton Korobeynikov
ffe31d7bf1 Move SLEB/ULEB size calculation routines from AsmPrinter to TargetAsmInfo. This makes JIT asmprinter-free. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54843 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-16 12:57:46 +00:00
Anton Korobeynikov
d0c1e29aec Reduce heap trashing due to std::string construction / concatenation via caching of section flags string representations 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54842 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-16 12:57:07 +00:00
Dan Gohman
172f0fa16b Build the X86GenFastISel.inc file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54806 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-14 23:18:11 +00:00
Dan Gohman
ef521f14b7 Also avoid pinsrw and pinsrb with a variable insertelement index. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54803 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-14 22:53:18 +00:00
Owen Anderson
44eb65cf58 Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54802 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-14 22:49:33 +00:00
Dan Gohman
c0573b13a1 Don't try to use the insertps instruction for vector 
element inserts with non-constant indices. This fixes
CodeGen/X86/vector-variable-idx.ll on machines that
have SSE4.1.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54801 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-14 22:43:26 +00:00
Owen Anderson
eaa009d963 Remove more uses of std::set. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54787 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-14 21:01:00 +00:00
Dan Gohman
ea9587bf41 Oops, check in these files too, for the FastISel -> Fast rename. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54750 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-13 19:55:00 +00:00
Bruno Cardoso Lopes
739e441311 Removed SELECT_CC custom lowering. This is not needed anymore, the SELECT node 
is lowered properly and covers everything LowerSELECT_CC did.
Added method printUnsignedImm in AsmPrinter to print uimm16 operands. This
avoid the ugly instruction by instruction checking in printOperand.
Added a swap instruction present in the allegrex core.
Added two conditional instructions present in the allegrex core : MOVZ and MOVN.
They both allow a more efficient SELECT operation for integers.
Also added SELECT patterns to optimize MOVZ and MOVN usage.
The brcond and setcc patterns were cleaned: redundant and suboptimal patterns
were
removed. The suboptimals were replaced by more efficient ones.
Fixed some instructions that were using immZExt16 instead of immSExt16.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54724 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-13 07:13:40 +00:00
Dale Johannesen
6f83be0c61 When resolving a stub in x86-64 JIT, use a PC-relative branch 
rather than the absolute address if the target is within range.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54708 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-12 23:20:24 +00:00
Dale Johannesen
5f777192a0 Make x86-64 JIT changes Darwin-specific. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54700 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-12 21:02:08 +00:00
Jim Grosbach
1a6c683315 Whitespace cleanup. Test commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54695 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-12 18:34:45 +00:00
Dale Johannesen
ec867a22b3 In the absence of a linker to build the GOT, use the 32-bit 
non_lazy_ptr mechanism on x86-64 Darwin JIT.  Fixes a bunch
of last night's failures.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54692 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-12 18:23:48 +00:00
Dale Johannesen
50dd1d0280 Some fixes for x86-64 JIT. Make it use small code 
model, except for external calls; this makes
addressing modes PC-relative.  Incomplete.

The assertion at the top of Emitter::runOnMachineFunction
was obviously bogus (always true) so I removed it.
If someone knows what the correct test should be to cover
all the various targets, please fix.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54656 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-11 23:46:25 +00:00
Nate Begeman
1db3c92306 Implement ISD::TRAP support on PPC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54644 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-11 17:36:31 +00:00
Chris Lattner
26e150f361 move some more stuff out of my email into readme.txt 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54603 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-10 01:14:08 +00:00
Chris Lattner
c90b866797 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54602 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-10 00:47:21 +00:00
Dan Gohman
d9ced09299 Add an EXTRACTPSmr pattern to match the pattern that 
X86ISelLowering creates.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54544 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-08 18:30:21 +00:00
Anton Korobeynikov
cbdf30af79 Properly print flags on Sparc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54543 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-08 18:26:10 +00:00
Anton Korobeynikov
16b7f5101b Generalize 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54542 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-08 18:25:52 +00:00
Anton Korobeynikov
25c6a087dd Use mergeable strings sections on sparc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54541 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-08 18:25:29 +00:00
Anton Korobeynikov
f5b6a47bb5 Handle visibility printing with all generality. Remove bunch of duplicate code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54540 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-08 18:25:07 +00:00
Anton Korobeynikov
382f002272 Use chars, where possible 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54539 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-08 18:24:10 +00:00
Anton Korobeynikov
7396e59543 Convert PPC/Linux to new section printing stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54538 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-08 18:23:49 +00:00
Anton Korobeynikov
bc331a8d6f Switch PPC/Darwin to new section handling stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54537 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-08 18:23:25 +00:00
Anton Korobeynikov
34da127be5 Cleanup 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54536 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-08 18:22:59 +00:00
Evan Cheng
42ccc21ce7 Undo most of r54519. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54534 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-08 17:56:50 +00:00
Evan Cheng
711b6dce24 It's not legal to output a GV in a coalesced section if it's used in an ARM PIC relative constantpool. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54519 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-08 06:56:16 +00:00
Evan Cheng
15621a2569 Fix indentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54518 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-08 06:43:59 +00:00
Bruno Cardoso Lopes
65ad452536 Support added for ctlz intrinsic, test case added. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54516 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-08 06:16:31 +00:00
Bruno Cardoso Lopes
f131fa26e6 Match raw "psp" triple target, as done by the homebrew toolchain. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54514 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-08 04:49:42 +00:00
Bruno Cardoso Lopes
7da151cd5d Added Mips support for DYNAMIC_STACKALLOC 
Fixed bug in adjustMipsStackFrame, which was breaking
while trying to access a dead stack object index. Also added
one more alignment before fixing the callee saved registers
stack offset adjustment.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54485 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-07 19:08:11 +00:00
Anton Korobeynikov
6a35daed6f Remove dead forward decl 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54461 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-07 09:55:25 +00:00
Anton Korobeynikov
feac94b18d Print section flags ok on platforms, which use '@' as comment string. Fix test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54460 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-07 09:55:06 +00:00
Anton Korobeynikov
1e27da3e6c Add assertion for easy debugging of missing stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54459 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-07 09:54:40 +00:00
Anton Korobeynikov
0f3cc65738 Switch ARM to new section handling stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54458 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-07 09:54:23 +00:00
Anton Korobeynikov
79579c911f Switch Alpha to new section handling stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54457 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-07 09:53:57 +00:00
Anton Korobeynikov
fcd99bb428 Use EmitAlignment consistently 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54456 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-07 09:53:38 +00:00
Anton Korobeynikov
2a166e9739 Cleanup 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54455 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-07 09:53:13 +00:00
Anton Korobeynikov
98a6dd0cf5 Cleanup 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54454 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-07 09:52:54 +00:00
Anton Korobeynikov
dc3ca2ec3c Switch IA64 to new section-handling stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54453 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-07 09:52:35 +00:00
Anton Korobeynikov
003bcab8f3 Cleanup 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54452 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-07 09:52:13 +00:00
Anton Korobeynikov
4578862dcc Provide convenient helpers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54451 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-07 09:51:54 +00:00
Anton Korobeynikov
5b794b98ce Switch Sparc to new section handling stuff. Refactor printing of module-level GVs significantly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54450 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-07 09:51:25 +00:00
Anton Korobeynikov
84e160e265 Add hook for constant pool section selection for darwin. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54449 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-07 09:51:02 +00:00
Anton Korobeynikov
93cacf131d Select section for constant pool entries 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54448 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-07 09:50:34 +00:00
Dan Gohman
e3d920699c Re-enable elimination of unnecessary SUBREG_TO_REG instructions in 
LowerSubregs, and fix an x86-64 isel bug that this exposed.

SUBREG_TO_REG for x86-64 implicit zero extension is only safe for
isel to generate when the source is known to always have zeros in
the high 32 bits. The EXTRACT_SUBREG instruction does not clear
the high 32 bits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54444 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-07 02:54:50 +00:00
Dan Gohman
8a1510d192 Re-introduce the 8-bit subreg zext-inreg patterns for x86-32, 
this time using MOV32to32_ and MOV16to16_. Thanks to Evan for
suggesting this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54418 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-06 18:27:21 +00:00
Dan Gohman
165660e417 xchg does not modify FLAGS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54411 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-06 15:52:50 +00:00
Bruno Cardoso Lopes
bbe51362d5 Added support for fp callee saved registers. 
Added fp register clobbering during calls.
Added AsmPrinter support for "fmask", a bitmask that indicates where on the 
stack the fp callee saved registers are.

Fixed the stack frame layout for Mips, now the callee saved regs 
are in the right stack location (a little documentation about how this
stack frame must look like is present in MipsRegisterInfo.cpp).
This was done using the method MipsRegisterInfo::adjustMipsStackFrame
To be more clear, these are examples of what is solves :  

1) FP and RA are also callee saved, and despite they aren't in CSI they 
   must be saved before the fp callee saved registers. 
2) The ABI requires that local varibles are allocated before the callee 
   saved register area, the opposite behavior from the default allocation.
3) CPU and FPU saved register area must be aligned independent of each
   other.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54403 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-06 06:14:43 +00:00
Evan Cheng
e9d5035838 Fix PR2620: Fix X86cmppd selection code so it expects operands to be v2f64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54376 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-05 22:19:15 +00:00
Dan Gohman
8f613f30a7 Trim #includes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54350 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-05 15:32:23 +00:00
Owen Anderson
6ac8df7f61 This option doesn't need to be a target option. It can be in SDISel instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54336 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-05 00:27:28 +00:00
Owen Anderson
bd3ba461eb - Fix SelectionDAG to generate correct CFGs. 
- Add a basic machine-level dead block eliminator.

These two have to go together, since many other parts of the code generator are unable to handle the unreachable blocks otherwise created.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54333 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-04 23:54:43 +00:00
Dan Gohman
d0859943ac Add an assert to catch invalid VECTOR_SHUFFLE mask indices. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54329 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-04 23:09:15 +00:00
Bruno Cardoso Lopes
f7f3b50cd8 Mips ISelLowering cleanup : Removed old LowerCALL and FORMAL_ARGS helpers, they 
aren't used anyway, they also used to broke compiling when fastcc was specified for a
function, but not anymore.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54316 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-04 07:12:52 +00:00
Bruno Cardoso Lopes
ea9d4d6ab0 Handle i32->f32 bitconvert results. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54315 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-04 06:44:31 +00:00
Andrew Lenharth
08ca62bb6f Add atomic sub for other sizes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54314 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-03 20:17:34 +00:00
Chris Lattner
e594fd473e Emit saveri with the correct operand order, patch by Richard Pennington! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54313 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-03 18:16:14 +00:00
Bruno Cardoso Lopes
64cf160fef Fix PR2615 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54312 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-03 15:37:43 +00:00
Bruno Cardoso Lopes
91ef849e6c Improved asm inline for hi,lo results 
Added hi,lo registers to be used,def implicitly. This provides better handle of
instructions which use hi/lo.
Fixes a small BranchAnalysis bug


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54274 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-02 19:42:36 +00:00
Bruno Cardoso Lopes
1906c5a63b Apply the same pattern used in 'and' lowering for 'or' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54273 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-02 19:37:33 +00:00
Bruno Cardoso Lopes
7bd7182e21 Expand fcopysign 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54250 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-31 18:50:54 +00:00
Bruno Cardoso Lopes
772837778b Handle more SELECT corner cases considering legalize types, probabily wont work with 
the default legalizer.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54249 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-31 18:31:28 +00:00
Dale Johannesen
7232464bda Add a flag to disable jump table generation (all 
switches use the binary search algorithm) for
environments that don't support it.  PPC64 JIT
is such an environment; turn the flag on for that.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54248 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-31 18:13:12 +00:00
Bruno Cardoso Lopes
7030ae7728 Added pattern for floating point zero immediate (avoiding a constant pool 
access).
Added pattern to match bitconvert node.
Fixed MTC1 asm string bug.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54229 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-30 19:00:31 +00:00
Dan Gohman
11ba3b1af6 Reapply r54147 with a constraint to only use the 8-bit 
subreg form on x86-64, to avoid the problem with x86-32
having GPRs that don't have 8-bit subregs.

Also, change several 16-bit instructions to use 
equivalent 32-bit instructions. These have a smaller
encoding and avoid partial-register updates.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54223 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-30 18:09:17 +00:00
Bruno Cardoso Lopes
4b877ca1c5 Fixed bug in global address lowering for functions and in Brcond lowering 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54215 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-30 17:06:13 +00:00
Bruno Cardoso Lopes
ea7930e618 Removed small section flag for mips, the assembler doesnt support this flag 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54214 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-30 17:04:04 +00:00