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17308 Commits

Author SHA1 Message Date
Jim Grosbach
8638692362 Simplify T2 operand assignment notation a bit. No need to specify a bit range 
for the source field when it's the whole thing that's being referenced.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121291 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 22:10:43 +00:00
Jim Grosbach
0c2c217244 Tweak ARM fixup value adjustments for Thumb to better handle the half-word 
ordering of thumb mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121280 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 20:32:07 +00:00
Andrew Trick
6b1207267f Generalize PostRAHazardRecognizer so it can be used in any pass for 
both forward and backward scheduling. Rename it to
ScoreboardHazardRecognizer (Scoreboard is one word). Remove integer
division from the scoreboard's critical path.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121274 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 20:04:29 +00:00
Owen Anderson
cc78f5c09c Improve comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121272 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 19:31:11 +00:00
Jim Grosbach
022ab3779c Add initializer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121262 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 15:36:45 +00:00
Evan Cheng
275bf63115 Add comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121238 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 06:29:02 +00:00
Bill Wendling
b8958b031e Add support for loading from a constant pool. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121226 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 01:57:09 +00:00
Jim Grosbach
5be6d2af38 Let target asm backends see assembler flags as they go by. Use that to handle 
thumb vs. arm mode differences in WriteNopData().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121219 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 01:16:55 +00:00
Owen Anderson
255eafbd49 Simplify the byte reordering logic slightly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121216 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 00:21:33 +00:00
Owen Anderson
d8e351b96f VLDR fixups need special handling under Thumb. While the encoding is the same, 
the order of the bytes in the data stream is flipped around.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121215 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 00:18:36 +00:00
Matt Beaumont-Gay
2bf315f087 Fix a warning about a variable which is only used in an assertion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121206 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 23:26:21 +00:00
Bill Wendling
d832fa053b Cleanup in the Darwin end. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121198 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 23:11:00 +00:00
Evan Cheng
06d65f5156 Fix a bad prologue / epilogue codegen bug where the compiler would emit illegal 
vpush instructions to save / restore VFP / NEON registers like this:
vpush {d8,d10,d11}
vpop {d8,d10,d11}

vpush and vpop do not allow gaps in the register list.
rdar://8728956


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121197 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 23:08:38 +00:00
Bill Wendling
52e635ea35 A bit of cleanup: early exit ApplyFixup and cache the Fixup offset. No 
functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121195 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 23:05:20 +00:00
Jim Grosbach
d967cd096a Binary encoding for ARM tLDRspi and tSTRspi. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121186 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 21:50:47 +00:00
Owen Anderson
bdf714450b Fix Thumb2 encoding of the S bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121182 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 20:50:15 +00:00
Jim Grosbach
97a884d602 Refactor the ARM CMPz* patterns to just use the normal CMP instructions when 
possible. They were duplicates for everything exception the source pattern
before.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121179 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 20:41:06 +00:00
Evan Cheng
52f21e35e8 Code clean up; no functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121176 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 20:11:46 +00:00
Evan Cheng
9801b5c822 Code clean up; no functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121172 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 19:59:34 +00:00
Bruno Cardoso Lopes
bd3af09cef Remove target specific node MipsISD::CMov, which is not used because all conditional moves are directly matched using tablegen patterns. If there's a need in the future, we can introduce it again 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121164 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 19:04:14 +00:00
Bruno Cardoso Lopes
ab8d53a56a Match a pattern generated by a dag combiner opt where: 
(select (load (load tga0)) (load tga1)) => (load (select (load tga0) tga1))

Thanks to Akira for pointing that.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121163 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 19:00:20 +00:00
Jim Grosbach
5169220624 Encode the literal field for tCMPzi instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121153 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 17:48:24 +00:00
Benjamin Kramer
6aa4943599 Add parens to pacify gcc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121142 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 15:50:35 +00:00
Jay Foad
40f8f6264d PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() and 
zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method
trunc(), to be const and to return a new value instead of modifying the
object in place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121120 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 08:25:19 +00:00
NAKAMURA Takumi
63fbb52163 lib/Target/X86/X86MCAsmInfo.cpp: [PR8741] On Win64, specify explicit PrivateGlobalPrefix as ".L". 
Or, global symbols @Lxxxx might be treated as temporal symbol by MCSymbol.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121103 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 02:43:45 +00:00
Owen Anderson
eb6779c5b9 Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121082 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 00:45:21 +00:00
Jim Grosbach
662a816e89 Add fixup for Thumb1 BL/BLX instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121072 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 23:57:07 +00:00
Wesley Peck
a3b2200472 Adding bug fix that was suppose to be part of 121044. 
patch contributed by Jack Whitham!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121049 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 22:19:28 +00:00
Wesley Peck
dc80380de8 Fixed reversed operands for IDIV and CMP instructions in MBlaze backend. 
Use BRAD instead of BRD for indirect branches in MBlaze backend.

patch contributed by Jack Whitham!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121044 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 22:06:49 +00:00
Wesley Peck
1e8cdd599c Fix a 16-bit immediate value detection bug in the MBlaze delay slot filler. 
Address more hazards in the MBlaze delay slot filler.

patch contributed by Jack Whitham!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121037 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 21:11:01 +00:00
Rafael Espindola
179821ac1f Remove the instruction fragment to data fragment lowering since it was causing 
freed data to be read. I will open a bug to track it being reenabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121028 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 19:08:48 +00:00
Owen Anderson
c76c59840b Revert r121021, which broke the buildbots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121026 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 18:57:40 +00:00
Jim Grosbach
ba3368ceae Trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121024 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 18:47:44 +00:00
Owen Anderson
4c386fc754 Improve handling of Thumb2 PC-relative loads by converting LDRpci (and friends) to Pseudos. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121021 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 18:35:51 +00:00
Jim Grosbach
04f74942f2 Encode the register operand of ARM CondCode operands correctly. ARM::CPSR if 
the instruction is predicated, reg0 otherwise.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121020 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 18:30:57 +00:00
Jim Grosbach
d67641b6f8 The ARM AsmMatcher needs to know that the CCOut operand is a register value, 
not an immediate. It stores either ARM::CPSR or reg0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121018 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 18:21:12 +00:00
Rafael Espindola
0bbe0b440e Second try at making direct object emission produce the same results 
as llc + llvm-mc. This time ELF is not changed and I tested that llvm-gcc
bootstrap on darwin10 using darwin9's assembler and linker.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121006 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 17:27:56 +00:00
Che-Liang Chiou
f964486771 ptx: add shift instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120982 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 04:00:03 +00:00
Evan Cheng
04e2b639c1 Eliminate unneeded #include's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120971 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-05 23:41:43 +00:00
NAKAMURA Takumi
714e07f75d ARM/CMakeLists.txt: Add missing MLxExpansionPass.cpp since r120960. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120966 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-05 23:08:57 +00:00
Evan Cheng
167be80ee7 Code clean up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120965 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-05 23:03:45 +00:00
Evan Cheng
f79ed109ec Remove an unused variable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120964 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-05 23:03:35 +00:00
Evan Cheng
48575f6ea7 Making use of VFP / NEON floating point multiply-accumulate / subtraction is 
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
   of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
   additional pipeline stall. So it's frequently better to single codegen
   vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
   stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
   vmla + vmla is very bad. But this isn't ideal either:
     vmul
     vadd
     vmla
   Instead, we want to expand the second vmla:
     vmla
     vmul
     vadd
   Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
   faster.

Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.

A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
   compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
   fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
   vmla / vmls will trigger one of the special hazards.

Work in progress, only A+B are enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120960 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-05 22:04:16 +00:00
Chris Lattner
9637d5b22e Teach X86ISelLowering that the second result of X86ISD::UMUL is a flags 
result.  This allows us to compile:

void *test12(long count) {
      return new int[count];
}

into:

test12:
	movl	$4, %ecx
	movq	%rdi, %rax
	mulq	%rcx
	movq	$-1, %rdi
	cmovnoq	%rax, %rdi
	jmp	__Znam                  ## TAILCALL

instead of:

test12:
	movl	$4, %ecx
	movq	%rdi, %rax
	mulq	%rcx
	seto	%cl
	testb	%cl, %cl
	movq	$-1, %rdi
	cmoveq	%rax, %rdi
	jmp	__Znam

Of course it would be even better if the regalloc inverted the cmov to 'cmovoq',
which would eliminate the need for the 'movq %rdi, %rax'.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120936 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-05 07:49:54 +00:00
Chris Lattner
b20e0b1fdd it turns out that when ".with.overflow" intrinsics were added to the X86 
backend that they were all implemented except umul.  This one fell back
to the default implementation that did a hi/lo multiply and compared the
top.  Fix this to check the overflow flag that the 'mul' instruction
sets, so we can avoid an explicit test.  Now we compile:

void *func(long count) {
      return new int[count];
}

into:

__Z4funcl:                              ## @_Z4funcl
	movl	$4, %ecx                ## encoding: [0xb9,0x04,0x00,0x00,0x00]
	movq	%rdi, %rax              ## encoding: [0x48,0x89,0xf8]
	mulq	%rcx                    ## encoding: [0x48,0xf7,0xe1]
	seto	%cl                     ## encoding: [0x0f,0x90,0xc1]
	testb	%cl, %cl                ## encoding: [0x84,0xc9]
	movq	$-1, %rdi               ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
	cmoveq	%rax, %rdi              ## encoding: [0x48,0x0f,0x44,0xf8]
	jmp	__Znam                  ## TAILCALL

instead of:

__Z4funcl:                              ## @_Z4funcl
	movl	$4, %ecx                ## encoding: [0xb9,0x04,0x00,0x00,0x00]
	movq	%rdi, %rax              ## encoding: [0x48,0x89,0xf8]
	mulq	%rcx                    ## encoding: [0x48,0xf7,0xe1]
	testq	%rdx, %rdx              ## encoding: [0x48,0x85,0xd2]
	movq	$-1, %rdi               ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
	cmoveq	%rax, %rdi              ## encoding: [0x48,0x0f,0x44,0xf8]
	jmp	__Znam                  ## TAILCALL

Other than the silly seto+test, this is using the o bit directly, so it's going in the right
direction.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120935 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-05 07:30:36 +00:00
Chris Lattner
96908b17ae generalize the previous check to handle -1 on either side of the 
select, inserting a not to compensate.  Add a missing isZero check
that I lost somehow.

This improves codegen of:

void *func(long count) {
      return new int[count];
}

from:

__Z4funcl:                              ## @_Z4funcl
	movl	$4, %ecx                ## encoding: [0xb9,0x04,0x00,0x00,0x00]
	movq	%rdi, %rax              ## encoding: [0x48,0x89,0xf8]
	mulq	%rcx                    ## encoding: [0x48,0xf7,0xe1]
	testq	%rdx, %rdx              ## encoding: [0x48,0x85,0xd2]
	movq	$-1, %rdi               ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
	cmoveq	%rax, %rdi              ## encoding: [0x48,0x0f,0x44,0xf8]
	jmp	__Znam                  ## TAILCALL
                                        ## encoding: [0xeb,A]

to:

__Z4funcl:                              ## @_Z4funcl
	movl	$4, %ecx                ## encoding: [0xb9,0x04,0x00,0x00,0x00]
	movq	%rdi, %rax              ## encoding: [0x48,0x89,0xf8]
	mulq	%rcx                    ## encoding: [0x48,0xf7,0xe1]
	cmpq	$1, %rdx                ## encoding: [0x48,0x83,0xfa,0x01]
	sbbq	%rdi, %rdi              ## encoding: [0x48,0x19,0xff]
	notq	%rdi                    ## encoding: [0x48,0xf7,0xd7]
	orq	%rax, %rdi              ## encoding: [0x48,0x09,0xc7]
	jmp	__Znam                  ## TAILCALL
                                        ## encoding: [0xeb,A]



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120932 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-05 02:00:51 +00:00
Chris Lattner
a2b5600e61 Improve an integer select optimization in two ways: 
1. generalize 
    (select (x == 0), -1, 0) -> (sign_bit (x - 1))
to:
    (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y

2. Handle the identical pattern that happens with !=:
   (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y

cmov is often high latency and can't fold immediates or
memory operands.  For example for (x == 0) ? -1 : 1, before 
we got:

< 	testb	%sil, %sil
< 	movl	$-1, %ecx
< 	movl	$1, %eax
< 	cmovel	%ecx, %eax

now we get:

> 	cmpb	$1, %sil
> 	sbbl	%eax, %eax
> 	orl	$1, %eax




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120929 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-05 01:23:24 +00:00
Bill Wendling
d643486058 Initialize HasPOPCNT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120923 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-04 23:57:24 +00:00
Benjamin Kramer
1292c22645 Add patterns for the x86 popcnt instruction. 
- Also adds a new POPCNT subtarget feature that is currently enabled if the target
  supports SSE4.2 (nehalem) or SSE4A (barcelona).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120917 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-04 20:32:23 +00:00
Benjamin Kramer
983839609f Simplify code. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120907 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-04 14:22:24 +00:00
Bob Wilson
c24130bade The Thumb tADDrSPi instruction is not valid when the destination is SP. 
Check for that and try narrowing it to tADDspi instead.  Radar 8724703.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120892 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-04 04:40:19 +00:00
Rafael Espindola
5d4918dbd1 There are two reasons why we might want to use 
foo = a - b
.long foo
instead of just
.long a - b

First, on darwin9 64 bits the assembler produces the wrong result. Second,
if "a" is the end of the section all darwin assemblers (9, 10 and mc) will not
consider a - b to be a constant but will if the dummy foo is created.

Split how we handle these cases. The first one is something MC should take care
of. The second one has to be handled by the caller.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120889 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-04 03:21:47 +00:00
Jim Grosbach
ceab50198e Encode condition code for Thumb1 conditional branch instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120865 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-04 00:20:40 +00:00
Jim Grosbach
ed09087dd3 Correctly size-reduce the t2CMPzrr instruction to tCMPzr when possible. 
tCMPzhir has undefined behavior when both source registers are low registers.
rdar://8728577

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120858 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 23:54:18 +00:00
Bill Wendling
fb62d550de Use correct variable names to match the patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120857 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 23:44:24 +00:00
Jim Grosbach
1b555d9f96 Match pattern operand names to expected encoding field names. This corrects the 
operand encoding ordering of the instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120852 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 23:21:25 +00:00
Jim Grosbach
4fa102b84e Remove incorrect BL target encoding (it's similar to, but not the same as the 
ARM instruction). Add encoding of bits 13 and 11.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120849 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 22:33:42 +00:00
Jim Grosbach
d91f4e40e6 Encode the 32-bit wide Thumb (and Thumb2) instructions with the high order 
halfword being emitted to the stream first. rdar://8728174

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120848 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 22:31:40 +00:00
Nate Begeman
5812b10adb Revert this change since it breaks a couple of the AVX tests. 
I'm unclear if the tests are actually correct or not, but reverting for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120847 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 22:29:15 +00:00
Nate Begeman
07c21d85b4 Scalar f32/f64 are also subregs of ymm regs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120844 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 21:54:39 +00:00
Nate Begeman
163e83d69a Remove SSE1-4 disable when AVX is enabled. While this may be useful for development, 
it completely breaks scalar fp in xmm regs when AVX is enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120843 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 21:54:14 +00:00
Jim Grosbach
41ad0c4c73 When using the 'push' mnemonic for Thumb2 stmdb, be explicit when it's the 
32-bit wide version by adding the .w suffix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120838 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 20:33:01 +00:00
Benjamin Kramer
b3a04d46e8 Remove unused variable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120836 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 19:55:37 +00:00
Jim Grosbach
6e57298127 Reduce t2 ldr/str instructions to the correct t1 versions when there's an 
immediate offset.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120833 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 19:47:11 +00:00
Jason W Kim
2ccf148fba fix ARM::fixup_arm_branch, cleanup, and share more code between ELF and Darwin 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120832 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 19:40:23 +00:00
Jim Grosbach
0b951ceb02 No need to declare EncoderMethod property anymore; just assign to it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120831 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 19:31:00 +00:00
Jim Grosbach
d253545c17 Add FIXMEs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120824 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 18:37:17 +00:00
Jim Grosbach
2c971ab9d9 Size reduction for tPUSH come from t2STMDB_UPD, not t2STMIA_UPD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120822 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 18:31:03 +00:00
Bill Wendling
278b6e81c8 Don't overwrite the opcode passed into the T1Special pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120782 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 02:02:58 +00:00
Bill Wendling
534a5e4305 Add Thumb encoding for some more instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120780 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 01:55:47 +00:00
Rafael Espindola
32a006e606 Try to resolve symbol differences early, and if successful create a plain 
data fragment. This reduces the time to assemble the test in 8711 from 60s to
54s.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120767 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 00:55:40 +00:00
Bill Wendling
0bdf0c05b9 The tLDR instruction wasn't encoded properly: 
<MCInst 2251 <MCOperand Reg:70> <MCOperand Reg:66> <MCOperand Imm:0> <MCOperand Reg:0> <MCOperand Imm:14> <MCOperand Reg:0>>

Notice that the "reg" here is 0, which is an invalid register. Put a check in
the code for this to prevent crashing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120766 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 00:53:22 +00:00
Jim Grosbach
7721e7f279 Trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120748 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-02 23:05:38 +00:00
Devang Patel
ee4854faf3 Use set directive for StartMinusEndExpr. 
This is a fix for llvm-gcc-i386-darwin9 buildbot failure.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120742 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-02 21:32:30 +00:00
Jim Grosbach
1ab4b211ea When expanding the MOVCCi32imm, make sure to use the ARM movt/movw opcodes, 
not thumb2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120711 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-02 16:42:25 +00:00
Jim Grosbach
ce4fadf884 Fix copy/pasto in vmin.f32 encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120709 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-02 16:30:58 +00:00
Wesley Peck
2e06398405 Teaching MBlaze backend how to reverse branch conditions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120707 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-02 16:17:11 +00:00
Jim Grosbach
dff84b0325 Add support for binary encoding of ARM 'adr' instructions referencing constant 
pool entries (LEApcrel pseudo). Ongoing saga of rdar://8542291.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120635 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-02 00:28:45 +00:00
Devang Patel
0be938e389 Revert r120580. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120630 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-02 00:22:29 +00:00
Evan Cheng
1bf891ae6e Fix and re-enable tail call optimization of expanded libcalls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120622 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 22:59:46 +00:00
Jason W Kim
0c628c2617 fixing style nit: move class static to global static 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120619 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 22:46:50 +00:00
Bill Wendling
cf590263cd Add a post encoder method to the VFP instructions to convert them to the Thumb2 
encoding if we're in that mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120608 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 21:54:50 +00:00
Jim Grosbach
5177f79c37 Use the correct fixup type for ARM VLDR* 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120604 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 21:09:40 +00:00
Jim Grosbach
5d14f9be7b Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADR 
instruction at MC lowering. Add binary encoding information for the ADR,
including fixup data for the label operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120594 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 19:47:31 +00:00
Owen Anderson
9d63d90de5 Add correct encodings for STRD and LDRD, including fixup support. Additionally, update these to unified syntax. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120589 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 19:18:46 +00:00
Jason W Kim
1920d82f75 kill trailing space 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120586 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 19:07:22 +00:00
Jim Grosbach
3990d8f89f 10 bits, not 12. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120584 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 18:51:32 +00:00
Devang Patel
056745cab6 Disable debug info for x86-darwin9 and earlier until PR 8715 and radar 8709290 are fixed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120580 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 16:59:34 +00:00
Duncan Sands
38169788fa I don't think it makes any sense to assert that the target supports SSE3 here. 
The user (i.e. whoever generated a call to the intrinsic in the first place) is
essentially asking for a particular instruction to be placed in the assembler.
If that instruction won't execute on the target machine, that's their problem
not ours.  Two buildbots with processors that don't support SSE3 were barfing
on the apm.ll test in CodeGen/X86 because of this assertion.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120574 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 12:58:13 +00:00
Che-Liang Chiou
3608d2ac67 ptx: bug fix: use after free 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120571 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 11:45:53 +00:00
Jim Grosbach
887c0e4cbf Elaborate on FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120552 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 04:01:17 +00:00
Jim Grosbach
baf120fbe8 Move the ARMAsmPrinter class defintiion into a header file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120551 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 03:45:07 +00:00
Evan Cheng
28cd48fffb Speculatively disable x86 portion of r120501 to appease the x86_64 buildbot. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120549 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 03:27:20 +00:00
Bill Wendling
ff25116a09 Remove "comparison of integers of different signs" warning by making the 
variable unsigned.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120541 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 02:49:04 +00:00
Bill Wendling
43f7b2d370 General cleanups of comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120536 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 02:42:55 +00:00
Jason W Kim
85fed5e0c5 ARM/MC/ELF relocation "hello world" for movw/movt. 
Lifted adjustFixupValue() from Darwin for sharing w ELF.
Test added
TODO:
  refactor ELFObjectWriter::RecordRelocation more.
  Possibly share more code with Darwin?
  Lots more relocations...



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120534 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 02:40:06 +00:00
Bill Wendling
0480e28fb2 Formatting. It's all the rage! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120533 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 02:36:55 +00:00
Bill Wendling
1d045ee884 More refactoring. This time the T1pI pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120532 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 02:28:08 +00:00
Eric Christopher
564857f776 Refactor load/store handling again. Simplify and make some room for 
reg+reg handling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120526 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 01:40:24 +00:00
Jan Wen Voung
a63bf704b4 Initialize an ARMConstantPoolValue field. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120525 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 01:38:58 +00:00