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14557 Commits

Author SHA1 Message Date
Johnny Chen
3c500e6947 Re-enable ARM/Thumb disassembler and add a workaround for a memcpy() call in 
ARMDecoderEmitter.cpp, with FIXME comment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100690 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 20:53:12 +00:00
Sean Callanan
90b7097f92 Added an AsmLexer for the ARM target, which uses 
a simple mapping of register names to IDs to
identify register tokens.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100685 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 20:29:34 +00:00
Dale Johannesen
375be7730a Educate GetInstrSizeInBytes implementations that 
DBG_VALUE does not generate code.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100681 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 19:51:44 +00:00
Anton Korobeynikov
4b38debf59 Remove late ARM codegen optimization pass committed by accident. 
It is not ready for public yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100673 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:23:27 +00:00
Anton Korobeynikov
e1676011c6 Split A8/A9 itins - they already were too big. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100672 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:22:11 +00:00
Anton Korobeynikov
895867326e Add some crude itin approximation for VFP load / stores on A9 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100671 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:22:03 +00:00
Anton Korobeynikov
67867135ec Add some crude approximation for neon load/store instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100670 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:21:58 +00:00
Anton Korobeynikov
9113052a1f Add some A8-based approximation for instructions with unknown cycle times 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100669 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:21:52 +00:00
Anton Korobeynikov
ebd4cb43c2 Move NEON-VFP domain fixer upper, so post-RA scheduler would benefit from it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100668 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:21:46 +00:00
Anton Korobeynikov
9ad709b523 Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100667 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:21:41 +00:00
Anton Korobeynikov
f3da92b2f2 Fix A8 FP NEON MAC itins 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100666 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:21:33 +00:00
Anton Korobeynikov
924369d58e A9 NEON FP itins 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100665 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:21:27 +00:00
Anton Korobeynikov
ec69dfa7ca Some permute goodness for A9 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100664 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:21:22 +00:00
Anton Korobeynikov
5ca13c6ee3 More shift itins for A9 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100663 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:21:16 +00:00
Anton Korobeynikov
ecc6406072 More fixes for itins 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100662 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:21:10 +00:00
Anton Korobeynikov
95102073e8 Fix invalid itins for 32-bit varians of VMLAL and friends 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100661 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:21:04 +00:00
Anton Korobeynikov
7930ac19e7 Add MAC stuff for A9 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100660 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:20:58 +00:00
Anton Korobeynikov
d76da03e91 Fix invalid NEON MAC itins on A8 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100659 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:20:53 +00:00
Anton Korobeynikov
dc0bab70cf Fix itins for VPAL 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100658 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:20:47 +00:00
Anton Korobeynikov
0a3e2b591c Fix itins for VABA 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100657 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:20:42 +00:00
Anton Korobeynikov
fc2b08438c Correct VMVN itinerary: operand is read in the second cycle, not in the first. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100656 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:20:36 +00:00
Anton Korobeynikov
e715b1e43a More A9 itineraries 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100655 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:20:29 +00:00
Anton Korobeynikov
1c03f2493f Correct itinerary class for VPADD 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100654 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:20:24 +00:00
Anton Korobeynikov
4ac0af851f VP{MAX, MIN} are of IIC_VSUBi4D itin class as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100653 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:20:18 +00:00
Anton Korobeynikov
f8b5c63617 VHADD differs from VHSUB at least on A9 - the former reads both operands in the second cycle, while the latter reads second operand in first cycle. Introduce new itin classes to catch this behavior. Whether this is true for A8 as well is WIP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100652 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:20:13 +00:00
Anton Korobeynikov
268b7446cf Some easy NEON scheduling goodness for A9 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100651 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:20:07 +00:00
Anton Korobeynikov
a31c6fb65e Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON ops. Define proper scheduling itinerary for them on A9. A8 TRM does not specify latency for them at all :( 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100650 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:20:02 +00:00
Anton Korobeynikov
63401e33cb FCONST{S,D} behaves the same way as FP unary instructions. This is true for both A8 and A9. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100649 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:19:56 +00:00
Anton Korobeynikov
bcc02d13bb Proper cycle times for locks, since wbck latency can be larger than fwd latency. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100648 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:19:51 +00:00
Anton Korobeynikov
c492e09455 Add new itin classes for FP16 <-> FP32 conversions and make uise of them for A9. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100647 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:19:46 +00:00
Anton Korobeynikov
391b3431e2 Make use of new reserved/required scheduling stuff: introduce VFP and NEON locks to model domain cross stalls precisly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100646 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:19:40 +00:00
Anton Korobeynikov
2eeeff8371 Some bits of A9 scheduling: VFP 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100643 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:19:18 +00:00
Anton Korobeynikov
035b23a0f4 Separate const from non-const stuff during mergeing 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100642 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:19:13 +00:00
Anton Korobeynikov
1e7b324fe5 Some initial version of global merger 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100641 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 18:19:07 +00:00
Sanjiv Gupta
d49baefaad Fix memory leaks for external symbol name strings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100601 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 03:36:01 +00:00
John McCall
b1fb4497b0 Clean up some signedness oddities in this code noticed by clang. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100599 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 01:49:15 +00:00
Dale Johannesen
343b42e428 Move printing of target-indepedent DEBUG_VALUE comments 
into AsmPrinter.  Target-dependent form is still generated
by FastISel and still handled in X86 code.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100596 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 01:15:14 +00:00
John McCall
795ee9dd1e Fix a number of clang -Wsign-compare warnings that didn't have an obvious 
solution.  The only reason these don't fire with gcc-4.2 is that gcc turns off
part of -Wsign-compare in C++ on accident.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100581 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-06 23:35:53 +00:00
Dale Johannesen
49d915bb9a Revert 100573, it's causing some testsuite problems. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100578 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-06 22:45:26 +00:00
Dale Johannesen
0a580d30e0 Move printing of DEBUG_VALUE comments to target-independent place. 
There is probably a more elegant way to do this.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100573 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-06 22:21:07 +00:00
Bob Wilson
d0910c4534 Expand SELECT and SELECT_CC for NEON vector types. 
Radar 7770501.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100568 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-06 22:02:24 +00:00
Jim Grosbach
fa85eb6237 Fix PR6696 and PR6663 
When a frame pointer is not otherwise required, and dynamic stack alignment
is necessary solely due to the spilling of a register with larger alignment
requirements than the default stack alignment, the frame pointer can be both
used as a general purpose register and a frame pointer. That goes poorly, for
obvious reasons. This patch brings back a bit of old logic for identifying
the use of such registers and conservatively reserves the frame pointer
during register allocation in such cases.

For now, implement for X86 only since it's 32-bit linux which is hitting this,
and we want a targeted fix for 2.7. As a follow-on, this will be expanded
to handle other targets, as theoretically the problem could arise elsewhere
as well.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100559 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-06 20:26:37 +00:00
Jakob Stoklund Olesen
8ba1c6ab87 Don't try to collapse DomainValues onto an incompatible SSE domain. 
This fixes the Bullet regression on i386/nocona.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100553 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-06 19:48:56 +00:00
Jakob Stoklund Olesen
fc8e1c3635 Properly enable load clustering. 
Operand 2 on a load instruction does not have to be a RegisterSDNode for this to
work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100497 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 23:48:02 +00:00
Evan Cheng
18ac410f4f Fix ADD32rr_alt instruction encoding bug. Patch by Marius Wachtler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100480 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 22:21:09 +00:00
Eric Christopher
b6290a170f Remove FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100466 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 21:14:32 +00:00
Chris Lattner
0333535054 don't use emitlabel in the arm asm printer yet, the order 
isn't well specified.  ARM really needs to have its instprinter
finished at some point.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100439 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 17:52:31 +00:00
Chris Lattner
0752cda4de fix a couple problems I introduced handling symbols 
with spaces in them.  Sym->getName()  !=   OS << *Sym




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100434 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 16:32:14 +00:00
Benjamin Kramer
75e818ad2f Disambiguate else. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100423 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 10:17:15 +00:00
Chris Lattner
ed3a8067a6 unthread MMI from FastISel 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100416 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 06:05:26 +00:00
Chris Lattner
a267b0076e remove the MMI pointer from MachineFrameInfo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100415 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 05:57:52 +00:00
Chris Lattner
66f20c8e82 simplify code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100412 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 05:48:36 +00:00
Johnny Chen
7fb053dd45 Get rid of traling whitespaces. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100404 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 04:51:50 +00:00
Johnny Chen
9d563b676c The disassembler impl. of MCDisassembler::getInstruction() was using the pattern 
uint32_t insn;
  MemoryObject.readBytes(Address, 4, (uint8_t*)&insn, NULL)

to read 4 bytes of memory contents into a 32-bit uint variable.  This leaves the
interpretation of byte order up to the host machine and causes PPC test cases of
arm-tests, neon-tests, and thumb-tests to fail.  Fixed to use a byte array for
reading the memory contents and shift the bytes into place for the 32-bit uint
variable in the ARM case and 16-bit halfword in the Thumb case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100403 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 04:46:17 +00:00
Chris Lattner
d7d44bd5a8 implement EmitFunctionEntryLabel to emit the .cc_top directive, 
allowing xcore to use the normal runOnMachineFunction 
implementation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100402 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 04:44:02 +00:00
Chris Lattner
0bcbe0e609 prune some #includes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100399 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 04:04:10 +00:00
Jakob Stoklund Olesen
fddb7667ca Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field. 
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.

This works well because TableGen resolves member references late:

class I : Instruction {
  AddrMode AM = AddrModeNone;
  let TSFlags{3-0} = AM.Value;
}

let AM = AddrMode4 in
def ADD : I;

TSFlags gets the expected bits from AddrMode4 in this example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100384 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 03:10:20 +00:00
Chris Lattner
d850ac79b5 fastisel doesn't need DwarfWriter, remove some tendricles. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100381 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 02:19:28 +00:00
Evan Cheng
cb86609421 Temporarily remove to disable building of ARM disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100380 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 01:57:50 +00:00
Evan Cheng
f6232cf8bb Re-apply 100265 but instead disable building of ARM disassembly for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100379 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 01:34:00 +00:00
Evan Cheng
1b0194d646 Reverting 100265 to try to get buildbots green again. Lots of self-hosting buildbots started complaining since this commit. Also xfail ARM disassembly tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100378 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 01:04:27 +00:00
Chris Lattner
90429c487f just have all targets create the DwarfWriter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100377 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 00:42:55 +00:00
Chris Lattner
8e680482c1 simplify various getAnalysisUsage implementations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100376 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 00:38:44 +00:00
Chris Lattner
3d22513611 eliminate the magic AbsoluteDebugSectionOffsets MAI hook, 
which is really a property of the section being referenced.
Add a predicate to MCSection to replace it.

Yay for reduction in magic.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100367 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 23:22:29 +00:00
Chris Lattner
1d20473c9d revert my patch, need to reconsider this and figure out what is really going on. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100358 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 21:49:31 +00:00
Chris Lattner
4166047030 fix pasto, this is the wrong setting for arm elf. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100357 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 21:37:20 +00:00
Jakob Stoklund Olesen
e0103f03f0 Clean up SSEDomainFix pass. 
Restrict bit mask operations to the DomainValue class. Rename methods for
clarity.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100353 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 21:27:26 +00:00
Chris Lattner
d290505f0f don't reset the default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100352 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 21:06:50 +00:00
Chris Lattner
3f53c8398d clean up the asmprinter header and privatize some stuff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100342 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 18:52:31 +00:00
Chris Lattner
9d1c1ada21 remove TargetMachine.h #include, also, TRI isn't used frequently 
enough to warrant caching in AsmPrinter, so remove it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100336 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 18:06:11 +00:00
Jakob Stoklund Olesen
bbef815a3b Switch SSEDomainFix to SpecificBumpPtrAllocator. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100332 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 18:00:21 +00:00
Chris Lattner
b23569aff0 Momentous day: remove the "O" member from AsmPrinter. Now all 
"asm printering" happens through MCStreamer.  This also 
Streamerizes PIC16 debug info, which escaped my attention.

This removes a leak from LLVMTargetMachine of the 'legacy'
output stream.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100327 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 08:18:47 +00:00
Chris Lattner
73ce0a63e6 mc'ize the remaining uses of O. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100322 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 07:23:00 +00:00
Chris Lattner
1841b34f53 finish eliminating uses of O. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100321 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 07:17:25 +00:00
Chris Lattner
2dc6fa67ee mcize more of ppc stub printing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100320 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 07:12:28 +00:00
Chris Lattner
9d7efd3081 mcize a bunch more stuff, using EmitRawText for things we 
don't have mcstreamer support for yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100319 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 07:05:53 +00:00
Chris Lattner
7ad07c4636 convert the non-MCInstPrinter'ized EmitInstruction 
implementations to use EmitRawText instead of writing
directly to "O".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100318 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 06:12:20 +00:00
Chris Lattner
f2777d7cd9 streamerize the rest of PIC16 asm printer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100317 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 05:53:03 +00:00
Chris Lattner
1ce3f565ef streamerize printing of dbg_value, the x86 backend is now fully 
streamerized for everything.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100316 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 05:40:34 +00:00
Chris Lattner
bfbab35653 split DEBUG_VALUE printing stuff out to its own method. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100315 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 05:38:19 +00:00
Chris Lattner
c82d9c4e5c mc'ize elf stub printing, convert cygwin stuff to EmitRawText, 
which will abort in .o file writing mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100314 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 05:35:04 +00:00
Chris Lattner
c75c028a15 fix PrintAsmOperand and PrintAsmMemoryOperand to pass down 
raw_ostream to print to.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100313 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 05:29:35 +00:00
Chris Lattner
e812d4c604 use predicates in DBG_VALUE printing code to simplify it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100312 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 05:21:31 +00:00
Chris Lattner
88db786712 remove more implicit uses of "O". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100311 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 05:19:20 +00:00
Chris Lattner
d374087be5 fix an ugly wart in the MCInstPrinter api where the 
raw_ostream to print an instruction to had to be specified
at MCInstPrinter construction time instead of being able
to pick at each call to printInstruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100307 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 05:04:31 +00:00
Chris Lattner
35c33bd772 change a ton of code to not implicitly use the "O" raw_ostream 
member of AsmPrinter.  Instead, pass it in explicitly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100306 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 04:47:45 +00:00
Mon P Wang
20adc9dc46 Reapply address space patch after fixing an issue in MemCopyOptimizer. 
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100304 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-04 03:10:48 +00:00
Chris Lattner
0c08d09204 asmstreamerize the .size directive for function bodies, force clients 
of printOffset to pass in a stream to print to.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100296 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-03 22:28:33 +00:00
Johnny Chen
7fed809484 Get rid of the middleman (ARMAlgorithm), which causes more trouble than the 
abstraction it brings.  And also get rid of the atexit() handler, it does not
belong in the lib directory. :-)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100265 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-03 04:10:56 +00:00
Johnny Chen
b7aaed83e2 Fix comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100259 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-03 01:17:30 +00:00
Johnny Chen
b35ae7f7d6 Register ARMAlgorithm::DoCleanup() to be called on exit to free the memory 
occuplied by the cached ARMAlgorithm objects.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100258 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-03 01:09:47 +00:00
Eric Christopher
b3500fd2f3 Rewrite aesimc handling. It only takes a single input and has a single 
dest.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100252 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-02 23:48:33 +00:00
Johnny Chen
a70261550e Fix another build warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100251 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-02 23:43:38 +00:00
Johnny Chen
b68a3ee82a Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen 
backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.

Reviewed by Chris Latter and Bob Wilson.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100233 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-02 22:27:38 +00:00
Sean Callanan
7626476733 Added support for reporting operand token ranges 
to the ARM AsmParser.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100232 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-02 22:27:05 +00:00
Eric Christopher
6d1cd1cd04 Separate out the AES-NI instructions from the SSE4.2 instructions. Add 
a new subtarget option for AES and check for the support.  Add "westmere"
line of processors and add AES-NI support to the core i7.

Add a couple of TODOs for information I couldn't verify.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100231 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-02 21:54:27 +00:00
Sean Callanan
a144c3f34d Fixes to the X86 disassembler. The disassembler will now 
return an error status in all failure cases, printing
messages to debugs() only when debugging is enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100229 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-02 21:23:51 +00:00
Chris Lattner
84e679beea rename NewDebugLoc -> DebugLoc, prune #includes in DebugLoc.h. 
This keeps around temporary typedef for clang/llvm-gcc so the
build won't break when I commit this :)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100218 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-02 20:21:22 +00:00
Chris Lattner
c7f3ace20c use DebugLoc default ctor instead of DebugLoc::getUnknownLoc() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100214 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-02 20:16:16 +00:00
Chris Lattner
de4845c163 Switch the code generator (except the JIT) onto the new DebugLoc 
representation.  This eliminates the 'DILocation' MDNodes for 
file/line/col tuples from -O0 -g codegen.

This remove the old DebugLoc class, making it a typedef for DebugLoc,
I'll rename NewDebugLoc next.

I didn't update the JIT to use the new apis, so it will continue to
work, but be as slow as before.  Someone should eventually do this
or, better yet, rip out the JIT debug info stuff and build the JIT
on top of MC.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100209 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-02 19:42:39 +00:00
Evan Cheng
f28f8bc40e Correctly lower memset / memcpy of undef. It should be a nop. PR6767. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100208 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-02 19:36:14 +00:00
Mon P Wang
e754d3fb85 Revert r100191 since it breaks objc in clang 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100199 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-02 18:43:02 +00:00
Mon P Wang
e33c848fa4 Reapply address space patch after fixing an issue in MemCopyOptimizer. 
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100191 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-02 18:04:15 +00:00
Eric Christopher
906af6f518 Remove FIXME - if there's a better way to do this it isn't here. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100176 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-02 04:32:37 +00:00
Dan Gohman
f860db2398 Revert the recent alignment changes. They're broken for -Os because, 
in particular, they end up aligning strings at 16-byte boundaries, and
there's no way for GlobalOpt to check OptForSize.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100172 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-02 03:04:37 +00:00
Dale Johannesen
93d6a7e9c2 Teach AnalyzeBranch, RemoveBranch and the branch 
folder to be tolerant of debug info following the
branch(es) at the end of a block.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100168 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-02 01:38:09 +00:00
Chandler Carruth
ae1d41c8ae Disambiguate conditional expression for newer GCCs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100167 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-02 01:31:24 +00:00
Dan Gohman
04d52f8435 Change variables which are exactly 16 bytes to be 16-byte-aligned too. 
This fixes test/Transforms/GlobalOpt/gv-align.ll.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100161 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-02 00:46:07 +00:00
Eric Christopher
1d8f83d0a0 Revert r100143. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100146 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-01 22:54:42 +00:00
Evan Cheng
3ea97550e3 In 64-bit mode, use i64 to lower memcpy / memset instead of f64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100137 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-01 20:27:45 +00:00
Evan Cheng
42642d06c9 Add comments about DstAlign and SrcAlign. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100132 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-01 20:10:42 +00:00
Evan Cheng
94107ba9ce - Avoid using floating point stores to implement memset unless the value is zero. 
- Do not try to infer GV alignment unless its type is sized. It's not possible to infer alignment if it has opaque type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100118 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-01 18:19:11 +00:00
Evan Cheng
255f20f7f7 Fix sdisel memcpy, memset, memmove lowering: 
1. Makes it possible to lower with floating point loads and stores.
2. Avoid unaligned loads / stores unless it's fast.
3. Fix some memcpy lowering logic bug related to when to optimize a
   load from constant string into a constant.
4. Adjust x86 memcpy lowering threshold to make it more sane.
5. Fix x86 target hook so it uses vector and floating point memory
   ops more effectively.
rdar://7774704


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100090 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-01 06:04:33 +00:00
Evan Cheng
48c58bb861 Nehalem unaligned memory access is fast. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100089 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-01 05:58:17 +00:00
Eric Christopher
ec306a9771 Add aeskeygenassist intrinsic and rename all of the aes intrinsics to 
aes instead of sse4.2.  Add a brief todo for a subtarget flag and rework
the aeskeygenassist instruction to more closely match the docs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100078 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-01 03:05:45 +00:00
Jim Grosbach
1118b5e490 vml[as] are slow on 1136jf-s also. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100066 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-01 00:13:43 +00:00
Chris Lattner
563d83ff53 reduce indentation, minor cleanups. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100042 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-31 20:32:51 +00:00
Jakob Stoklund Olesen
85ffee2c78 Use spaces, not tabs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100037 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-31 20:05:12 +00:00
Bill Wendling
d93bf04a07 Comment the changes for r98218 and friends inside the source code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100033 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-31 18:48:58 +00:00
Bill Wendling
5e1b55d672 Comment the changes for r98218 and friends inside the source code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100031 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-31 18:47:10 +00:00
Jakob Stoklund Olesen
5f282b5dfd Fix PR6750. Don't try to merge a DomainValue with itself. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100016 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-31 17:13:16 +00:00
Jakob Stoklund Olesen
d363b4ebc7 Replace V_SET0 with variants for each SSE execution domain. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99975 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-31 00:40:13 +00:00
Jakob Stoklund Olesen
b16df90b48 Fix typo. Thank you, valgrind. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99974 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-31 00:40:08 +00:00
Jakob Stoklund Olesen
bfcd61b907 Enable -sse-domain-fix by default. Now with tests! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99954 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-30 22:47:00 +00:00
Jakob Stoklund Olesen
428e152469 V_SETALLONES is an integer instruction. 
Since it is just a pxor in disguise, we should probably expand it to a full
polymorphic triple.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99953 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-30 22:46:55 +00:00
Jakob Stoklund Olesen
357be7f289 Renumber SSE execution domains for better code size. 
SSEDomainFix will collapse to the domain with the lower number when it has a
choice. The SSEPackedSingle domain often has smaller instructions, so prefer
that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99952 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-30 22:46:53 +00:00
Bob Wilson
100f090add Revert Mon Ping's change 99928, since it broke all the llvm-gcc buildbots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99948 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-30 22:27:04 +00:00
Jakob Stoklund Olesen
adffc9d20e Revert "Enable -sse-domain-fix by default. What could possibly go wrong?" 
Not running 'make check-all' before committing is a bad idea.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99933 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-30 21:36:32 +00:00
Jakob Stoklund Olesen
90b9df4e6f Enable -sse-domain-fix by default. What could possibly go wrong? 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99931 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-30 21:09:31 +00:00
Mon P Wang
808bab0169 Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset, 
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
A update of langref will occur in a subsequent checkin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99928 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-30 20:55:56 +00:00
Jakob Stoklund Olesen
1a5d2a8fa1 Add cross-block inference to SSEDomainFix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99916 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-30 20:04:01 +00:00
Eric Christopher
8258d0b4bf Remove the pmulld intrinsic and autoupdate it as a vector multiply. 
Rewrite the pmulld patterns, and make sure that they fold in loads of
arguments into the instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99910 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-30 18:49:01 +00:00
Chris Lattner
9b97a73ded Rip out the 'is temporary' nonsense from the MCContext interface to 
create symbols.  It is extremely error prone and a source of a lot
of the remaining integrated assembler bugs on x86-64.

This fixes rdar://7807601.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99902 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-30 18:10:53 +00:00
Benjamin Kramer
32e6518de3 XFAIL some PIC16 tests when running under valgrind-leaks. I don't expect these 
to be fixed any time soon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99888 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-30 14:34:13 +00:00
Benjamin Kramer
91b1d8fdbf PIC16: Plug a leak in PIC16Section by allocating name & address strings in the 
MCContext. There is still one leak left in PIC16Section (the Items vector).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99887 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-30 13:28:42 +00:00
Eric Christopher
4bd24c257e Add FIXME for operand promotion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99859 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-30 01:04:59 +00:00
Jakob Stoklund Olesen
d77f8181b4 Be gentle to MSVC. C++ is hard, after all. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99855 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-30 00:09:32 +00:00
Jakob Stoklund Olesen
e4b94b4efb Basic implementation of SSEDomainFix pass. 
Cross-block inference is primitive and wrong, but the pass is working otherwise.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99848 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-29 23:24:21 +00:00
Benjamin Kramer
34247a0f35 Make isInt?? and isUint?? template specializations of the generic versions. This 
makes calls a little bit more consistent and allows easy removal of the
specializations in the future. Convert all callers to the templated functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99838 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-29 21:13:41 +00:00
Eric Christopher
545d3b18d5 We'll never match these as instructions, just as intrinsics so remove 
the SDNodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99835 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-29 20:41:51 +00:00
Benjamin Kramer
7e09debcf1 Remove a bunch of integer width predicate functions in favor of MathExtras. 
Most of these were unused, some of them were wrong and unused (isS16Constant<short>,
isS10Constant<short>).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99827 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-29 19:07:58 +00:00
Chris Lattner
e27e02b1a4 From Kalle Raiskila: 
"the bigstack patch for SPU, with testcase. It is essentially the patch committed as 97091, and reverted as 97099, but with the following additions:
-in vararg handling, registers are marked to be live, to not confuse the register scavenger
-function prologue and epilogue are not emitted, if the stack size is 16. 16 means it is empty - there is only the register scavenger emergency spill slot, which is not used as there is no stack."



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99819 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-29 17:38:47 +00:00
Chris Lattner
f283e40b6a add a note. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99815 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-29 17:02:02 +00:00
Johnny Chen
79c4d820b4 Add NVTBLFrm to represent A8.6.406 VTBL, VTBX Vector Table Lookup Instructions. 
These instructions use byte index in a control vector (M:Vm) to lookup byte
values in a table and generate a new vector (D:Vd).  The table is specified via
a list of vectors, which can be:

{Dn}
{Dn D<n+1>}
{Dn D<n+1> D<n+2>}
{Dn D<n+1> D<n+2> D<n+3>}

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99789 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-29 01:14:22 +00:00
Chris Lattner
dc7500bbaf zap an extra line that Eli noticed! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99770 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-28 18:52:28 +00:00
Chris Lattner
263bd9abe2 fix a type contradition: XCoreISD::RETSP has one argument, not zero. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99760 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-28 08:47:39 +00:00
Chris Lattner
6269b6c9cb remove a pattern with no testcase that doesn't appear to be 
matchable: it seems like it would always constant fold.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99758 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-28 08:40:48 +00:00
Chris Lattner
0a00ed98f1 fix integer negates to use the proper type for the zero vectors, 
this also depends on the new "bitconvert dropping" behavior just
added to tblgen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99757 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-28 08:39:10 +00:00
Chris Lattner
e82f336d8f fix a typo, bitconvert from node to itself isn't valid. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99755 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-28 08:36:45 +00:00
Chris Lattner
b26fdcb48b fix vnot matching to explicitly specify the type of the 
input to be v8i8 or v16i8, which buildvectors get canonicalized to.

This allows the patterns that were previously using a bare 'vnot' to
match, before they couldn't.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99754 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-28 08:08:07 +00:00
Chris Lattner
e4c868ff6a fix up vnot matching, eliminating a dead pattern, correcting a couple of 
patterns that would never match because of bitcast, and eliminating use
of vnot_conv.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99753 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-28 08:00:23 +00:00
Chris Lattner
918472a77a stop using vnot_conv 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99750 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-28 07:48:17 +00:00
Chris Lattner
ed52c8f5f4 revert r99743, this is saying that the repmovs instructinos have an 
*input* of other type, which is the VT. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99749 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-28 07:38:39 +00:00
Chris Lattner
b616c6a25d remove a bunch of dead patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99748 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-28 07:38:00 +00:00
Chris Lattner
0b5d4908dd claiming to return other is pointless. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99743 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-28 05:57:36 +00:00
Chris Lattner
a591ff53d9 Improve systemz to model cmp and ucmp nodes as returning 
their flags correctly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99738 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-28 05:21:52 +00:00
Chris Lattner
af8752e901 the FPCmp node returns an i32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99737 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-28 05:12:57 +00:00
Chris Lattner
d486d77444 fix some modelling problems exposed by a patch I'm working on. bsr/bsf/ptest 
nodes all have an EFLAGS result when made by isel lowering.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99736 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-28 05:07:17 +00:00
Bob Wilson
2cd1a12fe0 Fix indentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99705 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-27 04:01:23 +00:00
Bob Wilson
10bc69c726 Add a format argument to the N3V and N3VX classes, removing the N3Vf class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99704 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-27 03:56:52 +00:00
Chris Lattner
baba4bb72f eliminate the last of the parallel's! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99700 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-27 02:47:14 +00:00
Johnny Chen
897dd0c588 Add NVMulSLFrm to represent "3-register multiply with scalar" operations and set 
it as the format for the appropriate N3V*SL*<> classes.  These instructions
require special handling of the M:Vm field which encodes the restricted Dm and
the lane index within Dm.

Examples are A8.6.325 VMLA, VMLAL, VMLS, VMLSL (by scalar):

	vmlal.s32	q3, d2, d10[0]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99690 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-27 01:03:13 +00:00
Chris Lattner
ec856800da eliminate almost all the rest of the x86-32 parallels. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99686 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-27 00:45:04 +00:00
Jim Grosbach
9ab0427015 Thumb2 storeFrom/LoadToStackSlot() need to handle tGPR regs directly, not pass 
through to the generic version. The generic functions use STR/LDR, but T2
needs the t2STR/t2LDR instead so we get the addressing mode correct.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99678 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-27 00:09:12 +00:00
Johnny Chen
9ee9d7d493 Remove the duplicate multiclass N3VSh_QHSD and use N3VInt_QHSD which is modified 
to now take a format argument.  N3VDInt<> and N3VQInt<> are modified to take a
format argument as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99676 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-26 23:49:07 +00:00
Johnny Chen
629c25cda6 Add NVExtFrm to represent NEON Vector Extract Instructions, that uses Inst{11-8} 
to encode the byte location of the extracted result in the concatenation of the
operands, from the least significant end.

Modify VEXTd and VEXTq classes to use the format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99659 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-26 22:28:56 +00:00
Johnny Chen
c6e704df8d Add N3RegVShFrm to represent 3-Register Vector Shift Instructions, which do not 
follow the N3RegFrm's operand order of D:Vd N:Vn M:Vm.  The operand order of
N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the first src operand).

Add a parent class N3Vf which requires passing a Format argument and which the
N3V class is modified to inherit from.  N3V class represents the "normal"
3-Register NEON Instructions with N3RegFrm.

Also add a multiclass N3VSh_QHSD to represent clusters of NEON 3-Register Shift
Instructions and replace 8 invocations with it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99655 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-26 21:26:28 +00:00
Jim Grosbach
9a52d0c352 vldm/vstm can only do up to 16 double-word registers at a time. 
Radar 7797856

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99630 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-26 18:41:09 +00:00
Johnny Chen
575c91cba7 Add N3RegFrm to represent "NEON 3 vector register format" instructions. 
Examples are VABA (Vector Absolute Difference and Accumulate), VABAL (Vector
Absolute Difference and Accumulate Long), and VABD (Vector Absolute Difference).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99628 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-26 18:32:20 +00:00
Evan Cheng
2c12cb47d9 Do not sibcall if stack needs to be dynamically aligned. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99620 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-26 16:26:03 +00:00
Evan Cheng
3c262eec53 Allow trivial sibcall of vararg callee when no arguments are being passed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99598 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-26 02:13:13 +00:00
Johnny Chen
0a3dc10eba Add N2RegVShLFrm and N2RegVShRFrm formats so that the disassembler can easily 
dispatch to the appropriate routines to handle the different interpretations of
the shift amount encoded in the imm6 field.  The Vd, Vm fields are interpreted
the same between the two, though.

See, for example, A8.6.367 VQSHL, VQSHLU (immediate) for N2RegVShLFrm format and
A8.6.368 VQSHRN, VQSHRUN for N2RegVShRFrm format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99590 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-26 01:07:59 +00:00
Jim Grosbach
7ec7a0e96b switch the flag for using NEON for SP floating point to a subtarget 'feature'. 
Re-commit. This time complete with testsuite updates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99570 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-25 23:47:34 +00:00
Jim Grosbach
78e496e165 need to fix 'make check' tests first. revert for a moment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99569 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-25 23:34:05 +00:00
Jim Grosbach
bd17bc96bf switch the flag for using NEON for SP floating point to a subtarget 'feature' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99568 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-25 23:32:19 +00:00
Johnny Chen
da9283cd57 Removed instruction class NI from ARMInstrFormats.td. 
It doesn't seem to be used anywhere.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99566 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-25 23:11:56 +00:00
Jim Grosbach
6b2e8dc9a0 switch the use-vml[as] instructions flag to a subtarget 'feature' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99565 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-25 23:11:16 +00:00
Johnny Chen
2d2898e6e9 Add NVDupLnFrm and change NVDupLane class to use that format. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99557 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-25 21:49:12 +00:00
Jim Grosbach
65cef00142 ARM cortex-a8 doesn't do vmla/vmls well. disable them by default for that cpu 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99549 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-25 20:48:50 +00:00
Johnny Chen
fa80bec349 Add NVCVTFrm (NEON Convert with fractional bits immediate) and modify N2VImm to 
expect a Format arg.  N2VCvtD/N2VCvtQ are modified to use the NVCVTFrm format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99548 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-25 20:39:04 +00:00
Daniel Dunbar
6307dd263f Fix -Asserts warning, again. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99542 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-25 19:35:53 +00:00
Jakob Stoklund Olesen
4a2a6e73d9 Tag SSE2 integer instructions as SSEPackedInt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99540 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-25 18:52:04 +00:00
Jakob Stoklund Olesen
70feca409e Teach TableGen to understand X.Y notation in the TSFlagsFields strings. 
Remove much horribleness from X86InstrFormats as a result. Similar
simplifications are probably possible for other targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99539 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-25 18:52:01 +00:00
Jakob Stoklund Olesen
352aa503fa Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings. 
On Nehalem and newer CPUs there is a 2 cycle latency penalty on using a register
in a different domain than where it was defined. Some instructions have
equvivalents for different domains, like por/orps/orpd.

The SSEDomainFix pass tries to minimize the number of domain crossings by
changing between equvivalent opcodes where possible.

This is a work in progress, in particular the pass doesn't do anything yet. SSE
instructions are tagged with their execution domain in TableGen using the last
two bits of TSFlags. Note that not all instructions are tagged correctly. Life
just isn't that simple.

The SSE execution domain issue is very similar to the ARM NEON/VFP pipeline
issue handled by NEONMoveFixPass. This pass may become target independent to
handle both.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99524 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-25 17:25:00 +00:00
Johnny Chen
e4614f7e84 Added a new instruction class NVDupLane to be inherited by VDUPLND and VDUPLNQ, 
instead of the current N2V.  Format of NVDupLane instances are set to NEONFrm
currently.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99518 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-25 17:01:27 +00:00
Bob Wilson
86afec7730 Reapply Kevin's change 94440, now that Chris has fixed the limitation on 
opcode values fitting in one byte (svn r99494).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99514 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-25 16:36:14 +00:00
Chris Lattner
589ad5d8c2 eliminate a bunch more parallels now that scheduling 
handles dead implicit results more aggressively.  More
to come, I think this is now just a data entry problem.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99486 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-25 05:44:01 +00:00
Evan Cheng
cb0f06e05c Disable folding loads into tail call in 32-bit PIC mode. It can introduce illegal code like this: 
addl    $12, %esp
        popl    %esi
        popl    %edi
        popl    %ebx
        popl    %ebp
        jmpl    *__Block_deallocator-L1$pb(%esi)  # TAILCALL

The problem is the global base register is assigned GR32 register class. TCRETURNmi needs the registers making up the address mode to have the GR32_TC register class.

The *proper* fix is for X86DAGToDAGISel::getGlobalBaseReg() to return a copy from the global base register of the machine function rather than returning the register itself. But that has the potential of causing it to be coalesced to a more restrictive register class: GR32_TC. It can introduce additional copies and spills. For something as important the PIC base, it's not worth it especially since this is not an issue on 64-bit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99455 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-25 00:10:31 +00:00
Bob Wilson
014dc4e720 Speculatively revert this to see if it fixes buildbot failures. 
--- Reverse-merging r99440 into '.':
U    test/MC/AsmParser/X86/x86_32-bit_cat.s
U    test/MC/AsmParser/X86/x86_32-encoding.s
U    include/llvm/IntrinsicsX86.td
U    include/llvm/CodeGen/SelectionDAGNodes.h
U    lib/Target/X86/X86InstrSSE.td
U    lib/Target/X86/X86ISelLowering.h


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99450 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-24 23:26:29 +00:00
Kevin Enderby
760c2f34d9 Added the Advanced Encryption Standard (AES) Instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99440 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-24 22:33:33 +00:00
Jim Grosbach
2676737e5e Make the use of the vmla and vmls VFP instructions controllable via cmd line. 
Preliminary testing shows significant performance wins by not using these
instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99436 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-24 22:31:46 +00:00
Kevin Enderby
044be39090 Fixed the SS42AI template for the SSE 4.2 instructions with TA prefix so it does 
not get an "Unknown immediate size" assert failure when used.  All instructions 
of this form have an 8-bit immediate.  Also added a test case of an example
instruction that is of this form.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99435 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-24 22:28:42 +00:00
Nate Begeman
1449f29100 Per chris's request, add some comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99434 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-24 22:19:06 +00:00
Johnny Chen
69631b1327 Trivial formating change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99428 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-24 21:25:07 +00:00
Nate Begeman
fdea31a463 BUILD_VECTOR was missing out on some prime opportunities to use SSE 4.1 inserts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99423 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-24 20:49:50 +00:00
Johnny Chen
2fadd6b221 Reverted r99326 which added NVdVmVCVTFrm, and later renamed to NVCVTFrm. 
NVCVTFrm will later be used to describe "vcvt with fractional bits".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99415 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-24 19:47:14 +00:00
Johnny Chen
7d85ac09f8 Reverted r99376. The disassembler will deal with the 2-reg format of these two 
N3VX instructions using special case code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99409 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-24 18:46:34 +00:00
Jim Grosbach
35075a7e81 tweak the arm if conversion heuristic 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99402 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-24 16:15:14 +00:00
Johnny Chen
b7ba5781e6 Mark VMOVDneon and VMOVQ as having the N2RegFrm form to help the disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99376 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-24 01:29:25 +00:00
Chris Lattner
c54a2f150d Switch INC8r to defining its pattern in terms of X86inc_flag 
and defining the add pattern with Pat<>, eliminating a use of
parallel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99375 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-24 01:02:12 +00:00