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834 Commits

Author SHA1 Message Date
Craig Topper
ec24e61ab0 Merge VPERM2F128/VPERM2I128 ISD node types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145485 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 07:47:51 +00:00
Craig Topper
316cd2a2c5 Merge decoding of VPERMILPD and VPERMILPS shuffle masks. Merge X86ISD node type for VPERMILPD/PS. Add instruction selection support for VINSERTI128/VEXTRACTI128. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145483 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 06:25:25 +00:00
Evan Cheng
a3438cf48b Add another missing pattern. llvm-gcc likes f64 but clang likes i64 so it was generating poor code for some SSE builtins. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145448 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 22:48:34 +00:00
Jakob Stoklund Olesen
0edd83bfff Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions. 
Like V_SET0, these instructions are expanded by ExpandPostRA to xorps /
vxorps so they can participate in execution domain swizzling.

This also makes the AVX variants redundant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145440 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 22:27:25 +00:00
Elena Demikhovsky
f68b214e2d Fixed vsqrt.ss intrinsic usage - order of input operands was wrong. 
Added a test.
Thanks Bruno for reviewing the patch.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145403 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 15:00:45 +00:00
Craig Topper
36e36ace77 Fix issues in shuffle decoding around VPERM* instructions. Fix shuffle decoding for VSHUFPS/D for 256-bit types. Add pattern matching for memory forms of VPERMILPS/VPERMILPD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145390 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 07:49:05 +00:00
Craig Topper
fe2a6c584a Fix VINSERTF128/VEXTRACTF128 to be marked as FP instructions. Allow execution dependency fix pass to convert them to their integer equivalents when AVX2 is enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145376 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 05:37:58 +00:00
Craig Topper
108126cfc6 Correctly mark VPERM2F128 as being an FP instruction and add execution domain fixing support to convert it to VPERM2I128 for AVX2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145370 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 03:57:34 +00:00
Evan Cheng
678cda052c Add missing avx pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145272 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-28 20:27:23 +00:00
Craig Topper
70b883b3a7 Add X86 instruction selection for VPERM2I128 when AVX2 is enabled. Merge VPERMILPS/VPERMILPD detection since they are pretty similar. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145238 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-28 10:14:51 +00:00
Craig Topper
38034c568c Merge 128-bit and 256-bit X86ISD node types for VPERMILPS and VPERMILPD. Simplify some shuffle lowering code since V1 can never be UNDEF due to canonalizing that occurs when shuffle nodes are created. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145153 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-26 22:55:48 +00:00
Craig Topper
06cb680779 Collapse X86ISD node types for PUNPCKH*, PUNPCKL*, UNPCKLP*, and UNPCKHP* to not be type specific. Now we just have integer high and low and floating point high and low. Pattern matching will choose the correct instruction based on the vector type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145148 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-26 20:47:44 +00:00
Craig Topper
705f2431a0 Remove 256-bit specific node types for UNPCKHPS/D and instead use the 128-bit versions and let the operand type disinquish. Also fix the load form of the v8i32 patterns for these to realize that the load would be promoted to v4i64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145126 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-24 22:57:10 +00:00
Craig Topper
f475a55bd4 Remove AVX2 specific X86ISD node types for PUNPCKH/L and instead just reuse the 128-bit versions and let the vector type distinguish. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145125 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-24 22:20:08 +00:00
Craig Topper
6fa583d787 Lowering for v32i8 to VPUNPCKLBW/VPUNPCKHBW when AVX2 is enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145028 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-21 08:26:50 +00:00
Craig Topper
6347e8662c Add support for lowering 256-bit shuffles to VPUNPCKL/H for i16, i32, i64 if AVX2 is enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145026 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-21 06:57:39 +00:00
Craig Topper
0d86d462f8 Add code for lowering v32i8 shifts by a splat to AVX2 immediate shift instructions. Remove 256-bit splat handling from LowerShift as it was already handled by PerformShiftCombine. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145005 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-20 00:12:05 +00:00
Craig Topper
745a86bac9 Use 256-bit vcmpeqd for creating an all ones vector when AVX2 is enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145004 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-19 22:34:59 +00:00
Craig Topper
ba798c5e51 Remove some of the special classes that worked around an old tablegen limitation of not being able to remove redundant bitconverts from patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145003 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-19 21:01:54 +00:00
Craig Topper
98fc72940b Custom lower AVX2 variable shift intrinsics to shl/srl/sra nodes and remove the intrinsic patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144999 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-19 17:46:46 +00:00
Craig Topper
54f952afac Synthesize SSSE3/AVX 128-bit horizontal integer add/sub instructions from add/sub of appropriate shuffle vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144989 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-19 09:02:40 +00:00
Craig Topper
3113384a34 Collapse X86 PSIGNB/PSIGNW/PSIGND node types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144988 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-19 07:33:10 +00:00
Craig Topper
1666cb6d63 Extend VPBLENDVB and VPSIGN lowering to work for AVX2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144987 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-19 07:07:26 +00:00
Craig Topper
60d9a9206e Remove unused parameters from the AVX maskmov classes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144985 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-19 04:49:22 +00:00
Nadav Rotem
cbbe33fde4 Add AVX2 vpbroadcast support 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144967 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-18 02:49:55 +00:00
Craig Topper
d90a191685 Fix SSE/AVX integer comparison patterns to understand that all integer vector loads are promoted to i64 vector loads so patterns need a bitconvert. Also slightly simplify the AVX2 variable shift patterns by using the predefined bitconvert pattern fragments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144896 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-17 07:49:38 +00:00
Craig Topper
ec43d1f553 Remove seemingly unnecessary duplicate VROUND definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144885 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-17 07:04:00 +00:00
Evan Cheng
2b89498979 Another missing X86ISD::MOVLPD pattern. rdar://10450317 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144839 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 22:24:44 +00:00
Craig Topper
12755b07ab Fix the execution domain on a bunch of SSE/AVX instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144784 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 07:30:46 +00:00
Evan Cheng
76c8f08567 Add a missing pattern for X86ISD::MOVLPD. rdar://10436044 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144566 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 20:35:52 +00:00
Craig Topper
3426a3efef Add neverHasSideEffects, mayLoad, and mayStore to many patternless SSE/AVX instructions. Remove MMX check from LowerVECTOR_SHUFFLE since MMX vector types won't go through it anyway. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144522 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 06:46:21 +00:00
Craig Topper
7be5dfd1a1 Add more AVX2 shift lowering support. Move AVX2 variable shift to use patterns instead of custom lowering code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144457 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 09:58:49 +00:00
Craig Topper
46154eb6fd Add lowering for AVX2 shift instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144380 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 07:39:23 +00:00
Nadav Rotem
4dbe96e22f AVX2: Add variable shift from memory. 
Note: These patterns only works in some cases because
many times the load sd node is bitcasted from a load
node of a different type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144266 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 06:54:20 +00:00
Nadav Rotem
c6c7e85a71 AVX2: Add patterns for variable shift operations 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144212 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 21:22:13 +00:00
Nadav Rotem
bb539bf973 Add AVX2 support for vselect of v32i8 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144187 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 13:21:28 +00:00
Craig Topper
0a15035f52 Add instruction selection for AVX2 integer comparisons. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144176 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 08:06:13 +00:00
Evan Cheng
7bc389b6b0 Add x86 isel logic and patterns to match movlps from clang generated IR for _mm_loadl_pi(). rdar://10134392, rdar://10050222 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144052 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 00:31:58 +00:00
Craig Topper
4c763ee613 Add AVX2 variable shift instructions and intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143915 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 08:26:24 +00:00
Craig Topper
28692044db Add AVX2 VPMOVMASK instructions and intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143904 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 03:20:35 +00:00
Craig Topper
69f5df7778 Add AVX2 VEXTRACTI128 and VINSERTI128 instructions. Fix VPERM2I128 to be qualified with HasAVX2 instead of HasAVX. Mark VINSERTF128 and VEXTRACTF128 as never having side effects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143902 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 02:00:04 +00:00
Craig Topper
c8eb880a7f More AVX2 instructions and their intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143895 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-06 23:04:08 +00:00
Craig Topper
27e5d0c72a Add more AVX2 instructions and intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143861 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-06 06:12:20 +00:00
Craig Topper
018262768f Add intrinsics for X86 vcvtps2ph and vcvtph2ps instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143683 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-04 06:59:49 +00:00
Craig Topper
98e0b9c86d Add new X86 AVX2 VBROADCAST instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143612 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-03 07:35:53 +00:00
Craig Topper
205e3378fd More AVX2 instructions and intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143536 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-02 06:54:17 +00:00
Craig Topper
3f2b2c218f Add a bunch more X86 AVX2 instructions and their corresponding intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143529 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-02 04:42:13 +00:00
Craig Topper
6b1c5fc02a Begin adding AVX2 instructions. No selection support yet other than intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143331 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-31 02:15:10 +00:00
Jakob Stoklund Olesen
0a951fba75 V_SET0 has no side effects. 
TableGen will mark any pattern-less instruction as having unmodeled side
effects. This is extra bad for V_SET0 which gets rematerialized a lot.

This was part of the cause for PR11125, but the real bug was fixed
in r141923.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141924 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-14 00:39:50 +00:00
Craig Topper
d501c714cd Add 'implicit EFLAGS' to patterns for popcnt and lzcnt 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141853 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-13 06:18:52 +00:00
Craig Topper
c48b301fb0 Add HasPOPCNT predicate to the POPCNT instructions. Also mark POPCNT as modifying EFLAGS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141656 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 07:13:09 +00:00
Craig Topper
227358e93c Make Ivy Bridge 16-bit floating point conversion instructions require AVX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141654 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 07:01:37 +00:00
Craig Topper
da394041c4 Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141505 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-09 07:31:39 +00:00
Craig Topper
6744a17dcf Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141065 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 06:30:42 +00:00
Craig Topper
581fe82c84 Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141007 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 17:28:23 +00:00
Jakob Stoklund Olesen
92fb79b7a6 Expand the x86 V_SET0* pseudos right after register allocation. 
This also makes it possible to reduce the number of pseudo instructions
and get rid of the encoding information.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140776 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-29 05:10:54 +00:00
Duncan Sands
04aa4aee89 Implement Chris's suggestion of legalizing the various SSE and AVX 
hadd/hsub intrinsics into the new fhadd/fhsub X86 node.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140383 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 16:10:22 +00:00
Duncan Sands
17470bee5f Synthesize SSE3/AVX 128 bit horizontal add/sub instructions from 
floating point add/sub of appropriate shuffle vectors.  Does not
synthesize the 256 bit AVX versions because they work differently.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140332 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 20:15:48 +00:00
Bruno Cardoso Lopes
f4b841d4e2 Revert r140097, working on a better approach 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140203 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 23:19:29 +00:00
Bruno Cardoso Lopes
448d986858 The wrong relocation was being emitted for several SSSE3 instructions. 
This fixes PR10963. Thanks to Benjamin for finding the wrong tablegen
declaration.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140184 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 21:39:21 +00:00
Bruno Cardoso Lopes
d91c6e058b Fix PR10949. Fix the encoding of VMOVPQIto64rr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140098 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:36:59 +00:00
Bruno Cardoso Lopes
97136c922e Based on the small opt Zvi's patch was trying to achieve, eliminate 
128-bit undef subvector insertion into a 256-bit vector

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140097 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:36:50 +00:00
Bruno Cardoso Lopes
97dc60b759 Match X86ISD::FSETCCsd and X86ISD::FSETCCss while in AVX mode. This fix 
PR10955 and PR10948.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140069 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 21:29:24 +00:00
Bruno Cardoso Lopes
2c693dc126 Describe more AVX 128-bit convert instructions without patterns to have 
mayLoad = 1

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139973 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 23:41:29 +00:00
Bruno Cardoso Lopes
7291272ab2 Add mayLoad attribute to AVX convert instructions, since non of them 
are declared with load patterns. This fix the crash in PR10941. No testcases,
since a fold is triggered and then converted back to the register form
afterwards.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139953 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 22:02:14 +00:00
Craig Topper
a08e255e1e Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND from being recognized by disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139691 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 06:41:26 +00:00
Bruno Cardoso Lopes
484ddf54c9 Teach the foldable tables about 128-bit AVX instructions and make the 
alignment check for 256-bit classes more strict. There're no testcases
but we catch more folding cases for AVX while running single and multi
sources in the llvm testsuite.

Since some 128-bit AVX instructions have different number of operands
than their SSE counterparts, they are placed in different tables.

256-bit AVX instructions should also be added in the table soon. And
there a few more 128-bit versions to handled, which should come in
the following commits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139687 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 02:36:58 +00:00
Nadav Rotem
dfb5935c76 swap vselect operand order - pr10907 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139630 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 19:56:38 +00:00
Bruno Cardoso Lopes
df24e1fb08 Add versions 256-bit versions of alignedstore and alignedload, to be 
more strict about the alignment checking. This was found by inspection
and I don't have any testcases so far, although the llvm testsuite runs
without any problem.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139625 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 19:33:03 +00:00
Craig Topper
58bbb81764 Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139588 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 06:54:58 +00:00
Craig Topper
6b0b2d6c41 Fix encoding of VMOVDQU to not simultaneously be 'TB OpSize' and 'XS'. 'XS' is correct and seems to have been taking priority. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139587 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 06:39:34 +00:00
Bruno Cardoso Lopes
5fc48100ee Fix PR10845. SUBREG_TO_REG shouldn't be used when the input and 
destination types are equal!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139553 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-12 22:59:23 +00:00
Bruno Cardoso Lopes
93474f5f7f Organize a bit the operand names for CMPPS and CMPPD 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139527 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-12 19:30:36 +00:00
Bruno Cardoso Lopes
cf355422d6 Realign BLEND patterns to match the general style for patterns in .td file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139526 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-12 19:30:33 +00:00
Bruno Cardoso Lopes
3445df77d4 Fix 80-columns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139525 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-12 19:30:29 +00:00
Nadav Rotem
5ed0983200 Format patterns, remove unused X86blend patterns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139491 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-12 08:41:50 +00:00
Craig Topper
136046c9a2 Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139486 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-11 23:19:54 +00:00
Nadav Rotem
fbad25e120 CR fixes per Bruno's request. 
Undo the changes from r139285 which added custom lowering to vselect.
Add tablegen lowering for vselect.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139479 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-11 15:02:23 +00:00
Nadav Rotem
8ffad56f8e Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139400 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 20:29:17 +00:00
Bruno Cardoso Lopes
7ec8fb8830 Add a AVX version of a simple i64 -> f64 bitcast. This could be 
triggered using llc with -O0, which wouldn't let it be folded and
expose the lack of this pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139320 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 21:52:33 +00:00
Bruno Cardoso Lopes
814c6ced85 Add AVX versions of blend vector operations and fix some issues noticed 
in Nadav's r139285 and r139287 commits.

1) Rename vsel.ll to a more descriptive name
2) Change the order of BLEND operands to "Op1, Op2, Cond", this is
necessary because PBLENDVB is already used in different places with
this order, and it was being emitted in the wrong way for vselect
3) Add AVX patterns and tests for the same SSE41 instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139305 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 18:05:08 +00:00
Bruno Cardoso Lopes
7db2d3a504 Fix PR10844: Add patterns to cover non foldable versions of X86vzmovl. 
Triggered using llc -O0. Also fix some SET0PS patterns to their AVX
forms and test it on the testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139304 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 18:05:02 +00:00
Nadav Rotem
ffe3e7da84 Add X86-SSE4 codegen support for vector-select. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139285 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 08:11:19 +00:00
Bruno Cardoso Lopes
2c84e96d3e Add AVX versions to match AESENC/AESDEC intrinsics. This hopefully ends 
the cycle of missing AVX counterparts of already present SSE* patterns

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139073 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-03 00:47:08 +00:00
Bruno Cardoso Lopes
9f63615b17 Add AVX version of a SSE4.1 VPBLENDVB pattern 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139072 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-03 00:47:05 +00:00
Bruno Cardoso Lopes
d01ef7d978 Add AVX versions of SSE4.1 EXTRACTPS patterns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139071 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-03 00:47:03 +00:00
Bruno Cardoso Lopes
2b0e0a42d1 Add AVX versions for SSE4.1 MOVZX* patterns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139070 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-03 00:47:01 +00:00
Bruno Cardoso Lopes
a67806530c Add one more AVX pattern for MOVZPQILo2PQI 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139069 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-03 00:46:58 +00:00
Bruno Cardoso Lopes
d29dd5ec9f Move PUNPCKLQDQ splat pattern close to the instruction definition and 
duplicate it for AVX mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139068 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-03 00:46:56 +00:00
Bruno Cardoso Lopes
914a2a319c Add AVX pattern versions for PSHUFB,PSIGN{B,W,D} 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139067 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-03 00:46:54 +00:00
Bruno Cardoso Lopes
a4ac989a1c Add AVX versions of MOVZDI2PDI patterns. Use SUBREG_TO_REG to indicate 
that the AVX versions (even the 128-bit ones) all clear the upper part
of the destination register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139066 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-03 00:46:51 +00:00
Bruno Cardoso Lopes
152a287374 Enforce subtarget checks in a few places to be explicit when the 
pattern should be matched

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139065 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-03 00:46:49 +00:00
Bruno Cardoso Lopes
5ab6dcc4bb Tidy up code moving patterns to their appropriate place! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139064 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-03 00:46:47 +00:00
Bruno Cardoso Lopes
0e59a04849 Add AVX versions of FsMOVAPS and FsMOVAPS. Teach X86InstrInfo how to use 
it!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139063 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-03 00:46:45 +00:00
Bruno Cardoso Lopes
1aab5515f6 Fix 80-column and style 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139061 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-03 00:46:40 +00:00
Bruno Cardoso Lopes
e4ccf8a86c Tidy up some SSE/AVX convert intrinsics. Also add an AVX version of 
OptForSize pattern

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139060 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-03 00:46:38 +00:00
Bruno Cardoso Lopes
fc7bc5889b Move more code around and duplicate AVX patterns: MOVHPS and MOVLPS 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138897 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 21:15:32 +00:00
Bruno Cardoso Lopes
06c982d0e0 Move MOVAPS,MOVUPS patterns close to the instructions definition 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138896 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 21:15:29 +00:00
Bruno Cardoso Lopes
453f4954f2 Remove "_Int" forms of MOVUPSmr and MOVAPSmr 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138895 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 21:15:22 +00:00
Bruno Cardoso Lopes
57d6a5e491 - Move all MOVSS and MOVSD patterns close to their definitions 
- Duplicate some store patterns to their AVX forms!
- Catched a bug while restricting the patterns subtarget, fix it
  and update a testcase to check it properly

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138851 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 03:04:20 +00:00