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564 Commits

Author SHA1 Message Date
David Blaikie
2dd674fdce Removing unused default switch cases in switches over enums that already account for all enumeration values explicitly. 
(This time I believe I've checked all the -Wreturn-type warnings from GCC & added the couple of llvm_unreachables necessary to silence them. If I've missed any, I'll happily fix them as soon as I know about them)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148262 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-16 23:24:27 +00:00
Matt Beaumont-Gay
19055cc271 Fix malformed assert. 
If anybody has strong feelings about 'default: assert(0 && "blah")' vs
'default: llvm_unreachable("blah")', feel free to regularize the instances of
each in this file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147459 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-03 19:03:59 +00:00
Jim Grosbach
4050bc4cab ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point). 
rdar://10558523

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147189 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 22:19:05 +00:00
Jim Grosbach
21bcca81f4 Tidy up. Use predicate function a bit more liberally. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147184 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 22:02:35 +00:00
Jim Grosbach
1aa149f5ac ARM pre-UAL aliases. fcmp[sd]. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147158 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 19:20:45 +00:00
Jim Grosbach
8d9550bde9 ARM assembler should accept shift-by-zero for any shifted-immediate operand. 
Just treat it as-if the shift wasn't there at all. 'as' compatibility.

rdar://10604767

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147153 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 18:04:04 +00:00
Jim Grosbach
de626ad872 ARM assembly parser canonicallize on 'lsl' for shift-by-zero form. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147152 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 17:37:00 +00:00
Jim Grosbach
18c8d12dea Tidy up. Trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147151 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 17:17:10 +00:00
Jim Grosbach
f1a88fc474 Nuke invalid comment from copy/paste. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147150 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 17:04:50 +00:00
Jim Grosbach
de4d83943a ARM asm parser should be more lenient w/ .thumb_func directive. 
Rather than require the symbol to be explicitly an argument of the directive,
allow it to look ahead and grab the symbol from the next non-whitespace
line.

rdar://10611140

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147100 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 22:30:16 +00:00
Jim Grosbach
520dc78d92 Thumb2 assembly parsing of 'mov rd, rn, rrx'. 
Maps to the RRX instruction. Missed this case earlier.

rdar://10615373

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147096 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 21:04:19 +00:00
Jim Grosbach
2cc5cda464 Thumb2 assembly parsing of 'mov(register shifted register)' aliases. 
These map to the ASR, LSR, LSL, ROR instruction definitions.

rdar://10615373

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147094 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 20:54:00 +00:00
Jim Grosbach
c931325d99 ARM assembly parsing allows constant expressions for lane indices. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147028 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 01:19:23 +00:00
Jim Grosbach
3471d4fbbd ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147025 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 00:38:54 +00:00
Jim Grosbach
aee718beac ARM .req register name aliases are case insensitive, just like regnames. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147009 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:11:00 +00:00
Jim Grosbach
3cbe43fe69 Move comment to appropriate place. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147000 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:26:38 +00:00
Jim Grosbach
5b484312c6 ARM assembly parsing and encoding for VST2 single-element, double spaced. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146990 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 20:46:29 +00:00
Jim Grosbach
95fad1c603 ARM assembly parsing and encoding for VLD2 single-element, double spaced. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146983 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 19:21:26 +00:00
Jason W Kim
d7c9e08b6b First steps in ARM AsmParser support for .eabi_attribute and .arch 
(Both used for Linux gnueabi)
No behavioral change yet (no tests need so far)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146977 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 17:38:12 +00:00
Jim Grosbach
04b5d93250 ARM assembly shifts by zero should be plain 'mov' instructions. 
"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.

rdar://10604663

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146937 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 00:59:38 +00:00
Jim Grosbach
9b0878512f ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates. 
e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117"

rdar://10603913

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146925 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 23:51:07 +00:00
Jim Grosbach
2f196747f1 ARM assembly parsing and encoding support for LDRD(label). 
rdar://9932658

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146921 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 23:06:24 +00:00
Jim Grosbach
6849019079 ARM VFP pre-UAL mnemonic aliases for fmul[sd]. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146892 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 19:43:50 +00:00
Jim Grosbach
9c39789c36 ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd]. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146887 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 19:02:41 +00:00
Jim Grosbach
eeaf1c1636 ARM NEON relax parse time diagnostics for alignment specifiers. 
There's more variation that we need to handle. Error checking will need
to be on operand predicates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146884 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 18:31:43 +00:00
Jim Grosbach
276ed0344c Silence warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146686 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 21:54:55 +00:00
Jim Grosbach
0aaf4cd9b3 ARM NEON two-register double spaced register list parsing support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146685 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 21:44:33 +00:00
Jim Grosbach
799ca9d1b7 ARM NEON better assembly operand range checking for lane indices of VLD/VST. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146608 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 23:35:06 +00:00
Jim Grosbach
9b1b390288 ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146605 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 23:25:46 +00:00
Jim Grosbach
a39cda7aff ARM assembler support for the target-specific .req directive. 
rdar://10549683


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146543 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 02:16:11 +00:00
Jim Grosbach
863d2af947 Thumb2 assembler aliases for "mov(shifted register)" 
rdar://10549767


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146520 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 22:45:11 +00:00
Jim Grosbach
27debd60a1 ARM LDM/STM system instruction variants. 
rdar://10550269

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146519 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 21:48:29 +00:00
Jim Grosbach
d7ea73a490 Thumb2 tweak for ccout handling in RSB parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146516 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 21:06:41 +00:00
Jim Grosbach
55b02f28c1 ARM thumb2 parsing of "rsb rd, rn, #0". 
rdar://10549741


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146515 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 20:50:38 +00:00
Jim Grosbach
f10154010e ARM add some more pre-UAL VFP mnemonics for convenience when porting old code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146508 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 20:13:48 +00:00
Daniel Dunbar
4ab406d7fc LLVMBuild: Remove trailing newline, which irked me. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146409 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-12 19:48:00 +00:00
Jim Grosbach
48171e7fbe ARM add some more pre-UAL VFP mnemonics for convenience when porting old code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146300 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-10 00:01:02 +00:00
Jim Grosbach
21d7fb814a ARM add some pre-UAL VFP mnemonics for convenience when porting old code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146296 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-09 23:34:09 +00:00
Jim Grosbach
8a12e3b5df ARM allows '' syntax, not just '#imm' for assembly. 
Backwards compatibility with 'gas'. #imm is the preferered and documented
syntax, but lots of existing code uses the '$' prefix, so we should
support it if we can.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146285 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-09 22:25:03 +00:00
Jim Grosbach
976c0da213 ARM convenience aliases for VSQRT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146201 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 22:51:25 +00:00
Jim Grosbach
6b044c2609 ARM VSHR implied destination operand form aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146192 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 22:06:06 +00:00
Jim Grosbach
a62d11ea94 ARM asm parser, just issue a warning for a duplicate reg in a list. 
For better 'gas' compatibility.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146185 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 21:34:20 +00:00
Jim Grosbach
40e2855547 ARM assembler support for register name aliases. 
rdar://10550084

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146170 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 19:27:38 +00:00
Jim Grosbach
730fe6c1b6 ARM NEON two-operand aliases for VSHL(immediate). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146125 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 01:30:04 +00:00
Jim Grosbach
8254f02231 ARM VFP support 'fmrs/fmsr' aliases for 'vldr' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146116 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:52:55 +00:00
Jim Grosbach
67ca1adf82 ARM VFP support 'flds/fldd' aliases for 'vldr' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146115 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:49:29 +00:00
Jim Grosbach
3bc8a3d3af ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146111 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:31:07 +00:00
Jim Grosbach
af4edea67b ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands. 
For 'gas' compatibility.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146106 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 23:40:58 +00:00
Jim Grosbach
9a70df99ca ARM support the .arm and .thumb directives for assembly mode switching. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146042 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 18:04:19 +00:00
Jim Grosbach
3b8991cc98 ARM: NEON SHLL instruction immediate operand range checking. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146003 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 01:07:24 +00:00
Jim Grosbach
df33e0d05e Thumb2 encoding choice correction for PLD. 
Using encoding T1 for offset of #0 and encoding T2 for #-0.

rdar://10532413

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145919 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 04:49:29 +00:00
Jim Grosbach
713c70238c Tweak ADDrr fix. Bad check for explicit .w 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145863 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 22:27:04 +00:00
Jim Grosbach
927b9df4c6 Thumb2 prefer ADD register encoding T2 to T3 when possible. 
rdar://10529664


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145860 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 22:16:39 +00:00
Jim Grosbach
da84786bee Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions. 
rdar://10529348


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145851 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 21:06:26 +00:00
Jim Grosbach
587f5062b9 ARM NEON VEXT aliases for data type suffices. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145726 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 23:34:39 +00:00
Jim Grosbach
84defb51ca ARM VST1 single lane assembly parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145718 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 22:34:51 +00:00
Jim Grosbach
872eedbb3a ARM VLD1 single lane assembly parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145712 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 22:01:52 +00:00
Jim Grosbach
dad2f8e7fb Clean up aliases for ARM VLD1 single-lane assembly parsing a bit. 
Add the 16-bit lane variants while I'm at it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145693 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 18:52:30 +00:00
Jim Grosbach
7636bf6530 ARM start parsing VLD1 single lane instructions. 
The alias pseudos need cleaned up for size suffix handling, but this gets
the basics working. Will be cleaning up and adding more.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145655 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 00:35:16 +00:00
Jim Grosbach
13af222bab ARM parsing for VLD1 two register all lanes, no writeback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145504 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 18:21:25 +00:00
Jim Grosbach
98b05a57b6 ARM parsing aliases for VLD1 single register all lanes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145464 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 01:09:44 +00:00
Jim Grosbach
6029b6ddaf Tidy up a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145458 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 23:51:09 +00:00
Daniel Dunbar
d782bae970 build/CMake: Finish removal of add_llvm_library_dependencies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145420 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 19:25:30 +00:00
Jim Grosbach
efed3d1f58 Clean up debug printing of ARM shifted operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144836 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 21:46:50 +00:00
Jim Grosbach
48b368bcd5 ARM assembly parsing for RRX mnemonic. 
rdar://9704684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144812 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 19:05:59 +00:00
Jim Grosbach
23f220705a ARM mode aliases for bitwise instructions w/ register operands. 
rdar://9704684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144803 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 18:31:45 +00:00
Jim Grosbach
e43862b6a6 ARM assembly parsing for register range syntax for VLD/VST register lists. 
For example,
vld1.f64 {d2-d5}, [r2,:128]!

Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!

It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.

rdar://10451128


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144727 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 23:19:15 +00:00
Jim Grosbach
6cb4b08182 ARM accept an immediate offset in memory operands w/o the '#'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144709 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 22:14:41 +00:00
Jim Grosbach
5c984e451d ARM enclosing curly braces optional on one-register VLD/VST instruction lists. 
'vld1.f32 d4, [r7]' should be parsed as equivalent to 'vld1.f32 {d4}, [r7]'

rdar://10450488.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144701 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 21:45:55 +00:00
Jim Grosbach
25e0a87e91 Fix typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144695 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 21:01:30 +00:00
Jim Grosbach
7f1ec9570d Thumb2 two-operand 'mul' instruction wide encoding parsing. 
rdar://10449724

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144684 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 19:55:16 +00:00
Jim Grosbach
1de0bd1945 Thumb2 assembly parsing for mul.w in IT block fix. 
When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.

rdar://10449281

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144679 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 19:29:45 +00:00
Jim Grosbach
430052b084 Tidy up. 80 column. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144538 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 17:52:47 +00:00
Jim Grosbach
9588c10b69 ARM refactor simple immediate asm operand render methods. 
These immediate operands all use the same simple logic for rendering to
MCInst, so have them share the method for doing so.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144439 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 00:58:43 +00:00
Jim Grosbach
7aef99b677 ARM vldm and vstm VFP instructions can take a data type suffix. 
It's ignored by the assembler when present, but is legal syntax. Other
instructions have something similar, but for some mnemonics it's
only sometimes not significant, so this quick check in the parser will
need refactored into something more robust soon-ish. This gets some
basics working in the meantime.

Partial for rdar://10435264

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144422 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 23:08:10 +00:00
Jim Grosbach
c3937b97c0 Nuke no longer accurate comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144411 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 22:30:06 +00:00
Jim Grosbach
ce485e7f70 ARM allow Q registers in vldm/vstm register lists. 
rdar://9672822

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144407 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 21:27:40 +00:00
Jim Grosbach
0352b4679e Thumb2 ldm/stm updating w/ one register in the list are LDR/STR. 
rdar://10429490

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144338 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 23:58:34 +00:00
Jim Grosbach
83ec87755e ARM let processInstruction() tranforms chain. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144337 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 23:42:14 +00:00
Jim Grosbach
5402637ff2 Thumb2 parsing for push/pop w/ hi registers in the reglist. 
rdar://10130228.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144331 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 23:17:11 +00:00
Jim Grosbach
fae02597bb Thumb1 diagnostics for reglist on PUSH/POP fix. 
Was not checking the first register in the register list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144329 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 23:01:27 +00:00
Jim Grosbach
1b332860ae Thumb MUL assembly parsing for 3-operand form. 
Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.

rdar://10428630

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144322 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 22:10:12 +00:00
Jim Grosbach
d475f8612b ARM .thumb_func directive for quoted symbol names. 
Use the getIdentifier() method of the token, not getString(), otherwise
we keep the quotes as part of the symbol name, which we don't want.

rdar://10428015

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144315 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 20:48:53 +00:00
Jim Grosbach
ee10ff89a2 ARM assembly parsing for LSR/LSL/ROR(immediate). 
More of rdar://9704684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144301 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 19:18:01 +00:00
Jim Grosbach
71810ab7c0 ARM assembly parsing for ASR(immediate). 
Start of rdar://9704684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144293 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 16:44:55 +00:00
Benjamin Kramer
5908536673 Replace (Lower|Upper)caseString in favor of StringRef's newest methods. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143891 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-06 20:37:06 +00:00
Daniel Dunbar
a3a2dfd4a2 build: Add initial cut at LLVMBuild.txt files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143634 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-03 18:53:17 +00:00
Jim Grosbach
6284afc293 ARM label operands can be quoted. 
For example, labels from Objective-C sources.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143511 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-01 22:38:31 +00:00
Jim Grosbach
ed6a0c5243 ARM label operands can have an optional '#' before them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143510 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-01 22:37:37 +00:00
Jim Grosbach
681460f954 ARM VLD/VST assembly parsing for symbolic address operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143413 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-01 01:24:45 +00:00
Jim Grosbach
4334e03252 ARM VST1 w/ writeback assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143369 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-31 21:50:31 +00:00
Jim Grosbach
e70ec84637 ARM mode 'mov' to 'mvn' assembler alias. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143237 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 22:50:54 +00:00
Jim Grosbach
89a6337085 Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm". 
When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example,
  mov r2, #-3
becomes
  mvn r2, #2

rdar://10349224


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143235 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 22:36:30 +00:00
Jim Grosbach
c73d73eb88 ARM Allow 'q' registers in VLD/VST vector lists. 
Just treat it as if the constituent D registers where specified.

rdar://10348896

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143167 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 00:06:50 +00:00
Jim Grosbach
a581328ceb Thumb2 ldr pc-relative encoding fixes. 
We were parsing label references to the i12 encoding, which isn't right.
They need to go to the pci variant instead.

More of rdar://10348687

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143068 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-26 22:22:01 +00:00
Jim Grosbach
758a519a22 ARM parse parenthesized expressions for label references. 
Partial fix for rdar://10348687.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143063 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-26 21:14:08 +00:00
Jim Grosbach
12431329d6 ARM assembly parsing and encoding for VLD1 w/ writeback. 
One and two length register list variants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142861 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-24 22:16:58 +00:00
Benjamin Kramer
1a2f9886a2 Move various generated tables into read-only memory, fixing up const correctness along the way. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142726 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-22 16:50:00 +00:00
Jim Grosbach
4661d4cac3 Assembly parsing for 2-register sequential variant of VLD2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142691 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 22:21:10 +00:00
Jim Grosbach
b6310316db Assembly parsing for 4-register variant of VLD1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142682 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 20:35:01 +00:00
Jim Grosbach
cdcfa28056 Assembly parsing for 3-register variant of VLD1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142675 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 20:02:19 +00:00
Jim Grosbach
280dfad489 ARM VLD parsing and encoding. 
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.

Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142670 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 18:54:25 +00:00
Owen Anderson
7784f1d2d8 Don't automatically set the "fc" bits on MSR instructions if the user didn't ask for them. This is a divergence from gas' behavior, but it is correct per the documentation and allows us to forge ahead with roundtrip testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142669 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 18:43:28 +00:00
Jim Grosbach
7926db8268 Nuke an #if0 that got accidentally left in. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142658 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 16:59:08 +00:00
Jim Grosbach
862019c37f ARM VTBL (one register) assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142441 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 23:02:30 +00:00
Jim Grosbach
f2f5bc60f6 ARM assembly parsing and encoding for VMOV.i64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142356 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 16:18:11 +00:00
Jim Grosbach
6248a546f2 ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142321 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 00:22:00 +00:00
Jim Grosbach
ea46110f57 ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142303 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 23:09:09 +00:00
Jim Grosbach
fa1ee88052 Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142297 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 22:41:42 +00:00
Jim Grosbach
0e387b2877 ARM NEON "vmov.i8" immediate assembly parsing and encoding. 
NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142293 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 22:26:03 +00:00
Chad Rosier
c378015d1c Removed set, but unused variables. 
Patch by Joe Abbey <jabbey@arxan.com>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142223 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 18:48:30 +00:00
Jim Grosbach
c66e7afcf2 Thumb2 assembly parsing and encoding for LDC/STC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141811 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 20:54:17 +00:00
Jim Grosbach
9b8f2a0b36 ARM parsing and encoding for the <option> form of LDC/STC instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141786 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 17:34:41 +00:00
Jim Grosbach
2bd0118472 ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. 
Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141721 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 21:55:36 +00:00
Jim Grosbach
57dcb85a30 ARM parse alignment specifier for NEON load/store instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141682 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 17:29:55 +00:00
Jim Grosbach
e53c87b302 ARM Rename operand sub-structure 'Mem' to 'Memory' for a bit more clarity. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141671 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 15:59:20 +00:00
Jim Grosbach
f6c35c59f5 Simplify operand Kind checks a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141592 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 23:06:42 +00:00
Jim Grosbach
460a90540b ARM NEON assembly parsing and encoding for VDUP(scalar). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141446 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 23:56:00 +00:00
Jim Grosbach
21ff17ce1b ARM prefix asmparser operand kind enums for readability. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141438 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 23:24:09 +00:00
Jim Grosbach
186ffac4d3 Improve ARM assembly parser diagnostic for unexpected tokens. 
Consider:
  mov r8, r11 fred

Previously, we issued the not very informative:
x.s:6:1: error: unexpected token in argument list

^

Now we generate:
x.s:5:14: error: unexpected token in argument list
  mov r8, r11 fred
              ^


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141380 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 18:27:04 +00:00
Owen Anderson
2dbb46a0a0 Support a valid, but not very useful, encoding of CPSIE where none of the AIF bits are set. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141190 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 17:16:40 +00:00
Jim Grosbach
9d39036f62 ARM assembly parsing and encoding for VMOV immediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141046 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 23:38:36 +00:00
Jim Grosbach
68259145d9 ARM parsing/encoding for VCMP/VCMPE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141038 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 22:30:24 +00:00
Jim Grosbach
5cd5ac6ad4 ARM assembly parsing and encoding for VMRS/FMSTAT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141025 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:12:43 +00:00
James Molloy
acad68da50 Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. 
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.

Add decoder and disassembler tests.

Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-28 14:21:38 +00:00
Owen Anderson
0afa0094af ASR #32 is not allowed on Thumb2 USAT and SSAT instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140560 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 21:06:22 +00:00
Owen Anderson
4d2a00147d Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset of #-0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140426 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 22:25:02 +00:00
Jim Grosbach
50f1c37123 Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140125 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 00:46:54 +00:00
Jim Grosbach
d5d0e81a4b Thumb2 assembly parsing and encoding for UMAAL/UMLAL/UMULL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140095 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:31:02 +00:00
Jim Grosbach
7f739bee26 Thumb2 assembly parsing and encoding for TBB/TBH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140078 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 22:21:13 +00:00
Jim Grosbach
326efe5891 Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140047 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 20:29:33 +00:00
Jim Grosbach
fb12f35545 ARM asm parsing should handle pre-indexed writeback w/o immediate. 
For example, 'ldrb r9, [sp]!' is odd, but valid.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140035 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 18:42:21 +00:00
Jim Grosbach
f67e8554bf Thumb2 assembly parsing and encoding for SUB(immediate). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139966 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 22:58:42 +00:00
Jim Grosbach
ee2c2a4f98 Thumb2 assembly parsing and encoding for STR. 
More addressing mode encoding bits. Handle pre increment for STR/STRB/STRH
and STR(register).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139949 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 21:55:56 +00:00
Jim Grosbach
8213c96655 Thumb2 assembly parsing and encoding for STMIA. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139938 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 20:50:13 +00:00
Jim Grosbach
3443ed525a Thumb2 assembly parsing and encoding for SMMULL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139921 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 18:05:48 +00:00
Jim Grosbach
db7e2e59dd Kill some dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139904 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 16:45:40 +00:00
Jim Grosbach
fb9cffea4a Tidy up a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139903 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 16:39:25 +00:00
Jim Grosbach
837fc5e9d5 Thumb2 assembly parsing and encoding for SMLAL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139902 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 16:38:00 +00:00
Owen Anderson
8adf62034a Fix a crasher in Thumb2 MOV-immediate encoding for certain inputs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139747 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 22:46:14 +00:00
Jim Grosbach
64944f48a1 Thumb2 assembly parsing and encoding for MUL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139735 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 21:00:40 +00:00
Jim Grosbach
bf841cf336 Thumb2 assembly parsing and encoding for MSR/MRS. 
Fix a bug in handling default flags for both ARM and Thumb encodings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139721 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 20:03:46 +00:00
Jim Grosbach
c2d3164ab4 Thumb2 assembly parsing for MOV in IT block. 
Select the right 16 vs. 32 bit encoding in an IT block.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139714 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 19:12:11 +00:00
Jim Grosbach
d0588e2a2e ARM fix assembly parser handling of ranges in register lists. 
Clean up register list handling in general a bit to explicitly check things
like all the registers being from the same register class.

rdar://8883573


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139707 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 18:08:35 +00:00
Jim Grosbach
d300b94e51 Remove unnecessary scope resolution operator. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139656 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 22:56:44 +00:00
Jim Grosbach
d7a2b3bea8 There's only 16 regs legal in a register list. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139637 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 20:35:57 +00:00
Owen Anderson
b6b7f515e2 Teach the Thumb ASM parser that BKPT is allowed in IT blocks, even though it is always executed unconditionally. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139610 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 17:59:19 +00:00
Jim Grosbach
2d539691a1 Tidy up a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139559 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-12 23:36:42 +00:00
Jim Grosbach
1ad60c2adc Thumb2 parsing and encoding for MOV(immediate). 
Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139440 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-10 00:15:36 +00:00
Owen Anderson
51f6a7abf2 Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139415 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 21:48:23 +00:00