Kevin Enderby
b80d571ea8
Updated the llvm-mc disassembler C API to support for the X86 target.
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rdar://10873652
As part of this I updated the llvm-mc disassembler C API to always call the
SymbolLookUp call back even if there is no getOpInfo call back. If there is a
getOpInfo call back that is tried first and then if that gets no information
then the SymbolLookUp is called. I also made the code more robust by
memset(3)'ing to zero the LLVMOpInfo1 struct before then setting
SymbolicOp.Value before for the call to getOpInfo. And also don't use any
values from the LLVMOpInfo1 struct if getOpInfo returns 0. And also don't
use any of the ReferenceType or ReferenceName values from SymbolLookUp if it
returns NULL. rdar://10873563 and rdar://10873683
For the X86 target also fixed bugs so the annotations get printed.
Also fixed a few places in the ARM target that was not producing symbolic
operands for some instructions. rdar://10878166
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151267 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 18:18:17 +00:00
Michael J. Spencer
c9c137b463
Properly emit _fltused with FastISel. Refactor to share code with SDAG.
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Patch by Joe Groff!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151183 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-22 19:06:13 +00:00
Chad Rosier
90f20044ad
Remove extra semi-colons.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151169 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-22 17:25:00 +00:00
Craig Topper
c528e462a1
Declare register classes as const. Fix a couple pointers to register classes that weren't already const.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151138 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-22 07:28:11 +00:00
Craig Topper
44d23825d6
Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151134 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-22 05:59:10 +00:00
Aaron Ballman
57708abb10
Adding support for Microsoft's thiscall calling convention. LLVM side of the patch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151123 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-22 03:04:40 +00:00
Ahmed Charles
b0934ab7d8
Remove dead code. Improve llvm_unreachable text. Simplify some control flow.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150918 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-19 11:37:01 +00:00
Craig Topper
1bf724b28b
Remove some unneeded includes and fix ordering in X86ISelLowering.cpp. Remove unneeded 'using namespace'.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150916 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-19 07:15:48 +00:00
Craig Topper
dd637ae0c3
Unify all shuffle mask checking functions take a mask and VT instead of VectorShuffleSDNode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150913 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-19 05:41:45 +00:00
Craig Topper
5aaffa8470
Make a bunch of X86ISelLowering shuffle functions static now that they are no longer needed by isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150908 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-19 02:53:47 +00:00
Jia Liu
44de83a7f6
some comment fix for X86 and ARM
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150902 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-19 02:03:36 +00:00
Craig Topper
28a713b20a
Add vmfunc instruction to X86 assembler and disassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150899 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-19 01:39:49 +00:00
Jia Liu
31d157ae1a
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-18 12:03:15 +00:00
Craig Topper
a771330366
Add X86InstrSVM.td that I forgot to add in r150873.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150874 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-18 08:34:12 +00:00
Craig Topper
9e3d0b3351
Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150873 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-18 08:19:49 +00:00
Craig Topper
6e94e68b75
Remove the last of the old vector_shuffle patterns from X86 isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150795 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-17 07:02:34 +00:00
Jakob Stoklund Olesen
8b0a3f2df9
Remove the YMM_HI_6_15 hack.
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Call clobbers are now represented with register mask operands. The
regmask can easily represent the fact that xmm6 is call-preserved while
ymm6 isn't. This is automatically computed by TableGen from the
CalleeSavedRegs containing xmm6.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150709 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16 17:56:06 +00:00
Jakob Stoklund Olesen
527a08b253
Use the same CALL instructions for Windows as for everything else.
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The different calling conventions and call-preserved registers are
represented with regmask operands that are added dynamically.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150708 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16 17:56:02 +00:00
Jakob Stoklund Olesen
8bcde2aa66
Enable register mask operands for x86 calls.
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Call instructions no longer have a list of 43 call-clobbered registers.
Instead, they get a single register mask operand with a bit vector of
call-preserved registers.
This saves a lot of memory, 42 x 32 bytes = 1344 bytes per call
instruction, and it speeds up building call instructions because those
43 imp-def operands no longer need to be added to use-def lists. (And
removed and shifted and re-added for every explicit call operand).
Passes like LiveVariables, LiveIntervals, RAGreedy, PEI, and
BranchFolding are significantly faster because they can deal with call
clobbers in bulk.
Overall, clang -O2 is between 0% and 8% faster, uniformly distributed
depending on call density in the compiled code. Debug builds using
clang -O0 are 0% - 3% faster.
I have verified that this patch doesn't change the assembly generated
for the LLVM nightly test suite when building with -disable-copyprop
and -disable-branch-fold.
Branch folding behaves slightly differently in a few cases because call
instructions have different hash values now.
Copy propagation flushes its data structures when it crosses a register
mask operand. This causes it to leave a few dead copies behind, on the
order of 20 instruction across the entire nightly test suite, including
SPEC. Fixing this properly would require the pass to use different data
structures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150638 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16 00:02:50 +00:00
Chad Rosier
15b4497333
Use a temporary variable, rather then a series of redundant calls.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150538 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15 00:36:26 +00:00
Pete Cooper
9989a63818
Stop custom lowering forr x86 DEC64m from happening if the load in the lowered sequence has more than 1 user
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150537 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15 00:33:37 +00:00
Craig Topper
233a64846e
Move old movl vector_shuffle patterns. Not needed anymore since vector_shuffles shouldn't reach isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150462 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14 08:14:53 +00:00
Craig Topper
7505626acd
Still more vector_shuffle pattern removal.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150365 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13 07:23:41 +00:00
Ahmed Charles
b83a67e1e3
Fix various issues (or do cleanups) found by enabling certain MSVC warnings.
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- Use unsigned literals when the desired result is unsigned. This mostly allows unsigned/signed mismatch warnings to be less noisy even if they aren't on by default.
- Remove misplaced llvm_unreachable.
- Add static to a declaration of a function on MSVC x86 only.
- Change some instances of calling a static function through a variable to simply calling that function while removing the unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150364 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13 06:30:56 +00:00
Craig Topper
4eaca023dc
Remove more vector_shuffle patterns for unpack. These should be target specific nodes when they get to isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150363 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13 05:48:49 +00:00
Craig Topper
3b17bf9a7c
Recommit r150328. Previous test failures should be fixed by r150360.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150362 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13 05:10:10 +00:00
Craig Topper
2dcd718c13
Update CanXFormVExtractWithShuffleIntoLoad to ensure bitcasts of loads only have one use. Matches DAGCombiner and prevents vector_shuffles from reaching isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150360 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13 04:30:38 +00:00
NAKAMURA Takumi
7f42e9886e
Revert r150328, "Remove more vector_shuffle patterns."
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It caused 3 failures on pre-penryn and non-x86(generic) hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150357 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13 00:10:15 +00:00
Pete Cooper
ce3900849a
Fixed bug when custom lowering DEC64m on x86.
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If the DEC node had more than one user, it was doing this lowering but
leaving the original DEC node around and so decrementing twice.
Fixes PR11964.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150356 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13 00:10:03 +00:00
Craig Topper
cc9231a05d
Remove more vector_shuffle patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150328 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-12 08:14:35 +00:00
Craig Topper
26f927951b
Remove more vector_shuffle patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150321 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-12 01:07:34 +00:00
Craig Topper
1f2fa99b2a
Remove more vector_shuffle patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150314 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11 23:31:01 +00:00
Anton Korobeynikov
d4a19b6a72
Add support for implicit TLS model used with MS VC runtime.
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Patch by Kai Nacke!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150307 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11 17:26:53 +00:00
Benjamin Kramer
6b30274e27
Don't mix declarations and code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150305 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11 16:01:02 +00:00
Benjamin Kramer
88b6fc06db
Make the EDis tables const.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150304 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11 14:51:07 +00:00
Benjamin Kramer
953362cdfb
Reuse the enum names from X86Desc in the X86Disassembler.
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This requires some gymnastics to make it available for C code. Remove the names
from the disassembler tables, making them relocation free.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150303 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11 14:50:54 +00:00
Craig Topper
a819c397e7
Remove some patterns for matching vector_shuffle instructions since vector_shuffles should be custom lowered before isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150299 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11 07:43:35 +00:00
Craig Topper
39a9e485f2
Fix shuffle lowering code to stop creating temporary DAG nodes to do shuffle mask checks on. This seemed to be confusing things such that vector_shuffle ops to got through to iselection. This is another step towards removing the vector_shuffle handling patterns from isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150296 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11 06:24:48 +00:00
Craig Topper
f41ab77847
More tweaks to get the size of the X86 disassembler tables down.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150167 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09 08:58:07 +00:00
Craig Topper
ce8f4c58d8
Flatten some of the arrays in the X86 disassembler tables to reduce space needed to store pointers on 64-bit hosts and reduce relocations needed at startup. Part of PR11953.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150161 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09 07:45:30 +00:00
Jakob Stoklund Olesen
450b3850ce
Handle register masks when searching for EFLAGS clobbers.
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Calls clobber the flags, but when using register masks there is no
EFLAGS<imp-def> operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150117 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09 00:17:22 +00:00
Elena Demikhovsky
f602040c49
Fixed a bug in printing "cmp" pseudo ops.
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> This IR code
> %res = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 14)
> fails with assertion:
>
> llc: X86ATTInstPrinter.cpp:62: void llvm::X86ATTInstPrinter::printSSECC(const llvm::MCInst*, unsigned int, llvm::raw_ostream&): Assertion `0 && "Invalid ssecc argument!"' failed.
> 0 llc 0x0000000001355803
> 1 llc 0x0000000001355dc9
> 2 libpthread.so.0 0x00007f79a30575d0
> 3 libc.so.6 0x00007f79a23a1945 gsignal + 53
> 4 libc.so.6 0x00007f79a23a2f21 abort + 385
> 5 libc.so.6 0x00007f79a239a810 __assert_fail + 240
> 6 llc 0x00000000011858d5 llvm::X86ATTInstPrinter::printSSECC(llvm::MCInst const*, unsigned int, llvm::raw_ostream&) + 119
I added the full testing for all possible pseudo-ops of cmp.
I extended X86AsmPrinter.cpp and X86IntelInstPrinter.cpp.
You'l also see lines alignments (unrelated to this fix) in X86IselLowering.cpp from my previous check-in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150068 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08 08:37:26 +00:00
Craig Topper
bc0e4bf754
Remove a couple unneeded intrinsic patterns
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150067 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08 08:29:30 +00:00
Craig Topper
5a313bb7e8
Remove GCC builtins for vpermilp* intrinsics as clang no longer needs them. Custom lower the intrinsics to the vpermilp target specific node and remove intrinsic patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150060 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08 06:36:57 +00:00
Evan Cheng
de1df103b9
Use LEA to adjust stack ptr for Atom. Patch by Andy Zhang.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150008 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-07 22:50:41 +00:00
Craig Topper
dbd98a4b1b
Add instruction selection for 256-bit VPSHUFD and 128-bit VPERMILPS/VPERMILPD.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149968 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-07 06:28:42 +00:00
Derek Schuff
2ea93875b2
Enable streaming of bitcode
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This CL delays reading of function bodies from initial parse until
materialization, allowing overlap of compilation with bitcode download.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149918 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-06 22:30:29 +00:00
Chris Lattner
7302d80490
Remove some dead code and tidy things up now that vectors use ConstantDataVector
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instead of always using ConstantVector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149912 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-06 21:56:39 +00:00
Benjamin Kramer
699ddcbcb3
X86: Don't call malloc for 4 bits. No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149866 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-06 12:06:18 +00:00
Craig Topper
d156dc11f9
Add shuffle decoding support for 256-bit pshufd. Merge vpermilp* and pshufd decoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149859 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-06 07:17:51 +00:00
Duncan Sands
5b8a1db7ea
Persuade GCC that there is nothing worth warning about here (there isn't).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149834 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05 14:20:11 +00:00
Chandler Carruth
69f44692bf
Begin fleshing out more convenience predicates in llvm::Triple and
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convert at least one client over to use them. Subsequent patches both to
LLVM and Clang will try to convert more people over to a common set of
predicates.
This round of predicates is focused on OS-categorization predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149815 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05 08:26:40 +00:00
Craig Topper
655b8de7b2
Convert assert(0) to llvm_unreachable
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149814 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05 07:21:30 +00:00
Craig Topper
6d1263acb9
Convert assert(0) to llvm_unreachable in X86 Target directory.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149809 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05 05:38:58 +00:00
Craig Topper
abb94d0687
Convert some assert(0) in default of switch statements to llvm_unreachable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149808 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05 03:43:23 +00:00
Craig Topper
5b209e84f4
Add target specific node for PMULUDQ. Change patterns to use it and custom lower intrinsics to it. Use it instead of intrinsic to handle 64-bit vector multiplies.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149807 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05 03:14:49 +00:00
Craig Topper
eea723fe02
Remove most of the intrinsics for XOP VPCMOV instruction. They all aliased to the same instruction with different types. This would be better accomplished with casts in the not yet created xopintrin.h header file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149795 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05 00:55:56 +00:00
Andrew Trick
061efcfb3e
TargetPassConfig: confine the MC configuration to TargetMachine.
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Passes prior to instructon selection are now split into separate configurable stages.
Header dependencies are simplified.
The bulk of this diff is simply removal of the silly DisableVerify flags.
Sorry for the target header churn. Attempting to stabilize them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149754 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-04 02:56:59 +00:00
Craig Topper
a02556679e
Remove getShuffleVPERMILPImmediate function, getShuffleSHUFImmediate performs the same calculation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149683 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 06:52:33 +00:00
Craig Topper
fa5b70e1d8
Remove unnecessary qualification on 256-bit vector handling in LowerBUILD_VECTOR. Condition was already guaranteed by earlier code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149680 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 06:32:21 +00:00
Andrew Trick
843ee2e6a4
Added TargetPassConfig. The first little step toward configuring codegen passes.
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Allows command line overrides to be centralized in LLVMTargetMachine.cpp.
LLVMTargetMachine can intercept common passes and give precedence to command line overrides.
Allows adding "internal" target configuration options without touching TargetOptions.
Encapsulates the PassManager.
Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs.
Allows modifying the target configuration hooks without rebuilding the world.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149672 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 05:12:41 +00:00
Andrew Trick
8247e0dca6
whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149671 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 05:12:30 +00:00
Lang Hames
6e3f7e4913
Incorporate suggestions Chad, Jakob and Evan's suggestions on r149957.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149655 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 01:13:49 +00:00
Jakob Stoklund Olesen
478a8a02bc
Require non-NULL register masks.
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It doesn't seem worthwhile to give meaning to a NULL register mask
pointer. It complicates all the code using register mask operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149646 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 23:52:57 +00:00
Elena Demikhovsky
0f1ead47a0
Minor change in signature of the getZeroVector()
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149601 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 09:20:18 +00:00
Elena Demikhovsky
dcabc7bca9
Optimization for SIGN_EXTEND operation on AVX.
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Special handling was added for v4i32 -> v4i64 and v8i16 -> v8i32
extensions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149600 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 09:10:43 +00:00
Francois Pichet
1ae52f686c
Unbreak the MSVC build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149599 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 08:36:09 +00:00
Lang Hames
50a36f7102
Set EFLAGS correctly in EmitLoweredSelect on X86.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149597 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 07:48:37 +00:00
Andrew Trick
922d314e8f
Instruction scheduling itinerary for Intel Atom.
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Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.
Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.
Adds a test to verify that the scheduler is working.
Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.
Patch by Preston Gurd!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01 23:20:51 +00:00
Mon P Wang
845b1899b6
Avoid creating an extract element to an illegal type after LegalizeTypes has run.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149548 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01 22:15:20 +00:00
Chad Rosier
c2348d5c08
Tidy up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149521 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01 18:45:51 +00:00
Elena Demikhovsky
1766971769
Passing AVX 256-bit structures in Win64 was wrong.
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Fixed Win64 calling conventions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149494 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01 10:46:14 +00:00
Elena Demikhovsky
732525758f
Shortened code in shuffle masks
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149493 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01 10:33:05 +00:00
Elena Demikhovsky
3ae98150e3
Optimization for "truncate" operation on AVX.
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Truncating v4i64 -> v4i32 and v8i32 -> v8i16 may be done with set of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149485 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01 07:56:44 +00:00
Craig Topper
a1902a18cd
Don't create VBROADCAST nodes if any nodes use the chain result from the load. Fixes PR11900.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149478 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01 06:51:58 +00:00
Devang Patel
0db58bfece
Add assembler dialect attribute in asm parser which lets target specific asm parser change dialect on the fly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149396 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31 18:14:05 +00:00
Craig Topper
cac50c5ab8
Remove pcmpgt/pcmpeq intrinsics as clang is not using them.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149367 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31 06:52:44 +00:00
Evan Cheng
893a045cdb
PR11834: Use macros which are defined on Windows. Patch by Marina Yatsina.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149294 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-30 23:10:32 +00:00
Devang Patel
885f65b4a1
Intel syntax. Adjust special code, used to recognize cmp<comparison code>{ss,sd,ps,pd}, for intel syntax.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149291 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-30 22:47:12 +00:00
Devang Patel
be3e310d5e
Intel syntax. Support .intel_syntax directive.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149270 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-30 20:02:42 +00:00
Benjamin Kramer
630ecf0f53
Fix refacto.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149269 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-30 20:01:35 +00:00
Douglas Gregor
b2f1b5028c
Eliminate narrowing conversion in initializer list, to make C++11 happy
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149254 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-30 16:57:18 +00:00
Benjamin Kramer
9c68354956
X86: Simplify shuffle mask generation code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149248 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-30 15:16:21 +00:00
Craig Topper
cc30006391
Fix pattern for memory form of PSHUFD for use with FP vectors to remove bitcast to an integer vector that normal code wouldn't have. Also remove bitcasts from code that turns splat vector loads into a shuffle as it was making the broken pattern necessary.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149232 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-30 07:50:31 +00:00
Craig Topper
86c7c583a3
Move some XOP patterns into instruction definition. Replae VPCMOV intrinsic patterns with custom lowering to a target specific nodes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149216 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-30 01:10:15 +00:00
Devang Patel
a28101e61a
Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320]
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149142 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-27 19:48:28 +00:00
Craig Topper
3982b3cc7b
Move some patterns back near their instructions and use AddedComplexity to fix priority. Merge some patterns into their instruction definition.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149122 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-27 07:09:40 +00:00
Jim Grosbach
cb5dca3815
Keep source location information for X86 MCFixup's.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149106 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-27 00:51:27 +00:00
Jakob Stoklund Olesen
53fa56e8dc
Handle call-clobbered ymm registers on Win64.
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The Win64 calling convention has xmm6-15 as callee-saved while still
clobbering all ymm registers.
Add a YMM_HI_6_15 pseudo-register that aliases the clobbered part of the
ymm registers, and mark that as call-clobbered. This allows live xmm
registers across calls.
This hack wouldn't be necessary with RegisterMask operands representing
the call clobbers, but they are not quite operational yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149088 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26 22:59:28 +00:00
Victor Umansky
668f7ac9e4
Fix for the following bug in AVX codegen for double-to-int conversions:
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. "fptosi" and "fptoui" IR instructions are defined with round-to-zero rounding mode.
. Currently for AVX mode for <4xdouble> and <8xdouble> the "VCVTPD2DQ.128" and "VCVTPD2DQ.256" instructions are selected (for .fp_to_sint. DAG node operation ) by AVX codegen. However they use round-to-nearest-even rounding mode.
. Consequently, the conversion produces incorrect numbers.
The fix is to replace selection of VCVTPD2DQ instructions with VCVTTPD2DQ instructions. The latter use truncate (i.e. round-to-zero) rounding mode.
As .fp_to_sint. DAG node operation is used only for lowering of "fptosi" and "fptoui" IR instructions, the fix in X86InstrSSE.td definition file doesn.t have an impact on other LLVM flows.
The patch includes changes in the .td file, LIT test for the changes and a fix in a legacy LIT test (which produced asm code conflicting with LLVN IR spec).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149056 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26 08:51:39 +00:00
Craig Topper
a3937416e4
Add HasXOP predicate check covering a bunch of XOP intrinsic patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149054 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26 07:51:55 +00:00
Craig Topper
15388c4666
Fix AVX vs SSE patterns ordering issue for VPCMPESTRM and VPCMPISTRM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149053 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26 07:31:30 +00:00
Craig Topper
e566cd0f4d
Remove some more patterns by custom lowering intrinsics to target specific nodes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149052 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26 07:18:03 +00:00
Chris Lattner
9748479590
fix a bug I introduced in r148929, this is not a splat!
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Thanks to Eli for noticing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148947 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 09:56:22 +00:00
Craig Topper
969ba287cd
Custom lower PSIGN and PSHUFB intrinsics to their corresponding target specific nodes so we can remove the isel patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148933 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 06:43:11 +00:00
Chris Lattner
4ca829e895
use ConstantVector::getSplat in a few places.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148929 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 06:02:56 +00:00
Craig Topper
4bb3f34b22
Custom lower phadd and phsub intrinsics to target specific nodes. Remove the patterns that are no longer necessary.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148927 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 05:37:32 +00:00
Craig Topper
bce73e0a8c
Remove AVX 256-bit unaligned load intrinsics. 128-bit versions had been removed a while ago.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148922 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 04:42:03 +00:00
Craig Topper
042883f5da
Merge intrinsic pattern and no pattern versions of VCVTSD2SI intruction definitions. Matches non-AVX version of same instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148914 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 03:52:09 +00:00
Devang Patel
3b96e1fe3b
Intel Syntax: Extend special hand coded logic, to recognize special instructions, for intel syntax.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148864 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 21:43:36 +00:00
Elena Demikhovsky
28d7e71a30
ZERO_EXTEND operation is optimized for AVX.
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v8i16 -> v8i32, v4i32 -> v4i64 - used vpunpck* instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148803 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 13:54:13 +00:00
Craig Topper
dfc8e470b6
Add comments near load pattern fragments indicating that all integer vector loads are promoted to v2i64 or v4i64 so that no one tries to reintroduce pattern fragments for other types.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148771 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 03:03:17 +00:00
Devang Patel
392ad6d8aa
Fix typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148751 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 23:56:33 +00:00
Devang Patel
f2d213745e
Intel syntax: Robustify parsing of memory operand's displacement experssion.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148737 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 22:35:25 +00:00
Devang Patel
3e08131185
Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI]
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148721 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 20:20:06 +00:00
Devang Patel
7c64fe651a
Intel syntax: Parse segment registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148712 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 18:31:58 +00:00
Craig Topper
7925e2555d
Custom lower PCMPEQ/PCMPGT intrinsics to target specific nodes and remove the intrinsic patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148687 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 08:18:28 +00:00
Craig Topper
7fb8b0c5d3
Update more places to use target specific nodes for vector shifts instead of intrinsics.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148685 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 06:46:22 +00:00
Craig Topper
80e46360e9
Custom lower vector shift intrinsics to target specific nodes and remove the patterns that are no longer needed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148684 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 06:16:53 +00:00
Craig Topper
2b21fbaf11
Remove pattern fragments for v32i8, v16i16, v8i32, v16i8, v8i16, and v4i32 loads. All integer vector loads are promoted to v2i64 or v4i64 so these pattern fragments can never match. Fix or remove patterns that used these fragments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148672 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 00:06:44 +00:00
Craig Topper
1906d32e55
Combine X86 CMPPD and CMPPS node types. Simplifies selection code and pattern matching.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148670 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-22 23:36:02 +00:00
Craig Topper
67609fd0eb
Merge PCMPEQB/PCMPEQW/PCMPEQD/PCMPEQQ and PCMPGTB/PCMPGTW/PCMPGTD/PCMPGTQ X86 ISD node types into only two node types. Simplifying opcode selection and pattern matching.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148667 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-22 22:42:16 +00:00
Craig Topper
ed2e13d667
Add target specific ISD node types for SSE/AVX vector shuffle instructions and change all the code that used to create intrinsic nodes to create the new nodes instead.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148664 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-22 19:15:14 +00:00
Craig Topper
07a276277f
Make code a little less verbose.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148651 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-22 03:07:48 +00:00
Craig Topper
6a32b6f0c0
Remove unused X86 ISD node type defines.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148644 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-22 01:15:56 +00:00
Craig Topper
6fdf3d54d2
Move some vector shift patterns into their instruction definitions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148643 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-22 00:41:20 +00:00
Craig Topper
babb1459f3
Add memory patterns for some of the fp<->integer conversion instructions. Fold some patterns into instruction definitions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148641 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-21 18:37:15 +00:00
Benjamin Kramer
8608cc9473
Remove unused variables.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148635 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-21 10:42:44 +00:00
Craig Topper
d9ec725db4
Fix PR11819 introduced by r148537. I'd commit the test case, but the generated code is terrible as it gets fully scalarized. Expect a future commit to fix that.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148632 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-21 08:49:33 +00:00
Devang Patel
1aea430b88
Intel syntax: Robustify register parsing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148591 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 22:32:05 +00:00
David Blaikie
4d6ccb5f68
More dead code removal (using -Wunreachable-code)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 21:51:11 +00:00
Devang Patel
fdd3b30151
Intel syntax: Parse ... PTR [-8]
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148570 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 21:21:01 +00:00
Devang Patel
cf0e269d16
Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148569 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 21:14:06 +00:00
Craig Topper
8f35c13842
Improve 256-bit shuffle splitting to allow 2 sources in each 128-bit lane. As long as only a single lane of the source is used in the lane in the destination. This makes the splitting match much closer to what happens with 256-bit shuffles when AVX is disabled and only 128-bit XMM is allowed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148537 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 09:29:03 +00:00
Craig Topper
0e2037ba2b
Add support for selecting 256-bit PALIGNR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148532 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 05:53:00 +00:00
Eli Friedman
9a2478ac1a
Support MSVC x86-32 sret convention. PR11688. Patch by Joe Groff.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148513 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 00:05:46 +00:00
Devang Patel
a951f77ca3
Post process 'and', 'sub' instructions and select better encoding, if available.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148489 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 18:40:55 +00:00
Devang Patel
e60540f380
Intel syntax: There is no need to create unary expr for simple negative displacement.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148486 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 18:15:51 +00:00
Devang Patel
ac0f048602
Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148485 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 17:53:25 +00:00
Craig Topper
40385c8104
Folding table additions and fixes for AVX.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148467 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 08:50:38 +00:00
Craig Topper
1a7700a3fa
Merge 128-bit and 256-bit SHUFPS/SHUFPD handling.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148466 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 08:19:12 +00:00
Nick Lewycky
22de16dc75
Add a TargetOption for disabling tail calls.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148442 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 00:34:10 +00:00
Jakob Stoklund Olesen
c38c4561cd
Add experimental -x86-use-regmask command line option.
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It adds register mask operands to x86 call instructions. Once all the
backend passes support register mask operands, this will be permanently
enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148438 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18 23:52:22 +00:00
Jakob Stoklund Olesen
71f0fc1ca8
Ignore register mask operands when lowering instructions to MC.
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This is similar to implicit register operands. MC doesn't understand
register liveness and call clobbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148437 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18 23:52:19 +00:00
Devang Patel
b8ba13f009
Process instructions after match to select alternative encoding which may be more desirable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148431 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18 22:42:29 +00:00
Jim Grosbach
ec3433852d
Tidy up. MCAsmBackend naming conventions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148400 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18 18:52:16 +00:00
Jakob Stoklund Olesen
31867660cb
Add a CoveredBySubRegs property to Register descriptions.
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When set, this bit indicates that a register is completely defined by
the value of its sub-registers.
Use the CoveredBySubRegs property to infer which super-registers are
call-preserved given a list of callee-saved registers. For example, the
ARM registers D8-D15 are callee-saved. This now automatically implies
that Q4-Q7 are call-preserved.
Conversely, Win64 callees save XMM6-XMM15, but the corresponding
YMM6-YMM15 registers are not call-preserved because they are not fully
defined by their sub-registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148363 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18 00:16:39 +00:00
Jakob Stoklund Olesen
0bd2ae92b0
Move X86 callee saved register lists to the X86CallConv .td file.
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Add a trivial implementation of the getCallPreservedMask() hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148347 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 22:47:01 +00:00
Devang Patel
2f8af1d643
Intel syntax: Fix parser match class to check memory operand size.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148338 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 21:48:03 +00:00
Devang Patel
6220fea2a8
Intel syntax: Parse "BYTE PTR [RDX + RCX]"
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148334 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 21:25:10 +00:00
Devang Patel
bc51e501a0
Untabify.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148322 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 19:09:22 +00:00
Devang Patel
9a3d293cf3
Intel syntax: Do not unncessarily create plus expression for memory operand displacement.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148321 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 19:08:07 +00:00
Devang Patel
d37ad247cc
Intel syntax: Robustify memory operand parsing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148312 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 18:00:18 +00:00
Nadav Rotem
a16d441430
Fix warning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148301 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 09:31:09 +00:00
Nadav Rotem
0b94b5f52b
Fix 11769.
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In CanXFormVExtractWithShuffleIntoLoad we assumed that EXTRACT_VECTOR_ELT can be later handled by the DAGCombiner.
However, in some cases on AVX, the EXTRACT_VECTOR_ELT is legalized to EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which
currently is not handled by the DAGCombiner. In this patch I added a check that we only extract from the XMM part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148298 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 09:13:19 +00:00
Craig Topper
8b5a6b63dd
Remove unnecessary AVX check from an assert. hasSSE2 is enough.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148295 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 08:23:44 +00:00
Craig Topper
37c2677fbc
Fix a crasher when PerformShiftCombine receives a BUILD_VECTOR of all UNDEF. Probably could use better handling in DAG combine or getNode. Fixes PR11772.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148285 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 04:44:50 +00:00
Eli Friedman
1857b51ef5
Make sure the non-SSE lowering for fences correctly clobbers EFLAGS. PR11768.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148240 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-16 16:42:21 +00:00
Eli Friedman
a20b71518a
Get rid of unused codegen-only instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148239 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-16 16:29:35 +00:00
Craig Topper
b7ab7fe053
Give priority to AVX over SSE for 128-bit floating point unpck instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148233 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-16 09:56:42 +00:00