Vincent Lejeune
98f5cf8000
R600: Properly set COUNT_3 bit in TEX clause initiating inst for pre EG gen.
...
Fixes rv7x0 bug in Heaven reported here:
https://bugs.freedesktop.org/show_bug.cgi?id=64257
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184116 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-17 20:16:26 +00:00
Tom Stellard
5aee09da12
R600: Add SI load support for v[24]i32 and store for v2i32
...
Also add a seperate vector lit test file, since r600 doesn't seem to handle
v2i32 load/store yet, but we can test both for SI.
Patch by: Aaron Watry
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184021 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-15 00:09:31 +00:00
Tom Stellard
d6055262d2
R600: Use correct encoding for Vertex Fetch instructions on Cayman
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Reviewed-by: Vincent Lejeune<vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184016 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-14 22:12:30 +00:00
Tom Stellard
4efccd0fb1
R600: Use EXPORT_RAT_INST_STORE_DWORD for stores on Cayman
...
We were using RAT_INST_STORE_RAW, which seemed to work, but the docs
say this instruction doesn't exist for Cayman, so it's probably safer
to use a documented instruction instead.
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184015 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-14 22:12:24 +00:00
Tom Stellard
c30b232349
R600: Factor the instruction encoding out the RAT_WRITE_CACHELESS_eg class
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Reviewed-by: Vincent Lejeune<vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184014 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-14 22:12:19 +00:00
Tom Stellard
2def95fc1e
R600: Move instruction encoding definitions into a separate .td file
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Reviewed-by: Vincent Lejeune<vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184013 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-14 22:12:09 +00:00
Tom Stellard
2948e693cb
R600: Don't try to fix reg class when copying IMPLICIT_DEF to a register
...
The test case for this is way too complex to be useful as a lit test,
and I was unable to reduce it.
https://bugs.freedesktop.org/show_bug.cgi?id=65438
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183937 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-13 20:14:00 +00:00
Benjamin Kramer
6c59c7a6fd
R600: Make helper functions static.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183744 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-11 13:32:25 +00:00
Vincent Lejeune
843c6c2d0e
R600: Use a refined heuristic to choose when switching clause
...
This is using a hint from AMD APP OpenCL Programming Guide with
empirically tweaked parameters.
I used Unigine Heaven 3.0 to determine best parameters on my system
(i7 2600/Radeon 6950/Kernel 3.9.4) the benchmark :
it went from 38.8 average fps to 39.6, which is ~3% gain.
(Lightmark 2008.2 gain is much more marginal: from 537 to 539)
There is no lit test provided as the parameter were determined
empirically and it it would be nearly impossiblet to find a test
program that check for optimal behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183593 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 23:30:34 +00:00
Vincent Lejeune
b01bdf87ff
R600: Anti dep better handled in tex clause
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183592 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 23:30:26 +00:00
Tom Stellard
df74b86e1e
R600: Fix calculation of stack offset in AMDGPUFrameLowering
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We weren't computing structure size correctly and we were relying on
the original alloca instruction to compute the offset, which isn't
always reliable.
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183568 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 20:52:05 +00:00
Tom Stellard
3ff0abfaab
R600: Rework subtarget info and remove AMDILDevice classes
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This should simplify the subtarget definitions and make it easier to
add new ones.
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183566 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 20:37:48 +00:00
Bill Wendling
b5632b5b45
Don't cache the instruction and register info from the TargetMachine, because
...
the internals of TargetMachine could change.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183561 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 20:28:55 +00:00
Tom Stellard
ce961477be
R600: Fix the fetch limits for R600 generation GPUs
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Reviewed-by: Vincent Lejeune <vljn@ovi.com>
https://bugs.freedesktop.org/show_bug.cgi?id=64257
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183560 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 20:28:55 +00:00
Tom Stellard
630547ada4
R600: Move Subtarget feature definitions into AMDGPU.td
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This is the convention used by the other targets.
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183559 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 20:28:49 +00:00
Tom Stellard
6f3b49323c
R600: Remove unnecessary include
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Reviewed-by: Vincent Lejeune <vljn@ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183558 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 20:28:43 +00:00
Benjamin Kramer
1983a4cbf1
R600: Don't compare iterators of different maps.
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Found be libstdc's debug mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183549 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 19:59:34 +00:00
Benjamin Kramer
2e0cebd881
Vincent says the element is at most once in the vector, so we don't need a full std::remove.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183541 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 18:18:12 +00:00
Benjamin Kramer
47b0c0a9a0
R600: Fix a potential iterator invalidation issue.
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As a bonus this reduces the loop from O(n^2) to O(n).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183532 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 16:13:49 +00:00
Vincent Lejeune
74f03455e5
R600: Remove an extra break in R600OptimizeVectorRegisters.cpp
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183528 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 15:44:53 +00:00
Vincent Lejeune
81c5d11c25
R600: Rewrite an awkward loop in R600MachineScheduler
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183458 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 23:08:32 +00:00
Vincent Lejeune
5f035d048e
R600: Remove leftover code in R600MachineScheduler.cpp
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Spotted by Benjamin Kramer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183413 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 14:18:29 +00:00
Bill Wendling
2ed7659b88
Cast to the correct type. Pointer, not reference.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183385 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 05:39:29 +00:00
NAKAMURA Takumi
0ac857462f
R600OptimizeVectorRegisters.cpp: Tweak a warning. [-Wsometimes-uninitialized]
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FIXME: Is it false alarm?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183371 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 02:15:12 +00:00
NAKAMURA Takumi
7b6d32a361
R600OptimizeVectorRegisters.cpp: Suppress a warning. [-Wunused-variable]
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183370 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 02:15:06 +00:00
NAKAMURA Takumi
3ebcf388cd
Trailing linefeed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183369 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 02:15:00 +00:00
Bill Wendling
b88cef5a16
Cast to the proper type.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183365 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 01:04:21 +00:00
Tom Stellard
c170230b3a
R600: Replace predicate loop with predicate function
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183351 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 23:39:50 +00:00
Vincent Lejeune
f3d6e32c09
R600: Add a pass that merge Vector Register
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Previously commited @183279 but tests were failing, reverted @183286
It was broken because @183336 was missing, now it's there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183343 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 21:38:04 +00:00
Vincent Lejeune
512119770e
R600: Schedule copy from phys register at beginning of block
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It allows regalloc pass to remove them by trivially assigning associated reg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183336 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 20:27:35 +00:00
Tom Stellard
ad7ecc65b1
R600: Make sure to schedule AR register uses and defs in the same clause
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Reviewed-by: vljn at ovi.com
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183294 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 03:43:06 +00:00
Rafael Espindola
6afb65c2b7
Revert "R600: Add a pass that merge Vector Register"
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This reverts commit r183279. CodeGen/R600/texture-input-merge.ll was failing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183286 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 01:48:30 +00:00
Vincent Lejeune
bbbdba891b
R600: Add a pass that merge Vector Register
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183279 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 23:17:26 +00:00
Vincent Lejeune
e67a4afb5d
R600: Const/Neg/Abs can be folded to dot4
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183278 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 23:17:15 +00:00
Vincent Lejeune
98017a015b
R600: Swizzle texture/export instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183229 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 15:04:53 +00:00
Aaron Ballman
f3d3952a8c
Silencing an MSVC warning about mixing bool and unsigned int.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183176 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 01:03:03 +00:00
Tom Stellard
e5fcc0dee4
R600/SI: Add support for work item and work group intrinsics
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183138 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 17:40:18 +00:00
Tom Stellard
e7397ee81a
R600/SI: Add a calling convention for compute shaders
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183137 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 17:40:11 +00:00
Tom Stellard
e86f9d70ca
R600/SI: Custom lower i64 sign_extend
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183136 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 17:40:03 +00:00
Tom Stellard
17e8ad67f0
R600/SI: Adjust some instructions' out register class after ISel
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This is necessary to avoid generating VGPR to SGPR copies in some
cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183135 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 17:39:58 +00:00
Tom Stellard
b89a467559
R600/SI: Handle REG_SEQUENCE in fitsRegClass()
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183134 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 17:39:54 +00:00
Tom Stellard
051a28e0e8
R600/SI: Handle nodes with glue results correctly SITargetLowering::foldOperands()
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183133 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 17:39:50 +00:00
Tom Stellard
8a72c73032
R600/SI: Fixup CopyToReg register class in PostprocessISelDAG()
...
The CopyToReg nodes will sometimes try to copy a value from a VGPR to an
SGPR. This kind of copy is not possible, so we need to detect
VGPR->SGPR copies and do something else. The current strategy is to
replace these copies with VGPR->VGPR copies and hope that all the users
of CopyToReg can accept VGPRs as arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183132 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 17:39:46 +00:00
Tom Stellard
132183510f
R600/SI: Add support for global loads
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183131 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 17:39:43 +00:00
Tom Stellard
4956bc61e1
R600/SI: Rework MUBUF store instructions
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The lowering of stores is now mostly handled in the tablegen files. No
more BUFFER_STORE nodes I generated during legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183130 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 17:39:37 +00:00
Vincent Lejeune
0c92287985
R600: 3 op instructions have no write bit but the result are store in PV
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183111 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 15:56:12 +00:00
Vincent Lejeune
fdf7ab1c69
R600: CALL_FS consumes a stack size entry
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183108 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 15:44:42 +00:00
Vincent Lejeune
96fe0be43b
R600: use capital letter for PV channel
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183107 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 15:44:35 +00:00
Vincent Lejeune
0962e147a4
R600: Constraints input regs of interp_xy,_zw
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183106 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 15:44:16 +00:00
Ahmed Bougacha
23ed37a6b7
Make SubRegIndex size mandatory, following r183020.
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This also makes TableGen able to compute sizes/offsets of synthesized
indices representing tuples.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183061 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-31 23:45:26 +00:00
Patrik Hagglund
92b4f20346
Temporary fix to get rid of gcc warning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182832 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-29 07:32:08 +00:00
Andrew Trick
ac6d9bec67
Track IR ordering of SelectionDAG nodes 2/4.
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Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-25 02:42:55 +00:00
Tom Stellard
d078070f6a
R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg
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Patch by: Vincent Lejeune
https://bugs.freedesktop.org/show_bug.cgi?id=64877
NOTE: This is a candidate for the 3.3 branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182600 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 18:26:42 +00:00
Benjamin Kramer
5c35290fa3
Move passes from namespace llvm into anonymous namespaces. Sort includes while there.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182594 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 17:10:37 +00:00
Benjamin Kramer
879b071bf5
R600: Hide symbols of implementation details.
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Also removes an unused function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182587 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 15:43:05 +00:00
Aaron Ballman
061ff3409d
Setting the default value (fixes CRT assertions about uninitialized variable use when doing debug MSVC builds), and fixing coding style.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182585 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 14:55:00 +00:00
Rafael Espindola
7eac032203
Fix 32 bit build in c++11 mode.
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The error was:
error: non-constant-expression cannot be narrowed from type 'long long' to 'long' in initializer list [-Wc++11-narrowing]
MI.getOperand(6).getImm() & 0x1F,
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182584 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 13:22:30 +00:00
Rafael Espindola
5110102f9f
Fix a leak on the r600 backend.
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This should bring the valgrind bot back to life.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182561 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 03:31:47 +00:00
Rafael Espindola
23e24bd284
clang-format this file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182560 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 03:28:39 +00:00
Rafael Espindola
812789dd3d
Fix use after free (pr16103).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182482 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 15:31:11 +00:00
Rafael Espindola
431c73bc33
Check that a function starts with llvm. before using GET_FUNCTION_RECOGNIZER.
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Fixes a use of uninitialized memory found by asan and valgind.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182480 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 14:57:42 +00:00
NAKAMURA Takumi
7849728485
R600ISelLowering.cpp: Avoid "using namespace Intrinsic;" to appease MSC. Specify namespaces explicitly here.
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MSC is confused about "memcpy" between <cstring> and llvm::Intrinsic::memcpy, when llvm::Intrinsic were exposed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182452 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 06:37:31 +00:00
NAKAMURA Takumi
51c2e124e3
R600: Whitespace and untabify.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182451 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 06:37:25 +00:00
Owen Anderson
f9c3ea31db
Create an FPOW SDNode opcode def in the target independent .td file rather than in a specific backend.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182450 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 06:36:09 +00:00
Rafael Espindola
bbc45a3e28
Attempt to fix the mingw32 bot.
...
This should hopefully fix
http://lab.llvm.org:8011/builders/clang-x86_64-darwin11-self-mingw32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182446 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 02:30:47 +00:00
Rafael Espindola
2134219b65
s/u_int32_t/uint32_t/
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182444 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 01:36:19 +00:00
Rafael Espindola
de2b854310
Fix warning in non-assert build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182443 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 01:29:38 +00:00
Benjamin Kramer
d54bf7ceef
R600: Fix bug detected by GCC warning.
...
R600TextureIntrinsicsReplacer.cpp:232: warning: the address of ‘ArgsType’ will always evaluate as ‘true’
This doesn't have any effect on the output as a vararg intrinsic behaves the
same way as a non-vararg one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182293 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 15:58:43 +00:00
Tom Stellard
5ad6d082fc
R600/SI: Use a multiclass for MUBUF_Load_Helper
...
This will simplify the instructions and also the pattern definitions.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182288 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 15:02:31 +00:00
Tom Stellard
307a84425c
R600/SI: Add a pattern for S_LOAD_DWORDX2_* instructions
...
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182287 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 15:02:28 +00:00
Tom Stellard
0bbfc9313c
R600/SI: Add pattern for rotr
...
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182286 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 15:02:24 +00:00
Tom Stellard
ba534c2143
R600: Swap the legality of rotl and rotr
...
The hardware supports rotr and not rotl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182285 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 15:02:19 +00:00
Tom Stellard
a9d5d0b346
R600/SI: Add patterns for 64-bit shift operations
...
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182284 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 15:02:12 +00:00
Tom Stellard
fbdd318120
R600/SI: Use the same names for VOP3 operands and encoding fields
...
This makes it possible to reorder the operands without breaking the
encoding.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182283 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 15:02:08 +00:00
Tom Stellard
9bf4590aaa
R600/SI: Make fitsRegClass() operands const
...
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182282 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 15:02:01 +00:00
Matt Arsenault
225ed7069c
Add LLVMContext argument to getSetCCResultType
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182180 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-18 00:21:46 +00:00
Rafael Espindola
eee6cdd781
Fix the build in c++11 mode.
...
The errors were:
non-constant-expression cannot be narrowed from type 'int64_t' (aka 'long') to 'uint32_t' (aka 'unsigned int') in initializer list
and
non-constant-expression cannot be narrowed from type 'long' to 'uint32_t' (aka 'unsigned int') in initializer list
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182168 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17 22:45:52 +00:00
Vincent Lejeune
df98ad3959
R600: Lower int_load_input to copyFromReg instead of Register node
...
It solves a bug uncovered by dot4 patch where the register class of
int_load_input use was ignored.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182130 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17 16:51:06 +00:00
Vincent Lejeune
76fc2d077f
R600: Use bottom up scheduling algorithm
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182129 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17 16:50:56 +00:00
Vincent Lejeune
21ca0b3ea4
R600: Use depth first scheduling algorithm
...
It should increase PV substitution opportunities and lower gpr
usage (pending computations path are "flushed" sooner)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182128 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17 16:50:44 +00:00
Vincent Lejeune
f63f85affa
R600: Replace big texture opcode switch in scheduler by usesTC/usesVC
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182127 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17 16:50:37 +00:00
Vincent Lejeune
4ed9917147
R600: Relax some vector constraints on Dot4.
...
Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register
coalescer to remove some unneeded COPY.
This patch also defines some structures/functions that can be used to handle
every vector instructions (CUBE, Cayman special instructions...) in a similar
fashion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182126 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17 16:50:32 +00:00
Vincent Lejeune
d3293b49f9
R600: Improve texture handling
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182125 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17 16:50:20 +00:00
Vincent Lejeune
4109bd8829
R600: Rename 128 bit registers.
...
Almost all instructions that takes a 128 bits reg as input (fetch, export...)
have the abilities to swizzle their argument and output. Instead of printing
default swizzle for each 128 bits reg, rename T*.XYZW to T* and let instructions
print potentially optimized swizzles themselves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182124 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17 16:50:09 +00:00
Vincent Lejeune
25c209e9a2
R600: Some factorization
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182123 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17 16:50:02 +00:00
Vincent Lejeune
dcfcf1d1ff
R600: Factorize Fetch size limit inside AMDGPUSubTarget
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182122 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17 16:49:55 +00:00
Vincent Lejeune
9a9e936650
R600: prettier dump of clamp
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182121 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17 16:49:49 +00:00
Tom Stellard
0976e3c6d9
R600: Fix encoding for R600 family GPUs
...
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
https://bugs.freedesktop.org/show_bug.cgi?id=64193
https://bugs.freedesktop.org/show_bug.cgi?id=64257
https://bugs.freedesktop.org/show_bug.cgi?id=64320
NOTE: This is a candidate for the 3.3 branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182113 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17 15:23:21 +00:00
Tom Stellard
34f533a6c3
R600: Pass MCSubtargetInfo reference to R600CodeEmitter
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182112 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17 15:23:12 +00:00
Christian Konig
e919678208
R600/SI: return undef instead of null for skipped arguments
...
This is a candidate for the stable branch.
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=64694
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182084 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17 09:46:48 +00:00
Tom Stellard
ec03792245
R600/SI: Add processor type for Hainan asic
...
Patch by: Alex Deucher
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
NOTE: This is a candidate for the 3.3 branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181792 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 14:42:56 +00:00
Rafael Espindola
6eb70ac034
Remove unused fields and arguments.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181706 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 14:34:48 +00:00
Rafael Espindola
4a971705bc
Remove the MachineMove class.
...
It was just a less powerful and more confusing version of
MCCFIInstruction. A side effect is that, since MCCFIInstruction uses
dwarf register numbers, calls to getDwarfRegNum are pushed out, which
should allow further simplifications.
I left the MachineModuleInfo::addFrameMove interface unchanged since
this patch was already fairly big.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181680 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 01:16:13 +00:00
Rafael Espindola
ed9fc9b8ee
Fix the R600 build.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181621 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 18:31:42 +00:00
Tom Stellard
58e87a68a8
R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen patterns
...
The BFE optimization was the only one we were actually using, and it was
emitting an intrinsic that we don't support.
https://bugs.freedesktop.org/show_bug.cgi?id=64201
Reviewed-by: Christian König <christian.koenig@amd.com>
NOTE: This is a candidate for the 3.3 branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181580 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 02:09:45 +00:00
Tom Stellard
dde6836456
R600: Expand SUB for v2i32/v4i32
...
Patch by: Aaron Watry
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>
NOTE: This is a candidate for the 3.3 branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181579 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 02:09:39 +00:00
Tom Stellard
6c40d40d70
R600: Expand MUL for v4i32/v2i32
...
Fixes piglit test for OpenCL builtin mul24, and allows mad24 to run.
Patch by: Aaron Watry
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>
NOTE: This is a candidate for the 3.3 branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181578 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 02:09:34 +00:00
Tom Stellard
4fca5c1440
R600: Expand SRA for v4i32/v2i32
...
v2: Add v4i32 test
Patch by: Aaron Watry
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>
NOTE: This is a candidate for the 3.3 branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181577 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 02:09:29 +00:00
Tom Stellard
bdd9b1e89f
R600: Expand vselect for v4i32 and v2i32
...
v2: Add vselect v4i32 test
Patch by: Aaron Watry
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>
NOTE: This is a candidate for the 3.3 branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181576 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 02:09:24 +00:00
Tom Stellard
3d834a44f6
R600/SI: Add intrinsic for MIMG IMAGE_GET_RESINFO opcode
...
Patch by: Michel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181269 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 23:02:19 +00:00
Tom Stellard
ea73bd8a54
R600/SI: Handle arbitrary destination type in SITargetLowering::adjustWritemask
...
Patch by: Michel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181268 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 23:02:15 +00:00
Tom Stellard
651a4c8ee0
R600/SI: Add intrinsic for texture image loading
...
Patch by: Michel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181267 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 23:02:12 +00:00
Tom Stellard
e756ffd888
R600/SI: Add pattern for uint_to_fp
...
Patch by: Michel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181266 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 23:02:07 +00:00
Tom Stellard
586862ae23
R600/SI: Add patterns for integer maxima / minima
...
Patch by: Michel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181265 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 23:02:04 +00:00
Tom Stellard
354769ba32
R600/SI: Add pattern for AMDGPU.trunc intrinsic
...
Patch by: Michel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181263 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 23:02:00 +00:00
Tom Stellard
32c76107d0
R600: Remove dead code from the CodeEmitter v2
...
v2:
- Replace switch statement with TSFlags query
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181229 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 17:50:57 +00:00
Tom Stellard
f07b5373d7
R600: Emit config values in register / value pairs
...
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181228 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 17:50:51 +00:00
Tom Stellard
4f3d8a6440
R600: Stop emitting the instruction type byte before each instruction
...
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181225 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 17:50:44 +00:00
Tom Stellard
58bf662c06
R600: Emit ISA for CALL_FS_* instructions
...
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181223 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 17:50:26 +00:00
Tom Stellard
19301d5d12
R600: Expand vector or, shl, srl, and xor nodes
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181035 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 17:21:31 +00:00
Tom Stellard
8b1c60c151
R600: BFI_INT is a vector-only instruction
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181034 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 17:21:24 +00:00
Tom Stellard
83f0a5a5e8
R600: Add pattern for SHA-256 Ma function
...
This can be optimized using the BFI_INT instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181033 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 17:21:20 +00:00
Tom Stellard
218b20a81e
R600: Clean up comments in Processors.td
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181032 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 17:21:14 +00:00
Vincent Lejeune
5ed88013e8
R600: Signed literals are 64bits wide
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180960 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 21:53:03 +00:00
Vincent Lejeune
152ebee8f3
R600: If previous bundle is dot4, PV valid chan is always X
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180959 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 21:52:55 +00:00
Vincent Lejeune
9e1808733e
R600: Improve asmPrint of ALU clause
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180957 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 21:52:40 +00:00
Vincent Lejeune
92f24d403f
R600: Prettier asmPrint of Alu
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180956 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 21:52:30 +00:00
Tom Stellard
399880527d
R600: Use new tablegen syntax for patterns
...
All but two patterns have been converted to the new syntax. The
remaining two patterns will require COPY_TO_REGCLASS instructions, which
the VLIW DAG Scheduler cannot handle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180922 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 15:30:12 +00:00
Tom Stellard
5ed242c240
R600/SI: remove nonsense select pattern
...
Fortunately this pattern never matched, otherwise
we would have generated incorrect code.
Signed-off-by: Christian K??nig <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180921 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 15:30:07 +00:00
Vincent Lejeune
4fb224e3bd
R600: Always use texture cache for compute shaders
...
This will improve the performance of memory reads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180762 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 00:14:44 +00:00
Vincent Lejeune
2c836f84db
R600: use native for alu
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180761 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 00:14:38 +00:00
Vincent Lejeune
25f259cde2
R600: Packetize instructions
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180760 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 00:14:27 +00:00
Vincent Lejeune
abcde265b1
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180759 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 00:14:17 +00:00
Vincent Lejeune
e332e3559b
R600: Add a Bank Swizzle operand
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180758 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 00:14:08 +00:00
Vincent Lejeune
7097b1ddea
R600: Take inner dependency into tex/vtx clauses
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180757 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 00:14:00 +00:00
Vincent Lejeune
b6379de427
R600: Turn TEX/VTX into native instructions
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180756 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 00:13:53 +00:00
Vincent Lejeune
631591e6f3
R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions
...
v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180755 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 00:13:39 +00:00
Vincent Lejeune
0dc415cf28
R600: Add some new processor variants
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180753 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 00:13:27 +00:00
Vincent Lejeune
8723c9ebf5
R600: Clean up instruction class definitions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180752 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 00:13:20 +00:00
Vincent Lejeune
86cdb70417
R600: config section now reports use of killgt
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180751 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 00:13:13 +00:00
Tom Stellard
d8b2da1136
R600: Use correct CF_END instruction on Northern Island GPUs
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180735 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-29 22:23:58 +00:00
Tom Stellard
015f586bc9
R600: Fix encoding of CF_END_{EG, R600} instructions
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The EOP bit was not being encoded.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180734 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-29 22:23:54 +00:00
Tom Stellard
99d8179a9b
R600: Initialize AMDGPUMachineFunction::ShaderType to ShaderType::COMPUTE
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We need to intialize this to something and since clang does not set
the shader type attribute and clang is used only for compute shaders,
initializing it to COMPUTE seems like the best choice.
Reviewed-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180620 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26 18:32:24 +00:00
Tom Stellard
aa6deab608
R600: Initialize BooleanVectorContents
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Fixes test/CodeGen/R600/setcc.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180231 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-24 23:56:18 +00:00
Tom Stellard
87cba4a4c1
R600: Use SHT_PROGBITS for the .AMDGPU.config section
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The libelf implementation that is distributed here:
http://www.mr511.de/software/english.html
will not parse sections that are marked SHT_NULL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180230 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-24 23:56:14 +00:00
Vincent Lejeune
2a74639bc7
R600: Use .AMDGPU.config section to emit stacksize
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180124 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-23 17:34:12 +00:00
Vincent Lejeune
7a28d8afa7
R600: Add CF_END
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180123 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-23 17:34:00 +00:00
Matt Arsenault
9a0e12a6ed
Remove unused DwarfSectionOffsetDirective string
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The value isn't actually used, and setting it emits a COFF specific
directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180064 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-22 22:49:11 +00:00
Michael Liao
2a8bea7a8e
ArrayRefize getMachineNode(). No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179901 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19 22:22:57 +00:00
Tom Stellard
48b809e6e5
R600: Add pattern for the BFI_INT instruction
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179830 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19 02:11:06 +00:00
Tom Stellard
ae2a8929d8
R600/SI: Use InstFlag for VOP3 modifier operands
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InstFlag has a default value of 0 and will simplify the VOP3 patterns.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179829 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19 02:11:00 +00:00
Vincent Lejeune
26ebd7aafc
R600: Make Export Instruction not duplicable
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179686 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-17 15:17:39 +00:00
Vincent Lejeune
58df169e82
R600: Export is emitted as a CF_NATIVE inst
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179685 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-17 15:17:32 +00:00
Vincent Lejeune
141ca7fc64
R600: Emit used GPRs count
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179684 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-17 15:17:25 +00:00
Tom Stellard
9a256300f8
R600/SI: Emit config values in register value pairs.
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Instead of emitting config values in a predefined order, the code
emitter will now emit a 32-bit register index followed by the 32-bit
config value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179546 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15 17:51:35 +00:00
Tom Stellard
bf1efe6421
R600/SI: Emit configuration value in the .AMDGPU.config ELF section
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179545 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15 17:51:30 +00:00
Tom Stellard
3a63bf27c5
R600: Emit ELF formatted code rather than raw ISA.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179544 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15 17:51:21 +00:00
NAKAMURA Takumi
4eb5f18956
R600ControlFlowFinalizer.cpp: Fix a warning. [-Wunused-variable]
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179263 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11 04:16:27 +00:00
NAKAMURA Takumi
e7a040f9ab
Whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179262 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11 04:16:22 +00:00
Michel Danzer
b187f8cd1c
R600/SI: Add pattern for AMDGPUurecip
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21 more little piglits with radeonsi.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179186 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10 17:17:56 +00:00