Chris Lattner
bead6612a5
The basic fneg cases are already autogen'd
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24592 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-04 19:04:38 +00:00
Chris Lattner
937a79dbe3
Autogen matching code for ADJCALLSTACK[UP|DOWN], thanks to Evan's tblgen
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improvements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24591 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-04 19:01:59 +00:00
Chris Lattner
60a4ab2d5c
Finish moving uncond br over to .td file, remove from .cpp file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24590 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-04 18:48:01 +00:00
Chris Lattner
1e48478557
Define BR in the .td file now that Evan made tblgen smarter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24589 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-04 18:42:54 +00:00
Evan Cheng
d35b8c1adb
Added isel patterns for RET, JMP, and WRITEPORT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24588 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-04 08:19:43 +00:00
Evan Cheng
f8ac814957
* Added instruction property hasCtrlDep for those which r/w control-flow
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chains.
* Added DAG node property SDNPHasChain for nodes which r/w control-flow
chains.
* Renamed SDTVT to SDTOther.
* Added several new SDTypeProfiles for BR, BRCOND, RET, and WRITEPORT.
* Added SDNode definitions for BR, BRCOND, RET, and WRITEPORT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24586 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-04 08:13:17 +00:00
Chris Lattner
df65de42cf
Fix PR672 another way which should be more robust
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24585 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-04 06:03:50 +00:00
Chris Lattner
a027ba885a
Fix test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll and PR672.
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This also fixes 177.mesa, the only program that fails with --enable-x86-fastcc
turned on. Given a clean nightly tester run, we should be able to turn it
on by default!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24578 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-03 07:15:55 +00:00
Chris Lattner
865874c88a
add a note
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24572 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-02 00:11:20 +00:00
Chris Lattner
18c778f8be
IA64 doesn't support the LOCATION node, and for some reason the ISelPattern
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stuff isn't using ISelLowering.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24567 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-01 18:19:53 +00:00
Chris Lattner
05f56a529c
Make sure these get added into the codegenmap when appropriate
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24566 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-01 18:09:22 +00:00
Andrew Lenharth
6251b36d88
major think-o
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24564 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-01 17:48:51 +00:00
Nate Begeman
6510b22cec
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
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work. This change has no effect on generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24563 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-01 04:51:06 +00:00
Nate Begeman
5dfc55c304
Cosmetic change, better reflects actual values
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24562 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-01 04:48:26 +00:00
Chris Lattner
db1cb2b3a1
Fix a regression caused by a patch earlier today
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24561 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-01 03:50:19 +00:00
Andrew Lenharth
9352622356
Flags where I think I need them, quick, before the nightly tester starts
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24560 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-01 01:53:10 +00:00
Evan Cheng
640f299b44
Proper support for shifts with register shift value.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24559 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-01 00:43:55 +00:00
Evan Cheng
c121e33e35
Use a getCopyToReg() variant to generate a flaggy CopyToReg node.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24558 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-01 00:41:50 +00:00
Chris Lattner
d5acfb4153
SelectNodeTo now returns its result, we must pay attention to it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24552 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-30 23:04:38 +00:00
Chris Lattner
b19b899181
Pay attn to the node returned by SelectNodeTo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24551 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-30 23:02:08 +00:00
Chris Lattner
350d22e14d
SelectNodeTo now returns its result, we must pay attention to it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24550 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-30 22:59:19 +00:00
Chris Lattner
71d3d50b4a
SelectNodeTo now returns N. Use it instead of return N directly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24549 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-30 22:53:06 +00:00
Chris Lattner
80720a9219
Fix Regression/CodeGen/PowerPC/2005-11-30-vastart-crash.ll
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24547 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-30 20:40:54 +00:00
Nate Begeman
85a168a734
Fix a typo in my latest change
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24542 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-30 18:57:39 +00:00
Nate Begeman
391c5d231a
No longer track value types for asm printer operands, and remove them as
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an argument to every operand printing function. Requires some slight
tweaks to x86, the only user.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24541 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-30 18:54:35 +00:00
Andrew Lenharth
72d32c222c
remove redundant code
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24538 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-30 17:14:11 +00:00
Andrew Lenharth
b2156f91f5
Make typesafe that which isn't: FCMOVxx
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24536 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-30 17:11:20 +00:00
Andrew Lenharth
cd80496ccc
FPSelect and more custom lowering
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24535 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-30 16:10:29 +00:00
Nate Begeman
f43a3ca26d
First chunk of actually generating vector code for packed types. These
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changes allow us to generate the following code:
_foo:
li r2, 0
lvx v0, r2, r3
vaddfp v0, v0, v0
stvx v0, r2, r3
blr
for this llvm:
void %foo(<4 x float>* %a) {
entry:
%tmp1 = load <4 x float>* %a
%tmp2 = add <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float>* %a
ret void
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24534 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-30 08:22:07 +00:00
Andrew Lenharth
7f0db91f86
All sorts of stuff.
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Getting in on the custom lowering thing, yay
evilness with fp setcc, yuck
trivial int select, hmmm
in memory args for functions, yay
DIV and REM, always handy. They should be custom lowered though.
Lots more stuff compiles now (go go single source!). Of course, none of it
probably works, but that is what the nightly tester can find out :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24533 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-30 07:19:56 +00:00
Chris Lattner
5b9bbc8792
Fix a bug in a recent patch that broke shifts
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24526 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-30 05:11:18 +00:00
Evan Cheng
bd3d25c6b1
Added support to STORE and shifts to DAG to DAG isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24525 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-30 02:51:20 +00:00
Evan Cheng
345c3f370d
Fixed a minor bug: - -offset != offset iff offset == MININT
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24522 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-30 01:59:00 +00:00
Nate Begeman
7ac8e6b6a8
Represent the encoding of the SPR instructions as they actually are, so
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that we can use the correct SPR numbers in the InstrInfo.td file. This is
necessary to support VRsave.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24521 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-29 22:42:50 +00:00
Evan Cheng
f0701842f7
Add more X86 ISel patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24520 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-29 19:38:52 +00:00
Nate Begeman
425a96971f
Hook up one type, v4f32, to the VR RegisterClass for now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24517 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-29 08:17:20 +00:00
Nate Begeman
9b14f66320
Add the remainder of the AltiVec 4 x float instructions. Further
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enhancements will be necessary to teach the code generator that since
there is no fmul, it will have to do vmaddfp, adding +0.0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24516 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-29 08:04:45 +00:00
Chris Lattner
f73bae1b73
No targets support line number info yet.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24513 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-29 06:16:21 +00:00
Nate Begeman
6a648614e8
Add the majority of the vector machien value types we expect to support,
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and make a few changes to the legalization machinery to support more than
16 types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24511 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-29 05:45:29 +00:00
Evan Cheng
5ee16ea417
Fixed a comment bug:
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createPPCPatternInstructionSelector -> createPPCISelPattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24510 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-29 04:59:46 +00:00
Chris Lattner
eedf3b57cb
refix typo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24505 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-29 00:42:30 +00:00
Chris Lattner
fd5df2b203
don't say this is i128, because it isn't yet. Hopefully nate will change
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this to be something sane, but in the mean time it is unused, so safe to
make something bogus.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24504 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-29 00:41:40 +00:00
Chris Lattner
46ec78646b
revert my change for the time being, which broke the build
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24503 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-29 00:24:08 +00:00
Chris Lattner
0ba7d71213
fix a typo :)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24501 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-28 22:42:15 +00:00
Chris Lattner
1e4ed93599
Add a missed optimization
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24495 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-28 04:52:39 +00:00
Nate Begeman
01595c52b3
Small tweaks noticed while on the plane.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24492 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-26 22:39:34 +00:00
Duraid Madina
7b1e154c5a
add support for dynamic_stackalloc to the dag isel (thanks andrew ;)
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next up: support argument passing in memory, not just registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24490 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-25 07:49:25 +00:00
Nate Begeman
e4f17a5f9b
Some first bits of AltiVec stuff: Instruction Formats, Encodings, and
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Registers. Apologies to Jim if the scheduling info so far isn't accurate.
There's a few more things like VRsave support that need to be finished up
in my local tree before I can commit code that Does The Right Thing for
turning 4 x float into the various altivec packed float instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24489 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-23 05:29:52 +00:00
Andrew Lenharth
4052f02cdb
Fix warning, the better way. Really, this is what this instruction is for, so use it
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24486 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-22 20:59:00 +00:00
Andrew Lenharth
475d31729d
Fix warning
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24485 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-22 20:56:05 +00:00