22 Commits

Author	SHA1	Message	Date
MHeinrichs	a85ced47d0	dma improved	2017-12-30 01:39:22 +01:00
MHeinrichs	f65f1a4bec	resetfix + pdfs	2016-12-29 21:50:37 +01:00
MHeinrichs	1152df45a6	Better timing & Resetfix	2016-11-30 23:10:23 +01:00
MHeinrichs	e79ab9bae7	Updated some JEDs	2016-10-26 22:26:40 +02:00
MHeinrichs	ba4bc7b8fc	timing timing timnig ... when will it end?	2016-10-16 19:58:33 +02:00
MHeinrichs	1e90c3fb4e	recompiled	2016-10-06 22:23:07 +02:00
MHeinrichs	6665071ebe	Improved speed on amiga cycles	2016-10-06 21:37:29 +02:00
MHeinrichs	ae77c5fb85	Cleaned up BRD-Files	2016-09-15 19:20:42 +02:00
MHeinrichs	cb8dfae058	Cleaned up and the preempting DSACK is unneccessary?!?	2016-08-25 22:30:49 +02:00
MHeinrichs	00726c0582	Working at 254Mhz in CDTV!	2016-08-24 23:34:13 +02:00
MHeinrichs	7b64ad431c	Horray! No Sync of Pos and Neg edges needed anymore!	2016-08-19 00:42:01 +02:00
MHeinrichs	23323633f9	Clarified some thing Timing can be adjusted with constants	2016-08-19 00:22:24 +02:00
MHeinrichs	0c2122cd7f	Clean up	2016-08-18 07:48:07 +02:00
MHeinrichs	96a7e32d95	Some jed-files generated	2016-01-28 21:34:20 +01:00
MHeinrichs	63002d2099	50Mhz version	2016-01-25 18:02:53 +01:00
MHeinrichs	5eee23fe31	Cleaned up a bit	2016-01-24 20:26:06 +01:00
MHeinrichs	7c8801d6ee	Reset-Circuit has less delay	2015-10-10 22:11:10 +02:00
MHeinrichs	a4ead08a9a	DMA-Bug fixed ... When BGACK gets deasserted, the DMA-Statemachine has to wait for AS_000 to deassert too!	2015-09-24 17:00:50 +02:00
MHeinrichs	c39e83d66d	some erratic tries	2015-07-18 14:06:08 +02:00
MHeinrichs	c808e2f06a	MIsc. Update	2015-06-26 18:32:40 +02:00
MHeinrichs	fa0999c496	Sources for GBA-TK060	2015-03-28 22:03:17 +01:00
MHeinrichs	aa7f8b7632	Reset-Problem solved ... The AMiga was not able to recover from a reste, because the e-clock was not generated properly during reste.	2015-03-15 13:50:46 +01:00