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MacPlus_MiSTer
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Update API.

This commit is contained in:
sorgelig 2018-03-06 01:40:43 +08:00
parent 3116fe40f5
commit fa3f62043c
45 changed files with 4857 additions and 841 deletions
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2
.gitignore vendored
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@ -35,3 +35,5 @@ c5_pin_model_dump.txt
*.bsf *.bsf
*~ *~
*.xml *.xml
*_netlist
*.cdf

4
MacPlus-lite.qsf
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@ -353,9 +353,9 @@ set_location_assignment PIN_W20 -to SW[3]
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl" set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
set_global_assignment -name CDF_FILE jtag_lite.cdf set_global_assignment -name CDF_FILE jtag.cdf
set_global_assignment -name QIP_FILE sys/sys.qip set_global_assignment -name QIP_FILE sys/sys.qip
set_global_assignment -name QIP_FILE sys/sysmem.qip set_global_assignment -name SYSTEMVERILOG_FILE sdram.sv
set_global_assignment -name VERILOG_FILE scsi.v set_global_assignment -name VERILOG_FILE scsi.v
set_global_assignment -name VERILOG_FILE ncr5380.v set_global_assignment -name VERILOG_FILE ncr5380.v
set_global_assignment -name VERILOG_FILE floppy_track_encoder.v set_global_assignment -name VERILOG_FILE floppy_track_encoder.v

5
MacPlus.qsf
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@ -49,7 +49,7 @@ set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name FITTER_EFFORT "STANDARD FIT" set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name OPTIMIZATION_MODE BALANCED set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
set_global_assignment -name SEED 1 set_global_assignment -name SEED 1
#============================================================ #============================================================
@ -353,7 +353,8 @@ set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
set_global_assignment -name CDF_FILE jtag.cdf set_global_assignment -name CDF_FILE jtag.cdf
set_global_assignment -name QIP_FILE sys/sys.qip set_global_assignment -name QIP_FILE sys/sys.qip
set_global_assignment -name QIP_FILE sys/vip.qip set_global_assignment -name QSYS_FILE sys/vip.qsys
set_global_assignment -name SYSTEMVERILOG_FILE sdram.sv
set_global_assignment -name VERILOG_FILE scsi.v set_global_assignment -name VERILOG_FILE scsi.v
set_global_assignment -name VERILOG_FILE ncr5380.v set_global_assignment -name VERILOG_FILE ncr5380.v
set_global_assignment -name VERILOG_FILE floppy_track_encoder.v set_global_assignment -name VERILOG_FILE floppy_track_encoder.v

62
MacPlus.srf
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@ -1,51 +1,29 @@
{ "" "" "" "Vip.Mixer: The MixerII register map changed in ACDS v16.0. Please refer to the VIP User Guide for details." { } { } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Vip.Reset_Source.reset_sys: Associated reset sinks not declared" { } { } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Vip.Reset_Source.reset_warm: Associated reset sinks not declared" { } { } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Vip.Reset_Source.reset_cold: Associated reset sinks not declared" { } { } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Vip.Video_Output.control: Interrupt sender control.av_mm_control_interrupt is not connected to an interrupt receiver" { } { } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Vip.Video_Output: Interrupt sender Video_Output.status_update_irq is not connected to an interrupt receiver" { } { } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Vip.: You have exported the interface HPS.f2h_sdram1_data but not its associated reset interface. Export the driver(s) of HPS.h2f_reset" { } { } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Vip.: You have exported the interface HPS.f2h_sdram2_data but not its associated reset interface. Export the driver(s) of HPS.h2f_reset" { } { } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "Port \"extclk\" on the entity instantiation of \"cyclonev_pll\" is connected to a signal of width 1. The formal width of the signal in the module is 2. The extra bits will be left dangling without any fan-out logic." { } { } 0 12030 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "Port \"trs\" on the entity instantiation of \"statemachine\" is connected to a signal of width 2. The formal width of the signal in the module is 1. The extra bits will be ignored." { } { } 0 12020 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "Port \"reset_value\" on the entity instantiation of \"h_counter\" is connected to a signal of width 32. The formal width of the signal in the module is 16. The extra bits will be ignored." { } { } 0 12020 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "LOCKED port on the PLL is not properly connected on instance \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "Vip.vip: Module dependency loop involving: \"HPS\"" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "alt_vip_cvo_mode_banks.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "altera_pll.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "altera_cyclonev_pll.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "altera_pll_reconfig_core.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "RST port on the PLL is not properly connected" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}

44
MacPlus.sv
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@ -2,7 +2,7 @@
// Macintosh Plus // Macintosh Plus
// //
// Port to MiSTer // Port to MiSTer
// Copyright (C) 2017 Sorgelig // Copyright (C) 2017,2018 Sorgelig
// //
// This program is free software; you can redistribute it and/or modify it // This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free // under the terms of the GNU General Public License as published by the Free
@ -29,7 +29,7 @@ module emu
input RESET, input RESET,
//Must be passed to hps_io module //Must be passed to hps_io module
inout [43:0] HPS_BUS, inout [44:0] HPS_BUS,
//Base video clock. Usually equals to CLK_SYS. //Base video clock. Usually equals to CLK_SYS.
output CLK_VIDEO, output CLK_VIDEO,
@ -51,7 +51,7 @@ module emu
output LED_USER, // 1 - ON, 0 - OFF. output LED_USER, // 1 - ON, 0 - OFF.
// b[1]: 0 - LED status is system status ORed with b[0] // b[1]: 0 - LED status is system status OR'd with b[0]
// 1 - LED status is controled solely by b[0] // 1 - LED status is controled solely by b[0]
// hint: supply 2'b00 to let the system control the LED. // hint: supply 2'b00 to let the system control the LED.
output [1:0] LED_POWER, output [1:0] LED_POWER,
@ -59,7 +59,8 @@ module emu
output [15:0] AUDIO_L, output [15:0] AUDIO_L,
output [15:0] AUDIO_R, output [15:0] AUDIO_R,
output AUDIO_S, // 1 - signed audio samples, 0 - unsigned output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
input TAPE_IN, input TAPE_IN,
// SD-SPI // SD-SPI
@ -67,6 +68,7 @@ module emu
output SD_MOSI, output SD_MOSI,
input SD_MISO, input SD_MISO,
output SD_CS, output SD_CS,
input SD_CD,
//High latency DDR3 RAM interface //High latency DDR3 RAM interface
//Use for non-critical time purposes //Use for non-critical time purposes
@ -118,7 +120,7 @@ localparam CONF_STR = {
"O9A,Memory,512KB,1MB,4MB;", "O9A,Memory,512KB,1MB,4MB;",
"O5,Speed,Normal,Turbo;", "O5,Speed,Normal,Turbo;",
"-;", "-;",
"T6,Reset;", "R6,Reset;",
"V,v1.00.",`BUILD_DATE "V,v1.00.",`BUILD_DATE
}; };
@ -191,13 +193,30 @@ wire [7:0] sd_buff_dout;
wire [7:0] sd_buff_din; wire [7:0] sd_buff_din;
wire sd_buff_wr; wire sd_buff_wr;
wire ioctl_wr; reg ioctl_wr;
wire ioctl_write;
reg ioctl_wait = 0; reg ioctl_wait = 0;
wire [64:0] ps2_key; wire [10:0] ps2_key;
wire [24:0] ps2_mouse; wire [24:0] ps2_mouse;
wire capslock; wire capslock;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_data;
always @(posedge clk_sys) begin
reg [7:0] temp;
ioctl_wr <= 0;
if(ioctl_write) begin
if(~ioctl_addr[0]) temp <= ioctl_data;
else begin
dio_data <= {temp, ioctl_data};
ioctl_wr <= 1;
end
end
end
hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io
( (
.clk_sys(clk_sys), .clk_sys(clk_sys),
@ -221,9 +240,9 @@ hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io
.ioctl_download(dio_download), .ioctl_download(dio_download),
.ioctl_index(dio_index), .ioctl_index(dio_index),
.ioctl_wr(ioctl_wr), .ioctl_wr(ioctl_write),
.ioctl_addr(dio_addr), .ioctl_addr(ioctl_addr),
.ioctl_dout(dio_data), .ioctl_dout(ioctl_data),
.ioctl_wait(ioctl_wait), .ioctl_wait(ioctl_wait),
@ -299,6 +318,7 @@ wire [10:0] audio;
assign AUDIO_L = {audio[10:0], 5'b00000}; assign AUDIO_L = {audio[10:0], 5'b00000};
assign AUDIO_R = {audio[10:0], 5'b00000}; assign AUDIO_R = {audio[10:0], 5'b00000};
assign AUDIO_S = 0; assign AUDIO_S = 0;
assign AUDIO_MIX = 0;
wire status_turbo = status[5]; wire status_turbo = status[5];
wire status_reset = status[6]; wire status_reset = status[6];
@ -442,9 +462,9 @@ end
// include ROM download helper // include ROM download helper
wire dio_download; wire dio_download;
reg dio_write; reg dio_write;
wire [23:0] dio_addr; wire [23:0] dio_addr = ioctl_addr[24:1];
wire [7:0] dio_index; wire [7:0] dio_index;
wire [15:0] dio_data; reg [15:0] dio_data;
// good floppy image sizes are 819200 bytes and 409600 bytes // good floppy image sizes are 819200 bytes and 409600 bytes
reg dsk_int_ds, dsk_ext_ds; // double sided image inserted reg dsk_int_ds, dsk_ext_ds; // double sided image inserted

3
clean.bat
View File

@ -31,7 +31,8 @@ del /s *.bsf
del /s *.f del /s *.f
del /s *.sopcinfo del /s *.sopcinfo
del /s *.xml del /s *.xml
del *.cdf
del *.rpt
del /s new_rtl_netlist del /s new_rtl_netlist
del /s old_rtl_netlist del /s old_rtl_netlist
pause pause

2
dataController_top.v
View File

@ -33,7 +33,7 @@ module dataController_top(
output [15:0] memoryDataOut, output [15:0] memoryDataOut,
// keyboard: // keyboard:
input [64:0] ps2_key, input [10:0] ps2_key,
output capslock, output capslock,
// mouse: // mouse:

15
jtag.cdf
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@ -1,15 +0,0 @@
/* Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Ign)
Device PartName(SOCVHPS) MfrSpec(OpMask(0));
P ActionCode(Cfg)
Device PartName(5CSEBA6U23) Path("output_files/") File("MacPlus.sof") MfrSpec(OpMask(1));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;

15
jtag_lite.cdf
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@ -1,15 +0,0 @@
/* Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Ign)
Device PartName(SOCVHPS) MfrSpec(OpMask(0));
P ActionCode(Cfg)
Device PartName(5CSEBA6U23) Path("output_files/") File("MacPlus-lite.sof") MfrSpec(OpMask(1));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;

14
ps2_kbd.sv
View File

@ -10,7 +10,7 @@ module ps2_kbd
input reset, input reset,
input [64:0] ps2_key, input [10:0] ps2_key,
output reg capslock, output reg capslock,
input [7:0] data_out, input [7:0] data_out,
@ -94,8 +94,8 @@ assign data_in = cmd_test ? 8'h7d :
key_pending ? (keymac[8] ? 8'h79 : keymac[7:0]) : key_pending ? (keymac[8] ? 8'h79 : keymac[7:0]) :
8'h7b; 8'h7b;
wire depress = (ps2_key[15:8] == 8'hf0) /* synthesis keep */; wire depress = ~ps2_key[9];
wire extended = (depress ? (ps2_key[23:16] == 8'he0) : (ps2_key[15:8] == 8'he0)) /* synthesis keep */; wire extended = ps2_key[8];
wire ignore_capslock = {extended,ps2_key[7:0]} == 9'h058 && capslock; wire ignore_capslock = {extended,ps2_key[7:0]} == 9'h058 && capslock;
/* Handle key_pending, and multi-byte keypad responses */ /* Handle key_pending, and multi-byte keypad responses */
@ -104,7 +104,7 @@ always @(posedge clk) begin
if (reset) begin if (reset) begin
key_pending <= 0; key_pending <= 0;
old_stb <= ps2_key[64]; old_stb <= ps2_key[10];
capslock <= 0; capslock <= 0;
end end
else if(ce) begin else if(ce) begin
@ -114,13 +114,13 @@ always @(posedge clk) begin
else key_pending <= 0; else key_pending <= 0;
end else begin end else begin
old_stb <= ps2_key[64]; old_stb <= ps2_key[10];
if(old_stb != ps2_key[64]) begin if(old_stb != ps2_key[10]) begin
/* Capslock handling */ /* Capslock handling */
if(ps2_key[7:0] == 8'h58 && !extended && !depress) capslock <= ~capslock; if(ps2_key[7:0] == 8'h58 && !extended && !depress) capslock <= ~capslock;
if(!key_pending && !ignore_capslock && !ps2_key[63:24]) begin if(!key_pending && !ignore_capslock) begin
key_pending <= 1; key_pending <= 1;
keymac <= {key_code[8],depress,key_code[6:0]}; keymac <= {key_code[8],depress,key_code[6:0]};
end end

0
sys/sdram.sv → sdram.sv
View File

60
sys/build_id.tcl
View File

@ -1,15 +1,6 @@
# ================================================================================
#
# Build ID Verilog Module Script
# Jeff Wiencrot - 8/1/2011
#
# Generates a Verilog module that contains a timestamp,
# from the current build. These values are available from the build_date, build_time,
# physical_address, and host_name output ports of the build_id module in the build_id.v
# Verilog source file.
#
# ================================================================================
# Build TimeStamp Verilog Module
# Jeff Wiencrot - 8/1/2011
proc generateBuildID_Verilog {} { proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
@ -31,5 +22,48 @@ proc generateBuildID_Verilog {} {
post_message "Time: $buildTime" post_message "Time: $buildTime"
} }
# Comment out this line to prevent the process from automatically executing when the file is sourced: # Build CDF file
generateBuildID_Verilog # Sorgelig - 17/2/2018
proc generateCDF {revision device outpath} {
set outputFileName "jtag.cdf"
set outputFile [open $outputFileName "w"]
puts $outputFile "JedecChain;"
puts $outputFile " FileRevision(JESD32A);"
puts $outputFile " DefaultMfr(6E);"
puts $outputFile ""
puts $outputFile " P ActionCode(Ign)"
puts $outputFile " Device PartName(SOCVHPS) MfrSpec(OpMask(0));"
puts $outputFile " P ActionCode(Cfg)"
puts $outputFile " Device PartName($device) Path(\"$outpath/\") File(\"$revision.sof\") MfrSpec(OpMask(1));"
puts $outputFile "ChainEnd;"
puts $outputFile ""
puts $outputFile "AlteraBegin;"
puts $outputFile " ChainType(JTAG);"
puts $outputFile "AlteraEnd;"
}
set project_name [lindex $quartus(args) 1]
set revision [lindex $quartus(args) 2]
if {[project_exists $project_name]} {
if {[string equal "" $revision]} {
project_open $project_name -revision [get_current_revision $project_name]
} else {
project_open $project_name -revision $revision
}
} else {
post_message -type error "Project $project_name does not exist"
exit
}
set device [get_global_assignment -name DEVICE]
set outpath [get_global_assignment -name PROJECT_OUTPUT_DIRECTORY]
if [is_project_open] {
project_close
}
generateBuildID_Verilog
generateCDF $revision $device $outpath

153
sys/ddram.sv
View File

@ -1,153 +0,0 @@
//
// ddram.v
//
// DE10-nano DDR3 memory interface
//
// Copyright (c) 2017 Sorgelig
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ------------------------------------------
//
module ddram
(
input RESET,
input DDRAM_CLK,
input DDRAM_BUSY,
output [7:0] DDRAM_BURSTCNT,
output [28:0] DDRAM_ADDR,
input [63:0] DDRAM_DOUT,
input DDRAM_DOUT_READY,
output DDRAM_RD,
output [63:0] DDRAM_DIN,
output [7:0] DDRAM_BE,
output DDRAM_WE,
input wb_clk, // chipset clock to which sdram state machine is synchonized
input [31:0] wb_dat_i, // data input from chipset/cpu
output reg [31:0] wb_dat_o, // data output to chipset/cpu
input [27:0] wb_adr, // lower 2 bits are ignored.
input [3:0] wb_sel, //
input [2:0] wb_cti, // cycle type.
input wb_stb, //
input wb_cyc, // cpu/chipset requests cycle
input wb_we, // cpu/chipset requests write
output reg wb_ack
);
assign DDRAM_BURSTCNT = burst;
assign DDRAM_BE = ({wb_sel&{4{wb_adr[2]}},wb_sel&{4{~wb_adr[2]}}}) | {8{ram_read}};
assign DDRAM_ADDR = {4'b0011, wb_adr[27:3]}; // RAM at 0x30000000
assign DDRAM_DIN = {wb_dat_i,wb_dat_i};
assign DDRAM_RD = ram_read;
assign DDRAM_WE = ram_write;
reg [31:0] ram_q[4];
reg ram_read;
reg ram_write;
reg op_req = 0, op_ack = 0;
reg op_we;
always @(posedge DDRAM_CLK)
begin
reg state = 0;
reg opr;
reg [7:0] c;
opr <= op_req;
if(RESET)
begin
state <= 0;
ram_write <= 0;
ram_read <= 0;
end
else
if(!DDRAM_BUSY)
begin
ram_write <= 0;
ram_read <= 0;
case(state)
0: if(op_ack != opr) begin
ram_write <= op_we;
ram_read <= ~op_we;
state <= 1;
c <= 1;
end
1: if(op_we)
begin
op_ack <= opr;
state <= 0;
end
else
if(DDRAM_DOUT_READY) begin
if(c[1]) {ram_q[3], ram_q[2]} <= DDRAM_DOUT;
else {ram_q[1], ram_q[0]} <= DDRAM_DOUT;
c <= c + 1'd1;
if(c >= burst) begin
state <= 0;
op_ack <= opr;
end
end
endcase
end
end
reg [7:0] burst;
always @(negedge wb_clk) begin
reg ack = 0;
reg state = 0;
reg [1:0] sz;
reg [1:0] cnt;
ack <= op_ack;
if(RESET) begin
state <= 0;
wb_ack <= 0;
end
else
case(state)
0: begin
wb_ack <= 0;
if(~wb_ack & wb_stb & wb_cyc) begin
op_we <= wb_we;
sz <= 0;
burst <= 1;
if((wb_cti == 2) && ~wb_we) begin
sz <= 3;
burst <= 2;
end
cnt <= wb_adr[2];
op_req <= ~op_req;
state <= 1;
end
end
1: if(ack == op_req)
begin
wb_ack <= 1;
if(~op_we) wb_dat_o <= ram_q[cnt];
cnt <= cnt + 1'd1;
if(cnt >= sz) state <= 0;
end
endcase
end
endmodule

113
sys/hdmi_config.sv
View File

@ -5,19 +5,8 @@ module hdmi_config
input iCLK, input iCLK,
input iRST_N, input iRST_N,
// 0 - 480i input dvi_mode,
// 1 - 480p input audio_96k,
// 2 - 576i
// 3 - 576p
// 4 - 720p
// 5-7 - reserved
input [2:0] iRES,
// 0 - 4:3
// 1 - 16:9
input iAR,
input audio_48k,
// I2C Side // I2C Side
output I2C_SCL, output I2C_SCL,
@ -31,7 +20,7 @@ wire mI2C_ACK;
reg [15:0] LUT_DATA; reg [15:0] LUT_DATA;
reg [7:0] LUT_INDEX = 0; reg [7:0] LUT_INDEX = 0;
I2C_Controller #(50_000_000, 400_000) i2c_av i2c #(50_000_000, 20_000) i2c_av
( (
.CLK(iCLK), .CLK(iCLK),
@ -72,32 +61,20 @@ always@(posedge iCLK or negedge iRST_N) begin
end end
end end
wire [15:0] res480i[6] = '{'h35_1D, 'h36_92, 'h37_05, 'h38_A0, 'h39_0F, 'h3A_00};
wire [15:0] res480p[6] = '{'h35_1F, 'h36_E8, 'h37_05, 'h38_A0, 'h39_1E, 'h3A_00};
wire [15:0] res576i[6] = '{'h35_20, 'h36_D6, 'h37_05, 'h38_A0, 'h39_12, 'h3A_00};
wire [15:0] res576p[6] = '{'h35_20, 'h36_EC, 'h37_05, 'h38_A0, 'h39_24, 'h3A_00};
wire [15:0] res720p[6] = '{'h35_40, 'h36_D9, 'h37_0A, 'h38_00, 'h39_2D, 'h3A_00};
reg [15:0] resVar[6];
always_comb begin
case(iRES)
0: resVar <= res480i;
1: resVar <= res480p;
2: resVar <= res576i;
3: resVar <= res576p;
4: resVar <= res720p;
default: resVar <= res720p;
endcase
end
//////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////
///////////////////// Config Data LUT ////////////////////////// ///////////////////// Config Data LUT //////////////////////////
wire [15:0] init_data[58] = wire [15:0] init_data[58] =
'{ '{
16'h4110, // Power Down control
16'h9803, // ADI required Write. 16'h9803, // ADI required Write.
{8'hD6, 8'b1100_0000}, // [7:6] HPD Control...
// 00 = HPD is from both HPD pin or CDC HPD
// 01 = HPD is from CDC HPD
// 10 = HPD is from HPD pin
// 11 = HPD is always high
16'h4110, // Power Down control
16'h9A70, // ADI required Write. 16'h9A70, // ADI required Write.
16'h9C30, // ADI required Write. 16'h9C30, // ADI required Write.
{8'h9D, 8'b0110_0001}, // [7:4] must be b0110!. {8'h9D, 8'b0110_0001}, // [7:4] must be b0110!.
@ -108,13 +85,13 @@ wire [15:0] init_data[58] =
16'hE0D0, // ADI required Write. 16'hE0D0, // ADI required Write.
resVar[0], 16'h35_40,
resVar[1], 16'h36_D9,
resVar[2], 16'h37_0A,
resVar[3], 16'h38_00,
resVar[4], 16'h39_2D,
resVar[5], 16'h3A_00,
{8'h16, 8'b0011_1000}, // Output Format 444 [7]=0. {8'h16, 8'b0011_1000}, // Output Format 444 [7]=0.
// [6] must be 0! // [6] must be 0!
// Colour Depth for Input Video data [5:4] b11 = 8-bit. // Colour Depth for Input Video data [5:4] b11 = 8-bit.
@ -122,39 +99,15 @@ wire [15:0] init_data[58] =
// DDR Input Edge falling [1]=0 (not using DDR atm). // DDR Input Edge falling [1]=0 (not using DDR atm).
// Output Colour Space RGB [0]=0. // Output Colour Space RGB [0]=0.
// {8'h16, 8'b1011_0101}, // Output Format 422 [7]=1. {8'h17, 8'b01100010}, // Aspect ratio 16:9 [1]=1, 4:3 [1]=0
// [6] must be 0!
// Colour Depth for Input Video data [5:4] b11 = 8-bit.
// Input Style [3:2] b01 = Style 2.
// DDR Input Edge falling [1]=0 (not using DDR atm).
// Output Colour Space YPrPb [0]=1.
// {8'h17, 8'b0110_0000}, // Aspect ratio 4:3 [1]=0. DE Generation DISabled [0]=0.
// Vsync polarity HIGH [6]=0, LOW [6]=1.
// Hsync polarity HIGH [5]=0, LOW [5]=1.
// {8'h17, 8'b0110_0001}, // Aspect ratio 4:3 [1]=0. DE Generation ENabled [0]=1.
// {8'h17, 8'b0110_0011}, // Aspect ratio 16:9 [1]=1. DE Generation ENabled [0]=1.
{8'h17, 6'b011000, iAR, 1'b0}, // Aspect ratio 16:9 [1]=1, 4:3 [1]=0
{8'h18, 8'b0100_0110}, // CSC disabled [7]=0. {8'h18, 8'b0100_0110}, // CSC disabled [7]=0.
// CSC Scaling Factor [6:5] b10 = +/- 4.0, -16384 - 16380. // CSC Scaling Factor [6:5] b10 = +/- 4.0, -16384 - 16380.
// CSC Equation 3 [4:0] b00110. // CSC Equation 3 [4:0] b00110.
// {8'h3B, 8'b0000_1010}, // Pixel repetition [6:5] b00 AUTO. [4:3] b01 x2 mult of input clock. [2:1] b01 x2 pixel rep to send to HDMI Rx.
{8'h3B, 8'b0000_0000}, // Pixel repetition [6:5] b00 AUTO. [4:3] b00 x1 mult of input clock. [2:1] b00 x1 pixel rep to send to HDMI Rx. {8'h3B, 8'b0000_0000}, // Pixel repetition [6:5] b00 AUTO. [4:3] b00 x1 mult of input clock. [2:1] b00 x1 pixel rep to send to HDMI Rx.
// {8'h3B, 8'b0110_1010}, // Pixel repetition [6:5] b11 MANUAL. [4:3] b01 x2 mult of input clock. [2:1] b01 x2 pixel rep to send to HDMI Rx.
// {8'h3C, 8'b0000_0110}, // VIC#6 480i-60, 2x clk, 4:3.
// {8'h3C, 8'b0000_0001}, // VIC#1 VGA (640x480), 2x clk, 4:3.
// {8'h3C, 8'b0000_0010}, // VIC#2 480p (720x480), 2x clk, 4:3.
16'h4000, // General Control Packet Enable 16'h4000, // General Control Packet Enable
{8'h48, 8'b0000_1000}, // [6]=0 Normal bus order! {8'h48, 8'b0000_1000}, // [6]=0 Normal bus order!
@ -165,24 +118,20 @@ wire [15:0] init_data[58] =
16'h4C00, // ADI required Write. 16'h4C00, // ADI required Write.
{8'h55, 8'b0001_0000}, // [7] must be 0!. Set RGB444 in AVinfo Frame [6:5], Set active format [4]. {8'h55, 8'b0001_0000}, // [7] must be 0!. Set RGB444 in AVinfo Frame [6:5], Set active format [4].
// {8'h55, 8'b0101_0000}, // [7] must be 0!. Set YCbCr 444 in AVinfo Frame [6:5], Set active format [4].
// {8'h55, 8'b0011_0001}, // [7] must be 0!. Set YCbCr 422 in AVinfo Frame [6:5].
// AVI InfoFrame Valid [4]. // AVI InfoFrame Valid [4].
// Bar Info [3:2] b00 Bars invalid. b01 Bars vertical. b10 Bars horizontal. b11 Bars both. // Bar Info [3:2] b00 Bars invalid. b01 Bars vertical. b10 Bars horizontal. b11 Bars both.
// Scan Info [1:0] b00 (No data). b01 TV. b10 PC. b11 None. // Scan Info [1:0] b00 (No data). b01 TV. b10 PC. b11 None.
// {8'h94, 8'b1000_0000}, // [7]=1 HPD Interrupt ENabled.
16'h7301, 16'h7301,
16'h9400, // HPD Interrupt disabled. {8'h94, 8'b1000_0000}, // [7]=1 HPD Interrupt ENabled.
16'h9902, // ADI required Write. 16'h9902, // ADI required Write.
16'h9B18, // ADI required Write. 16'h9B18, // ADI required Write.
16'h9F00, // ADI required Write. 16'h9F00, // ADI required Write.
{8'hA1, 8'b0100_0000}, // [6]=1 Monitor Sense Power Down DISabled. {8'hA1, 8'b0000_0000}, // [6]=1 Monitor Sense Power Down DISabled.
16'hA408, // ADI required Write. 16'hA408, // ADI required Write.
16'hA504, // ADI required Write. 16'hA504, // ADI required Write.
@ -193,7 +142,7 @@ wire [15:0] init_data[58] =
16'hAA00, // ADI required Write. 16'hAA00, // ADI required Write.
16'hAB40, // ADI required Write. 16'hAB40, // ADI required Write.
{8'hAF, 8'b0001_0110}, // [7]=0 HDCP Disabled. {8'hAF, 6'b0001_01,~dvi_mode,1'b0}, // [7]=0 HDCP Disabled.
// [6:5] must be b00! // [6:5] must be b00!
// [4]=1 Current frame IS HDCP encrypted!??? (HDCP disabled anyway?) // [4]=1 Current frame IS HDCP encrypted!??? (HDCP disabled anyway?)
// [3:2] must be b01! // [3:2] must be b01!
@ -214,12 +163,6 @@ wire [15:0] init_data[58] =
16'hBB00, // ADI required Write. 16'hBB00, // ADI required Write.
{8'hD6, 8'b1100_0000}, // [7:6] HPD Control...
// 00 = HPD is from both HPD pin or CDC HPD
// 01 = HPD is from CDC HPD
// 10 = HPD is from HPD pin
// 11 = HPD is always high
16'hDE9C, // ADI required Write. 16'hDE9C, // ADI required Write.
16'hE460, // ADI required Write. 16'hE460, // ADI required Write.
16'hFA7D, // Nbr of times to search for good phase 16'hFA7D, // Nbr of times to search for good phase
@ -239,18 +182,12 @@ wire [15:0] init_data[58] =
{8'h0D, 8'b0001_0000}, // [4:0] I2S Bit (Word) Width for Right-Justified. {8'h0D, 8'b0001_0000}, // [4:0] I2S Bit (Word) Width for Right-Justified.
{8'h14, 8'b0000_0010}, // [3:0] Audio Word Length. b0010 = 16 bits. {8'h14, 8'b0000_0010}, // [3:0] Audio Word Length. b0010 = 16 bits.
{8'h15, ~audio_48k, 7'b010_0000}, // I2S Sampling Rate [7:4]. b0000 = (44.1KHz). b0010 = 48KHz. {8'h15, audio_96k, 7'b010_0000}, // I2S Sampling Rate [7:4]. b0000 = (44.1KHz). b0010 = 48KHz.
// Input ID [3:1] b000 (0) = 24-bit RGB 444 or YCrCb 444 with Separate Syncs. // Input ID [3:1] b000 (0) = 24-bit RGB 444 or YCrCb 444 with Separate Syncs.
// {8'h15, 8'b0010_0001}, // I2S Sampling Rate [7:4]. b0000 = (44.1KHz). b0010 = 48KHz.
// Input ID [3:0] b0001 (1) = 16, 20, 24 bit YCbCr 4:2:2 with Separate Syncs.
// {8'h15, 8'b0010_0011}, // I2S Sampling Rate [7:4]. b0000 = (44.1KHz). b0010 = 48KHz.
// Input ID [3:0] b0011 (3) = 16, 20, 24 bit YCbCr 4:2:2 (2x Pixel Clock, with Separate Syncs).
// Audio Clock Config // Audio Clock Config
16'h0100, // 16'h0100, //
audio_48k ? 16'h0218 : 16'h0230, // Set N Value 12288/6144 audio_96k ? 16'h0230 : 16'h0218, // Set N Value 12288/6144
16'h0300, // 16'h0300, //
16'h0701, // 16'h0701, //

395
sys/hdmi_lite.sv Normal file
View File

@ -0,0 +1,395 @@
//============================================================================
//
// HDMI Lite output module
// Copyright (C) 2017 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
//============================================================================
module hdmi_lite
(
input reset,
input clk_video,
input ce_pixel,
input video_vs,
input video_de,
input [23:0] video_d,
input clk_hdmi,
input hdmi_hde,
input hdmi_vde,
output reg hdmi_de,
output [23:0] hdmi_d,
input [11:0] screen_w,
input [11:0] screen_h,
input quadbuf,
// 0-3 => scale 1-4
input [1:0] scale_x,
input [1:0] scale_y,
input scale_auto,
input clk_vbuf,
output [27:0] vbuf_address,
input [127:0] vbuf_readdata,
output [127:0] vbuf_writedata,
output [7:0] vbuf_burstcount,
output [15:0] vbuf_byteenable,
input vbuf_waitrequest,
input vbuf_readdatavalid,
output reg vbuf_read,
output reg vbuf_write
);
localparam [7:0] burstsz = 64;
reg [1:0] nbuf = 0;
wire [27:0] read_buf = {4'd2, 3'b000, (quadbuf ? nbuf-2'd1 : 2'b00), 19'd0};
wire [27:0] write_buf = {4'd2, 3'b000, (quadbuf ? nbuf+2'd1 : 2'b00), 19'd0};
assign vbuf_address = vbuf_write ? vbuf_waddress : vbuf_raddress;
assign vbuf_burstcount = vbuf_write ? vbuf_wburstcount : vbuf_rburstcount;
wire [95:0] hf_out;
wire [7:0] hf_usedw;
reg hf_reset = 0;
vbuf_fifo out_fifo
(
.aclr(hf_reset),
.wrclk(clk_vbuf),
.wrreq(vbuf_readdatavalid),
.data({vbuf_readdata[96+:24],vbuf_readdata[64+:24],vbuf_readdata[32+:24],vbuf_readdata[0+:24]}),
.wrusedw(hf_usedw),
.rdclk(~clk_hdmi),
.rdreq(hf_rdreq),
.q(hf_out)
);
reg [11:0] rd_stride;
wire [7:0] rd_burst = (burstsz < rd_stride) ? burstsz : rd_stride[7:0];
reg [27:0] vbuf_raddress;
reg [7:0] vbuf_rburstcount;
always @(posedge clk_vbuf) begin
reg [18:0] rdcnt;
reg [7:0] bcnt;
reg vde1, vde2;
reg [1:0] mcnt;
reg [1:0] my;
reg [18:0] fsz;
reg [11:0] strd;
vde1 <= hdmi_vde;
vde2 <= vde1;
if(vbuf_readdatavalid) begin
rdcnt <= rdcnt + 1'd1;
if(bcnt) bcnt <= bcnt - 1'd1;
vbuf_raddress <= vbuf_raddress + 1'd1;
end
if(!bcnt && reading) reading <= 0;
vbuf_read <= 0;
if(~vbuf_waitrequest) begin
if(!hf_reset && rdcnt<fsz && !bcnt && hf_usedw < burstsz && allow_rd) begin
vbuf_read <= 1;
reading <= 1;
bcnt <= rd_burst;
vbuf_rburstcount <= rd_burst;
rd_stride <= rd_stride - rd_burst;
if(!(rd_stride - rd_burst)) rd_stride <= strd;
if(!rdcnt) begin
vbuf_raddress <= read_buf;
mcnt <= my;
end
else if (rd_stride == strd) begin
mcnt <= mcnt - 1'd1;
if(!mcnt) mcnt <= my;
else vbuf_raddress <= vbuf_raddress - strd;
end
end
end
hf_reset <= 0;
if(vde2 & ~vde1) begin
hf_reset <= 1;
rdcnt <= 0;
bcnt <= 0;
rd_stride <= stride;
strd <= stride;
fsz <= framesz;
my <= mult_y;
end
end
reg [11:0] off_x, off_y;
reg [11:0] x, y;
reg [11:0] vh_height;
reg [11:0] vh_width;
reg [1:0] pcnt;
reg [1:0] hload;
wire hf_rdreq = (x>=off_x) && (x<(vh_width+off_x)) && (y>=off_y) && (y<(vh_height+off_y)) && !hload && !pcnt;
wire de_in = hdmi_hde & hdmi_vde;
always @(posedge clk_hdmi) begin
reg [71:0] px_out;
reg [1:0] mx;
reg vde;
vde <= hdmi_vde;
if(vde & ~hdmi_vde) begin
off_x <= (screen_w>v_width) ? (screen_w - v_width)>>1 : 12'd0;
off_y <= (screen_h>v_height) ? (screen_h - v_height)>>1 : 12'd0;
vh_height <= v_height;
vh_width <= v_width;
mx <= mult_x;
end
pcnt <= pcnt + 1'd1;
if(pcnt == mx) begin
pcnt <= 0;
hload <= hload + 1'd1;
end
if(~de_in || x<off_x || y<off_y) begin
hload <= 0;
pcnt <= 0;
end
hdmi_de <= de_in;
x <= x + 1'd1;
if(~hdmi_de & de_in) x <= 0;
if(hdmi_de & ~de_in) y <= y + 1'd1;
if(~hdmi_vde) y <= 0;
if(!pcnt) {px_out, hdmi_d} <= {24'd0, px_out};
if(hf_rdreq) {px_out, hdmi_d} <= hf_out;
end
//////////////////////////////////////////////////////////////////////////////
reg reading = 0;
reg writing = 0;
reg op_split = 0;
always @(posedge clk_vbuf) op_split <= ~op_split;
wire allow_rd = ~reading & ~writing & op_split & ~reset;
wire allow_wr = ~reading & ~writing & ~op_split & ~reset;
//////////////////////////////////////////////////////////////////////////////
reg vf_rdreq = 0;
wire [95:0] vf_out;
assign vbuf_writedata = {8'h00, vf_out[95:72], 8'h00, vf_out[71:48], 8'h00, vf_out[47:24], 8'h00, vf_out[23:0]};
vbuf_fifo in_fifo
(
.aclr(video_vs),
.rdclk(clk_vbuf),
.rdreq(vf_rdreq & ~vbuf_waitrequest),
.q(vf_out),
.wrclk(clk_video),
.wrreq(infifo_wr),
.data({video_de ? video_d : 24'd0, pix_acc})
);
assign vbuf_byteenable = '1;
reg [35:0] addrque[3:0] = '{0,0,0,0};
reg [7:0] flush_size;
reg [27:0] flush_addr;
reg flush_req = 0;
reg flush_ack = 0;
reg [27:0] vbuf_waddress;
reg [7:0] vbuf_wburstcount;
always @(posedge clk_vbuf) begin
reg [7:0] ibcnt = 0;
reg reqd = 0;
reqd <= flush_req;
if(~vbuf_waitrequest) begin
vbuf_write <= vf_rdreq;
if(~vf_rdreq && writing) writing <= 0;
if(!vf_rdreq && !vbuf_write && addrque[0] && allow_wr) begin
{vbuf_waddress, vbuf_wburstcount} <= addrque[0];
ibcnt <= addrque[0][7:0];
addrque[0] <= addrque[1];
addrque[1] <= addrque[2];
addrque[2] <= addrque[3];
addrque[3] <= 0;
vf_rdreq <= 1;
writing <= 1;
end
else if(flush_ack != reqd) begin
if(!addrque[0]) addrque[0] <= {flush_addr, flush_size};
else if(!addrque[1]) addrque[1] <= {flush_addr, flush_size};
else if(!addrque[2]) addrque[2] <= {flush_addr, flush_size};
else if(!addrque[3]) addrque[3] <= {flush_addr, flush_size};
flush_ack <= reqd;
end
if(vf_rdreq) begin
if(ibcnt == 1) vf_rdreq <= 0;
ibcnt <= ibcnt - 1'd1;
end
end
end
reg [11:0] stride;
reg [18:0] framesz;
reg [11:0] v_height;
reg [11:0] v_width;
reg [1:0] mult_x;
reg [1:0] mult_y;
reg [71:0] pix_acc;
wire pix_wr = ce_pixel && video_de;
reg [27:0] cur_addr;
reg [11:0] video_x;
reg [11:0] video_y;
wire infifo_tail = ~video_de && video_x[1:0];
wire infifo_wr = (pix_wr && &video_x[1:0]) || infifo_tail;
wire [1:0] tm_y = (video_y > (screen_h/2)) ? 2'b00 : (video_y > (screen_h/3)) ? 2'b01 : (video_y > (screen_h/4)) ? 2'b10 : 2'b11;
wire [1:0] tm_x = (l1_width > (screen_w/2)) ? 2'b00 : (l1_width > (screen_w/3)) ? 2'b01 : (l1_width > (screen_w/4)) ? 2'b10 : 2'b11;
wire [1:0] tm_xy = (tm_x < tm_y) ? tm_x : tm_y;
wire [1:0] tmf_y = scale_auto ? tm_xy : scale_y;
wire [1:0] tmf_x = scale_auto ? tm_xy : scale_x;
wire [11:0] t_height = video_y + (tmf_y[0] ? video_y : 12'd0) + (tmf_y[1] ? video_y<<1 : 12'd0);
wire [11:0] t_width = l1_width + (tmf_x[0] ? l1_width : 12'd0) + (tmf_x[1] ? l1_width<<1 : 12'd0);
wire [23:0] t_fsz = l1_stride * t_height;
reg [11:0] l1_width;
reg [11:0] l1_stride;
always @(posedge clk_video) begin
reg [7:0] loaded = 0;
reg [11:0] strd = 0;
reg old_de = 0;
reg old_vs = 0;
old_vs <= video_vs;
if(~old_vs & video_vs) begin
cur_addr<= write_buf;
video_x <= 0;
video_y <= 0;
loaded <= 0;
strd <= 0;
nbuf <= nbuf + 1'd1;
stride <= l1_stride;
framesz <= t_fsz[18:0];
v_height<= t_height;
v_width <= t_width;
mult_x <= tmf_x;
mult_y <= tmf_y;
end
if(pix_wr) begin
case(video_x[1:0])
0: pix_acc <= video_d; // zeroes upper bits too
1: pix_acc[47:24] <= video_d;
2: pix_acc[71:48] <= video_d;
3: loaded <= loaded + 1'd1;
endcase
if(video_x<screen_w) video_x <= video_x + 1'd1;
end
old_de <= video_de;
if((!video_x[1:0] && loaded >= burstsz) || (old_de & ~video_de)) begin
if(loaded + infifo_tail) begin
flush_size <= loaded + infifo_tail;
flush_addr <= cur_addr;
flush_req <= ~flush_req;
loaded <= 0;
strd <= strd + loaded;
end
cur_addr <= cur_addr + loaded + infifo_tail;
if(~video_de) begin
if(video_y<screen_h) video_y <= video_y + 1'd1;
video_x <= 0;
strd <= 0;
// measure width by first line (same as VIP)
if(!video_y) begin
l1_width <= video_x;
l1_stride <= strd + loaded + infifo_tail;
end
end
end
end
endmodule
module vbuf_fifo
(
input aclr,
input rdclk,
input rdreq,
output [95:0] q,
input wrclk,
input wrreq,
input [95:0] data,
output [7:0] wrusedw
);
dcfifo dcfifo_component
(
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (q),
.wrusedw (wrusedw),
.eccstatus (),
.rdempty (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull ()
);
defparam
dcfifo_component.intended_device_family = "Cyclone V",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 96,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 5;
endmodule

82
sys/hps_io.v
View File

@ -33,7 +33,7 @@
module hps_io #(parameter STRLEN=0, PS2DIV=2000, WIDE=0, VDNUM=1, PS2WE=0) module hps_io #(parameter STRLEN=0, PS2DIV=2000, WIDE=0, VDNUM=1, PS2WE=0)
( (
input clk_sys, input clk_sys,
inout [43:0] HPS_BUS, inout [44:0] HPS_BUS,
// parameter STRLEN and the actual length of conf_str have to match // parameter STRLEN and the actual length of conf_str have to match
input [(8*STRLEN)-1:0] conf_str, input [(8*STRLEN)-1:0] conf_str,
@ -74,12 +74,15 @@ module hps_io #(parameter STRLEN=0, PS2DIV=2000, WIDE=0, VDNUM=1, PS2WE=0)
output reg ioctl_download = 0, // signal indicating an active download output reg ioctl_download = 0, // signal indicating an active download
output reg [7:0] ioctl_index, // menu index used to upload the file output reg [7:0] ioctl_index, // menu index used to upload the file
output reg ioctl_wr, output reg ioctl_wr,
output reg [23:0] ioctl_addr, // in WIDE mode address will be incremented by 2 output reg [24:0] ioctl_addr, // in WIDE mode address will be incremented by 2
output reg [15:0] ioctl_dout, output reg [DW:0] ioctl_dout,
input ioctl_wait, input ioctl_wait,
// RTC MSM6242B layout // RTC MSM6242B layout
output reg [63:0] RTC, output reg [64:0] RTC,
// Seconds since 1970-01-01 00:00:00
output reg [32:0] TIMESTAMP,
// ps2 keyboard emulation // ps2 keyboard emulation
output ps2_kbd_clk_out, output ps2_kbd_clk_out,
@ -96,7 +99,11 @@ module hps_io #(parameter STRLEN=0, PS2DIV=2000, WIDE=0, VDNUM=1, PS2WE=0)
input ps2_mouse_data_in, input ps2_mouse_data_in,
// ps2 alternative interface. // ps2 alternative interface.
output reg [64:0] ps2_key = 0, // up to 8 bytes per key (pause)
// [8] - extended, [9] - pressed, [10] - toggles with every press/release
output reg [10:0] ps2_key = 0,
// [24] - toggles with every event
output reg [24:0] ps2_mouse = 0 output reg [24:0] ps2_mouse = 0
); );
@ -148,6 +155,7 @@ wire ce_pix = HPS_BUS[41];
wire de = HPS_BUS[40]; wire de = HPS_BUS[40];
wire hs = HPS_BUS[39]; wire hs = HPS_BUS[39];
wire vs = HPS_BUS[38]; wire vs = HPS_BUS[38];
wire vs_hdmi = HPS_BUS[44];
reg [31:0] vid_hcnt = 0; reg [31:0] vid_hcnt = 0;
reg [31:0] vid_vcnt = 0; reg [31:0] vid_vcnt = 0;
@ -219,13 +227,35 @@ always @(posedge clk_100) begin
if(old_de2 & ~old_de) calch <= 0; if(old_de2 & ~old_de) calch <= 0;
end end
reg [31:0] vid_vtime_hdmi;
always @(posedge clk_100) begin
integer vtime;
reg old_vs, old_vs2;
old_vs <= vs_hdmi;
old_vs2 <= old_vs;
vtime <= vtime + 1'd1;
if(~old_vs2 & old_vs) begin
vid_vtime_hdmi <= vtime;
vtime <= 0;
end
end
///////////////////////////////////////////////////////// /////////////////////////////////////////////////////////
reg [31:0] ps2_key_raw = 0;
wire pressed = (ps2_key_raw[15:8] != 8'hf0);
wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
always@(posedge clk_sys) begin always@(posedge clk_sys) begin
reg [15:0] cmd; reg [15:0] cmd;
reg [9:0] byte_cnt; // counts bytes reg [9:0] byte_cnt; // counts bytes
reg [2:0] b_wr; reg [2:0] b_wr;
reg [2:0] stick_idx; reg [2:0] stick_idx;
reg ps2skip = 0;
sd_buff_wr <= b_wr[0]; sd_buff_wr <= b_wr[0];
if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1; if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
@ -234,13 +264,21 @@ always@(posedge clk_sys) begin
{kbd_rd,kbd_we,mouse_rd,mouse_we} <= 0; {kbd_rd,kbd_we,mouse_rd,mouse_we} <= 0;
if(~io_enable) begin if(~io_enable) begin
if(cmd == 4 && !PS2WE) ps2_mouse[24] <= ~ps2_mouse[24]; if(cmd == 4 && !ps2skip) ps2_mouse[24] <= ~ps2_mouse[24];
if(cmd == 5 && !PS2WE) ps2_key[64] <= ~ps2_key[64]; if(cmd == 5 && !ps2skip) begin
ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed
end
if(cmd == 'h22) RTC[64] <= ~RTC[64];
if(cmd == 'h24) TIMESTAMP[32] <= ~TIMESTAMP[32];
cmd <= 0; cmd <= 0;
byte_cnt <= 0; byte_cnt <= 0;
sd_ack <= 0; sd_ack <= 0;
sd_ack_conf <= 0; sd_ack_conf <= 0;
io_dout <= 0; io_dout <= 0;
ps2skip <= 0;
end else begin end else begin
if(io_strobe) begin if(io_strobe) begin
@ -258,7 +296,7 @@ always@(posedge clk_sys) begin
sd_buff_addr <= 0; sd_buff_addr <= 0;
img_mounted <= 0; img_mounted <= 0;
if(io_din == 5) ps2_key[63:0] <= 0; if(io_din == 5) ps2_key_raw <= 0;
end else begin end else begin
case(cmd) case(cmd)
@ -271,7 +309,8 @@ always@(posedge clk_sys) begin
'h04: begin 'h04: begin
mouse_data <= io_din[7:0]; mouse_data <= io_din[7:0];
mouse_we <= 1; mouse_we <= 1;
if(!PS2WE) begin if(&io_din[15:8]) ps2skip <= 1;
if(~&io_din[15:8] & ~ps2skip) begin
case(byte_cnt) case(byte_cnt)
1: ps2_mouse[7:0] <= io_din[7:0]; 1: ps2_mouse[7:0] <= io_din[7:0];
2: ps2_mouse[15:8] <= io_din[7:0]; 2: ps2_mouse[15:8] <= io_din[7:0];
@ -282,7 +321,8 @@ always@(posedge clk_sys) begin
// store incoming ps2 keyboard bytes // store incoming ps2 keyboard bytes
'h05: begin 'h05: begin
if(!PS2WE) ps2_key[63:0] <= {ps2_key[55:0], io_din[7:0]}; if(&io_din[15:8]) ps2skip <= 1;
if(~&io_din[15:8] & ~ps2skip) ps2_key_raw[31:0] <= {ps2_key_raw[23:0], io_din[7:0]};
kbd_data <= io_din[7:0]; kbd_data <= io_din[7:0];
kbd_we <= 1; kbd_we <= 1;
end end
@ -375,8 +415,13 @@ always@(posedge clk_sys) begin
9: io_dout <= vid_vtime[31:16]; 9: io_dout <= vid_vtime[31:16];
10: io_dout <= vid_pix[15:0]; 10: io_dout <= vid_pix[15:0];
11: io_dout <= vid_pix[31:16]; 11: io_dout <= vid_pix[31:16];
12: io_dout <= vid_vtime_hdmi[15:0];
13: io_dout <= vid_vtime_hdmi[31:16];
endcase endcase
end end
//RTC
'h24: TIMESTAMP[(byte_cnt-6'd1)<<4 +:16] <= io_din;
endcase endcase
end end
end end
@ -453,7 +498,6 @@ always@(posedge clk_sys) begin
reg has_cmd; reg has_cmd;
reg [24:0] addr; reg [24:0] addr;
reg wr; reg wr;
reg [7:0] tmp;
ioctl_wr <= wr; ioctl_wr <= wr;
wr <= 0; wr <= 0;
@ -479,20 +523,17 @@ always@(posedge clk_sys) begin
addr <= 0; addr <= 0;
ioctl_download <= 1; ioctl_download <= 1;
end else begin end else begin
ioctl_addr <= addr[24:1]; ioctl_addr <= addr;
ioctl_download <= 0; ioctl_download <= 0;
end end
end end
UIO_FILE_TX_DAT: UIO_FILE_TX_DAT:
begin begin
if(addr[0]) begin ioctl_addr <= addr;
ioctl_addr <= addr[24:1]; ioctl_dout <= io_din[DW:0];
ioctl_dout <= {tmp, io_din[7:0]}; wr <= 1;
wr <= 1; addr <= addr + (WIDE ? 2'd2 : 2'd1);
end
tmp <= io_din[7:0];
addr <= addr + 1'd1;
end end
endcase endcase
end end
@ -515,6 +556,7 @@ module ps2_device #(parameter PS2_FIFO_BITS=5)
input ps2_clk, input ps2_clk,
output reg ps2_clk_out, output reg ps2_clk_out,
output reg ps2_dat_out, output reg ps2_dat_out,
output reg tx_empty,
input ps2_clk_in, input ps2_clk_in,
input ps2_dat_in, input ps2_dat_in,
@ -547,6 +589,8 @@ always@(posedge clk_sys) begin
reg c1,c2,d1; reg c1,c2,d1;
tx_empty <= ((wptr == rptr) && (tx_state == 0));
if(we) begin if(we) begin
fifo[wptr] <= wdata; fifo[wptr] <= wdata;
wptr <= wptr + 1'd1; wptr <= wptr + 1'd1;

2
sys/i2c.v
View File

@ -1,5 +1,5 @@
module I2C_Controller module i2c
( (
input CLK, input CLK,

61
sys/i2s.v
View File

@ -22,16 +22,39 @@ localparam WHOLE_CYCLES = (CLK_RATE) / (AUDIO_RATE*AUDIO_DW*4);
localparam ERROR_BASE = 10000; localparam ERROR_BASE = 10000;
localparam [63:0] ERRORS_PER_BIT = ((CLK_RATE * ERROR_BASE) / (AUDIO_RATE*AUDIO_DW*4)) - (WHOLE_CYCLES * ERROR_BASE); localparam [63:0] ERRORS_PER_BIT = ((CLK_RATE * ERROR_BASE) / (AUDIO_RATE*AUDIO_DW*4)) - (WHOLE_CYCLES * ERROR_BASE);
reg lpf_ce;
wire [AUDIO_DW-1:0] al, ar;
lpf_i2s lpf_l
(
.CLK(clk_sys),
.CE(lpf_ce),
.IDATA(left_chan),
.ODATA(al)
);
lpf_i2s lpf_r
(
.CLK(clk_sys),
.CE(lpf_ce),
.IDATA(right_chan),
.ODATA(ar)
);
always @(posedge clk_sys) begin always @(posedge clk_sys) begin
reg [31:0] count_q; reg [31:0] count_q;
reg [31:0] error_q; reg [31:0] error_q;
reg [7:0] bit_cnt; reg [7:0] bit_cnt;
reg skip = 0;
reg [AUDIO_DW-1:0] left; reg [AUDIO_DW-1:0] left;
reg [AUDIO_DW-1:0] right; reg [AUDIO_DW-1:0] right;
reg msclk; reg msclk;
reg ce; reg ce;
lpf_ce <= 0;
if (reset) begin if (reset) begin
count_q <= 0; count_q <= 0;
@ -64,12 +87,14 @@ always @(posedge clk_sys) begin
if(~half_rate || ce) begin if(~half_rate || ce) begin
msclk <= ~msclk; msclk <= ~msclk;
if(msclk) begin if(msclk) begin
skip <= ~skip;
if(skip) lpf_ce <= 1;
if(bit_cnt >= AUDIO_DW) begin if(bit_cnt >= AUDIO_DW) begin
bit_cnt <= 1; bit_cnt <= 1;
lrclk <= ~lrclk; lrclk <= ~lrclk;
if(lrclk) begin if(lrclk) begin
left <= left_chan; left <= al;
right <= right_chan; right <= ar;
end end
end end
else begin else begin
@ -83,3 +108,29 @@ always @(posedge clk_sys) begin
end end
endmodule endmodule
module lpf_i2s
(
input CLK,
input CE,
input [15:0] IDATA,
output reg [15:0] ODATA
);
reg [511:0] acc;
reg [20:0] sum;
always @(*) begin
integer i;
sum = 0;
for (i = 0; i < 32; i = i+1) sum = sum + {{5{acc[(i*16)+15]}}, acc[i*16 +:16]};
end
always @(posedge CLK) begin
if(CE) begin
acc <= {acc[495:0], IDATA};
ODATA <= sum[20:5];
end
end
endmodule

10
sys/ip/avalon_combiner_hw.tcl
View File

@ -1,11 +1,11 @@
# TCL File Generated by Component Editor 16.1 # TCL File Generated by Component Editor 17.0
# Sat Mar 25 22:55:53 CST 2017 # Wed Dec 13 01:40:49 CST 2017
# DO NOT MODIFY # DO NOT MODIFY
# #
# avalon_combiner "avalon_combiner" v1.0 # avalon_combiner "avalon_combiner" v17.0
# 2017.03.25.22:55:53 # sorgelig 2017.12.13.01:40:49
# #
# #
@ -20,7 +20,7 @@ package require -exact qsys 16.1
# #
set_module_property DESCRIPTION "" set_module_property DESCRIPTION ""
set_module_property NAME avalon_combiner set_module_property NAME avalon_combiner
set_module_property VERSION 1.0 set_module_property VERSION 17.0
set_module_property INTERNAL false set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR sorgelig set_module_property AUTHOR sorgelig

2
sys/ip/de10_hps_hw.tcl
View File

@ -22,7 +22,7 @@ package require -exact altera_terp 1.0
package require quartus::advanced_wysiwyg package require quartus::advanced_wysiwyg
set_module_property NAME altera_hps_lite set_module_property NAME altera_hps_lite
set_module_property VERSION 16.1 set_module_property VERSION 17.0
set_module_property AUTHOR "Altera Corporation/Sorgelig" set_module_property AUTHOR "Altera Corporation/Sorgelig"
set_module_property SUPPORTED_DEVICE_FAMILIES {CYCLONEV ARRIAV} set_module_property SUPPORTED_DEVICE_FAMILIES {CYCLONEV ARRIAV}

52
sys/ip/in_split.v Normal file
View File

@ -0,0 +1,52 @@
// in_split.v
`timescale 1 ps / 1 ps
module in_split (
input wire clk, // input.clk
input wire ce, // .ce
input wire de, // .de
input wire h_sync, // .h_sync
input wire v_sync, // .v_sync
input wire f, // .f
input wire [23:0] data, // .data
output wire vid_clk, // Output.vid_clk
output reg vid_datavalid, // .vid_datavalid
output reg [1:0] vid_de, // .vid_de
output reg [1:0] vid_f, // .vid_f
output reg [1:0] vid_h_sync, // .vid_h_sync
output reg [1:0] vid_v_sync, // .vid_v_sync
output reg [47:0] vid_data, // .vid_data
output wire vid_locked, // .vid_locked
output wire [7:0] vid_color_encoding, // .vid_color_encoding
output wire [7:0] vid_bit_width, // .vid_bit_width
input wire clipping, // .clipping
input wire overflow, // .overflow
input wire sof, // .sof
input wire sof_locked, // .sof_locked
input wire refclk_div, // .refclk_div
input wire padding // .padding
);
assign vid_bit_width = 0;
assign vid_color_encoding = 0;
assign vid_locked = 1;
assign vid_clk = clk;
always @(posedge clk) begin
reg odd = 0;
vid_datavalid <= 0;
if(ce) begin
vid_de[odd] <= de;
vid_f[odd] <= f;
vid_h_sync[odd] <= h_sync;
vid_v_sync[odd] <= v_sync;
if(odd) vid_data[47:24] <= data;
else vid_data[23:0] <= data;
odd <= ~odd;
vid_datavalid <= odd;
end
end
endmodule

104
sys/ip/in_split_hw.tcl Normal file
View File

@ -0,0 +1,104 @@
# TCL File Generated by Component Editor 17.0
# Thu Jan 25 18:50:29 CST 2018
# DO NOT MODIFY
#
# in_split "Input Splitter" v17.0
# Sorgelig 2018.01.25.18:50:29
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module in_split
#
set_module_property DESCRIPTION ""
set_module_property NAME in_split
set_module_property VERSION 17.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR Sorgelig
set_module_property DISPLAY_NAME "Input Splitter"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL in_split
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file in_split.v VERILOG PATH in_split.v TOP_LEVEL_FILE
#
# parameters
#
#
# display items
#
#
# connection point input
#
add_interface input conduit end
set_interface_property input associatedClock ""
set_interface_property input associatedReset ""
set_interface_property input ENABLED true
set_interface_property input EXPORT_OF ""
set_interface_property input PORT_NAME_MAP ""
set_interface_property input CMSIS_SVD_VARIABLES ""
set_interface_property input SVD_ADDRESS_GROUP ""
add_interface_port input clk clk Input 1
add_interface_port input ce ce Input 1
add_interface_port input de de Input 1
add_interface_port input h_sync h_sync Input 1
add_interface_port input v_sync v_sync Input 1
add_interface_port input f f Input 1
add_interface_port input data data Input 24
#
# connection point Output
#
add_interface Output conduit end
set_interface_property Output associatedClock ""
set_interface_property Output associatedReset ""
set_interface_property Output ENABLED true
set_interface_property Output EXPORT_OF ""
set_interface_property Output PORT_NAME_MAP ""
set_interface_property Output CMSIS_SVD_VARIABLES ""
set_interface_property Output SVD_ADDRESS_GROUP ""
add_interface_port Output vid_clk vid_clk Output 1
add_interface_port Output vid_datavalid vid_datavalid Output 1
add_interface_port Output vid_de vid_de Output 2
add_interface_port Output vid_f vid_f Output 2
add_interface_port Output vid_h_sync vid_h_sync Output 2
add_interface_port Output vid_v_sync vid_v_sync Output 2
add_interface_port Output vid_data vid_data Output 48
add_interface_port Output vid_locked vid_locked Output 1
add_interface_port Output vid_color_encoding vid_color_encoding Output 8
add_interface_port Output vid_bit_width vid_bit_width Output 8
add_interface_port Output clipping clipping Input 1
add_interface_port Output overflow overflow Input 1
add_interface_port Output sof sof Input 1
add_interface_port Output sof_locked sof_locked Input 1
add_interface_port Output refclk_div refclk_div Input 1
add_interface_port Output padding padding Input 1

44
sys/ip/out_mix.v Normal file
View File

@ -0,0 +1,44 @@
// out_mix.v
`timescale 1 ps / 1 ps
module out_mix (
input wire clk, // Output.clk
output reg de, // .de
output reg h_sync, // .h_sync
output reg v_sync, // .v_sync
output reg [23:0] data, // .data
output reg vid_clk, // input.vid_clk
input wire [1:0] vid_datavalid, // .vid_datavalid
input wire [1:0] vid_h_sync, // .vid_h_sync
input wire [1:0] vid_v_sync, // .vid_v_sync
input wire [47:0] vid_data, // .vid_data
input wire underflow, // .underflow
input wire vid_mode_change, // .vid_mode_change
input wire [1:0] vid_std, // .vid_std
input wire [1:0] vid_f, // .vid_f
input wire [1:0] vid_h, // .vid_h
input wire [1:0] vid_v // .vid_v
);
reg r_de;
reg r_h_sync;
reg r_v_sync;
reg [23:0] r_data;
always @(posedge clk) begin
vid_clk <= ~vid_clk;
if(~vid_clk) begin
{r_de,de} <= vid_datavalid;
{r_h_sync, h_sync} <= vid_h_sync;
{r_v_sync, v_sync} <= vid_v_sync;
{r_data, data} <= vid_data;
end else begin
de <= r_de;
h_sync <= r_h_sync;
v_sync <= r_v_sync;
data <= r_data;
end
end
endmodule

97
sys/ip/out_mix_hw.tcl Normal file
View File

@ -0,0 +1,97 @@
# TCL File Generated by Component Editor 17.0
# Thu Jan 25 06:51:26 CST 2018
# DO NOT MODIFY
#
# out_mix "Output Mixer" v1.0
# Sorgelig 2018.01.25.06:51:26
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module out_mix
#
set_module_property DESCRIPTION ""
set_module_property NAME out_mix
set_module_property VERSION 17.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR Sorgelig
set_module_property DISPLAY_NAME "Output Mixer"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL out_mix
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file out_mix.v VERILOG PATH out_mix.v TOP_LEVEL_FILE
#
# parameters
#
#
# display items
#
#
# connection point Output
#
add_interface Output conduit end
set_interface_property Output associatedClock ""
set_interface_property Output associatedReset ""
set_interface_property Output ENABLED true
set_interface_property Output EXPORT_OF ""
set_interface_property Output PORT_NAME_MAP ""
set_interface_property Output CMSIS_SVD_VARIABLES ""
set_interface_property Output SVD_ADDRESS_GROUP ""
add_interface_port Output clk clk Input 1
add_interface_port Output de de Output 1
add_interface_port Output h_sync h_sync Output 1
add_interface_port Output v_sync v_sync Output 1
add_interface_port Output data data Output 24
#
# connection point input
#
add_interface input conduit end
set_interface_property input associatedClock ""
set_interface_property input associatedReset ""
set_interface_property input ENABLED true
set_interface_property input EXPORT_OF ""
set_interface_property input PORT_NAME_MAP ""
set_interface_property input CMSIS_SVD_VARIABLES ""
set_interface_property input SVD_ADDRESS_GROUP ""
add_interface_port input vid_clk vid_clk Output 1
add_interface_port input vid_datavalid vid_datavalid Input 2
add_interface_port input vid_h_sync vid_h_sync Input 2
add_interface_port input vid_v_sync vid_v_sync Input 2
add_interface_port input vid_data vid_data Input 48
add_interface_port input underflow underflow Input 1
add_interface_port input vid_mode_change vid_mode_change Input 1
add_interface_port input vid_std vid_std Input 2
add_interface_port input vid_f vid_f Input 2
add_interface_port input vid_h vid_h Input 2
add_interface_port input vid_v vid_v Input 2

38
sys/ip/reset_source.v
View File

@ -1,32 +1,34 @@
// reset_source.v // reset_source.v
// This file was auto-generated as a prototype implementation of a module // This file was auto-generated as a prototype implementation of a module
// created in component editor. It ties off all outputs to ground and // created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something // ignores all inputs. It needs to be edited to make it do something
// useful. // useful.
// //
// This file will not be automatically regenerated. You should check it in // This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it. // to your version control system if you want to keep it.
`timescale 1 ps / 1 ps `timescale 1 ps / 1 ps
module reset_source module reset_source
( (
input wire clk, // clock.clk input wire clk, // clock.clk
input wire reset_hps, // reset_hps.reset input wire reset_hps, // reset_hps.reset
output wire reset_sys, // reset_sys.reset output wire reset_sys, // reset_sys.reset
output wire reset_cold, // reset_cold.reset output wire reset_cold, // reset_cold.reset
input wire cold_req, // reset_ctl.cold_req input wire cold_req, // reset_ctl.cold_req
output wire reset, // .reset output wire reset, // .reset
input wire reset_req, // .reset_req input wire reset_req, // .reset_req
input wire warm_req, // .warm_req input wire reset_vip, // .reset_vip
output wire reset_warm // reset_warm.reset input wire warm_req, // .warm_req
output wire reset_warm // reset_warm.reset
); );
assign reset_cold = cold_req; assign reset_cold = cold_req;
assign reset_warm = warm_req; assign reset_warm = warm_req;
assign reset = reset_sys; wire reset_m = sys_reset | reset_hps | reset_req;
assign reset_sys = sys_reset | reset_hps | reset_req; assign reset = reset_m;
assign reset_sys = reset_m | reset_vip;
reg sys_reset = 1; reg sys_reset = 1;
always @(posedge clk) begin always @(posedge clk) begin

11
sys/ip/reset_source_hw.tcl
View File

@ -1,11 +1,11 @@
# TCL File Generated by Component Editor 16.1 # TCL File Generated by Component Editor 17.0
# Thu Apr 20 14:20:36 CST 2017 # Tue Feb 20 07:55:55 CST 2018
# DO NOT MODIFY # DO NOT MODIFY
# #
# reset_source "reset_source" v1.0 # reset_source "reset_source" v17.0
# Sorgelig 2017.04.20.14:20:36 # Sorgelig 2018.02.20.07:55:55
# #
# #
@ -20,7 +20,7 @@ package require -exact qsys 16.1
# #
set_module_property DESCRIPTION "" set_module_property DESCRIPTION ""
set_module_property NAME reset_source set_module_property NAME reset_source
set_module_property VERSION 1.0 set_module_property VERSION 17.0
set_module_property INTERNAL false set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR Sorgelig set_module_property AUTHOR Sorgelig
@ -114,6 +114,7 @@ add_interface_port reset_ctl cold_req cold_req Input 1
add_interface_port reset_ctl reset reset Output 1 add_interface_port reset_ctl reset reset Output 1
add_interface_port reset_ctl reset_req reset_req Input 1 add_interface_port reset_ctl reset_req reset_req Input 1
add_interface_port reset_ctl warm_req warm_req Input 1 add_interface_port reset_ctl warm_req warm_req Input 1
add_interface_port reset_ctl reset_vip reset_vip Input 1
# #

117
sys/osd.v
View File

@ -7,12 +7,13 @@ module osd
input io_osd, input io_osd,
input io_strobe, input io_strobe,
input [7:0] io_din, input [15:0] io_din,
input clk_video, input clk_video,
input [23:0] din, input [23:0] din,
output [23:0] dout, output [23:0] dout,
input de input de_in,
output reg de_out
); );
parameter OSD_COLOR = 3'd4; parameter OSD_COLOR = 3'd4;
@ -22,14 +23,16 @@ parameter OSD_Y_OFFSET = 12'd0;
localparam OSD_WIDTH = 12'd256; localparam OSD_WIDTH = 12'd256;
localparam OSD_HEIGHT = 12'd64; localparam OSD_HEIGHT = 12'd64;
// this core supports only the display related OSD commands
// of the minimig v1
reg osd_enable; reg osd_enable;
(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[4096]; // the OSD buffer itself (* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[4096];
reg highres = 0; reg highres = 0;
reg info = 0;
reg [8:0] infoh;
reg [8:0] infow;
reg [11:0] infox;
reg [21:0] infoy;
// the OSD has its own SPI interface to the io controller
always@(posedge clk_sys) begin always@(posedge clk_sys) begin
reg [11:0] bcnt; reg [11:0] bcnt;
reg [7:0] cmd; reg [7:0] cmd;
@ -41,24 +44,37 @@ always@(posedge clk_sys) begin
if(~io_osd) begin if(~io_osd) begin
bcnt <= 0; bcnt <= 0;
has_cmd <= 0; has_cmd <= 0;
cmd <= 0;
if(cmd[7:4] == 4) osd_enable <= cmd[0];
end else begin end else begin
if(~old_strobe & io_strobe) begin if(~old_strobe & io_strobe) begin
if(!has_cmd) begin if(!has_cmd) begin
has_cmd <= 1; has_cmd <= 1;
cmd <= io_din; cmd <= io_din[7:0];
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE // command 0x40: OSDCMDENABLE, OSDCMDDISABLE
if(io_din[7:4] == 4'b0100) begin if(io_din[7:4] == 4) begin
osd_enable <= io_din[0];
if(!io_din[0]) highres <= 0; if(!io_din[0]) highres <= 0;
info <= io_din[2];
bcnt <= 0;
end end
bcnt <= {io_din[3:0], 8'h00};
if(io_din[7:3] == 5'b00101) highres <= 1;
end else begin
// command 0x20: OSDCMDWRITE // command 0x20: OSDCMDWRITE
if(cmd[7:4] == 4'b0010) begin if(io_din[7:4] == 2) begin
osd_buffer[bcnt] <= io_din; if(io_din[3]) highres <= 1;
bcnt <= bcnt + 1'd1; bcnt <= {io_din[3:0], 8'h00};
end end
end else begin
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
if(cmd[7:4] == 4) begin
if(bcnt == 0) infox <= io_din[11:0];
if(bcnt == 1) infoy <= io_din[11:0];
if(bcnt == 2) infow <= {io_din[5:0], 3'b000};
if(bcnt == 3) infoh <= {io_din[5:0], 3'b000};
end
// command 0x20: OSDCMDWRITE
if(cmd[7:4] == 2) osd_buffer[bcnt] <= io_din[7:0];
bcnt <= bcnt + 1'd1;
end end
end end
end end
@ -71,15 +87,15 @@ always @(negedge clk_video) begin
reg deD; reg deD;
cnt <= cnt + 1; cnt <= cnt + 1;
deD <= de; deD <= de_in;
pixcnt <= pixcnt + 1; pixcnt <= pixcnt + 1;
if(pixcnt == pixsz) pixcnt <= 0; if(pixcnt == pixsz) pixcnt <= 0;
ce_pix <= !pixcnt; ce_pix <= !pixcnt;
if(~deD && de) cnt <= 0; if(~deD && de_in) cnt <= 0;
if(deD && ~de) begin if(deD && ~de_in) begin
pixsz <= (((cnt+1'b1) >> 9) > 1) ? (((cnt+1'b1) >> 9) - 1) : 0; pixsz <= (((cnt+1'b1) >> 9) > 1) ? (((cnt+1'b1) >> 9) - 1) : 0;
pixcnt <= 0; pixcnt <= 0;
end end
@ -93,7 +109,8 @@ reg [7:0] osd_byte;
reg [21:0] osd_vcnt; reg [21:0] osd_vcnt;
reg [21:0] fheight; reg [21:0] fheight;
wire [21:0] hrheight = (OSD_HEIGHT<<highres); reg [21:0] finfoy;
wire [21:0] hrheight = info ? infoh : (OSD_HEIGHT<<highres);
always @(posedge clk_video) begin always @(posedge clk_video) begin
reg deD; reg deD;
@ -102,34 +119,43 @@ always @(posedge clk_video) begin
if(ce_pix) begin if(ce_pix) begin
deD <= de; deD <= de_in;
if(~&h_cnt) h_cnt <= h_cnt + 1'd1; if(~&h_cnt) h_cnt <= h_cnt + 1'd1;
// falling edge of de // falling edge of de
if(!de && deD) dsp_width <= h_cnt[21:0]; if(!de_in && deD) dsp_width <= h_cnt[21:0];
// rising edge of de // rising edge of de
if(de && !deD) begin if(de_in && !deD) begin
v_cnt <= v_cnt + 1'd1; v_cnt <= v_cnt + 1'd1;
if(h_cnt > {dsp_width, 2'b00}) begin if(h_cnt > {dsp_width, 2'b00}) begin
v_cnt <= 0; v_cnt <= 0;
dsp_height <= v_cnt; dsp_height <= v_cnt;
if(v_cnt<320) begin if(osd_enable) begin
multiscan <= 0; if(v_cnt<320) begin
fheight <= hrheight; multiscan <= 0;
end fheight <= hrheight;
else if(v_cnt<640) begin finfoy <= infoy;
multiscan <= 1; end
fheight <= hrheight << 1; else if(v_cnt<640) begin
end multiscan <= 1;
else if(v_cnt<960) begin fheight <= hrheight << 1;
multiscan <= 2; finfoy <= infoy << 1;
fheight <= hrheight + (hrheight<<1); end
else if(v_cnt<960) begin
multiscan <= 2;
fheight <= hrheight + (hrheight<<1);
finfoy <= infoy + (infoy << 1);
end
else begin
multiscan <= 3;
fheight <= hrheight << 2;
finfoy <= infoy << 2;
end
end end
else begin else begin
multiscan <= 3; fheight <= 0;
fheight <= hrheight << 2;
end end
end end
h_cnt <= 0; h_cnt <= 0;
@ -147,22 +173,27 @@ always @(posedge clk_video) begin
end end
// area in which OSD is being displayed // area in which OSD is being displayed
wire [21:0] h_osd_start = ((dsp_width - OSD_WIDTH)>>1) + OSD_X_OFFSET; wire [21:0] h_osd_start = info ? infox : ((dsp_width - OSD_WIDTH)>>1) + OSD_X_OFFSET;
wire [21:0] h_osd_end = h_osd_start + OSD_WIDTH; wire [21:0] h_osd_end = info ? (h_osd_start + infow) : (h_osd_start + OSD_WIDTH);
wire [21:0] v_osd_start = ((dsp_height- fheight)>>1) + OSD_Y_OFFSET; wire [21:0] v_osd_start = info ? finfoy : ((dsp_height- fheight)>>1) + OSD_Y_OFFSET;
wire [21:0] v_osd_end = v_osd_start + fheight; wire [21:0] v_osd_end = v_osd_start + fheight;
wire [21:0] osd_hcnt = h_cnt[21:0] - h_osd_start + 1'd1; wire [21:0] osd_hcnt = h_cnt[21:0] - h_osd_start + 1'd1;
wire osd_de = osd_enable && wire osd_de = osd_enable && fheight &&
(h_cnt >= h_osd_start) && (h_cnt < h_osd_end) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
(v_cnt >= v_osd_start) && (v_cnt < v_osd_end); (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
wire osd_pixel = osd_byte[osd_vcnt[2:0]]; wire osd_pixel = osd_byte[osd_vcnt[2:0]];
reg [23:0] rdout;
assign dout = !osd_de ? din : {{osd_pixel, osd_pixel, OSD_COLOR[2], din[23:19]}, assign dout = rdout;
always @(posedge clk_video) begin
rdout <= !osd_de ? din : {{osd_pixel, osd_pixel, OSD_COLOR[2], din[23:19]},
{osd_pixel, osd_pixel, OSD_COLOR[1], din[15:11]}, {osd_pixel, osd_pixel, OSD_COLOR[1], din[15:11]},
{osd_pixel, osd_pixel, OSD_COLOR[0], din[7:3]}}; {osd_pixel, osd_pixel, OSD_COLOR[0], din[7:3]}};
de_out <= de_in;
end
endmodule endmodule

164
sys/pll_hdmi.qip
View File

@ -31,7 +31,9 @@ set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPO
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU=" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s=" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ=" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2ZyYWN0aW9uYWxfY291dA==::MzI=::cGxsX2ZyYWN0aW9uYWxfY291dA=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::cGxsX2RzbV9vdXRfc2Vs"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU=" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::ZmFsc2U=::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA==" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::ZmFsc2U=::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
@ -41,11 +43,11 @@ set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPO
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ==" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::NzQuMjU=::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MTQ4LjU=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MzkwODQyMDE1Mw==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MzkwODQyMDE1Mw==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::Ng==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::Mw==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
@ -53,7 +55,7 @@ set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPO
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::NjUuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
@ -65,7 +67,7 @@ set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPO
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MjcuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
@ -256,7 +258,7 @@ set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPO
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::NzQuMjUwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MTQ4LjUwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA=" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
@ -312,13 +314,157 @@ set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPO
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ=" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ=" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA==" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::dHJ1ZQ==::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU=" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::Q3ljbG9uZSBW::UExMIFRZUEU="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU=" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::UmVjb25maWd1cmFibGU=::UExMIFNVQlRZUEU="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bV9jbnRfaGlfZGl2::NA==::bV9jbnRfaGlfZGl2"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bV9jbnRfbG9fZGl2::NA==::bV9jbnRfbG9fZGl2"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bl9jbnRfaGlfZGl2::MjU2::bl9jbnRfaGlfZGl2"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bl9jbnRfbG9fZGl2::MjU2::bl9jbnRfbG9fZGl2"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bV9jbnRfYnlwYXNzX2Vu::ZmFsc2U=::bV9jbnRfYnlwYXNzX2Vu"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bl9jbnRfYnlwYXNzX2Vu::dHJ1ZQ==::bl9jbnRfYnlwYXNzX2Vu"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bV9jbnRfb2RkX2Rpdl9kdXR5X2Vu::ZmFsc2U=::bV9jbnRfb2RkX2Rpdl9kdXR5X2Vu"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bl9jbnRfb2RkX2Rpdl9kdXR5X2Vu::ZmFsc2U=::bl9jbnRfb2RkX2Rpdl9kdXR5X2Vu"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MA==::Mg==::Y19jbnRfaGlfZGl2MA=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MA==::MQ==::Y19jbnRfbG9fZGl2MA=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDA=::MQ==::Y19jbnRfcHJzdDA="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qw::MA==::Y19jbnRfcGhfbXV4X3Byc3Qw"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMA==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMA=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMA==::ZmFsc2U=::Y19jbnRfYnlwYXNzX2VuMA=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMA==::dHJ1ZQ==::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMA=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MQ==::MQ==::Y19jbnRfaGlfZGl2MQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MQ==::MQ==::Y19jbnRfbG9fZGl2MQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE=::MQ==::Y19jbnRfcHJzdDE="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qx::MA==::Y19jbnRfcGhfbXV4X3Byc3Qx"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMQ==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMQ==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMQ==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Mg==::MQ==::Y19jbnRfaGlfZGl2Mg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Mg==::MQ==::Y19jbnRfbG9fZGl2Mg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDI=::MQ==::Y19jbnRfcHJzdDI="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qy::MA==::Y19jbnRfcGhfbXV4X3Byc3Qy"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMg==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMg==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMg==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Mw==::MQ==::Y19jbnRfaGlfZGl2Mw=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Mw==::MQ==::Y19jbnRfbG9fZGl2Mw=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDM=::MQ==::Y19jbnRfcHJzdDM="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qz::MA==::Y19jbnRfcGhfbXV4X3Byc3Qz"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMw==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMw=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMw==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMw=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMw==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMw=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2NA==::MQ==::Y19jbnRfaGlfZGl2NA=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2NA==::MQ==::Y19jbnRfbG9fZGl2NA=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDQ=::MQ==::Y19jbnRfcHJzdDQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q0::MA==::Y19jbnRfcGhfbXV4X3Byc3Q0"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNA==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNA=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNA==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNA=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNA==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNA=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2NQ==::MQ==::Y19jbnRfaGlfZGl2NQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2NQ==::MQ==::Y19jbnRfbG9fZGl2NQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDU=::MQ==::Y19jbnRfcHJzdDU="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q1::MA==::Y19jbnRfcGhfbXV4X3Byc3Q1"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNQ==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNQ==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNQ==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Ng==::MQ==::Y19jbnRfaGlfZGl2Ng=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Ng==::MQ==::Y19jbnRfbG9fZGl2Ng=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDY=::MQ==::Y19jbnRfcHJzdDY="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q2::MA==::Y19jbnRfcGhfbXV4X3Byc3Q2"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNg==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNg==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNg==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Nw==::MQ==::Y19jbnRfaGlfZGl2Nw=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Nw==::MQ==::Y19jbnRfbG9fZGl2Nw=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDc=::MQ==::Y19jbnRfcHJzdDc="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q3::MA==::Y19jbnRfcGhfbXV4X3Byc3Q3"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNw==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNw=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNw==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNw=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNw==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNw=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2OA==::MQ==::Y19jbnRfaGlfZGl2OA=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2OA==::MQ==::Y19jbnRfbG9fZGl2OA=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDg=::MQ==::Y19jbnRfcHJzdDg="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q4::MA==::Y19jbnRfcGhfbXV4X3Byc3Q4"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjOA==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjOA=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuOA==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuOA=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOA==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOA=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2OQ==::MQ==::Y19jbnRfaGlfZGl2OQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2OQ==::MQ==::Y19jbnRfbG9fZGl2OQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDk=::MQ==::Y19jbnRfcHJzdDk="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q5::MA==::Y19jbnRfcGhfbXV4X3Byc3Q5"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjOQ==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjOQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuOQ==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuOQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOQ==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTA=::MQ==::Y19jbnRfaGlfZGl2MTA="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTA=::MQ==::Y19jbnRfbG9fZGl2MTA="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEw::MQ==::Y19jbnRfcHJzdDEw"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMA==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMA=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTA=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTA="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTA=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTA="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTA=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTA="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTE=::MQ==::Y19jbnRfaGlfZGl2MTE="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTE=::MQ==::Y19jbnRfbG9fZGl2MTE="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEx::MQ==::Y19jbnRfcHJzdDEx"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMQ==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTE=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTE="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTE=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTE="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTE=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTE="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTI=::MQ==::Y19jbnRfaGlfZGl2MTI="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTI=::MQ==::Y19jbnRfbG9fZGl2MTI="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEy::MQ==::Y19jbnRfcHJzdDEy"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMg==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTI=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTI="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTI=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTI="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTI=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTI="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTM=::MQ==::Y19jbnRfaGlfZGl2MTM="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTM=::MQ==::Y19jbnRfbG9fZGl2MTM="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEz::MQ==::Y19jbnRfcHJzdDEz"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMw==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMw=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTM=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTM="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTM=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTM="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTM=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTM="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTQ=::MQ==::Y19jbnRfaGlfZGl2MTQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTQ=::MQ==::Y19jbnRfbG9fZGl2MTQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE0::MQ==::Y19jbnRfcHJzdDE0"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNA==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNA=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTQ=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTQ=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTQ=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTU=::MQ==::Y19jbnRfaGlfZGl2MTU="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTU=::MQ==::Y19jbnRfbG9fZGl2MTU="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE1::MQ==::Y19jbnRfcHJzdDE1"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNQ==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTU=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTU="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTU=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTU="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTU=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTU="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTY=::MQ==::Y19jbnRfaGlfZGl2MTY="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTY=::MQ==::Y19jbnRfbG9fZGl2MTY="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE2::MQ==::Y19jbnRfcHJzdDE2"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNg==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTY=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTY="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTY=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTY="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTY=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTY="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTc=::MQ==::Y19jbnRfaGlfZGl2MTc="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTc=::MQ==::Y19jbnRfbG9fZGl2MTc="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE3::MQ==::Y19jbnRfcHJzdDE3"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNw==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNw=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTc=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTc="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTc=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTc="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTc=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTc="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3Zjb19kaXY=::Mg==::cGxsX3Zjb19kaXY="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2NwX2N1cnJlbnQ=::MjA=::cGxsX2NwX2N1cnJlbnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2J3Y3RybA==::NDAwMA==::cGxsX2J3Y3RybA=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX291dHB1dF9jbGtfZnJlcXVlbmN5::NDQ1LjQ5OTk5OSBNSHo=::cGxsX291dHB1dF9jbGtfZnJlcXVlbmN5"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2ZyYWN0aW9uYWxfZGl2aXNpb24=::MzkwODQyMDE1Mw==::cGxsX2ZyYWN0aW9uYWxfZGl2aXNpb24="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bWltaWNfZmJjbGtfdHlwZQ==::bm9uZQ==::bWltaWNfZmJjbGtfdHlwZQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2ZiY2xrX211eF8x::Z2xi::cGxsX2ZiY2xrX211eF8x"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2ZiY2xrX211eF8y::bV9jbnQ=::cGxsX2ZiY2xrX211eF8y"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX21fY250X2luX3NyYw==::cGhfbXV4X2Nsaw==::cGxsX21fY250X2luX3NyYw=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3NsZl9yc3Q=::dHJ1ZQ==::cGxsX3NsZl9yc3Q="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NCw0LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSwzLDMsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMiwyMCw0MDAwLDQ0NS40OTk5OTkgTUh6LDM5MDg0MjAxNTMsbm9uZSxnbGIsbV9jbnQscGhfbXV4X2Nsayx0cnVl::UGFyYW1ldGVyIFZhbHVlcw==" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NCw0LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSwyLDEsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwyLDIwLDQwMDAsNDQ1LjQ5OTk5OSBNSHosMzkwODQyMDE1Myxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU=" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc=" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u" set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"

28
sys/pll_hdmi.v
View File

@ -6,16 +6,20 @@
`timescale 1 ps / 1 ps `timescale 1 ps / 1 ps
module pll_hdmi ( module pll_hdmi (
input wire refclk, // refclk.clk input wire refclk, // refclk.clk
input wire rst, // reset.reset input wire rst, // reset.reset
output wire outclk_0 // outclk0.clk output wire outclk_0, // outclk0.clk
input wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll
output wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll
); );
pll_hdmi_0002 pll_hdmi_inst ( pll_hdmi_0002 pll_hdmi_inst (
.refclk (refclk), // refclk.clk .refclk (refclk), // refclk.clk
.rst (rst), // reset.reset .rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk .outclk_0 (outclk_0), // outclk0.clk
.locked () // (terminated) .reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll
.reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll
.locked () // (terminated)
); );
endmodule endmodule
@ -25,7 +29,7 @@ endmodule
// ************************************************************ // ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************ // ************************************************************
// Copyright (C) 1991-2017 Altera Corporation // Copyright (C) 1991-2018 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted), // Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other // support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner // associated documentation or information provided by Altera or a partner
@ -65,7 +69,7 @@ endmodule
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" /> // Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_divide_factor_n" value="1" /> // Retrieval info: <generic name="gui_divide_factor_n" value="1" />
// Retrieval info: <generic name="gui_cascade_counter0" value="false" /> // Retrieval info: <generic name="gui_cascade_counter0" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency0" value="74.25" /> // Retrieval info: <generic name="gui_output_clock_frequency0" value="148.5" />
// Retrieval info: <generic name="gui_divide_factor_c0" value="1" /> // Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" /> // Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units0" value="ps" /> // Retrieval info: <generic name="gui_ps_units0" value="ps" />
@ -74,7 +78,7 @@ endmodule
// Retrieval info: <generic name="gui_actual_phase_shift0" value="0" /> // Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_duty_cycle0" value="50" /> // Retrieval info: <generic name="gui_duty_cycle0" value="50" />
// Retrieval info: <generic name="gui_cascade_counter1" value="false" /> // Retrieval info: <generic name="gui_cascade_counter1" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency1" value="100.0" /> // Retrieval info: <generic name="gui_output_clock_frequency1" value="65.0" />
// Retrieval info: <generic name="gui_divide_factor_c1" value="1" /> // Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" /> // Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units1" value="ps" /> // Retrieval info: <generic name="gui_ps_units1" value="ps" />
@ -83,7 +87,7 @@ endmodule
// Retrieval info: <generic name="gui_actual_phase_shift1" value="0" /> // Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_duty_cycle1" value="50" /> // Retrieval info: <generic name="gui_duty_cycle1" value="50" />
// Retrieval info: <generic name="gui_cascade_counter2" value="false" /> // Retrieval info: <generic name="gui_cascade_counter2" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" /> // Retrieval info: <generic name="gui_output_clock_frequency2" value="27.0" />
// Retrieval info: <generic name="gui_divide_factor_c2" value="1" /> // Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" /> // Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units2" value="ps" /> // Retrieval info: <generic name="gui_ps_units2" value="ps" />
@ -228,7 +232,7 @@ endmodule
// Retrieval info: <generic name="gui_duty_cycle17" value="50" /> // Retrieval info: <generic name="gui_duty_cycle17" value="50" />
// Retrieval info: <generic name="gui_pll_auto_reset" value="On" /> // Retrieval info: <generic name="gui_pll_auto_reset" value="On" />
// Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" /> // Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
// Retrieval info: <generic name="gui_en_reconf" value="false" /> // Retrieval info: <generic name="gui_en_reconf" value="true" />
// Retrieval info: <generic name="gui_en_dps_ports" value="false" /> // Retrieval info: <generic name="gui_en_dps_ports" value="false" />
// Retrieval info: <generic name="gui_en_phout_ports" value="false" /> // Retrieval info: <generic name="gui_en_phout_ports" value="false" />
// Retrieval info: <generic name="gui_phout_division" value="1" /> // Retrieval info: <generic name="gui_phout_division" value="1" />

4
sys/pll_hdmi/pll_hdmi_0002.qip
View File

@ -1,4 +1,2 @@
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"

164
sys/pll_hdmi/pll_hdmi_0002.v
View File

@ -11,15 +11,23 @@ module pll_hdmi_0002(
output wire outclk_0, output wire outclk_0,
// interface 'locked' // interface 'locked'
output wire locked output wire locked,
// interface 'reconfig_to_pll'
input wire [63:0] reconfig_to_pll,
// interface 'reconfig_from_pll'
output wire [63:0] reconfig_from_pll
); );
altera_pll #( altera_pll #(
.fractional_vco_multiplier("true"), .fractional_vco_multiplier("true"),
.reference_clock_frequency("50.0 MHz"), .reference_clock_frequency("50.0 MHz"),
.pll_fractional_cout(32),
.pll_dsm_out_sel("1st_order"),
.operation_mode("direct"), .operation_mode("direct"),
.number_of_clocks(1), .number_of_clocks(1),
.output_clock_frequency0("74.250000 MHz"), .output_clock_frequency0("148.500000 MHz"),
.phase_shift0("0 ps"), .phase_shift0("0 ps"),
.duty_cycle0(50), .duty_cycle0(50),
.output_clock_frequency1("0 MHz"), .output_clock_frequency1("0 MHz"),
@ -73,15 +81,161 @@ module pll_hdmi_0002(
.output_clock_frequency17("0 MHz"), .output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"), .phase_shift17("0 ps"),
.duty_cycle17(50), .duty_cycle17(50),
.pll_type("General"), .pll_type("Cyclone V"),
.pll_subtype("General") .pll_subtype("Reconfigurable"),
.m_cnt_hi_div(4),
.m_cnt_lo_div(4),
.n_cnt_hi_div(256),
.n_cnt_lo_div(256),
.m_cnt_bypass_en("false"),
.n_cnt_bypass_en("true"),
.m_cnt_odd_div_duty_en("false"),
.n_cnt_odd_div_duty_en("false"),
.c_cnt_hi_div0(2),
.c_cnt_lo_div0(1),
.c_cnt_prst0(1),
.c_cnt_ph_mux_prst0(0),
.c_cnt_in_src0("ph_mux_clk"),
.c_cnt_bypass_en0("false"),
.c_cnt_odd_div_duty_en0("true"),
.c_cnt_hi_div1(1),
.c_cnt_lo_div1(1),
.c_cnt_prst1(1),
.c_cnt_ph_mux_prst1(0),
.c_cnt_in_src1("ph_mux_clk"),
.c_cnt_bypass_en1("true"),
.c_cnt_odd_div_duty_en1("false"),
.c_cnt_hi_div2(1),
.c_cnt_lo_div2(1),
.c_cnt_prst2(1),
.c_cnt_ph_mux_prst2(0),
.c_cnt_in_src2("ph_mux_clk"),
.c_cnt_bypass_en2("true"),
.c_cnt_odd_div_duty_en2("false"),
.c_cnt_hi_div3(1),
.c_cnt_lo_div3(1),
.c_cnt_prst3(1),
.c_cnt_ph_mux_prst3(0),
.c_cnt_in_src3("ph_mux_clk"),
.c_cnt_bypass_en3("true"),
.c_cnt_odd_div_duty_en3("false"),
.c_cnt_hi_div4(1),
.c_cnt_lo_div4(1),
.c_cnt_prst4(1),
.c_cnt_ph_mux_prst4(0),
.c_cnt_in_src4("ph_mux_clk"),
.c_cnt_bypass_en4("true"),
.c_cnt_odd_div_duty_en4("false"),
.c_cnt_hi_div5(1),
.c_cnt_lo_div5(1),
.c_cnt_prst5(1),
.c_cnt_ph_mux_prst5(0),
.c_cnt_in_src5("ph_mux_clk"),
.c_cnt_bypass_en5("true"),
.c_cnt_odd_div_duty_en5("false"),
.c_cnt_hi_div6(1),
.c_cnt_lo_div6(1),
.c_cnt_prst6(1),
.c_cnt_ph_mux_prst6(0),
.c_cnt_in_src6("ph_mux_clk"),
.c_cnt_bypass_en6("true"),
.c_cnt_odd_div_duty_en6("false"),
.c_cnt_hi_div7(1),
.c_cnt_lo_div7(1),
.c_cnt_prst7(1),
.c_cnt_ph_mux_prst7(0),
.c_cnt_in_src7("ph_mux_clk"),
.c_cnt_bypass_en7("true"),
.c_cnt_odd_div_duty_en7("false"),
.c_cnt_hi_div8(1),
.c_cnt_lo_div8(1),
.c_cnt_prst8(1),
.c_cnt_ph_mux_prst8(0),
.c_cnt_in_src8("ph_mux_clk"),
.c_cnt_bypass_en8("true"),
.c_cnt_odd_div_duty_en8("false"),
.c_cnt_hi_div9(1),
.c_cnt_lo_div9(1),
.c_cnt_prst9(1),
.c_cnt_ph_mux_prst9(0),
.c_cnt_in_src9("ph_mux_clk"),
.c_cnt_bypass_en9("true"),
.c_cnt_odd_div_duty_en9("false"),
.c_cnt_hi_div10(1),
.c_cnt_lo_div10(1),
.c_cnt_prst10(1),
.c_cnt_ph_mux_prst10(0),
.c_cnt_in_src10("ph_mux_clk"),
.c_cnt_bypass_en10("true"),
.c_cnt_odd_div_duty_en10("false"),
.c_cnt_hi_div11(1),
.c_cnt_lo_div11(1),
.c_cnt_prst11(1),
.c_cnt_ph_mux_prst11(0),
.c_cnt_in_src11("ph_mux_clk"),
.c_cnt_bypass_en11("true"),
.c_cnt_odd_div_duty_en11("false"),
.c_cnt_hi_div12(1),
.c_cnt_lo_div12(1),
.c_cnt_prst12(1),
.c_cnt_ph_mux_prst12(0),
.c_cnt_in_src12("ph_mux_clk"),
.c_cnt_bypass_en12("true"),
.c_cnt_odd_div_duty_en12("false"),
.c_cnt_hi_div13(1),
.c_cnt_lo_div13(1),
.c_cnt_prst13(1),
.c_cnt_ph_mux_prst13(0),
.c_cnt_in_src13("ph_mux_clk"),
.c_cnt_bypass_en13("true"),
.c_cnt_odd_div_duty_en13("false"),
.c_cnt_hi_div14(1),
.c_cnt_lo_div14(1),
.c_cnt_prst14(1),
.c_cnt_ph_mux_prst14(0),
.c_cnt_in_src14("ph_mux_clk"),
.c_cnt_bypass_en14("true"),
.c_cnt_odd_div_duty_en14("false"),
.c_cnt_hi_div15(1),
.c_cnt_lo_div15(1),
.c_cnt_prst15(1),
.c_cnt_ph_mux_prst15(0),
.c_cnt_in_src15("ph_mux_clk"),
.c_cnt_bypass_en15("true"),
.c_cnt_odd_div_duty_en15("false"),
.c_cnt_hi_div16(1),
.c_cnt_lo_div16(1),
.c_cnt_prst16(1),
.c_cnt_ph_mux_prst16(0),
.c_cnt_in_src16("ph_mux_clk"),
.c_cnt_bypass_en16("true"),
.c_cnt_odd_div_duty_en16("false"),
.c_cnt_hi_div17(1),
.c_cnt_lo_div17(1),
.c_cnt_prst17(1),
.c_cnt_ph_mux_prst17(0),
.c_cnt_in_src17("ph_mux_clk"),
.c_cnt_bypass_en17("true"),
.c_cnt_odd_div_duty_en17("false"),
.pll_vco_div(2),
.pll_cp_current(20),
.pll_bwctrl(4000),
.pll_output_clk_frequency("445.499999 MHz"),
.pll_fractional_division("3908420153"),
.mimic_fbclk_type("none"),
.pll_fbclk_mux_1("glb"),
.pll_fbclk_mux_2("m_cnt"),
.pll_m_cnt_in_src("ph_mux_clk"),
.pll_slf_rst("true")
) altera_pll_i ( ) altera_pll_i (
.rst (rst), .rst (rst),
.outclk ({outclk_0}), .outclk ({outclk_0}),
.locked (locked), .locked (locked),
.reconfig_to_pll (reconfig_to_pll),
.fboutclk ( ), .fboutclk ( ),
.fbclk (1'b0), .fbclk (1'b0),
.refclk (refclk) .refclk (refclk),
.reconfig_from_pll (reconfig_from_pll)
); );
endmodule endmodule

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set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_TOOL_NAME "altera_pll_reconfig"
set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_TOOL_VERSION "17.0"
set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "pll_hdmi_cfg" -name MISC_FILE [file join $::quartus(qip_path) "pll_hdmi_cfg.cmp"]
set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_QSYS_MODE "UNKNOWN"
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_NAME "cGxsX2hkbWlfY2Zn"
set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw=="
set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_VERSION "MTcuMA=="
set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ=="
set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA=="
set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA=="
set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA=="
set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA=="
set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo"
set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw=="
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_NAME "YWx0ZXJhX3BsbF9yZWNvbmZpZ190b3A="
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw=="
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_VERSION "MTcuMA=="
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ=="
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "ZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::ZGV2aWNlX2ZhbWlseQ=="
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01JRg==::ZmFsc2U=::RW5hYmxlIE1JRiBTdHJlYW1pbmc="
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA=="
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA=="
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA=="
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA=="
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo"
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw=="
set_global_assignment -library "pll_hdmi_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi_cfg.v"]
set_global_assignment -library "pll_hdmi_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi_cfg/altera_pll_reconfig_top.v"]
set_global_assignment -library "pll_hdmi_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi_cfg/altera_pll_reconfig_core.v"]
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_TOOL_NAME "altera_pll_reconfig"
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_TOOL_VERSION "17.0"
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_TOOL_ENV "mwpim"

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sys/pll_hdmi_cfg.v Normal file
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// megafunction wizard: %Altera PLL Reconfig v17.0%
// GENERATION: XML
// pll_hdmi_cfg.v
// Generated using ACDS version 17.0 598
`timescale 1 ps / 1 ps
module pll_hdmi_cfg #(
parameter ENABLE_BYTEENABLE = 0,
parameter BYTEENABLE_WIDTH = 4,
parameter RECONFIG_ADDR_WIDTH = 6,
parameter RECONFIG_DATA_WIDTH = 32,
parameter reconf_width = 64,
parameter WAIT_FOR_LOCK = 1
) (
input wire mgmt_clk, // mgmt_clk.clk
input wire mgmt_reset, // mgmt_reset.reset
output wire mgmt_waitrequest, // mgmt_avalon_slave.waitrequest
input wire mgmt_read, // .read
input wire mgmt_write, // .write
output wire [31:0] mgmt_readdata, // .readdata
input wire [5:0] mgmt_address, // .address
input wire [31:0] mgmt_writedata, // .writedata
output wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll
input wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll
);
altera_pll_reconfig_top #(
.device_family ("Cyclone V"),
.ENABLE_MIF (0),
.MIF_FILE_NAME ("sys/pll_hdmi_cfg.mif"),
.ENABLE_BYTEENABLE (ENABLE_BYTEENABLE),
.BYTEENABLE_WIDTH (BYTEENABLE_WIDTH),
.RECONFIG_ADDR_WIDTH (RECONFIG_ADDR_WIDTH),
.RECONFIG_DATA_WIDTH (RECONFIG_DATA_WIDTH),
.reconf_width (reconf_width),
.WAIT_FOR_LOCK (WAIT_FOR_LOCK)
) pll_hdmi_cfg_inst (
.mgmt_clk (mgmt_clk), // mgmt_clk.clk
.mgmt_reset (mgmt_reset), // mgmt_reset.reset
.mgmt_waitrequest (mgmt_waitrequest), // mgmt_avalon_slave.waitrequest
.mgmt_read (mgmt_read), // .read
.mgmt_write (mgmt_write), // .write
.mgmt_readdata (mgmt_readdata), // .readdata
.mgmt_address (mgmt_address), // .address
.mgmt_writedata (mgmt_writedata), // .writedata
.reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll
.reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll
.mgmt_byteenable (4'b0000) // (terminated)
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2018 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_pll_reconfig" version="17.0" >
// Retrieval info: <generic name="device_family" value="Cyclone V" />
// Retrieval info: <generic name="ENABLE_MIF" value="false" />
// Retrieval info: <generic name="MIF_FILE_NAME" value="sys/pll_hdmi_cfg.mif" />
// Retrieval info: <generic name="ENABLE_BYTEENABLE" value="false" />
// Retrieval info: </instance>
// IPFS_FILES : pll_hdmi_cfg.vo
// RELATED_FILES: pll_hdmi_cfg.v, altera_pll_reconfig_top.v, altera_pll_reconfig_core.v, altera_std_synchronizer.v

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sys/pll_hdmi_cfg/altera_pll_reconfig_top.v Normal file
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// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1ps/1ps
module altera_pll_reconfig_top
#(
parameter reconf_width = 64,
parameter device_family = "Stratix V",
parameter RECONFIG_ADDR_WIDTH = 6,
parameter RECONFIG_DATA_WIDTH = 32,
parameter ROM_ADDR_WIDTH = 9,
parameter ROM_DATA_WIDTH = 32,
parameter ROM_NUM_WORDS = 512,
parameter ENABLE_MIF = 0,
parameter MIF_FILE_NAME = "",
parameter ENABLE_BYTEENABLE = 0,
parameter BYTEENABLE_WIDTH = 4,
parameter WAIT_FOR_LOCK = 1
) (
//input
input wire mgmt_clk,
input wire mgmt_reset,
//conduits
output wire [reconf_width-1:0] reconfig_to_pll,
input wire [reconf_width-1:0] reconfig_from_pll,
// user data (avalon-MM slave interface)
output wire [RECONFIG_DATA_WIDTH-1:0] mgmt_readdata,
output wire mgmt_waitrequest,
input wire [RECONFIG_ADDR_WIDTH-1:0] mgmt_address,
input wire mgmt_read,
input wire mgmt_write,
input wire [RECONFIG_DATA_WIDTH-1:0] mgmt_writedata,
//conditional input
input wire [BYTEENABLE_WIDTH-1:0] mgmt_byteenable
);
localparam NM28_START_REG = 6'b000010;
localparam NM20_START_REG = 9'b000000000;
localparam NM20_MIFSTART_ADDR = 9'b000010000;
localparam MIF_STATE_DONE = 2'b00;
localparam MIF_STATE_START = 2'b01;
localparam MIF_STATE_BUSY = 2'b10;
wire mgmt_byteenable_write;
assign mgmt_byteenable_write = (ENABLE_BYTEENABLE == 1) ?
((mgmt_byteenable == {BYTEENABLE_WIDTH{1'b1}}) ? mgmt_write : 1'b0) :
mgmt_write;
generate
if (device_family == "Arria 10")
begin:nm20_reconfig
if(ENABLE_MIF == 1)
begin:mif_reconfig_20nm // Generate Reconfig with MIF
// MIF-related regs/wires
reg [RECONFIG_ADDR_WIDTH-1:0] reconfig_mgmt_addr;
reg reconfig_mgmt_read;
reg reconfig_mgmt_write;
reg [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_writedata;
wire reconfig_mgmt_waitrequest;
wire [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_readdata;
wire [RECONFIG_ADDR_WIDTH-1:0] mif2reconfig_addr;
wire mif_busy;
wire mif2reconfig_read;
wire mif2reconfig_write;
wire [RECONFIG_DATA_WIDTH-1:0] mif2reconfig_writedata;
wire [ROM_ADDR_WIDTH-1:0] mif_base_addr;
reg mif_select;
//wire mif_user_start; // start signal provided by user to start mif
//reg user_start;
reg [1:0] mif_curstate;
reg [1:0] mif_nextstate;
wire mif_start; //start signal to mif reader
assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif_busy;// | user_start;
// Don't output readdata if MIF streaming is taking place
assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata;
//user must lower this by the time mif streaming is done - suggest to lower after 1 cycle
assign mif_start = mgmt_byteenable_write & (mgmt_address == NM20_MIFSTART_ADDR);
//mif base addr is initially specified by the user
assign mif_base_addr = mgmt_writedata[ROM_ADDR_WIDTH-1:0];
//MIF statemachine
always @(posedge mgmt_clk)
begin
if(mgmt_reset)
mif_curstate <= MIF_STATE_DONE;
else
mif_curstate <= mif_nextstate;
end
always @(*)
begin
case (mif_curstate)
MIF_STATE_DONE:
begin
if(mif_start)
mif_nextstate <= MIF_STATE_START;
else
mif_nextstate <= MIF_STATE_DONE;
end
MIF_STATE_START:
begin
mif_nextstate <= MIF_STATE_BUSY;
end
MIF_STATE_BUSY:
begin
if(mif_busy)
mif_nextstate <= MIF_STATE_BUSY;
else
mif_nextstate <= MIF_STATE_DONE;
end
endcase
end
//Mif muxes
always @(*)
begin
if (mgmt_reset)
begin
reconfig_mgmt_addr <= 0;
reconfig_mgmt_read <= 0;
reconfig_mgmt_write <= 0;
reconfig_mgmt_writedata <= 0;
//user_start <= 0;
end
else
begin
reconfig_mgmt_addr <= (mif_select) ? mif2reconfig_addr : mgmt_address;
reconfig_mgmt_read <= (mif_select) ? mif2reconfig_read : mgmt_read;
reconfig_mgmt_write <= (mif_select) ? mif2reconfig_write : mgmt_byteenable_write;
reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata;
//user_start <= (mgmt_address == NM20_START_REG && mgmt_write == 1'b1) ? 1'b1 : 1'b0;
end
end
always @(*)
begin
if (mgmt_reset)
begin
mif_select <= 0;
end
else
begin
mif_select <= (mif_start || mif_busy) ? 1'b1 : 1'b0;
end
end
twentynm_pll_reconfig_mif_reader
#(
.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
.ROM_NUM_WORDS(ROM_NUM_WORDS),
.DEVICE_FAMILY(device_family),
.ENABLE_MIF(ENABLE_MIF),
.MIF_FILE_NAME(MIF_FILE_NAME)
) twentynm_pll_reconfig_mif_reader_inst0 (
.mif_clk(mgmt_clk),
.mif_rst(mgmt_reset),
//Altera_PLL Reconfig interface
//inputs
.reconfig_waitrequest(reconfig_mgmt_waitrequest),
//.reconfig_read_data(reconfig_mgmt_readdata),
//outputs
.reconfig_write_data(mif2reconfig_writedata),
.reconfig_addr(mif2reconfig_addr),
.reconfig_write(mif2reconfig_write),
.reconfig_read(mif2reconfig_read),
//MIF Ctrl Interface
//inputs
.mif_base_addr(mif_base_addr),
.mif_start(mif_start),
//outputs
.mif_busy(mif_busy)
);
// ------ END MIF-RELATED MANAGEMENT ------
twentynm_iopll_reconfig_core
#(
.WAIT_FOR_LOCK(WAIT_FOR_LOCK)
) twentynm_iopll_reconfig_core_inst (
// Inputs
.mgmt_clk(mgmt_clk),
.mgmt_rst_n(~mgmt_reset),
.mgmt_read(reconfig_mgmt_read),
.mgmt_write(reconfig_mgmt_write),
.mgmt_address(reconfig_mgmt_addr),
.mgmt_writedata(reconfig_mgmt_writedata),
// Outputs
.mgmt_readdata(reconfig_mgmt_readdata),
.mgmt_waitrequest(reconfig_mgmt_waitrequest),
// PLL Conduits
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll)
);
end // End generate reconfig with MIF
else
begin:reconfig_core_20nm
twentynm_iopll_reconfig_core
#(
.WAIT_FOR_LOCK(WAIT_FOR_LOCK)
) twentynm_iopll_reconfig_core_inst (
// Inputs
.mgmt_clk(mgmt_clk),
.mgmt_rst_n(~mgmt_reset),
.mgmt_read(mgmt_read),
.mgmt_write(mgmt_byteenable_write),
.mgmt_address(mgmt_address),
.mgmt_writedata(mgmt_writedata),
// Outputs
.mgmt_readdata(mgmt_readdata),
.mgmt_waitrequest(mgmt_waitrequest),
// PLL Conduits
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll)
);
end
end // 20nm reconfig
else
begin:NM28_reconfig
if (ENABLE_MIF == 1)
begin:mif_reconfig // Generate Reconfig with MIF
// MIF-related regs/wires
reg [RECONFIG_ADDR_WIDTH-1:0] reconfig_mgmt_addr;
reg reconfig_mgmt_read;
reg reconfig_mgmt_write;
reg [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_writedata;
wire reconfig_mgmt_waitrequest;
wire [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_readdata;
wire [RECONFIG_ADDR_WIDTH-1:0] mif2reconfig_addr;
wire mif2reconfig_busy;
wire mif2reconfig_read;
wire mif2reconfig_write;
wire [RECONFIG_DATA_WIDTH-1:0] mif2reconfig_writedata;
wire [ROM_ADDR_WIDTH-1:0] mif_base_addr;
reg mif_select;
reg user_start;
wire reconfig2mif_start_out;
assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif2reconfig_busy | user_start;
// Don't output readdata if MIF streaming is taking place
assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata;
always @(posedge mgmt_clk)
begin
if (mgmt_reset)
begin
reconfig_mgmt_addr <= 0;
reconfig_mgmt_read <= 0;
reconfig_mgmt_write <= 0;
reconfig_mgmt_writedata <= 0;
user_start <= 0;
end
else
begin
reconfig_mgmt_addr <= (mif_select) ? mif2reconfig_addr : mgmt_address;
reconfig_mgmt_read <= (mif_select) ? mif2reconfig_read : mgmt_read;
reconfig_mgmt_write <= (mif_select) ? mif2reconfig_write : mgmt_byteenable_write;
reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata;
user_start <= (mgmt_address == NM28_START_REG && mgmt_byteenable_write == 1'b1) ? 1'b1 : 1'b0;
end
end
always @(*)
begin
if (mgmt_reset)
begin
mif_select <= 0;
end
else
begin
mif_select <= (reconfig2mif_start_out || mif2reconfig_busy) ? 1'b1 : 1'b0;
end
end
altera_pll_reconfig_mif_reader
#(
.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
.ROM_NUM_WORDS(ROM_NUM_WORDS),
.DEVICE_FAMILY(device_family),
.ENABLE_MIF(ENABLE_MIF),
.MIF_FILE_NAME(MIF_FILE_NAME)
) altera_pll_reconfig_mif_reader_inst0 (
.mif_clk(mgmt_clk),
.mif_rst(mgmt_reset),
//Altera_PLL Reconfig interface
//inputs
.reconfig_busy(reconfig_mgmt_waitrequest),
.reconfig_read_data(reconfig_mgmt_readdata),
//outputs
.reconfig_write_data(mif2reconfig_writedata),
.reconfig_addr(mif2reconfig_addr),
.reconfig_write(mif2reconfig_write),
.reconfig_read(mif2reconfig_read),
//MIF Ctrl Interface
//inputs
.mif_base_addr(mif_base_addr),
.mif_start(reconfig2mif_start_out),
//outputs
.mif_busy(mif2reconfig_busy)
);
// ------ END MIF-RELATED MANAGEMENT ------
altera_pll_reconfig_core
#(
.reconf_width(reconf_width),
.device_family(device_family),
.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
.ROM_NUM_WORDS(ROM_NUM_WORDS)
) altera_pll_reconfig_core_inst0 (
//inputs
.mgmt_clk(mgmt_clk),
.mgmt_reset(mgmt_reset),
//PLL interface conduits
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll),
//User data outputs
.mgmt_readdata(reconfig_mgmt_readdata),
.mgmt_waitrequest(reconfig_mgmt_waitrequest),
//User data inputs
.mgmt_address(reconfig_mgmt_addr),
.mgmt_read(reconfig_mgmt_read),
.mgmt_write(reconfig_mgmt_write),
.mgmt_writedata(reconfig_mgmt_writedata),
// other
.mif_start_out(reconfig2mif_start_out),
.mif_base_addr(mif_base_addr)
);
end // End generate reconfig with MIF
else
begin:reconfig_core // Generate Reconfig core only
wire reconfig2mif_start_out;
wire [ROM_ADDR_WIDTH-1:0] mif_base_addr;
altera_pll_reconfig_core
#(
.reconf_width(reconf_width),
.device_family(device_family),
.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
.ROM_NUM_WORDS(ROM_NUM_WORDS)
) altera_pll_reconfig_core_inst0 (
//inputs
.mgmt_clk(mgmt_clk),
.mgmt_reset(mgmt_reset),
//PLL interface conduits
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll),
//User data outputs
.mgmt_readdata(mgmt_readdata),
.mgmt_waitrequest(mgmt_waitrequest),
//User data inputs
.mgmt_address(mgmt_address),
.mgmt_read(mgmt_read),
.mgmt_write(mgmt_byteenable_write),
.mgmt_writedata(mgmt_writedata),
// other
.mif_start_out(reconfig2mif_start_out),
.mif_base_addr(mif_base_addr)
);
end // End generate reconfig core only
end // End 28nm Reconfig
endgenerate
endmodule

36
sys/spdif.v
View File

@ -62,6 +62,40 @@ module spdif
output sample_req_o output sample_req_o
); );
reg lpf_ce;
always @(negedge clk_i) begin
reg [3:0] div;
div <= div + 1'd1;
if(div == 13) div <= 0;
lpf_ce <= !div;
end
wire [15:0] al, ar;
lpf48k #(15) lpf_l
(
.RESET(rst_i),
.CLK(clk_i),
.CE(lpf_ce),
.ENABLE(1),
.IDATA(audio_l),
.ODATA(al)
);
lpf48k #(15) lpf_r
(
.RESET(rst_i),
.CLK(clk_i),
.CE(lpf_ce),
.ENABLE(1),
.IDATA(audio_r),
.ODATA(ar)
);
reg bit_clk_q; reg bit_clk_q;
// Clock pulse generator // Clock pulse generator
@ -104,7 +138,7 @@ end
// Core SPDIF // Core SPDIF
//----------------------------------------------------------------- //-----------------------------------------------------------------
wire [31:0] sample_i = {audio_r, audio_l}; wire [31:0] sample_i = {ar, al};
spdif_core spdif_core
u_core u_core

73
sys/sync_vg.v
View File

@ -1,48 +1,33 @@
module sync_vg module sync_vg
#( #(
parameter X_BITS=12, parameter X_BITS=12, Y_BITS=12
Y_BITS=12
) )
( (
input wire clk, input wire clk,
input wire reset, input wire reset,
input wire interlaced,
input wire [Y_BITS-1:0] v_total_0, input wire [Y_BITS-1:0] v_total,
input wire [Y_BITS-1:0] v_fp_0, input wire [Y_BITS-1:0] v_fp,
input wire [Y_BITS-1:0] v_bp_0, input wire [Y_BITS-1:0] v_bp,
input wire [Y_BITS-1:0] v_sync_0, input wire [Y_BITS-1:0] v_sync,
input wire [Y_BITS-1:0] v_total_1,
input wire [Y_BITS-1:0] v_fp_1,
input wire [Y_BITS-1:0] v_bp_1,
input wire [Y_BITS-1:0] v_sync_1,
input wire [X_BITS-1:0] h_total, input wire [X_BITS-1:0] h_total,
input wire [X_BITS-1:0] h_fp, input wire [X_BITS-1:0] h_fp,
input wire [X_BITS-1:0] h_bp, input wire [X_BITS-1:0] h_bp,
input wire [X_BITS-1:0] h_sync, input wire [X_BITS-1:0] h_sync,
input wire [X_BITS-1:0] hv_offset_0, input wire [X_BITS-1:0] hv_offset,
input wire [X_BITS-1:0] hv_offset_1,
output reg vs_out, output reg vs_out,
output reg hs_out, output reg hs_out,
output reg hde_out, output reg hde_out,
output reg vde_out, output reg vde_out,
output reg [Y_BITS:0] v_count_out, output reg [Y_BITS-1:0] v_count_out,
output reg [X_BITS-1:0] h_count_out, output reg [X_BITS-1:0] h_count_out,
output reg [X_BITS-1:0] x_out, output reg [X_BITS-1:0] x_out,
output reg [Y_BITS:0] y_out, output reg [Y_BITS-1:0] y_out
output reg field_out,
output wire clk_out
); );
reg [X_BITS-1:0] h_count; reg [X_BITS-1:0] h_count;
reg [Y_BITS-1:0] v_count; reg [Y_BITS-1:0] v_count;
reg field;
reg [Y_BITS-1:0] v_total;
reg [Y_BITS-1:0] v_fp;
reg [Y_BITS-1:0] v_bp;
reg [Y_BITS-1:0] v_sync;
reg [X_BITS-1:0] hv_offset;
assign clk_out = !clk;
/* horizontal counter */ /* horizontal counter */
always @(posedge clk) always @(posedge clk)
@ -67,31 +52,9 @@ always @(posedge clk)
v_count <= v_count + 1'd1; v_count <= v_count + 1'd1;
end end
/* field */
always @(posedge clk) always @(posedge clk)
if (reset) if (reset)
begin { vs_out, hs_out, hde_out, vde_out } <= 0;
field <= 0;
v_total <= v_total_0;
v_fp <= interlaced ? v_fp_1 : v_fp_0; // In the interlaced mode this value must be inverted as v_fp_1 is still in field0
v_bp <= v_bp_0;
v_sync <= v_sync_0;
hv_offset <= hv_offset_0;
end
else
if ((interlaced) && ((v_count == v_total - 1) && (h_count == h_total - 1)))
begin
field <= field + interlaced;
v_total <= field ? v_total_0 : v_total_1;
v_fp <= field ? v_fp_1 : v_fp_0; // This order is inverted as v_fp_1 is still in field0
v_bp <= field ? v_bp_0 : v_bp_1;
v_sync <= field ? v_sync_0 : v_sync_1;
hv_offset <= field ? hv_offset_0 : hv_offset_1;
end
always @(posedge clk)
if (reset)
{ vs_out, hs_out, hde_out, vde_out, field_out } <= 4'b0;
else begin else begin
hs_out <= ((h_count < h_sync)); hs_out <= ((h_count < h_sync));
@ -105,19 +68,11 @@ always @(posedge clk)
/* H_COUNT_OUT and V_COUNT_OUT */ /* H_COUNT_OUT and V_COUNT_OUT */
h_count_out <= h_count; h_count_out <= h_count;
if (field) v_count_out <= v_count;
v_count_out <= v_count + v_total_0;
else
v_count_out <= v_count;
/* X and Y coords <EFBFBD> for a backend pattern generator */ /* X and Y coords for a backend pattern generator */
x_out <= h_count - (h_sync + h_bp); x_out <= h_count - (h_sync + h_bp);
if (interlaced) y_out <= v_count - (v_sync + v_bp);
y_out <= { (v_count - (v_sync + v_bp)) , field };
else
y_out <= { 1'b0, (v_count - (v_sync + v_bp)) };
field_out <= field;
end end
endmodule endmodule

7
sys/sys.qip
View File

@ -2,8 +2,8 @@ set_global_assignment -name VERILOG_FILE sys/sys_top.v
set_global_assignment -name SDC_FILE sys/sys_top.sdc set_global_assignment -name SDC_FILE sys/sys_top.sdc
set_global_assignment -name QIP_FILE sys/pll.qip set_global_assignment -name QIP_FILE sys/pll.qip
set_global_assignment -name QIP_FILE sys/pll_hdmi.qip set_global_assignment -name QIP_FILE sys/pll_hdmi.qip
set_global_assignment -name SYSTEMVERILOG_FILE sys/sdram.sv set_global_assignment -name QIP_FILE sys/pll_hdmi_cfg.qip
set_global_assignment -name SYSTEMVERILOG_FILE sys/ddram.sv set_global_assignment -name SYSTEMVERILOG_FILE sys/hdmi_lite.sv
set_global_assignment -name SYSTEMVERILOG_FILE sys/hq2x.sv set_global_assignment -name SYSTEMVERILOG_FILE sys/hq2x.sv
set_global_assignment -name VERILOG_FILE sys/scandoubler.v set_global_assignment -name VERILOG_FILE sys/scandoubler.v
set_global_assignment -name SYSTEMVERILOG_FILE sys/video_mixer.sv set_global_assignment -name SYSTEMVERILOG_FILE sys/video_mixer.sv
@ -17,4 +17,7 @@ set_global_assignment -name VERILOG_FILE sys/spdif.v
set_global_assignment -name VERILOG_FILE sys/sigma_delta_dac.v set_global_assignment -name VERILOG_FILE sys/sigma_delta_dac.v
set_global_assignment -name SYSTEMVERILOG_FILE sys/lpf48k.sv set_global_assignment -name SYSTEMVERILOG_FILE sys/lpf48k.sv
set_global_assignment -name SYSTEMVERILOG_FILE sys/hdmi_config.sv set_global_assignment -name SYSTEMVERILOG_FILE sys/hdmi_config.sv
set_global_assignment -name SYSTEMVERILOG_FILE sys/sysmem.sv
set_global_assignment -name VERILOG_FILE sys/ip/reset_source.v
set_global_assignment -name SYSTEMVERILOG_FILE sys/vip_config.sv
set_global_assignment -name VERILOG_FILE sys/hps_io.v set_global_assignment -name VERILOG_FILE sys/hps_io.v

30
sys/sys_top.sdc
View File

@ -1,3 +1,4 @@
# Specify root clocks
create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50] create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50]
create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50] create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50]
create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50] create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50]
@ -5,11 +6,21 @@ create_clock -period "100.0 MHz" [get_pins -compatibility_mode *|h2f_user0_clk]
derive_pll_clocks derive_pll_clocks
# Specify PLL-generated clock(s)
create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \ create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-name SDRAM_CLK [get_ports {SDRAM_CLK}] -name SDRAM_CLK [get_ports {SDRAM_CLK}]
create_generated_clock -source [get_pins -compatibility_mode {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \
-name HDMI_CLK [get_ports HDMI_TX_CLK]
create_generated_clock -source [get_pins { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \
-name VID_CLK -divide_by 2 -duty_cycle 50 [get_nets {vip|output_inst|vid_clk}]
derive_clock_uncertainty derive_clock_uncertainty
# Set acceptable delays for SDRAM chip (See correspondent chip datasheet)
set_input_delay -max -clock SDRAM_CLK 6.4ns [get_ports SDRAM_DQ[*]] set_input_delay -max -clock SDRAM_CLK 6.4ns [get_ports SDRAM_DQ[*]]
set_input_delay -min -clock SDRAM_CLK 3.7ns [get_ports SDRAM_DQ[*]] set_input_delay -min -clock SDRAM_CLK 3.7ns [get_ports SDRAM_DQ[*]]
@ -20,8 +31,23 @@ set_multicycle_path -from [get_clocks {SDRAM_CLK}] \
set_output_delay -max -clock SDRAM_CLK 1.6ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] set_output_delay -max -clock SDRAM_CLK 1.6ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -min -clock SDRAM_CLK -0.9ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] set_output_delay -min -clock SDRAM_CLK -0.9ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
# Decouple different clock groups (to simplify routing)
set_clock_groups -asynchronous \
-group [get_clocks { *|pll|pll_inst|altera_pll_i|general[*].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk VID_CLK}] \
-group [get_clocks { *|h2f_user0_clk}] \
-group [get_clocks { FPGA_CLK1_50 FPGA_CLK2_50 FPGA_CLK3_50}]
set_output_delay -max -clock HDMI_CLK 2.0ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
set_output_delay -min -clock HDMI_CLK -1.5ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
# Put constraints on input ports
set_false_path -from [get_ports {KEY*}] -to *
set_false_path -from [get_ports {BTN_*}] -to *
# Put constraints on output ports
set_false_path -from * -to [get_ports {LED_*}] set_false_path -from * -to [get_ports {LED_*}]
set_false_path -from * -to [get_ports {BTN_*}]
set_false_path -from * -to [get_ports {VGA_*}] set_false_path -from * -to [get_ports {VGA_*}]
set_false_path -from * -to [get_ports {AUDIO_SPDIF}]
set_false_path -from * -to [get_ports {AUDIO_L}] set_false_path -from * -to [get_ports {AUDIO_L}]
set_false_path -from * -to [get_ports {AUDIO_R}] set_false_path -from * -to [get_ports {AUDIO_R}]

461
sys/sys_top.v
View File

@ -1,7 +1,7 @@
//============================================================================ //============================================================================
// //
// DE10-nano HAL top module // MiSTer hardware abstraction module
// (c)2017 Sorgelig // (c)2017,2018 Sorgelig
// //
// This program is free software; you can redistribute it and/or modify it // This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free // under the terms of the GNU General Public License as published by the Free
@ -30,9 +30,9 @@ module sys_top
output [5:0] VGA_R, output [5:0] VGA_R,
output [5:0] VGA_G, output [5:0] VGA_G,
output [5:0] VGA_B, output [5:0] VGA_B,
output VGA_HS, inout VGA_HS, // VGA_HS is secondary SD card detect when VGA_EN = 1 (inactive)
output VGA_VS, output VGA_VS,
input VGA_EN, input VGA_EN, // active low
/////////// AUDIO ////////// /////////// AUDIO //////////
output AUDIO_L, output AUDIO_L,
@ -53,6 +53,8 @@ module sys_top
output [23:0] HDMI_TX_D, output [23:0] HDMI_TX_D,
output HDMI_TX_HS, output HDMI_TX_HS,
output HDMI_TX_VS, output HDMI_TX_VS,
input HDMI_TX_INT,
//////////// SDR /////////// //////////// SDR ///////////
output [12:0] SDRAM_A, output [12:0] SDRAM_A,
@ -84,6 +86,9 @@ module sys_top
////////// MB KEY /////////// ////////// MB KEY ///////////
input [1:0] KEY, input [1:0] KEY,
////////// MB SWITCH ////////
input [3:0] SW,
////////// MB LED /////////// ////////// MB LED ///////////
output [7:0] LED output [7:0] LED
); );
@ -91,8 +96,12 @@ module sys_top
assign SDIO_DAT[2:1] = 2'bZZ; assign SDIO_DAT[2:1] = 2'bZZ;
////////////////////////// LEDs /////////////////////////////////////// ////////////////////////// LEDs ///////////////////////////////////////
reg [7:0] led_overtake = 0;
reg [7:0] led_state = 0;
wire led_p = led_power[1] ? ~led_power[0] : 1'b0; wire led_p = led_power[1] ? ~led_power[0] : 1'b0;
wire led_d = led_disk[1] ? ~led_disk[0] : ~(led_disk[0] | gp_out[29]); wire led_d = led_disk[1] ? ~led_disk[0] : ~(led_disk[0] | gp_out[29]);
wire led_u = ~led_user; wire led_u = ~led_user;
@ -102,7 +111,7 @@ assign LED_HDD = led_d ? 1'bZ : 1'b0;
assign LED_USER = led_u ? 1'bZ : 1'b0; assign LED_USER = led_u ? 1'bZ : 1'b0;
//LEDs on main board //LEDs on main board
assign LED = {3'b000, ~led_p, 1'b0, ~led_d, 1'b0, ~led_u}; assign LED = (led_overtake & led_state) | (~led_overtake & {3'b000, ~led_p, 1'b0, ~led_d, 1'b0, ~led_u});
////////////////////////// Buttons /////////////////////////////////// ////////////////////////// Buttons ///////////////////////////////////
@ -180,18 +189,29 @@ cyclonev_hps_interface_mpu_general_purpose h2f_gp
reg [15:0] cfg; reg [15:0] cfg;
reg cfg_ready = 0; reg cfg_got = 0;
wire audio_96k = cfg[6]; reg cfg_set = 0;
wire ypbpr_en = cfg[5]; //wire [2:0] hdmi_res = cfg[10:8];
wire csync = cfg[3]; wire dvi_mode = cfg[7];
wire audio_96k = cfg[6];
wire ypbpr_en = cfg[5];
wire csync = cfg[3];
`ifndef LITE `ifndef LITE
wire vga_scaler= cfg[2]; wire vga_scaler= cfg[2];
`endif `endif
reg cfg_custom_t = 0;
reg [5:0] cfg_custom_p1;
reg [31:0] cfg_custom_p2;
reg [4:0] vol_att = 0;
reg vip_newcfg = 0;
always@(posedge clk_sys) begin always@(posedge clk_sys) begin
reg [7:0] cmd; reg [7:0] cmd;
reg has_cmd; reg has_cmd;
reg old_strobe; reg old_strobe;
reg [7:0] cnt = 0;
old_strobe <= io_strobe; old_strobe <= io_strobe;
@ -201,15 +221,60 @@ always@(posedge clk_sys) begin
if(!has_cmd) begin if(!has_cmd) begin
has_cmd <= 1; has_cmd <= 1;
cmd <= io_din[7:0]; cmd <= io_din[7:0];
cnt <= 0;
end end
else else begin
if(cmd == 1) begin if(cmd == 1) begin
cfg <= io_din; cfg <= io_din;
cfg_ready <= 1; cfg_set <= 1;
end
if(cmd == 'h20) begin
cfg_set <= 0;
cnt <= cnt + 1'd1;
if(cnt<8) begin
if(!cnt) vip_newcfg <= ~cfg_ready;
case(cnt)
0: if(WIDTH != io_din[11:0]) begin WIDTH <= io_din[11:0]; vip_newcfg <= 1; end
1: if(HFP != io_din[11:0]) begin HFP <= io_din[11:0]; vip_newcfg <= 1; end
2: if(HS != io_din[11:0]) begin HS <= io_din[11:0]; vip_newcfg <= 1; end
3: if(HBP != io_din[11:0]) begin HBP <= io_din[11:0]; vip_newcfg <= 1; end
4: if(HEIGHT != io_din[11:0]) begin HEIGHT <= io_din[11:0]; vip_newcfg <= 1; end
5: if(VFP != io_din[11:0]) begin VFP <= io_din[11:0]; vip_newcfg <= 1; end
6: if(VS != io_din[11:0]) begin VS <= io_din[11:0]; vip_newcfg <= 1; end
7: if(VBP != io_din[11:0]) begin VBP <= io_din[11:0]; vip_newcfg <= 1; end
endcase
if(cnt == 1) begin
cfg_custom_p1 <= 0;
cfg_custom_p2 <= 0;
cfg_custom_t <= ~cfg_custom_t;
end
end
else begin
if(cnt[1:0]==0) cfg_custom_p1 <= io_din[5:0];
if(cnt[1:0]==1) cfg_custom_p2[15:0] <= io_din;
if(cnt[1:0]==2) begin
cfg_custom_p2[31:16] <= io_din;
cfg_custom_t <= ~cfg_custom_t;
cnt[1:0] <= 0;
end
end
end
if(cmd == 'h25) {led_overtake, led_state} <= io_din;
if(cmd == 'h26) vol_att <= io_din[4:0];
if(cmd == 'h27) VSET <= io_din[11:0];
end end
end end
end end
always @(posedge clk_sys) begin
reg vsd, vsd2;
if(~cfg_ready || ~cfg_set) cfg_got <= cfg_set;
else begin
vsd <= HDMI_TX_VS;
vsd2 <= vsd;
if(~vsd2 & vsd) cfg_got <= cfg_set;
end
end
/////////////////////////// RESET /////////////////////////////////// /////////////////////////// RESET ///////////////////////////////////
@ -231,19 +296,21 @@ always @(posedge FPGA_CLK2_50) begin
resetd2 <= resetd; resetd2 <= resetd;
end end
// 100MHz wire clk_ctl;
wire ctl_clk;
///////////////////////// VIP version /////////////////////////////// ///////////////////////// VIP version ///////////////////////////////
wire iHdmiClk = ~HDMI_TX_CLK; // Internal HDMI clock, inverted in relation to external clock
`ifndef LITE `ifndef LITE
wire reset; wire reset;
vip vip vip vip
( (
//Reset/Clock //Reset/Clock
.reset_reset_req(reset_req), .reset_reset_req(reset_req | ~cfg_ready),
.reset_reset(reset), .reset_reset(reset),
.reset_reset_vip(0),
//DE10-nano has no reset signal on GPIO, so core has to emulate cold reset button. //DE10-nano has no reset signal on GPIO, so core has to emulate cold reset button.
.reset_cold_req(~btn_reset), .reset_cold_req(~btn_reset),
@ -254,7 +321,7 @@ vip vip
.ctl_write(ctl_write), .ctl_write(ctl_write),
.ctl_writedata(ctl_writedata), .ctl_writedata(ctl_writedata),
.ctl_waitrequest(ctl_waitrequest), .ctl_waitrequest(ctl_waitrequest),
.ctl_clock(ctl_clk), .ctl_clock(clk_ctl),
.ctl_reset(ctl_reset), .ctl_reset(ctl_reset),
//64-bit DDR3 RAM access //64-bit DDR3 RAM access
@ -284,23 +351,20 @@ vip vip
.ram2_write(0), .ram2_write(0),
//Video input //Video input
.in_vid_clk(clk_vid), .in_clk(clk_vid),
.in_vid_data({r_out, g_out, b_out}), .in_data({r_out, g_out, b_out}),
.in_vid_de(de), .in_de(de),
.in_vid_v_sync(vs), .in_v_sync(vs),
.in_vid_h_sync(hs), .in_h_sync(hs),
.in_vid_datavalid(ce_pix), .in_ce(ce_pix),
.in_vid_locked(1), .in_f(0),
.in_vid_f(0),
.in_vid_color_encoding(0),
.in_vid_bit_width(0),
//HDMI output //HDMI output
.hdmi_vid_clk(~HDMI_TX_CLK), .hdmi_clk(iHdmiClk),
.hdmi_vid_data(hdmi_data), .hdmi_data(hdmi_data),
.hdmi_vid_datavalid(HDMI_TX_DE), .hdmi_de(hdmi_de),
.hdmi_vid_v_sync(HDMI_TX_VS), .hdmi_v_sync(HDMI_TX_VS),
.hdmi_vid_h_sync(HDMI_TX_HS) .hdmi_h_sync(HDMI_TX_HS)
); );
wire [8:0] ctl_address; wire [8:0] ctl_address;
@ -312,11 +376,22 @@ wire [7:0] ARX, ARY;
vip_config vip_config vip_config vip_config
( (
.clk(ctl_clk), .clk(clk_ctl),
.reset(ctl_reset), .reset(ctl_reset),
.ARX(ARX), .ARX(ARX),
.ARY(ARY), .ARY(ARY),
.CFG_SET(vip_newcfg & cfg_got),
.WIDTH(WIDTH),
.HFP(HFP),
.HBP(HBP),
.HS(HS),
.HEIGHT(HEIGHT),
.VFP(VFP),
.VBP(VBP),
.VS(VS),
.VSET(VSET),
.address(ctl_address), .address(ctl_address),
.write(ctl_write), .write(ctl_write),
@ -330,45 +405,22 @@ vip_config vip_config
`ifdef LITE `ifdef LITE
wire INTERLACED = 0;
wire [11:0] V_TOTAL_0 = 750;
wire [11:0] V_FP_0 = 5;
wire [11:0] V_BP_0 = 20;
wire [11:0] V_SYNC_0 = 5;
wire [11:0] V_TOTAL_1 = 0;
wire [11:0] V_FP_1 = 0;
wire [11:0] V_BP_1 = 0;
wire [11:0] V_SYNC_1 = 0;
wire [11:0] H_TOTAL = 1650;
wire [11:0] H_FP = 110;
wire [11:0] H_BP = 220;
wire [11:0] H_SYNC = 40;
wire [11:0] HV_OFFSET_0 = 0;
wire [11:0] HV_OFFSET_1 = 0;
wire [11:0] x; wire [11:0] x;
wire [12:0] y; wire [11:0] y;
sync_vg #(.X_BITS(12), .Y_BITS(12)) sync_vg sync_vg #(.X_BITS(12), .Y_BITS(12)) sync_vg
( (
.clk(HDMI_TX_CLK), .clk(iHdmiClk),
.reset(reset), .reset(reset),
.interlaced(INTERLACED), .v_total(HEIGHT+VFP+VBP+VS),
.clk_out(), // inverted output clock - unconnected .v_fp(VFP),
.v_total_0(V_TOTAL_0), .v_bp(VBP),
.v_fp_0(V_FP_0), .v_sync(VS),
.v_bp_0(V_BP_0), .h_total(WIDTH+HFP+HBP+HS),
.v_sync_0(V_SYNC_0), .h_fp(HFP),
.v_total_1(V_TOTAL_1), .h_bp(HBP),
.v_fp_1(V_FP_1), .h_sync(HS),
.v_bp_1(V_BP_1), .hv_offset(0),
.v_sync_1(V_SYNC_1),
.h_total(H_TOTAL),
.h_fp(H_FP),
.h_bp(H_BP),
.h_sync(H_SYNC),
.hv_offset_0(HV_OFFSET_0),
.hv_offset_1(HV_OFFSET_1),
.vde_out(vde), .vde_out(vde),
.hde_out(hde), .hde_out(hde),
.vs_out(vs_hdmi), .vs_out(vs_hdmi),
@ -376,14 +428,14 @@ sync_vg #(.X_BITS(12), .Y_BITS(12)) sync_vg
.h_count_out(), .h_count_out(),
.x_out(x), .x_out(x),
.y_out(y), .y_out(y),
.hs_out(hs_hdmi), .hs_out(hs_hdmi)
.field_out(field)
); );
wire vde, hde; wire vde, hde;
wire vs_hdmi; wire vs_hdmi;
wire hs_hdmi; wire hs_hdmi;
wire field;
/*
pattern_vg pattern_vg
#( #(
@ -395,9 +447,9 @@ pattern_vg
pattern_vg pattern_vg
( (
.reset(reset), .reset(reset),
.clk_in(HDMI_TX_CLK), .clk_in(iHdmiClk),
.x(x), .x(x),
.y(y[11:0]), .y(y),
.vn_in(vs_hdmi), .vn_in(vs_hdmi),
.hn_in(hs_hdmi), .hn_in(hs_hdmi),
.dn_in(vde & hde), .dn_in(vde & hde),
@ -410,11 +462,12 @@ pattern_vg
.r_out(hdmi_data[23:16]), .r_out(hdmi_data[23:16]),
.g_out(hdmi_data[15:8]), .g_out(hdmi_data[15:8]),
.b_out(hdmi_data[7:0]), .b_out(hdmi_data[7:0]),
.total_active_pix(H_TOTAL - (H_FP + H_BP + H_SYNC)), .total_active_pix(WIDTH),
.total_active_lines(INTERLACED ? (V_TOTAL_0 - (V_FP_0 + V_BP_0 + V_SYNC_0)) + (V_TOTAL_1 - (V_FP_1 + V_BP_1 + V_SYNC_1)) : (V_TOTAL_0 - (V_FP_0 + V_BP_0 + V_SYNC_0))), // originally: 13'd480 .total_active_lines(HEIGHT),
.pattern(4), .pattern(4),
.ramp_step(20'h0333) .ramp_step(20'h0333)
); );
*/
wire reset; wire reset;
sysmem_lite sysmem sysmem_lite sysmem
@ -422,7 +475,7 @@ sysmem_lite sysmem
//Reset/Clock //Reset/Clock
.reset_reset_req(reset_req), .reset_reset_req(reset_req),
.reset_reset(reset), .reset_reset(reset),
.ctl_clock(ctl_clk), .ctl_clock(clk_ctl),
//DE10-nano has no reset signal on GPIO, so core has to emulate cold reset button. //DE10-nano has no reset signal on GPIO, so core has to emulate cold reset button.
.reset_cold_req(~btn_reset), .reset_cold_req(~btn_reset),
@ -452,7 +505,67 @@ sysmem_lite sysmem
.ram2_read(0), .ram2_read(0),
.ram2_writedata(0), .ram2_writedata(0),
.ram2_byteenable(0), .ram2_byteenable(0),
.ram2_write(0) .ram2_write(0),
// HDMI frame buffer
.vbuf_clk(clk_ctl),
.vbuf_address(vbuf_address),
.vbuf_burstcount(vbuf_burstcount),
.vbuf_waitrequest(vbuf_waitrequest),
.vbuf_writedata(vbuf_writedata),
.vbuf_byteenable(vbuf_byteenable),
.vbuf_write(vbuf_write),
.vbuf_readdata(vbuf_readdata),
.vbuf_readdatavalid(vbuf_readdatavalid),
.vbuf_read(vbuf_read)
);
wire [27:0] vbuf_address;
wire [7:0] vbuf_burstcount;
wire vbuf_waitrequest;
wire [127:0] vbuf_readdata;
wire vbuf_readdatavalid;
wire vbuf_read;
wire [127:0] vbuf_writedata;
wire [15:0] vbuf_byteenable;
wire vbuf_write;
assign HDMI_TX_VS = vs_hdmi;
assign HDMI_TX_HS = hs_hdmi;
hdmi_lite hdmi_lite
(
.reset(reset),
.clk_video(clk_vid),
.ce_pixel(ce_pix),
.video_vs(vs),
.video_de(de),
.video_d({r_out,g_out,b_out}),
.clk_hdmi(HDMI_TX_CLK),
.hdmi_hde(hde),
.hdmi_vde(vde),
.hdmi_d(hdmi_data),
.hdmi_de(hdmi_de),
.screen_w(WIDTH),
.screen_h(HEIGHT),
.quadbuf(1),
.scale_x(0),
.scale_y(0),
.scale_auto(1),
.clk_vbuf(clk_ctl),
.vbuf_address(vbuf_address),
.vbuf_burstcount(vbuf_burstcount),
.vbuf_waitrequest(vbuf_waitrequest),
.vbuf_writedata(vbuf_writedata),
.vbuf_byteenable(vbuf_byteenable),
.vbuf_write(vbuf_write),
.vbuf_readdata(vbuf_readdata),
.vbuf_readdatavalid(vbuf_readdatavalid),
.vbuf_read(vbuf_read)
); );
`endif `endif
@ -463,42 +576,109 @@ sysmem_lite sysmem
pll_hdmi pll_hdmi pll_hdmi pll_hdmi
( (
.refclk(FPGA_CLK1_50), .refclk(FPGA_CLK1_50),
.rst(reset), .rst(reset_req),
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll),
.outclk_0(HDMI_TX_CLK) .outclk_0(HDMI_TX_CLK)
); );
//1920x1080@60 PCLK=148.5MHz CEA
reg [11:0] WIDTH = 1920;
reg [11:0] HFP = 88;
reg [11:0] HS = 48;
reg [11:0] HBP = 148;
reg [11:0] HEIGHT = 1080;
reg [11:0] VFP = 4;
reg [11:0] VS = 5;
reg [11:0] VBP = 36;
reg [11:0] VSET = 0;
wire [63:0] reconfig_to_pll;
wire [63:0] reconfig_from_pll;
wire cfg_waitrequest;
reg cfg_write;
reg [5:0] cfg_address;
reg [31:0] cfg_data;
pll_hdmi_cfg pll_hdmi_cfg
(
.mgmt_clk(FPGA_CLK1_50),
.mgmt_reset(reset_req),
.mgmt_waitrequest(cfg_waitrequest),
.mgmt_read(0),
.mgmt_readdata(),
.mgmt_write(cfg_write),
.mgmt_address(cfg_address),
.mgmt_writedata(cfg_data),
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll)
);
reg cfg_ready = 0;
always @(posedge FPGA_CLK1_50) begin
reg gotd = 0, gotd2 = 0;
reg custd = 0, custd2 = 0;
reg old_wait = 0;
gotd <= cfg_got;
gotd2 <= gotd;
cfg_write <= 0;
custd <= cfg_custom_t;
custd2 <= custd;
if(custd2 != custd & ~gotd) begin
cfg_address <= cfg_custom_p1;
cfg_data <= cfg_custom_p2;
cfg_write <= 1;
end
if(~gotd2 & gotd) begin
cfg_address <= 2;
cfg_data <= 0;
cfg_write <= 1;
end
old_wait <= cfg_waitrequest;
if(old_wait & ~cfg_waitrequest & gotd) cfg_ready <= 1;
end
hdmi_config hdmi_config hdmi_config hdmi_config
( (
.iCLK(FPGA_CLK1_50), .iCLK(FPGA_CLK1_50),
.iRST_N(cfg_ready), .iRST_N(cfg_ready & ~HDMI_TX_INT),
.I2C_SCL(HDMI_I2C_SCL), .I2C_SCL(HDMI_I2C_SCL),
.I2C_SDA(HDMI_I2C_SDA), .I2C_SDA(HDMI_I2C_SDA),
.audio_48k(~audio_96k), .dvi_mode(dvi_mode),
.iRES(4), // 720p .audio_96k(audio_96k)
.iAR(1) // Aspect Ratio
); );
wire [23:0] hdmi_data; wire [23:0] hdmi_data;
wire hdmi_de;
osd hdmi_osd osd hdmi_osd
( (
.clk_sys(clk_sys), .clk_sys(clk_sys),
.io_osd(io_osd), .io_osd(io_osd),
.io_strobe(io_strobe), .io_strobe(io_strobe),
.io_din(io_din[7:0]), .io_din(io_din),
.clk_video(HDMI_TX_CLK), .clk_video(iHdmiClk),
.din(hdmi_data), .din(hdmi_data),
.dout(HDMI_TX_D), .dout(HDMI_TX_D),
.de(HDMI_TX_DE) .de_in(hdmi_de),
.de_out(HDMI_TX_DE)
); );
assign HDMI_MCLK = 0; assign HDMI_MCLK = 0;
i2s i2s i2s i2s
( (
.reset(~cfg_ready), .reset(~cfg_ready),
.clk_sys(FPGA_CLK1_50), .clk_sys(FPGA_CLK3_50),
.half_rate(~audio_96k), .half_rate(~audio_96k),
.sclk(HDMI_SCLK), .sclk(HDMI_SCLK),
@ -520,12 +700,12 @@ osd vga_osd
.io_osd(io_osd), .io_osd(io_osd),
.io_strobe(io_strobe), .io_strobe(io_strobe),
.io_din(io_din[7:0]), .io_din(io_din),
.clk_video(clk_vid), .clk_video(clk_vid),
.din(de ? {r_out, g_out, b_out} : 24'd0), .din(de ? {r_out, g_out, b_out} : 24'd0),
.dout(vga_q), .dout(vga_q),
.de(de) .de_in(de)
); );
wire [23:0] vga_o; wire [23:0] vga_o;
@ -559,12 +739,14 @@ assign VGA_B = VGA_EN ? 6'bZZZZZZ : vga_o[7:2];
///////////////////////// Audio output //////////////////////////////// ///////////////////////// Audio output ////////////////////////////////
wire al, ar, aspdif;
sigma_delta_dac #(15) dac_l sigma_delta_dac #(15) dac_l
( (
.CLK(FPGA_CLK3_50), .CLK(FPGA_CLK3_50),
.RESET(reset), .RESET(reset),
.DACin({audio_l[15] ^ audio_s, audio_l[14:0]}), .DACin({audio_l[15] ^ audio_s, audio_l[14:0]}),
.DACout(AUDIO_L) .DACout(al)
); );
sigma_delta_dac #(15) dac_r sigma_delta_dac #(15) dac_r
@ -572,7 +754,7 @@ sigma_delta_dac #(15) dac_r
.CLK(FPGA_CLK3_50), .CLK(FPGA_CLK3_50),
.RESET(reset), .RESET(reset),
.DACin({audio_r[15] ^ audio_s, audio_r[14:0]}), .DACin({audio_r[15] ^ audio_s, audio_r[14:0]}),
.DACout(AUDIO_R) .DACout(ar)
); );
spdif toslink spdif toslink
@ -585,14 +767,63 @@ spdif toslink
.audio_l(audio_l >> !audio_s), .audio_l(audio_l >> !audio_s),
.audio_r(audio_r >> !audio_s), .audio_r(audio_r >> !audio_s),
.spdif_o(AUDIO_SPDIF) .spdif_o(aspdif)
); );
assign AUDIO_SPDIF = SW[0] ? HDMI_LRCLK : aspdif;
assign AUDIO_R = SW[0] ? HDMI_I2S : ar;
assign AUDIO_L = SW[0] ? HDMI_SCLK : al;
reg [15:0] audio_l;
reg [15:0] audio_r;
always @(posedge FPGA_CLK3_50) begin
reg signed [15:0] al;
reg signed [15:0] ar;
case({audio_s,audio_mix})
'b000: al <= audio_ls;
'b001: al <= audio_ls - (audio_ls >> 3) + (audio_rs >> 3);
'b010: al <= audio_ls - (audio_ls >> 2) + (audio_rs >> 2);
'b011: al <= (audio_ls >> 1) + (audio_rs >> 1);
'b100: al <= audio_ls;
'b101: al <= audio_ls - (audio_ls >>> 3) + (audio_rs >>> 3);
'b110: al <= audio_ls - (audio_ls >>> 2) + (audio_rs >>> 2);
'b111: al <= (audio_ls >>> 1) + (audio_rs >>> 1);
endcase
case({audio_s,audio_mix})
'b000: ar <= audio_rs;
'b001: ar <= audio_rs - (audio_rs >> 3) + (audio_ls >> 3);
'b010: ar <= audio_rs - (audio_rs >> 2) + (audio_ls >> 2);
'b011: ar <= (audio_rs >> 1) + (audio_ls >> 1);
'b100: ar <= audio_rs;
'b101: ar <= audio_rs - (audio_rs >>> 3) + (audio_ls >>> 3);
'b110: ar <= audio_rs - (audio_rs >>> 2) + (audio_ls >>> 2);
'b111: ar <= (audio_rs >>> 1) + (audio_ls >>> 1);
endcase
if(vol_att[4]) begin
audio_l <= 0;
audio_r <= 0;
end
else
if(audio_s) begin
audio_l <= al >>> vol_att[3:0];
audio_r <= ar >>> vol_att[3:0];
end
else
begin
audio_l <= al >> vol_att[3:0];
audio_r <= ar >> vol_att[3:0];
end
end
/////////////////// User module connection //////////////////////////// /////////////////// User module connection ////////////////////////////
wire [15:0] audio_l, audio_r; wire signed [15:0] audio_ls, audio_rs;
wire audio_s; wire audio_s;
wire [1:0] audio_mix;
wire [7:0] r_out, g_out, b_out; wire [7:0] r_out, g_out, b_out;
wire vs, hs, de; wire vs, hs, de;
wire clk_sys, clk_vid, ce_pix; wire clk_sys, clk_vid, ce_pix;
@ -612,11 +843,15 @@ wire led_user;
wire [1:0] led_power; wire [1:0] led_power;
wire [1:0] led_disk; wire [1:0] led_disk;
wire vs_emu, hs_emu;
sync_fix sync_v(FPGA_CLK3_50, vs_emu, vs);
sync_fix sync_h(FPGA_CLK3_50, hs_emu, hs);
emu emu emu emu
( (
.CLK_50M(FPGA_CLK3_50), .CLK_50M(FPGA_CLK3_50),
.RESET(reset), .RESET(reset),
.HPS_BUS({ctl_clk, clk_vid, ce_pix, de, hs, vs, io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}), .HPS_BUS({HDMI_TX_VS, clk_ctl, clk_vid, ce_pix, de, hs, vs, io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}),
.CLK_VIDEO(clk_vid), .CLK_VIDEO(clk_vid),
.CE_PIXEL(ce_pix), .CE_PIXEL(ce_pix),
@ -624,8 +859,8 @@ emu emu
.VGA_R(r_out), .VGA_R(r_out),
.VGA_G(g_out), .VGA_G(g_out),
.VGA_B(b_out), .VGA_B(b_out),
.VGA_HS(hs), .VGA_HS(hs_emu),
.VGA_VS(vs), .VGA_VS(vs_emu),
.VGA_DE(de), .VGA_DE(de),
.LED_USER(led_user), .LED_USER(led_user),
@ -637,9 +872,10 @@ emu emu
.VIDEO_ARY(ARY), .VIDEO_ARY(ARY),
`endif `endif
.AUDIO_L(audio_l), .AUDIO_L(audio_ls),
.AUDIO_R(audio_r), .AUDIO_R(audio_rs),
.AUDIO_S(audio_s), .AUDIO_S(audio_s),
.AUDIO_MIX(audio_mix),
.TAPE_IN(0), .TAPE_IN(0),
// SCK -> CLK // SCK -> CLK
@ -647,12 +883,12 @@ emu emu
// MISO <- DAT0 // MISO <- DAT0
// Z -> DAT1 // Z -> DAT1
// Z -> DAT2 // Z -> DAT2
// CS -> DAT3 // CS -> DAT3
.SD_SCK(SDIO_CLK), .SD_SCK(SDIO_CLK),
.SD_MOSI(SDIO_CMD), .SD_MOSI(SDIO_CMD),
.SD_MISO(SDIO_DAT[0]), .SD_MISO(SDIO_DAT[0]),
.SD_CS(SDIO_DAT[3]), .SD_CS(SDIO_DAT[3]),
.SD_CD(VGA_EN ? VGA_HS : SDIO_CD),
.DDRAM_CLK(ram_clk), .DDRAM_CLK(ram_clk),
.DDRAM_ADDR(ram_address), .DDRAM_ADDR(ram_address),
@ -679,3 +915,32 @@ emu emu
); );
endmodule endmodule
module sync_fix
(
input clk,
input sync_in,
output sync_out
);
assign sync_out = sync_in ^ pol;
reg pol;
always @(posedge clk) begin
integer pos = 0, neg = 0, cnt = 0;
reg s1,s2;
s1 <= sync_in;
s2 <= s1;
if(~s2 & s1) neg <= cnt;
if(s2 & ~s1) pos <= cnt;
cnt <= cnt + 1;
if(s2 != s1) cnt <= 0;
pol <= pos > neg;
end
endmodule

2
sys/sysmem.qip
View File

@ -1,2 +0,0 @@
set_global_assignment -name SYSTEMVERILOG_FILE sys/sysmem.sv
set_global_assignment -name VERILOG_FILE sys/ip/reset_source.v

34
sys/sysmem.sv
View File

@ -27,7 +27,18 @@ module sysmem_lite
input reset_cold_req, // reset.cold_req input reset_cold_req, // reset.cold_req
output reset_reset, // .reset output reset_reset, // .reset
input reset_reset_req, // .reset_req input reset_reset_req, // .reset_req
input reset_warm_req // .warm_req input reset_warm_req, // .warm_req
input vbuf_clk, // vbuf.clk
input [27:0] vbuf_address, // vbuf.address
input [7:0] vbuf_burstcount, // .burstcount
output vbuf_waitrequest, // .waitrequest
output [127:0] vbuf_readdata, // .readdata
output vbuf_readdatavalid, // .readdatavalid
input vbuf_read, // .read
input [127:0] vbuf_writedata, // .writedata
input [15:0] vbuf_byteenable, // .byteenable
input vbuf_write // .write
); );
assign ctl_clock = clk_vip_clk; assign ctl_clock = clk_vip_clk;
@ -42,16 +53,16 @@ sysmem_HPS_fpga_interfaces fpga_interfaces (
.f2h_warm_rst_req_n (~reset_source_reset_warm_reset), // f2h_warm_reset_req.reset_n .f2h_warm_rst_req_n (~reset_source_reset_warm_reset), // f2h_warm_reset_req.reset_n
.h2f_user0_clk (clk_vip_clk), // h2f_user0_clock.clk .h2f_user0_clk (clk_vip_clk), // h2f_user0_clock.clk
.h2f_rst_n (hps_h2f_reset_reset), // h2f_reset.reset_n .h2f_rst_n (hps_h2f_reset_reset), // h2f_reset.reset_n
.f2h_sdram0_clk (clk_vip_clk), // f2h_sdram0_clock.clk .f2h_sdram0_clk (vbuf_clk), // f2h_sdram0_clock.clk
.f2h_sdram0_ADDRESS (0), // f2h_sdram0_data.address .f2h_sdram0_ADDRESS (vbuf_address), // f2h_sdram0_data.address
.f2h_sdram0_BURSTCOUNT (0), // .burstcount .f2h_sdram0_BURSTCOUNT (vbuf_burstcount), // .burstcount
.f2h_sdram0_WAITREQUEST (), // .waitrequest .f2h_sdram0_WAITREQUEST (vbuf_waitrequest), // .waitrequest
.f2h_sdram0_READDATA (), // .readdata .f2h_sdram0_READDATA (vbuf_readdata), // .readdata
.f2h_sdram0_READDATAVALID (), // .readdatavalid .f2h_sdram0_READDATAVALID (vbuf_readdatavalid), // .readdatavalid
.f2h_sdram0_READ (0), // .read .f2h_sdram0_READ (vbuf_read), // .read
.f2h_sdram0_WRITEDATA (0), // .writedata .f2h_sdram0_WRITEDATA (vbuf_writedata), // .writedata
.f2h_sdram0_BYTEENABLE (0), // .byteenable .f2h_sdram0_BYTEENABLE (vbuf_byteenable), // .byteenable
.f2h_sdram0_WRITE (0), // .write .f2h_sdram0_WRITE (vbuf_write), // .write
.f2h_sdram1_clk (ramclk1_clk), // f2h_sdram1_clock.clk .f2h_sdram1_clk (ramclk1_clk), // f2h_sdram1_clock.clk
.f2h_sdram1_ADDRESS (ram1_address), // f2h_sdram1_data.address .f2h_sdram1_ADDRESS (ram1_address), // f2h_sdram1_data.address
.f2h_sdram1_BURSTCOUNT (ram1_burstcount), // .burstcount .f2h_sdram1_BURSTCOUNT (ram1_burstcount), // .burstcount
@ -81,6 +92,7 @@ reset_source reset_source (
.cold_req (reset_cold_req), // reset_ctl.cold_req .cold_req (reset_cold_req), // reset_ctl.cold_req
.reset (reset_reset), // .reset .reset (reset_reset), // .reset
.reset_req (reset_reset_req), // .reset_req .reset_req (reset_reset_req), // .reset_req
.reset_vip (0), // .reset_vip
.warm_req (reset_warm_req), // .warm_req .warm_req (reset_warm_req), // .warm_req
.reset_warm (reset_source_reset_warm_reset), // reset_warm.reset .reset_warm (reset_source_reset_warm_reset), // reset_warm.reset
.reset_cold (reset_source_reset_cold_reset) // reset_cold.reset .reset_cold (reset_source_reset_cold_reset) // reset_cold.reset

2
sys/vip.qip
View File

@ -1,2 +0,0 @@
set_global_assignment -name SYSTEMVERILOG_FILE sys/vip_config.sv
set_global_assignment -name QIP_FILE sys/vip/synthesis/vip.qip

190
sys/vip.qsys
View File

@ -13,7 +13,7 @@
{ {
datum _sortIndex datum _sortIndex
{ {
value = "7"; value = "9";
type = "int"; type = "int";
} }
} }
@ -21,7 +21,7 @@
{ {
datum _sortIndex datum _sortIndex
{ {
value = "3"; value = "4";
type = "int"; type = "int";
} }
} }
@ -33,11 +33,27 @@
type = "int"; type = "int";
} }
} }
element Input
{
datum _sortIndex
{
value = "2";
type = "int";
}
}
element Mixer element Mixer
{ {
datum _sortIndex datum _sortIndex
{ {
value = "5"; value = "6";
type = "int";
}
}
element Output
{
datum _sortIndex
{
value = "8";
type = "int"; type = "int";
} }
} }
@ -53,7 +69,7 @@
{ {
datum _sortIndex datum _sortIndex
{ {
value = "4"; value = "5";
type = "int"; type = "int";
} }
} }
@ -61,7 +77,7 @@
{ {
datum _sortIndex datum _sortIndex
{ {
value = "2"; value = "3";
type = "int"; type = "int";
} }
} }
@ -69,7 +85,7 @@
{ {
datum _sortIndex datum _sortIndex
{ {
value = "6"; value = "7";
type = "int"; type = "int";
} }
} }
@ -489,6 +505,62 @@
type = "String"; type = "String";
} }
} }
element vip
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
element vip
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
element vip
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
element vip
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
element vip
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
element vip
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
element vip
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
} }
]]></parameter> ]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" /> <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
@ -512,16 +584,10 @@
<instanceScript></instanceScript> <instanceScript></instanceScript>
<interface name="ctl" internal="Controller.control" type="conduit" dir="end" /> <interface name="ctl" internal="Controller.control" type="conduit" dir="end" />
<interface name="finish" internal="Reset_Source.reset_cold_req" /> <interface name="finish" internal="Reset_Source.reset_cold_req" />
<interface <interface name="hdmi" internal="Output.Output" type="conduit" dir="end" />
name="hdmi" <interface name="in" internal="Input.input" type="conduit" dir="end" />
internal="Video_Output.clocked_video" <interface name="out_mix_0_Output" internal="Output.Output1" />
type="conduit" <interface name="out_mix_0_input" internal="Output.input1" />
dir="end" />
<interface
name="in"
internal="Video_Input.clocked_video"
type="conduit"
dir="end" />
<interface name="ram1" internal="HPS.f2h_sdram1_data" type="avalon" dir="end" /> <interface name="ram1" internal="HPS.f2h_sdram1_data" type="avalon" dir="end" />
<interface name="ram2" internal="HPS.f2h_sdram2_data" type="avalon" dir="end" /> <interface name="ram2" internal="HPS.f2h_sdram2_data" type="avalon" dir="end" />
<interface name="ramclk1" internal="HPS.f2h_sdram1_clock" type="clock" dir="end" /> <interface name="ramclk1" internal="HPS.f2h_sdram1_clock" type="clock" dir="end" />
@ -531,13 +597,13 @@
internal="Reset_Source.reset_ctl" internal="Reset_Source.reset_ctl"
type="conduit" type="conduit"
dir="end" /> dir="end" />
<module name="Controller" kind="avalon_combiner" version="1.0" enabled="1" /> <module name="Controller" kind="avalon_combiner" version="17.0" enabled="1" />
<module name="Frame_Buffer" kind="alt_vip_cl_vfb" version="17.0" enabled="1"> <module name="Frame_Buffer" kind="alt_vip_cl_vfb" version="17.0" enabled="1">
<parameter name="AUTO_DEVICE" value="5CSEBA6U23I7" /> <parameter name="AUTO_DEVICE" value="5CSEBA6U23I7" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" /> <parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" />
<parameter name="BITS_PER_SYMBOL" value="8" /> <parameter name="BITS_PER_SYMBOL" value="8" />
<parameter name="BURST_ALIGNMENT" value="1" /> <parameter name="BURST_ALIGNMENT" value="1" />
<parameter name="CLOCKS_ARE_SEPARATE" value="1" /> <parameter name="CLOCKS_ARE_SEPARATE" value="0" />
<parameter name="COLOR_PLANES_ARE_IN_PARALLEL" value="1" /> <parameter name="COLOR_PLANES_ARE_IN_PARALLEL" value="1" />
<parameter name="CONTROLLED_DROP_REPEAT" value="0" /> <parameter name="CONTROLLED_DROP_REPEAT" value="0" />
<parameter name="DROP_FRAMES" value="1" /> <parameter name="DROP_FRAMES" value="1" />
@ -557,20 +623,20 @@
<parameter name="MEM_PORT_WIDTH" value="128" /> <parameter name="MEM_PORT_WIDTH" value="128" />
<parameter name="MULTI_FRAME_DELAY" value="1" /> <parameter name="MULTI_FRAME_DELAY" value="1" />
<parameter name="NUMBER_OF_COLOR_PLANES" value="3" /> <parameter name="NUMBER_OF_COLOR_PLANES" value="3" />
<parameter name="PIXELS_IN_PARALLEL" value="1" /> <parameter name="PIXELS_IN_PARALLEL" value="2" />
<parameter name="READER_RUNTIME_CONTROL" value="0" /> <parameter name="READER_RUNTIME_CONTROL" value="0" />
<parameter name="READY_LATENCY" value="1" /> <parameter name="READY_LATENCY" value="1" />
<parameter name="READ_BURST_TARGET" value="32" /> <parameter name="READ_BURST_TARGET" value="64" />
<parameter name="READ_FIFO_DEPTH" value="512" /> <parameter name="READ_FIFO_DEPTH" value="512" />
<parameter name="REPEAT_FRAMES" value="1" /> <parameter name="REPEAT_FRAMES" value="1" />
<parameter name="TEST_INIT" value="0" /> <parameter name="TEST_INIT" value="0" />
<parameter name="USER_PACKETS_MAX_STORAGE" value="1" /> <parameter name="USER_PACKETS_MAX_STORAGE" value="1" />
<parameter name="USE_BUFFER_OFFSET" value="0" /> <parameter name="USE_BUFFER_OFFSET" value="0" />
<parameter name="WRITER_RUNTIME_CONTROL" value="0" /> <parameter name="WRITER_RUNTIME_CONTROL" value="0" />
<parameter name="WRITE_BURST_TARGET" value="32" /> <parameter name="WRITE_BURST_TARGET" value="64" />
<parameter name="WRITE_FIFO_DEPTH" value="512" /> <parameter name="WRITE_FIFO_DEPTH" value="512" />
</module> </module>
<module name="HPS" kind="altera_hps_lite" version="16.1" enabled="1"> <module name="HPS" kind="altera_hps_lite" version="17.0" enabled="1">
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" /> <parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" />
<parameter name="BONDING_OUT_ENABLED" value="false" /> <parameter name="BONDING_OUT_ENABLED" value="false" />
<parameter name="BOOTFROMFPGA_Enable" value="false" /> <parameter name="BOOTFROMFPGA_Enable" value="false" />
@ -784,6 +850,7 @@
<parameter name="usb_mp_clk_div" value="0" /> <parameter name="usb_mp_clk_div" value="0" />
<parameter name="use_default_mpu_clk" value="true" /> <parameter name="use_default_mpu_clk" value="true" />
</module> </module>
<module name="Input" kind="in_split" version="17.0" enabled="1" />
<module name="Mixer" kind="alt_vip_cl_mixer" version="17.0" enabled="1"> <module name="Mixer" kind="alt_vip_cl_mixer" version="17.0" enabled="1">
<parameter name="ALPHA_ENABLE" value="0" /> <parameter name="ALPHA_ENABLE" value="0" />
<parameter name="ALPHA_STREAMS_ENABLE" value="0" /> <parameter name="ALPHA_STREAMS_ENABLE" value="0" />
@ -801,18 +868,19 @@
<parameter name="NUMBER_OF_COLOR_PLANES" value="2" /> <parameter name="NUMBER_OF_COLOR_PLANES" value="2" />
<parameter name="PATTERN" value="uniform" /> <parameter name="PATTERN" value="uniform" />
<parameter name="PIPELINE_READY" value="0" /> <parameter name="PIPELINE_READY" value="0" />
<parameter name="PIXELS_IN_PARALLEL" value="1" /> <parameter name="PIXELS_IN_PARALLEL" value="2" />
<parameter name="UNIFORM_VALUE_BCR" value="0" /> <parameter name="UNIFORM_VALUE_BCR" value="0" />
<parameter name="UNIFORM_VALUE_GCB" value="0" /> <parameter name="UNIFORM_VALUE_GCB" value="0" />
<parameter name="UNIFORM_VALUE_RY" value="0" /> <parameter name="UNIFORM_VALUE_RY" value="0" />
<parameter name="USER_PACKET_FIFO_DEPTH" value="0" /> <parameter name="USER_PACKET_FIFO_DEPTH" value="0" />
<parameter name="USER_PACKET_SUPPORT" value="DISCARD" /> <parameter name="USER_PACKET_SUPPORT" value="DISCARD" />
</module> </module>
<module name="Reset_Source" kind="reset_source" version="1.0" enabled="1" /> <module name="Output" kind="out_mix" version="17.0" enabled="1" />
<module name="Reset_Source" kind="reset_source" version="17.0" enabled="1" />
<module name="Scaler" kind="alt_vip_cl_scl" version="17.0" enabled="1"> <module name="Scaler" kind="alt_vip_cl_scl" version="17.0" enabled="1">
<parameter name="ALGORITHM_NAME" value="BICUBIC" /> <parameter name="ALGORITHM_NAME" value="POLYPHASE" />
<parameter name="ALWAYS_DOWNSCALE" value="0" /> <parameter name="ALWAYS_DOWNSCALE" value="0" />
<parameter name="ARE_IDENTICAL" value="0" /> <parameter name="ARE_IDENTICAL" value="1" />
<parameter name="AUTO_DEVICE" value="5CSEBA6U23I7" /> <parameter name="AUTO_DEVICE" value="5CSEBA6U23I7" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" /> <parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" />
<parameter name="BITS_PER_SYMBOL" value="8" /> <parameter name="BITS_PER_SYMBOL" value="8" />
@ -820,7 +888,7 @@
<parameter name="DEFAULT_LOWER_BLUR" value="0" /> <parameter name="DEFAULT_LOWER_BLUR" value="0" />
<parameter name="DEFAULT_UPPER_BLUR" value="0" /> <parameter name="DEFAULT_UPPER_BLUR" value="0" />
<parameter name="ENABLE_FIR" value="0" /> <parameter name="ENABLE_FIR" value="0" />
<parameter name="EXTRA_PIPELINING" value="0" /> <parameter name="EXTRA_PIPELINING" value="1" />
<parameter name="FAMILY" value="Cyclone V" /> <parameter name="FAMILY" value="Cyclone V" />
<parameter name="H_BANKS" value="1" /> <parameter name="H_BANKS" value="1" />
<parameter name="H_COEFF_FILE"><![CDATA[<enter file name (including full path)>]]></parameter> <parameter name="H_COEFF_FILE"><![CDATA[<enter file name (including full path)>]]></parameter>
@ -840,7 +908,7 @@
<parameter name="MAX_OUT_HEIGHT" value="1080" /> <parameter name="MAX_OUT_HEIGHT" value="1080" />
<parameter name="MAX_OUT_WIDTH" value="1920" /> <parameter name="MAX_OUT_WIDTH" value="1920" />
<parameter name="NO_BLANKING" value="0" /> <parameter name="NO_BLANKING" value="0" />
<parameter name="PIXELS_IN_PARALLEL" value="1" /> <parameter name="PIXELS_IN_PARALLEL" value="2" />
<parameter name="PRESERVE_BITS" value="0" /> <parameter name="PRESERVE_BITS" value="0" />
<parameter name="RUNTIME_CONTROL" value="1" /> <parameter name="RUNTIME_CONTROL" value="1" />
<parameter name="SYMBOLS_IN_PAR" value="3" /> <parameter name="SYMBOLS_IN_PAR" value="3" />
@ -850,9 +918,9 @@
<parameter name="V_BANKS" value="1" /> <parameter name="V_BANKS" value="1" />
<parameter name="V_COEFF_FILE"><![CDATA[<enter file name (including full path)>]]></parameter> <parameter name="V_COEFF_FILE"><![CDATA[<enter file name (including full path)>]]></parameter>
<parameter name="V_FRACTION_BITS" value="7" /> <parameter name="V_FRACTION_BITS" value="7" />
<parameter name="V_FUNCTION" value="LANCZOS_3" /> <parameter name="V_FUNCTION" value="LANCZOS_2" />
<parameter name="V_INTEGER_BITS" value="1" /> <parameter name="V_INTEGER_BITS" value="1" />
<parameter name="V_PHASES" value="16" /> <parameter name="V_PHASES" value="32" />
<parameter name="V_SIGNED" value="1" /> <parameter name="V_SIGNED" value="1" />
<parameter name="V_SYMMETRIC" value="0" /> <parameter name="V_SYMMETRIC" value="0" />
<parameter name="V_TAPS" value="4" /> <parameter name="V_TAPS" value="4" />
@ -877,7 +945,7 @@
<parameter name="NO_OF_CHANNELS" value="1" /> <parameter name="NO_OF_CHANNELS" value="1" />
<parameter name="NUMBER_OF_COLOUR_PLANES" value="3" /> <parameter name="NUMBER_OF_COLOUR_PLANES" value="3" />
<parameter name="OVERFLOW_HANDLING" value="0" /> <parameter name="OVERFLOW_HANDLING" value="0" />
<parameter name="PIXELS_IN_PARALLEL" value="1" /> <parameter name="PIXELS_IN_PARALLEL" value="2" />
<parameter name="STD_WIDTH" value="1" /> <parameter name="STD_WIDTH" value="1" />
<parameter name="SYNC_TO" value="2" /> <parameter name="SYNC_TO" value="2" />
<parameter name="USE_CONTROL" value="0" /> <parameter name="USE_CONTROL" value="0" />
@ -909,27 +977,27 @@
<parameter name="F_FALLING_EDGE" value="0" /> <parameter name="F_FALLING_EDGE" value="0" />
<parameter name="F_RISING_EDGE" value="0" /> <parameter name="F_RISING_EDGE" value="0" />
<parameter name="GENERATE_SYNC" value="0" /> <parameter name="GENERATE_SYNC" value="0" />
<parameter name="H_ACTIVE_PIXELS" value="1280" /> <parameter name="H_ACTIVE_PIXELS" value="1920" />
<parameter name="H_BACK_PORCH" value="220" /> <parameter name="H_BACK_PORCH" value="148" />
<parameter name="H_BLANK" value="0" /> <parameter name="H_BLANK" value="0" />
<parameter name="H_FRONT_PORCH" value="110" /> <parameter name="H_FRONT_PORCH" value="88" />
<parameter name="H_SYNC_LENGTH" value="40" /> <parameter name="H_SYNC_LENGTH" value="44" />
<parameter name="INTERLACED" value="0" /> <parameter name="INTERLACED" value="0" />
<parameter name="LOW_LATENCY" value="0" /> <parameter name="LOW_LATENCY" value="1" />
<parameter name="NO_OF_CHANNELS" value="1" /> <parameter name="NO_OF_CHANNELS" value="1" />
<parameter name="NO_OF_MODES" value="1" /> <parameter name="NO_OF_MODES" value="1" />
<parameter name="NUMBER_OF_COLOUR_PLANES" value="3" /> <parameter name="NUMBER_OF_COLOUR_PLANES" value="3" />
<parameter name="PIXELS_IN_PARALLEL" value="1" /> <parameter name="PIXELS_IN_PARALLEL" value="2" />
<parameter name="SRC_WIDTH" value="8" /> <parameter name="SRC_WIDTH" value="8" />
<parameter name="STD_WIDTH" value="1" /> <parameter name="STD_WIDTH" value="1" />
<parameter name="TASK_WIDTH" value="8" /> <parameter name="TASK_WIDTH" value="8" />
<parameter name="THRESHOLD" value="1999" /> <parameter name="THRESHOLD" value="1999" />
<parameter name="USE_CONTROL" value="1" /> <parameter name="USE_CONTROL" value="1" />
<parameter name="USE_EMBEDDED_SYNCS" value="0" /> <parameter name="USE_EMBEDDED_SYNCS" value="0" />
<parameter name="V_ACTIVE_LINES" value="720" /> <parameter name="V_ACTIVE_LINES" value="1080" />
<parameter name="V_BACK_PORCH" value="20" /> <parameter name="V_BACK_PORCH" value="15" />
<parameter name="V_BLANK" value="0" /> <parameter name="V_BLANK" value="0" />
<parameter name="V_FRONT_PORCH" value="5" /> <parameter name="V_FRONT_PORCH" value="2" />
<parameter name="V_SYNC_LENGTH" value="5" /> <parameter name="V_SYNC_LENGTH" value="5" />
</module> </module>
<connection <connection
@ -980,13 +1048,13 @@
<connection <connection
kind="avalon_streaming" kind="avalon_streaming"
version="17.0" version="17.0"
start="Frame_Buffer.dout" start="Mixer.dout"
end="Scaler.din" /> end="Video_Output.din" />
<connection <connection
kind="avalon_streaming" kind="avalon_streaming"
version="17.0" version="17.0"
start="Mixer.dout" start="Frame_Buffer.dout"
end="Video_Output.din" /> end="Scaler.din" />
<connection <connection
kind="avalon_streaming" kind="avalon_streaming"
version="17.0" version="17.0"
@ -1017,6 +1085,11 @@
version="17.0" version="17.0"
start="HPS.h2f_user0_clock" start="HPS.h2f_user0_clock"
end="Video_Input.main_clock" /> end="Video_Input.main_clock" />
<connection
kind="clock"
version="17.0"
start="HPS.h2f_user0_clock"
end="Frame_Buffer.main_clock" />
<connection <connection
kind="clock" kind="clock"
version="17.0" version="17.0"
@ -1033,15 +1106,27 @@
start="HPS.h2f_user0_clock" start="HPS.h2f_user0_clock"
end="Video_Output.main_clock" /> end="Video_Output.main_clock" />
<connection <connection
kind="clock" kind="conduit"
version="17.0" version="17.0"
start="HPS.h2f_user0_clock" start="Video_Input.clocked_video"
end="Frame_Buffer.main_clock" /> end="Input.Output">
<parameter name="endPort" value="" />
<parameter name="endPortLSB" value="0" />
<parameter name="startPort" value="" />
<parameter name="startPortLSB" value="0" />
<parameter name="width" value="0" />
</connection>
<connection <connection
kind="clock" kind="conduit"
version="17.0" version="17.0"
start="HPS.h2f_user0_clock" start="Video_Output.clocked_video"
end="Frame_Buffer.mem_clock" /> end="Output.input">
<parameter name="endPort" value="" />
<parameter name="endPortLSB" value="0" />
<parameter name="startPort" value="" />
<parameter name="startPortLSB" value="0" />
<parameter name="width" value="0" />
</connection>
<connection <connection
kind="reset" kind="reset"
version="17.0" version="17.0"
@ -1077,11 +1162,6 @@
version="17.0" version="17.0"
start="Reset_Source.reset_sys" start="Reset_Source.reset_sys"
end="Video_Output.main_reset" /> end="Video_Output.main_reset" />
<connection
kind="reset"
version="17.0"
start="Reset_Source.reset_sys"
end="Frame_Buffer.mem_reset" />
<connection <connection
kind="reset" kind="reset"
version="17.0" version="17.0"

254
sys/vip_config.sv
View File

@ -6,6 +6,18 @@ module vip_config
input [7:0] ARX, input [7:0] ARX,
input [7:0] ARY, input [7:0] ARY,
input CFG_SET,
input [11:0] WIDTH,
input [11:0] HFP,
input [11:0] HBP,
input [11:0] HS,
input [11:0] HEIGHT,
input [11:0] VFP,
input [11:0] VBP,
input [11:0] VS,
input [11:0] VSET,
output reg [8:0] address, output reg [8:0] address,
output reg write, output reg write,
@ -13,156 +25,134 @@ module vip_config
input waitrequest input waitrequest
); );
//Any input video resolution up to 1920x1080 is supported.
//Output video parameters. reg newres = 1;
//It's good to keep 1280x720@60 resolution among all cores as most compatible resolution.
parameter WIDTH = 1280;
parameter HEIGHT = 720;
parameter HFP = 110;
parameter HBP = 220;
parameter HS = 40;
parameter VFP = 5;
parameter VBP = 20;
parameter VS = 5;
wire [21:0] init[23] =
'{
//video mode
{newres, 2'd2, 7'd04, 12'd0 }, //Bank
{newres, 2'd2, 7'd30, 12'd0 }, //Valid
{newres, 2'd2, 7'd05, 12'd0 }, //Progressive/Interlaced
{newres, 2'd2, 7'd06, w }, //Active pixel count
{newres, 2'd2, 7'd07, h }, //Active line count
{newres, 2'd2, 7'd09, hfp }, //Horizontal Front Porch
{newres, 2'd2, 7'd10, hs }, //Horizontal Sync Length
{newres, 2'd2, 7'd11, hb }, //Horizontal Blanking (HFP+HBP+HSync)
{newres, 2'd2, 7'd12, vfp }, //Vertical Front Porch
{newres, 2'd2, 7'd13, vs }, //Vertical Sync Length
{newres, 2'd2, 7'd14, vb }, //Vertical blanking (VFP+VBP+VSync)
{newres, 2'd2, 7'd30, 12'd1 }, //Valid
{newres, 2'd2, 7'd00, 12'd1 }, //Go
reg [31:0] wcalc; //mixer
reg [31:0] hcalc; { 1'd1, 2'd1, 7'd03, w }, //Bkg Width
{ 1'd1, 2'd1, 7'd04, h }, //Bkg Height
{ 1'd1, 2'd1, 7'd08, posx }, //Pos X
{ 1'd1, 2'd1, 7'd09, posy }, //Pos Y
{ 1'd1, 2'd1, 7'd10, 12'd1 }, //Enable Video 0
{ 1'd1, 2'd1, 7'd00, 12'd1 }, //Go
wire [31:0] videow = (wcalc > WIDTH) ? WIDTH : wcalc; //scaler
wire [31:0] videoh = (hcalc > HEIGHT) ? HEIGHT : hcalc; { 1'd1, 2'd0, 7'd03, videow }, //Output Width
{ 1'd1, 2'd0, 7'd04, videoh }, //Output Height
{ 1'd1, 2'd0, 7'd00, 12'd1 }, //Go
wire [31:0] posx = (WIDTH - videow)>>1; 22'h3FFFFF
wire [31:0] posy = (HEIGHT- videoh)>>1; };
reg [11:0] w;
reg [11:0] hfp;
reg [11:0] hbp;
reg [11:0] hs;
reg [11:0] hb;
reg [11:0] h;
reg [11:0] vfp;
reg [11:0] vbp;
reg [11:0] vs;
reg [11:0] vb;
reg [11:0] videow;
reg [11:0] videoh;
reg [11:0] posx;
reg [11:0] posy;
always @(posedge clk) begin always @(posedge clk) begin
reg [7:0] state = 0; reg [7:0] state = 0;
reg [7:0] arx, ary; reg [7:0] arx, ary;
integer timeout = 0; reg [7:0] arxd, aryd;
reg [11:0] vset, vsetd;
reg cfg, cfgd;
reg [31:0] wcalc;
reg [31:0] hcalc;
reg [12:0] timeout = 0;
if(reset || (!state && ((arx != ARX) || (ary != ARY)))) begin arxd <= ARX;
arx <= ARX; aryd <= ARY;
ary <= ARY; vsetd <= VSET;
timeout <= 0;
write <= 0; cfg <= CFG_SET;
cfgd <= cfg;
write <= 0;
if(reset || (arx != arxd) || (ary != aryd) || (vset != vsetd) || (~cfgd && cfg)) begin
arx <= arxd;
ary <= aryd;
vset <= vsetd;
timeout <= '1;
state <= 0;
if(reset || (~cfgd && cfg)) newres <= 1;
end end
else else
if(timeout < 1000000) if(timeout > 0)
begin begin
timeout <= timeout + 1; timeout <= timeout - 1'd1;
write <= 0;
state <= 1; state <= 1;
if(!(timeout & 'h1f)) case(timeout>>5)
5: begin
w <= WIDTH;
hfp <= HFP;
hbp <= HBP;
hs <= HS;
h <= HEIGHT;
vfp <= VFP;
vbp <= VBP;
vs <= VS;
end
4: begin
hb <= hfp+hbp+hs;
vb <= vfp+vbp+vs;
end
3: begin
wcalc <= vset ? (vset*arx)/ary : (h*arx)/ary;
hcalc <= (w*ary)/arx;
end
2: begin
videow <= (!vset && (wcalc > w)) ? w : wcalc[11:0];
videoh <= vset ? vset : (hcalc > h) ? h : hcalc[11:0];
end
1: begin
posx <= (w - videow)>>1;
posy <= (h - videoh)>>1;
end
endcase
end end
else else
if(~waitrequest && state) if(~waitrequest && state)
begin begin
state <= state + 1'd1; state <= state + 1'd1;
write <= 1; write <= 0;
if((state&3)==3) begin
case(state) if(init[state>>2] == 22'h3FFFFF) begin
01: begin state <= 0;
wcalc <= (HEIGHT*arx)/ary; newres <= 0;
hcalc <= (WIDTH*ary)/arx; end
end else begin
endcase writedata <= 0;
{write, address, writedata[11:0]} <= init[state>>2];
if(state&3) write <= 0; end
else end
case(state>>2)
//scaler
01: begin
address <= 'h003; //Output Width
writedata <= videow;
end
02: begin
address <= 'h004; //Output Height
writedata <= videoh;
end
03: begin
address <= 'h000; //Go
writedata <= 1;
end
//mixer
10: begin
address <= 'h083; //Bkg Width
writedata <= WIDTH;
end
11: begin
address <= 'h084; //Bkg Height
writedata <= HEIGHT;
end
12: begin
address <= 'h088; //Pos X
writedata <= posx;
end
13: begin
address <= 'h089; //Pos Y
writedata <= posy;
end
14: begin
address <= 'h08A; //Enable Video 0
writedata <= 1;
end
15: begin
address <= 'h080; //Go
writedata <= 1;
end
//video mode
20: begin
address <= 'h104; //Bank
writedata <= 0;
end
21: begin
address <= 'h105; //Progressive/Interlaced
writedata <= 0;
end
22: begin
address <= 'h106; //Active pixel count
writedata <= WIDTH;
end
23: begin
address <= 'h107; //Active line count
writedata <= HEIGHT;
end
24: begin
address <= 'h109; //Horizontal Front Porch
writedata <= HFP;
end
25: begin
address <= 'h10A; //Horizontal Sync Length
writedata <= HS;
end
26: begin
address <= 'h10B; //Horizontal Blanking (HFP+HBP+HSync)
writedata <= HFP+HBP+HS;
end
27: begin
address <= 'h10C; //Vertical Front Porch
writedata <= VFP;
end
28: begin
address <= 'h10D; //Vertical Sync Length
writedata <= VS;
end
29: begin
address <= 'h10E; //Vertical blanking (VFP+VBP+VSync)
writedata <= VFP+VBP+VS;
end
30: begin
address <= 'h11E; //Valid
writedata <= 1;
end
31: begin
address <= 'h100; //Go
writedata <= 1;
end
default: write <= 0;
endcase
end end
end end