Thomas Harte
3097c4ccae
Improves MEMPTR testing and some results.
2020-02-24 23:32:18 -05:00
Thomas Harte
7959d243f6
Adds single-stepping. Of a kind.
2020-02-24 23:31:42 -05:00
Thomas Harte
79dd402bc8
Consolidates different test port input selection.
2020-02-23 16:12:28 -05:00
Thomas Harte
3f3229851b
Implements MEMPTR for IN.
2020-02-23 00:32:33 -05:00
Thomas Harte
989628a024
Switches to looking for "Result: all tests passed." as a success/failure test.
2020-02-22 23:07:14 -05:00
Thomas Harte
e0475343f5
Makes collated text easier to read.
2020-02-22 18:58:24 -05:00
Thomas Harte
da0a9113d4
Introduces the full range of tests.
...
Albeit that I don't know the correct output yet.
2020-02-22 18:44:15 -05:00
Thomas Harte
cf7ab97451
Gets the first test to run (and terminate).
2020-02-22 18:42:23 -05:00
Thomas Harte
2370575eb5
Starts introducing the Patrik Rak tests.
2020-02-22 15:49:36 -05:00
Thomas Harte
825b68e5c4
Adds separate entry points for zexall and zexdoc.
2020-02-22 12:34:47 -05:00
Thomas Harte
851cba0b25
Corrects lambda capture.
2020-02-22 12:34:16 -05:00
Thomas Harte
9ca2d8f9f2
Tried to be less lazy with lambda captures.
...
This is primarily defensive.
2020-02-14 23:39:08 -05:00
Thomas Harte
085529ed72
Makes the shifter behaviour conform to its documentation.
2020-02-02 17:26:39 -05:00
Thomas Harte
8b1f183198
Reduce test duration much closer to two frames.
2020-01-28 23:25:01 -05:00
Thomas Harte
5c4623e9f7
Adds a sequence-point test for 72Hz mode.
...
Which immediately appears to trigger the hsync issue I'm also seeing in manual testing.
2020-01-28 20:27:24 -05:00
Thomas Harte
189122ab84
Fixes test units.
2020-01-27 20:35:58 -05:00
Thomas Harte
294e09f275
All these 'override's can be 'final's.
...
At least for the purpose of being communicative. I doubt there's much to gain in terms of compiler output — the DiskImageHolder can avoid some virtual lookups but nothing else leaps out.
2020-01-23 22:57:51 -05:00
Thomas Harte
f42655a0fc
Promote DigitalPhaseLockedLoop to a template, simplify to O(1) add_pulse.
2020-01-12 17:25:21 -05:00
Thomas Harte
6595f8f527
Introduces a timing test for LSL. Which already passes.
2020-01-08 22:35:28 -05:00
Thomas Harte
c1bae49a92
Standardises on read
and write
for bus accesses.
...
Logic being: name these things for the bus action they model, not the effect they have.
2020-01-05 13:40:02 -05:00
Thomas Harte
9f2f547932
Adds and satisfies test on the function code word.
...
Thanks to ijor's "68000 Address and Bus Error Stack Frame" re: contents.
2020-01-04 23:58:07 -05:00
Thomas Harte
f0d5bbecf2
Introduces a test of stack contents after an address error.
...
Fixes: stacked PC, address of fault.
2020-01-04 23:22:07 -05:00
Thomas Harte
a28c52c250
Fixes A7-relative JSRs.
...
I completely withdraw my earlier statement re: the test cases.
2020-01-04 22:22:33 -05:00
Thomas Harte
937cba8978
After rerunning all tests, adds some notes on questionable results.
...
Also renames a file. But no code changes are currently suggested, at least until I can learn more about DIVU/DIVS.
2020-01-04 16:31:45 -05:00
Thomas Harte
ca12ba297b
Renames all files that test multiple opcodes; introduces DIV and MUL tests.
2020-01-03 22:43:24 -05:00
Thomas Harte
617e0bada9
Adds some minor extra testing. Highly duplicative, to be honest.
2020-01-02 23:14:05 -05:00
Thomas Harte
cb7d6c185c
Further expands test coverage.
2020-01-01 20:00:37 -05:00
Thomas Harte
5be30b1f7b
Introduces further comparative tests, prompting a new CHK fix.
...
Specifically: how to set N when both is_under and is_over are true, and to eliminate a failure fully to prefetch in the longer addressing modes.
2020-01-01 19:11:36 -05:00
Thomas Harte
b33218c61e
Fixes reload test, which really needs to sense the CRT-headed vsync output.
...
i.e. not the one heading back to the CPU.
2019-12-29 20:55:34 -05:00
Thomas Harte
5361ee2526
Adds specific Union Demo test.
2019-12-29 17:48:43 -05:00
Thomas Harte
214b6a254a
Adds a delay on visibility of the hsync signal, and a test on address reload.
2019-12-29 17:37:09 -05:00
Thomas Harte
93f6964d8a
Introduces some preliminary line length unit tests.
...
Thereby fixes one potential issue with load_ toggling.
2019-12-28 22:50:34 -05:00
Thomas Harte
d26ce65236
Introduces an RTR test.
2019-12-25 19:50:12 -05:00
Thomas Harte
ed831e5912
Fixes test syntax errors.
2019-12-23 22:13:25 -05:00
Thomas Harte
0dae608da5
Embraces std::make_[unique/shared] in place of .reset(new .
2019-12-23 21:31:46 -05:00
Thomas Harte
a847654ef2
Corrects various old-fashioned bits of indentation, plus the odd const.
2019-12-22 00:00:23 -05:00
Thomas Harte
9464658d1e
Adds a count summary.
2019-12-17 22:19:23 -05:00
Thomas Harte
e969b386f1
Eliminates DIVU/S and MULU/S from this file.
2019-12-17 20:15:11 -05:00
Thomas Harte
0d23f141d6
Regenerates without accidentally hitting MODE to SR.
2019-12-16 22:37:57 -05:00
Thomas Harte
ba2436206f
Withdraws test of CHK (exception taken).
2019-12-16 20:00:42 -05:00
Thomas Harte
60a9b260b1
Corrects collection of instruction codes.
2019-12-16 00:01:18 -05:00
Thomas Harte
e603fc6aaa
Simplifies failure output for me.
2019-12-15 21:26:47 -05:00
Thomas Harte
81cc278b98
Introduces a barrage of further tests.
2019-12-15 21:26:35 -05:00
Thomas Harte
1bf4686c59
Adds plentiful additional tests. Though still only a fraction of the anticipated total.
2019-12-14 22:58:51 -05:00
Thomas Harte
a500fbcd73
Expands tests to most of ORI, EORI, ANDI, ADDI and SUBI.
2019-12-14 22:23:40 -05:00
Thomas Harte
d0ef41f11e
Adds a temporary manual escape clause for testing specific features.
2019-12-14 21:40:21 -05:00
Thomas Harte
adf6723bf6
Ensures state is evaluated directly at opcode end.
2019-12-14 15:09:06 -05:00
Thomas Harte
37e26c0c37
Eliminates a class of incorrect sign comparison errors.
2019-12-14 14:50:39 -05:00
Thomas Harte
ac1575be27
Resolves false negatives from checking wrong state.
2019-12-14 14:46:00 -05:00
Thomas Harte
923287bf01
Attempts to introduce a basic means for comparative 68000 testing.
...
i.e. mine versus another source.
2019-12-14 14:26:33 -05:00
Thomas Harte
4536c6a224
Resolves printf type errors.
2019-12-08 11:56:05 -05:00
Thomas Harte
72cb3a1cf6
Integrates basic unit test for Atari ST video event prediction.
2019-11-19 21:54:13 -05:00
Thomas Harte
ade8df7217
Permits a delay on DE propagation back to the CPU. Plus tests.
...
Currently set at 28 cycles, but I don't know.
2019-11-18 22:12:24 -05:00
Thomas Harte
1c154131f9
Expands size of storage in Cycles/HalfCycles; adjusts widely to compensate.
2019-10-29 22:36:29 -04:00
Thomas Harte
1aba1db62c
Corrects test.
2019-10-27 21:30:58 -04:00
Thomas Harte
f88dc23c71
Corrects comment.
2019-08-04 20:30:41 -04:00
Thomas Harte
e334abfe20
Partitions the 68000 arithmetic tests, to allow easier per-instruction execution.
2019-08-03 17:44:47 -04:00
Thomas Harte
f2ae04597f
Updates test case.
2019-07-24 22:07:17 -04:00
Thomas Harte
0187fd8eae
Hides all runtime Program member accesses behind macros.
...
... and fixes unit tests.
2019-07-24 12:01:30 -04:00
Thomas Harte
5a9f3cfc1e
Completes Mac GCR decoding and its associated test.
2019-07-11 17:37:07 -04:00
Thomas Harte
8f28b33342
Starts work on Macintosh GCR decoding.
2019-07-11 16:28:52 -04:00
Thomas Harte
886946cc8c
Rejigs time-until-event tracking.
2019-07-09 23:27:27 -04:00
Thomas Harte
210bcaa56d
Introduces an initial shift unit test, and makes it pass.
2019-07-07 22:13:36 -04:00
Thomas Harte
a5f0761a43
Copies in notes for required test functions.
2019-07-07 14:13:00 -04:00
Thomas Harte
ebb6313eef
Corrects missing file.
2019-07-01 18:18:46 -04:00
Thomas Harte
11d8f765b2
Corrects divide-by-zero exception length, enables all other DIVS checks.
2019-07-01 15:46:04 -04:00
Thomas Harte
514e57b3e9
Corrects DIVU timing and flags, improves DIVS.
2019-07-01 14:24:32 -04:00
Thomas Harte
d30e7504c2
Factors out MOVE tests, and ensures test machine RAM is zero initialised.
2019-06-30 21:43:30 -04:00
Thomas Harte
8d0cd356fd
Corrects TRAP, TRAPV and CHK timing.
2019-06-29 21:25:22 -04:00
Thomas Harte
aff40bf00a
Imports AND tests.
2019-06-29 20:16:10 -04:00
Thomas Harte
eedf7358b4
Imports first part of AND tests.
2019-06-29 16:29:47 -04:00
Thomas Harte
26aebcc167
Imports ROXL and ROXR tests.
...
Confirming the significant deficiencies I suspected.
2019-06-29 15:26:09 -04:00
Thomas Harte
9d420c727e
Factors out rolls and shifts.
2019-06-29 14:12:52 -04:00
Thomas Harte
60fe84ad16
Imports Bcc tests.
2019-06-29 14:07:21 -04:00
Thomas Harte
6a44c682ad
Factors out control flow tests.
2019-06-29 13:47:05 -04:00
Thomas Harte
60df44f0ca
Imports CMPI tests.
2019-06-29 13:40:02 -04:00
Thomas Harte
ac926f5070
Factors BCD out of general arithmetic.
2019-06-29 13:31:24 -04:00
Thomas Harte
6e9a4a48f7
Imports TAS tests.
2019-06-28 22:56:35 -04:00
Thomas Harte
a8894b308a
Splits out arithmetic tests, as so far implemented.
...
Further subdivision may be advisable.
2019-06-28 22:08:32 -04:00
Thomas Harte
7cc91e1bc5
Factors the bitwise tests out of the main bundle, as that pushes up towards 6,000 lines.
2019-06-28 21:58:38 -04:00
Thomas Harte
9eb51f164c
Imports ANDI, ORI and EORI tests.
2019-06-28 21:42:58 -04:00
Thomas Harte
a1c00e9318
Adds BSR tests.
2019-06-28 21:31:41 -04:00
Thomas Harte
241d29ff7c
Imports SBCD and NBCD tests, and fixes corresponding operation.
2019-06-28 19:39:08 -04:00
Thomas Harte
c5039a4719
Imports ANDI, ORI and EORI to SR tests.
...
Hence corrects supervisor/user privileges for SR/CCR.
2019-06-28 15:05:46 -04:00
Thomas Harte
fd604048db
Imports SUBX tests.
2019-06-28 14:30:26 -04:00
Thomas Harte
6a77ed1e07
Imports SUBI test.
2019-06-28 13:53:53 -04:00
Thomas Harte
9e38815ec4
Imports SUBQ tests.
2019-06-28 13:48:02 -04:00
Thomas Harte
86c325c4ec
Imports MOVEA tests.
2019-06-28 13:41:37 -04:00
Thomas Harte
bfcc6cf12c
Imports MULU tests.
...
Timing is wrong for now.
2019-06-28 13:33:41 -04:00
Thomas Harte
8ba8cf7c23
Imports TST tests.
2019-06-28 13:17:21 -04:00
Thomas Harte
651fd9c4a5
Imports EOR tests.
2019-06-28 13:03:27 -04:00
Thomas Harte
5d0db2198c
Imports BRA, EORI CCR and ORI CCR tests, extends PEA tests.
2019-06-27 23:05:00 -04:00
Thomas Harte
da351a3e32
Imports MOVEQ tests.
2019-06-26 22:36:48 -04:00
Thomas Harte
c0591090f5
Imports DIVU tests.
2019-06-26 22:25:48 -04:00
Thomas Harte
538aecb46e
Imports CMP tests, and fixes CMP.l timing.
2019-06-26 22:02:04 -04:00
Thomas Harte
dbdbea85c2
Imports CMPA tests, and fixes CMPA.w.
2019-06-26 21:42:48 -04:00
Thomas Harte
ba2224dd06
Imports NEGX tests and thereby fixes NEGX's zero flag.
2019-06-26 19:39:04 -04:00
Thomas Harte
44e2aa9183
Imports MOVEP tests; code corrections to come.
2019-06-26 19:01:09 -04:00
Thomas Harte
202bff70fe
Imports BCLR and BTST tests.
2019-06-26 17:51:07 -04:00
Thomas Harte
26c0cd7f7c
Imports ADDI tests.
2019-06-26 16:42:23 -04:00
Thomas Harte
cb76301fbe
Imports BCHG tests.
2019-06-26 16:33:23 -04:00
Thomas Harte
8bfa12edf1
Adds lengths to ADD tests, imports ANDI ,CCR and MOVE to CCR.
2019-06-26 16:12:27 -04:00
Thomas Harte
7daa969a5a
Imports SUBA tests.
2019-06-26 15:47:59 -04:00
Thomas Harte
4aeb60100d
Completes import of MOVEM tests.
2019-06-26 15:31:21 -04:00
Thomas Harte
e2c7aaac5a
Imports CLR tests.
2019-06-25 22:47:30 -04:00
Thomas Harte
6ff661c30d
Imports OR tests.
2019-06-25 22:34:04 -04:00
Thomas Harte
79066f8628
Imports NOT tests, fixes NOT overflow and carry flags.
2019-06-25 22:18:11 -04:00
Thomas Harte
2c813a2692
Imports CMPM tests and fixes CMPM.bw source/destination order.
2019-06-25 21:46:01 -04:00
Thomas Harte
cc4abcb00a
Imports ADDQ tests.
2019-06-25 21:19:04 -04:00
Thomas Harte
c1ca85987f
Incorporates MOVE to SR test.
2019-06-25 19:30:51 -04:00
Thomas Harte
ecb5a0b8cc
Incorporates ADDX tests and fixes ADDX PreDec.
2019-06-25 19:18:07 -04:00
Thomas Harte
e12e8fc616
Incorporates ASR tests, and fixes ASR (xxx).w.
...
... which was re-injecting the wrong bit to preserve sign.
2019-06-25 18:44:31 -04:00
Thomas Harte
1fbbf32cd2
Adds ASL tests, and corrects ASL (xxx).w.
...
Overflow is wrong on other ASLs though, I think.
2019-06-25 18:09:01 -04:00
Thomas Harte
d7883d18d4
Imports CHK tests.
...
Proving that I need to do some research on CHK's flags.
2019-06-25 14:55:03 -04:00
Thomas Harte
40100773d3
Imports LSR tests.
2019-06-25 13:57:42 -04:00
Thomas Harte
4048ed3a33
Imports ROR tests.
2019-06-25 13:16:44 -04:00
Thomas Harte
11f2d3cea7
Imports EXT tests.
2019-06-24 22:12:29 -04:00
Thomas Harte
aa656a39b8
Imports SUB tests.
2019-06-24 22:00:37 -04:00
Thomas Harte
e830d23533
Incorporates TRAPV tests.
2019-06-24 21:21:35 -04:00
Thomas Harte
9a666fb8cc
Imports NEG tests and fixes NEG.l Dn timing.
2019-06-24 19:43:30 -04:00
Thomas Harte
0e208ed432
Fixes cycle counting in the test machine.
2019-06-24 17:55:09 -04:00
Thomas Harte
c8b769de8a
Completes import of LSL tests and fixes various LSL issues.
...
Including LSL (xxx).w actually being LSR, and the carry flag generally being questionable.
2019-06-24 17:45:38 -04:00
Thomas Harte
c447655047
Resolves assumption that shifts greater than the bit count of the relevant int are well-defined in C.
2019-06-24 16:51:43 -04:00
Thomas Harte
3ec9a1d869
Incorporates JMP tests, fixes JSR (xxx).l timing.
2019-06-24 15:36:33 -04:00
Thomas Harte
d326886852
Completes BSET tests.
2019-06-24 14:04:08 -04:00
Thomas Harte
faef917cbd
Improves resizeable microcycle test.
2019-06-24 10:55:22 -04:00
Thomas Harte
d27ba90c07
Attempts to introduce more rigour to variable-length instruction handling.
2019-06-24 10:43:28 -04:00
Thomas Harte
db4ca746e3
Introduces BSET tests, fixes BSET timing.
2019-06-23 22:53:37 -04:00
Thomas Harte
d50fbfb506
Imports EXG and PEA tests, and fixes EXG timing.
2019-06-23 22:21:25 -04:00
Thomas Harte
5d283a9f1f
Imports LEA tests.
2019-06-23 21:48:47 -04:00
Thomas Harte
86fdc75feb
Incorporates RTR test, adding a ProcessorState helper.
2019-06-23 18:37:32 -04:00
Thomas Harte
b63231523a
Completes import of ROL tests.
2019-06-23 17:33:12 -04:00
Thomas Harte
70e296674d
Starts import of ROL tests.
...
Including time tests, this time.
2019-06-22 22:42:57 -04:00
Thomas Harte
5089fcd2f6
Makes a slightly futile attempt to resolve Heisen-failures.
2019-06-22 18:52:06 -04:00
Thomas Harte
df2ce8ca6f
Imports MOVE tests.
2019-06-21 22:03:27 -04:00
Thomas Harte
7e209353bb
Imports UNLINK and NOP tests.
2019-06-21 21:29:02 -04:00
Thomas Harte
c2806a94e2
Imports further MOVEM tests.
2019-06-21 21:20:13 -04:00
Thomas Harte
d428120776
Completes import of LINK tests.
2019-06-21 18:33:44 -04:00
Thomas Harte
6b996ae57d
Improves test machine and incorporates a first test of LINK.
2019-06-21 18:20:13 -04:00
Thomas Harte
ccfe1b13cb
Imports DIVS, MULS and MOVE from SR tests.
...
Not all passing.
2019-06-21 16:03:11 -04:00
Thomas Harte
0c1c10bc66
Introduces a test that proves that DIVS' attempt to set proper timing isn't working.
2019-06-20 19:29:02 -04:00
Thomas Harte
fafd1801fe
Introduces first DIVS test, and associated fixes.
2019-06-20 19:02:03 -04:00
Thomas Harte
bcf6f665b8
Simplifies and completes DBcc tests.
...
Subject to omitting a few that look to me like duplicates.
2019-06-20 17:19:25 -04:00
Thomas Harte
bd069490b5
Incorporates approximately half of the DBcc tests.
2019-06-20 16:29:32 -04:00
Thomas Harte
624b0b6372
Adds Scc tests. No implementation fixes required.
2019-06-19 21:42:54 -04:00
Thomas Harte
7976cf5b3c
Adds ADDA tests. All passing without 68000 changes.
2019-06-19 21:31:14 -04:00
Thomas Harte
440f52c943
Incorporates TRAP test.
2019-06-19 21:18:30 -04:00
Thomas Harte
47b1218a68
Adds a couple of the one-shots: SWAP, MOVE USP.
2019-06-19 19:10:36 -04:00
Thomas Harte
91ced056d2
Adds tests for ADD. No failures.
2019-06-19 18:56:21 -04:00
Thomas Harte
8dace34e63
Imports third-party tests for ABCD, and thereby fixes ABCD.
2019-06-19 18:13:06 -04:00
Thomas Harte
b98f10cb45
Substitutes working GCR test.
2019-06-18 14:24:55 -04:00
Thomas Harte
df56e6fe53
Fixed: the sector number also goes into sector bodies.
...
Also the checksum is written in the other order, and the final byte of data isn't output.
2019-06-18 10:34:10 -04:00
Thomas Harte
5c8aacdc17
Fixes the more obvious issues with GCR encoding: byte order, top bit selection.
2019-06-16 17:17:24 -04:00
Thomas Harte
745a5ab749
Introduces failing test of Macintosh GCR data encoding.
2019-06-16 16:53:03 -04:00
Thomas Harte
fe0dc4df88
Starts building out some tests for Apple GCR encoding.
2019-06-15 22:48:24 -04:00
Thomas Harte
5e2496d59c
Simplifies and corrects MOVE logic.
2019-05-28 15:17:03 -04:00
Thomas Harte
c52da9d802
Adds some logging preparatory to a MOVE change.
2019-05-28 15:05:42 -04:00
Thomas Harte
4f9f73ca81
Corrects tests affected by change in run_for_instructions semantics and new program base address.
2019-05-03 15:05:14 -04:00
Thomas Harte
93616a4903
Completes test of a vectored interrupt.
...
Correcting issues uncovered.
2019-05-02 00:00:09 -04:00
Thomas Harte
bb07206c55
Corrects internet response to work as currently implemented.
...
Also makes corrections to the bus error and address error exceptions.
2019-05-01 21:59:06 -04:00
Thomas Harte
e430f2658f
Adds a test and by that means fixes divide-by-zero exception return addresses.
2019-04-29 23:09:50 -04:00
Thomas Harte
7332c64964
Improves testing of function as distinct from timing.
2019-04-29 22:08:37 -04:00
Thomas Harte
d6e16d0042
Adds a test of TOS 1.00, as far as it goes without meaningful hardware.
2019-04-29 18:04:57 -04:00
Thomas Harte
8e02d29ae6
Trims test to length of trace capture.
2019-04-29 17:56:49 -04:00
Thomas Harte
c0e9c37cc7
Improves memory map model, as far as it goes.
2019-04-29 17:27:44 -04:00
Thomas Harte
5b5bfc8445
Applies trace testing to EmuTOS.
2019-04-29 16:55:21 -04:00
Thomas Harte
c466b6f9e7
Factors out the [unit testing] stuff of being a trace-checking 68000 bus handler.
2019-04-29 16:11:01 -04:00
Thomas Harte
407643c575
Tweaks test length slightly to ensure this doesn't run beyond the final line's end.
2019-04-29 15:40:17 -04:00
Thomas Harte
d9071ee9f1
Starts sketching out the asynchronous bus.
2019-04-29 13:45:53 -04:00
Thomas Harte
d9278e9827
Attempts to complete the list of things I can't disassemble.
...
Mysteries to be solved here, definitely. But: 13 missing opcodes remaining.
2019-04-28 23:11:49 -04:00
Thomas Harte
0298b1b3b7
Implements LINK and UNLINK.
...
Also starts excluding opcodes that I can't determine the mapping of from the list of those tested against.
Due to those two things together, the latter incomplete: 627 opcodes outstanding. But only STOP and MOVEP remain on my list of things to implement prior to exceptions.
2019-04-28 17:12:31 -04:00
Thomas Harte
cf547ef569
Improves semantic communications and temporarily omits A- and F-line instructions.
...
So it looks like 2773 instructions left to go.
2019-04-27 15:15:03 -04:00
Thomas Harte
40f68b70c1
Adds quantification of reports.
...
Depressingly; 11,841 opcodes are still missing. Better get on with it!
2019-04-26 13:25:34 -04:00
Thomas Harte
a3b6d2d16e
Corrects test and resolves all instances of opcodes that are valid but shouldn't be.
...
The converse case will require implementation of the remaining instructions.
2019-04-25 22:54:58 -04:00
Thomas Harte
3983f8303f
Introduces failing test of 68000 opcode coverage.
2019-04-25 22:06:05 -04:00
Thomas Harte
7cbd5e0ef6
Imports additional files used as test cases.
2019-04-25 21:43:47 -04:00
Thomas Harte
7df85ea695
Cleans up and formally introduces a comparative source for QL startup.
2019-04-25 15:42:41 -04:00
Thomas Harte
a08043ae88
Ensures that MOVE.b #, (xxx).l writes only a byte.
...
Also rearranges some of the temporary logging functionality.
2019-04-23 19:01:58 -04:00
Thomas Harte
6d6046757d
Fixes predecrementing MOVEM to leave the proper address in the relevant register.
2019-04-22 15:41:09 -04:00
Thomas Harte
44eb4e51ed
Ensures DBcc properly signals program fetches.
2019-04-21 22:54:20 -04:00
Thomas Harte
3cb042a49d
Corrects the carry and extend flags for various long-word operations.
2019-04-21 22:08:18 -04:00
Thomas Harte
0be9a0cb88
Corrects Scc (and other conditionals) for complex addressing modes.
2019-04-20 18:35:19 -04:00
Thomas Harte
ef33b004f9
Corrects word access order of MOVEM.l.
2019-04-20 15:13:12 -04:00
Thomas Harte
2cac4b0d74
Corrects EA usage for ADDA and SUBA.
2019-04-19 23:02:41 -04:00
Thomas Harte
a49f516265
Corrects direction of MOVE [to/from] USP.
2019-04-19 22:41:06 -04:00
Thomas Harte
2d97fc1f59
Beefs up documentation and developer support.
2019-04-19 13:29:35 -04:00
Thomas Harte
ee7ae11e90
Implements EXG and SWAP.
2019-04-19 11:27:43 -04:00
Thomas Harte
c265ea9847
Corrects byte writes in both test machines.
2019-04-17 16:39:10 -04:00
Thomas Harte
b64da2710a
Corrects a few MOVE #s.
2019-04-17 10:00:14 -04:00
Thomas Harte
82b08d0e3a
Corrects addressing behaviour of nRd[+-].
2019-04-17 08:53:34 -04:00
Thomas Harte
62e4c23961
Corrects memory map, causing the RAM test no longer to fail.
2019-04-15 13:03:32 -04:00
Thomas Harte
a223cd90a1
Adds predecrement TSTs, increases QL running time, reduces logging.
2019-04-15 12:36:08 -04:00
Thomas Harte
fba210f7ce
Corrects MOVE.l Dn, (An)[+].
2019-04-15 09:30:49 -04:00
Thomas Harte
52e33e861c
Starts to introduce the QL as a second source for 68000 testing.
...
It's advantageous over the ST in that a commented disassembly of the ROM is available.
2019-04-14 22:15:09 -04:00
Thomas Harte
2ba66c4457
Corrects MOVEA, adds extra test safeguards.
2019-04-12 16:10:17 -04:00
Thomas Harte
06a2f59bd0
Implements DBcc.
2019-04-06 23:21:01 -04:00
Thomas Harte
0af57806da
Adds a hard-coded value sufficient to advance in TOS startup.
2019-04-06 20:00:34 -04:00
Thomas Harte
73e1c8c780
Corrects now-unimplemented ADD/SUB.
2019-04-03 19:43:54 -04:00
Thomas Harte
2c5ff9ada0
Switches to running the real TOS, at least temporarily, and enables better testing.
2019-03-31 22:27:57 -04:00
Thomas Harte
b0b2798f39
Updates to track Swift.
2019-03-27 21:25:51 -04:00
Thomas Harte
47359dc8f1
Adds tests for MOVE.l (An), Dn, and thereby correct their implementation.
2019-03-23 21:41:47 -04:00
Thomas Harte
d7c3d4ce52
Adds test for MOVEA.w (0x1000), A1 and fixes implementation thereof.
2019-03-22 23:27:48 -04:00
Thomas Harte
87420881c8
Extends to a failing test.
2019-03-21 23:32:03 -04:00
Thomas Harte
fdc598f2e1
Starts MOVE tests; in pursuit of which talks the 68000 into obeying run lengths.
2019-03-21 22:30:41 -04:00
Thomas Harte
0d7bbdad54
Begins a basic get/set state API, allowing some actual unit tests, implying an ABCD fix.
2019-03-17 21:57:00 -04:00
Thomas Harte
388d808536
Switches to providing UDS and LDS implicitly via address.
...
Also makes sure that the difference between a non-data cycle that starts without the address strobe active and one that starts with it active can be discerned.
2019-03-16 17:54:58 -04:00
Thomas Harte
720aba3f2d
Adds an implementation of SBCD and slightly neatens syntax for building programs.
2019-03-14 21:22:02 -04:00
Thomas Harte
f9101de956
This might very well be the 68000's first real gasp: performing an ABCD.
2019-03-14 19:32:15 -04:00
Thomas Harte
9e8928aad9
Implements as much as I currently care about of the Atari ST memory map.
2019-03-11 22:47:37 -04:00
Thomas Harte
89c71f9119
Introduces EmuTOS, and starts constructing test cases around it.
2019-03-10 18:40:12 -04:00
Thomas Harte
a4f6db6719
Removes ArrayBuilderTests as the ArrayBuilder is long gone. Disables TIA tests for now.
2019-03-10 18:07:23 -04:00
Thomas Harte
6a93d2d006
Corrects some minor spaces-instead-of-tabs errors.
2019-01-24 22:59:03 -05:00
Thomas Harte
ee89be6730
Removes many stray spaces.
2018-11-23 22:32:32 -05:00
Thomas Harte
a8645f80bf
Introduces 'non-exclusive' emulator-space keyboards.
...
i.e. sets of keys that don't amount to an entire keyboard in the modern sense. Experimentally used by the Master System for its reset key.
2018-10-24 21:59:30 -04:00
Thomas Harte
c07f9fed99
Corrects test and implementation to pass the exhaustive VDP interrupt prediction test.
2018-10-21 18:42:49 -04:00
Thomas Harte
616777517d
Makes the failing test more communicative, in the hope of more easily debugging errors.
2018-10-21 14:35:44 -04:00
Thomas Harte
b3f1677da5
Introduces new failing test for rational continuous interrupt prediction.
2018-10-21 13:59:14 -04:00
Thomas Harte
725b364bbc
Improves testing; now tests for time to the first interrupt.
2018-10-20 18:25:55 -04:00
Thomas Harte
acdc84e08c
Improves test slightly, and fixes line interrupt reload value setting.
2018-10-09 22:14:35 -04:00
Thomas Harte
c128ddb549
Introduces a first unit test for line interrupts and corrects backup behaviour.
2018-10-09 21:49:21 -04:00
Thomas Harte
fc84ae611e
Resolves various instances of spaces in place of tabs.
2018-09-09 20:33:56 -04:00
Thomas Harte
ddf45a0010
Ensures NMI and RST reset D on 65C02s.
2018-08-14 19:49:14 -04:00
Thomas Harte
261fb3d4f8
Implements proper test for ADC/SBC 65C02 NZ, though not yet the proper timing.
...
This gets Klaus Dorman's test to pass.
2018-08-10 22:42:35 -04:00
Thomas Harte
b63e0cff72
Improves has-completed test.
2018-08-10 22:27:01 -04:00
Thomas Harte
5d6e479338
Implements RMB and SMB, and fixes SBC (zero).
2018-08-10 22:13:51 -04:00
Thomas Harte
90094529a5
Implements TSB and TRB, and adds the extra BIT instructions.
2018-08-10 22:04:45 -04:00
Thomas Harte
aed4c0539e
Implements STZ.
2018-08-10 21:17:02 -04:00
Thomas Harte
95164b79c9
Attempted implementation of (zp) addressing mode.
2018-08-09 21:51:14 -04:00
Thomas Harte
bb680b40d8
Implements the 65C02's JMPs.
2018-08-08 22:26:57 -04:00
Thomas Harte
e3f6da6994
Implements the 65C02 NOPs.
2018-08-08 20:00:14 -04:00
Thomas Harte
32338bea4d
Implements BRA.
2018-08-06 22:37:30 -04:00
Thomas Harte
1a44ef0469
Introduces Klaus Dorman's 65C02 tests. All failing.
2018-08-06 21:48:43 -04:00
Thomas Harte
ebce9a2e51
Fixes test target.
2018-08-06 21:15:13 -04:00
Thomas Harte
abca38a548
Makes an initial removal of PCMPatchedTrack
. Farewell, old friend.
2018-07-01 22:49:57 -04:00
Thomas Harte
853261364e
Generalised CRC generation and created specific subclasses for the CCITT CRC16 and CRC32.
2018-05-23 22:21:57 -04:00
Thomas Harte
0b771ce61a
Removes all instances of the copyright symbol.
2018-05-13 15:19:52 -04:00
Thomas Harte
05e31d7594
Mutates testComplicatedTrackSeek
into an actual test.
...
Which frustratingly passes.
2018-05-01 19:52:12 -04:00
Thomas Harte
f4097290c2
Made various corrections following a quick for-loop constness audit.
2018-04-30 22:23:57 -04:00
Thomas Harte
b32538f3c8
Adds an additional test.
2018-04-30 22:05:44 -04:00
Thomas Harte
e7618bb32e
Corrects types (/chickens out).
2018-04-30 22:04:05 -04:00
Thomas Harte
e599e65087
Switches to use of the TargetList
typedef wherever possible.
2018-04-14 19:46:38 -04:00
Thomas Harte
389979923e
Performs update to and satisfaction of Xcode 9.3's preferred warnings.
2018-03-30 10:25:01 -04:00
Thomas Harte
f0f9d5a6af
Corrects memptr leakage via BIT, and ld (de/bc/nn), A behaviour.
2018-03-08 20:30:22 -05:00
Thomas Harte
fdef914137
Corrects test target regression.
2018-03-06 18:32:21 -05:00
Thomas Harte
66faed4008
Gives MachineForTargets
complete responsibility for initial machine state.
2018-01-25 18:28:19 -05:00
Thomas Harte
21efb32b6f
Integrates the static and nascent dynamic analyser namespaces.
2018-01-24 21:48:44 -05:00
Thomas Harte
ed564cb810
Implements the main four cartridge banking schemes.
...
Slightly proof of concept for now.
2018-01-04 22:18:18 -05:00
Thomas Harte
c8367a017f
Cleans up test and makes attempt to factor in cartridge type popularity.
2018-01-01 21:21:05 -05:00
Thomas Harte
344a12566b
Tweaks a couple of expected cartridge types.
2018-01-01 20:14:56 -05:00
Thomas Harte
c07113ea95
Ensures no illegal accesses while testing MSX ROM type detection.
...
Specifically: the static analyser doesn't even correctly identify everything that is an MSX ROM yet, let alone then properly determine type.
2018-01-01 17:38:26 -05:00
Thomas Harte
bc2879c412
Corrects the MSX ROM unit test.
...
I.e. the test is correct now, for those SHAs I could find. The static analyser is still wrong just slightly less than half the time.
2018-01-01 17:35:13 -05:00
Thomas Harte
db25b4554b
Introduces failing tests of the MSX static analyser.
2018-01-01 16:38:26 -05:00
Thomas Harte
05b95ea2e0
Corrects Xcode tests.
2018-01-01 16:04:13 -05:00
Thomas Harte
6e1d69581c
Eliminates a variety of end-of-line spaces.
2017-11-07 22:54:22 -05:00
Thomas Harte
f95515ae81
Eliminates a large number of instance of end-of-line tabs.
2017-11-07 22:51:06 -05:00
Thomas Harte
064f1dfdbc
Removes usages of deprecated initialiser.
2017-10-05 18:10:47 -04:00
Thomas Harte
ff24e1de31
Corrects 6522 bridge per has-a-not-is-a template switch.
2017-09-04 21:56:21 -04:00
Thomas Harte
7af3de010e
Suspected my mode 1 interrupt timing might be off. Reminded myself of the sources. Persuaded myself that it wasn't. Added appropriate comments.
2017-08-23 22:25:31 -04:00
Thomas Harte
ee71be0e7e
Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.
2017-08-21 21:56:42 -04:00
Thomas Harte
761afad118
Corrected timestamp return, and its testing by the 6502 timing tests.
2017-07-27 21:19:16 -04:00
Thomas Harte
37950143fc
Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.
2017-07-27 20:17:13 -04:00
Thomas Harte
9257a3f6d7
Added test for 16-bit arithmetic, and fixed implementation.
2017-07-26 19:04:52 -04:00
Thomas Harte
728143247d
Added a test for RLD and RRD. Which already passes.
2017-07-26 18:56:35 -04:00
Thomas Harte
6ec4e4e3d7
Merge branch 'master' into Memptr
2017-07-25 23:01:34 -04:00
Thomas Harte
37ccb9d3b6
Fixed 6502 timing tests.
2017-07-25 23:00:39 -04:00
Thomas Harte
3c254360ba
Completed fixture of the 6502 BCD test.
2017-07-25 22:55:45 -04:00
Thomas Harte
3ca51bedc6
Discovered legitimate uses of the jam opcode so reinstated it. Corrected illegitimate uses.
2017-07-25 22:48:44 -04:00
Thomas Harte
36076b7ea5
Eliminated final vestige of professed jam handling. This should make it clear which tests still think they can capture jams.
2017-07-25 22:38:26 -04:00
Thomas Harte
df4732be2e
Corrected test.
2017-07-24 22:33:49 -04:00
Thomas Harte
9435c1e12a
The 1540 is now a ClockReceiver
.
2017-07-24 22:32:41 -04:00
Thomas Harte
2912d7055b
The 6532 is now a ClockReceiver
.
2017-07-24 21:57:24 -04:00
Thomas Harte
13f7aa4063
The TIA is now a ClockReceiver
.
2017-07-24 21:48:34 -04:00
Thomas Harte
b3ae920746
Converted the DPLL and disk controller classes to be ClockReceiver
s.
2017-07-24 21:04:47 -04:00
Thomas Harte
e6578defcd
It turns out that quite a few tests still rely on CSTestMachine6502JamOpcode. Though since it no longer works, that'll need to be fixed. In the meantime, fixed the test build process at least, as it's not really what this branch is meant to be invested in.
2017-07-23 22:22:50 -04:00
Thomas Harte
ace8e30818
Bubbled the Z80's move into clock receiver territory up into the Z80 test machine.
2017-07-23 22:21:39 -04:00
Thomas Harte
b0c2325adc
Corrected run call, and accepted that jam handling is gone forever.
2017-07-22 22:21:26 -04:00
Thomas Harte
4ea835e50b
Added test for EX (SP), rp, which passes.
2017-07-22 17:17:32 -04:00
Thomas Harte
6437c43147
Added CPI and CPD tests: at last two that pass without requiring implementation changes!
2017-07-22 12:38:18 -04:00
Thomas Harte
5928a24803
Transcribed missing tests as TODOs.
2017-07-22 11:44:17 -04:00
Thomas Harte
20a6bcc676
Added tests for the various LD (nn), rr
instructions and corrected implementation to pass.
2017-07-22 11:39:13 -04:00
Thomas Harte
eaf313b0f6
Added a test on LD A, (DE) and LD A, (BC), and adjusted implementation to pass.
2017-07-22 11:20:21 -04:00
Thomas Harte
d51b66c204
Expanded test to hit all 65536 possibilities (and not to allocate a fresh Z80 test machine each time, as that's unnecessary and slow), and fixed implementation to pass test.
2017-07-21 23:01:35 -04:00
Thomas Harte
660f0e4c40
Added Objective-C through wiring and a Swift test class for Memptr modifications. So far with a single test, that fails.
2017-07-21 22:52:25 -04:00
Thomas Harte
7b5f93510b
Fixed the DigitalPhaseLockedLoopBridge
bridge, once again fixing tests.
2017-07-16 20:55:57 -04:00
Thomas Harte
8ddd686049
Removed redundant variable.
2017-07-16 19:04:03 -04:00
Thomas Harte
2fb0aea990
Updated the C1540 test vessel to the new world.
2017-07-16 17:00:39 -04:00
Thomas Harte
95a6b0f85c
Introduced an NMI/wait interrupt timing test, and adjusted the Z80 to conform to information posted by Wilf Rigter.
2017-06-22 21:09:26 -04:00
Thomas Harte
0e0ce379b4
Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle.
2017-06-21 20:38:08 -04:00
Thomas Harte
36e8a11505
Sought to simplify the way partial machine cycles are communicated, for ease of machine implementation. Also implemented the wait line.
2017-06-21 20:32:08 -04:00
Thomas Harte
108da64562
Fixed LD H, (HL) and LD L, (HL) by ensuring that whatever the subclass does goes to a temporary place before updating the address. Corrected the LD (IX+d), n machine cycle test for my new best-guess timing. This should leave only interrupt timing as currently amiss.
2017-06-20 22:25:00 -04:00
Thomas Harte
184b371649
Attempted to get to 'proper' timing for LD (IX+d),n, albeit that proper is a guess.
2017-06-20 21:48:50 -04:00
Thomas Harte
27ac342928
Corrected conditional call timing, and its test.
2017-06-20 20:57:23 -04:00
Thomas Harte
6752f165db
Added failing tests for both kinds of CALL.
2017-06-19 22:03:29 -04:00
Thomas Harte
e05076b258
Added tests for everything except CALL. All passing.
2017-06-19 22:00:04 -04:00
Thomas Harte
fadbfdf801
Added DJNZ test.
2017-06-19 21:31:56 -04:00
Thomas Harte
cb277b8d1e
Added JP and JR tests.
2017-06-19 21:27:23 -04:00
Thomas Harte
234f14dbbe
Tests were at fault; all passing now.
2017-06-19 21:14:40 -04:00
Thomas Harte
99ede3a9ef
BIT/SET (IX+d) were incorrectly encoded. Hence fixed BIT (IX+d).
2017-06-19 21:04:14 -04:00
Thomas Harte
378233f53d
Extended to BITs and SETs, accruing three new failures.
2017-06-19 21:01:30 -04:00
Thomas Harte
f903408980
Caught up on comments.
2017-06-19 20:53:22 -04:00