Thomas Harte
af02ce9c6e
Attempts to correct various instances of PC-relative addressing.
2019-04-05 23:49:13 -04:00
Thomas Harte
56e42859ab
Ensures the supervisor flag is updated properly on MOVE to SR.
2019-04-05 23:21:50 -04:00
Thomas Harte
2d153359f8
Adds BTST.
2019-04-04 21:43:22 -04:00
Thomas Harte
068ce23716
Adds a few more MOVEs.
2019-04-04 19:49:19 -04:00
Thomas Harte
03be2e3652
Adds decoding of ADDA and SUBA.
2019-04-03 22:39:01 -04:00
Thomas Harte
4ef2c0bed8
Completes ADD and SUB.
2019-04-03 21:41:59 -04:00
Thomas Harte
bfd405613c
Reuse of addresses is also no longer implicit.
2019-04-03 21:27:11 -04:00
Thomas Harte
73e1c8c780
Corrects now-unimplemented ADD/SUB.
2019-04-03 19:43:54 -04:00
Thomas Harte
689ba1d4a2
Effective address adjustments now have to be explicit.
2019-04-03 19:13:10 -04:00
Thomas Harte
39b9d00550
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-02 21:50:58 -04:00
Thomas Harte
64f99d83a4
Takes a stab at offering ADD, ADDA, SUB and SUBA operations.
...
Not yet decoded.
2019-04-01 21:21:26 -04:00
Thomas Harte
8f1faefa1c
Implements further MOVEs and fixes a potential error in program formation.
2019-03-31 22:34:28 -04:00
Thomas Harte
a9ceef5c37
Improves communication slightly.
2019-03-31 22:27:33 -04:00
Thomas Harte
c6f977ed4b
Corrects CMPI and documentation; implements JMP.
2019-03-31 21:13:26 -04:00
Thomas Harte
cb240cd32a
Switches to a more explicit tokeniser, to allow for greater flexibility momentarily.
2019-03-30 23:11:39 -04:00
Thomas Harte
bc6349f823
Adds RESET, fixes branches and attempts to fix CMPI.
2019-03-29 23:40:54 -04:00
Thomas Harte
a93a1ae40f
Completes MOVE.blw <ea>, Dn/An/(An)/(An)+, implements MOVEq.
2019-03-29 23:13:41 -04:00
Thomas Harte
25254255fe
Implements a few additional MOVEs.
2019-03-27 21:26:04 -04:00
Thomas Harte
42634b500c
Implements LEA.
2019-03-26 22:07:28 -04:00
Thomas Harte
be4b38c76a
Adds BRA and Bcc.
2019-03-25 22:54:49 -04:00
Thomas Harte
7163b1132c
Takes a run at CMPI.
...
Also factors out a couple of mode things, clarifies on where things from the
prefetch are assembled to, and switches to ordering implemented instructions
alphabetically.
2019-03-24 23:05:57 -04:00
Thomas Harte
3ccec1c996
Implements MOVE to SR, fleshing out the final bits of storage for the status word.
2019-03-24 18:20:54 -04:00
Thomas Harte
47359dc8f1
Adds tests for MOVE.l (An), Dn, and thereby correct their implementation.
2019-03-23 21:41:47 -04:00
Thomas Harte
43532c8455
Starts to make incursions into MOVE[A].l.
2019-03-23 21:03:52 -04:00
Thomas Harte
d7c3d4ce52
Adds test for MOVEA.w (0x1000), A1 and fixes implementation thereof.
2019-03-22 23:27:48 -04:00
Thomas Harte
ed7060a105
Made an initial stab at completing MOVEA.w.
...
I think I'm probably peeking into the prefetch queue incorrectly.
2019-03-22 21:43:51 -04:00
Thomas Harte
db0da4b741
Improves get/set state.
2019-03-22 19:34:17 -04:00
Thomas Harte
c9c16968bb
Implements MOVEA as distinct from MOVE.
...
At least as far as MOVE is implemented, that is.
2019-03-22 19:25:53 -04:00
Thomas Harte
fdc598f2e1
Starts MOVE tests; in pursuit of which talks the 68000 into obeying run lengths.
2019-03-21 22:30:41 -04:00
Thomas Harte
f679145bd1
Makes a further push into the MOVEs.
...
With some quick notation shortening.
2019-03-20 23:21:02 -04:00
Thomas Harte
eeb161ec51
Converts the prefetch queue into a 32-bit quantity.
2019-03-19 21:33:52 -04:00
Thomas Harte
21cb7307d0
Adds MOVE #, Dn
and MOVEA An, An
.
...
As well as the scheduling for `(d16,PC), Dd` and `MOVE (d8,As,Xn), Dd` other than the .ls.
2019-03-19 11:53:37 -04:00
Thomas Harte
412a1eb7ee
Takes an initial run at (An)+, -(An), (d16,An) and (d8,An,Xn) addressing modes.
...
With only MOVEs from those to a data register implemented so far.
2019-03-18 22:51:32 -04:00
Thomas Harte
1d801acf72
Switched to a better ABCD fix.
2019-03-17 22:04:32 -04:00
Thomas Harte
0d7bbdad54
Begins a basic get/set state API, allowing some actual unit tests, implying an ABCD fix.
2019-03-17 21:57:00 -04:00
Thomas Harte
53b3d9cf9d
Implements a few more MOVE variants, plus MOVEA.
2019-03-17 14:34:16 -04:00
Thomas Harte
c3ebbfb10e
Implements all MOVE Dn, Dn
.
2019-03-16 23:14:18 -04:00
Thomas Harte
58f035e31a
Makes error more communicative.
2019-03-16 23:05:12 -04:00
Thomas Harte
a8f1d98d40
Small further adjustments; seems likely to be correct now.
2019-03-16 23:01:56 -04:00
Thomas Harte
cf6fa98433
Corrects detection of terminal micro-ops.
2019-03-16 22:50:44 -04:00
Thomas Harte
937b3ca81d
Attempts properly to honour the bus-op and microcycle contract.
2019-03-16 22:36:09 -04:00
Thomas Harte
d0c5cf0d2d
Starts attempting to kill the need to prepare all bus step sequences in advance.
2019-03-16 21:47:46 -04:00
Thomas Harte
4cbf2bef82
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp.
...
As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 19:41:07 -04:00
Thomas Harte
388d808536
Switches to providing UDS and LDS implicitly via address.
...
Also makes sure that the difference between a non-data cycle that starts without the address strobe active and one that starts with it active can be discerned.
2019-03-16 17:54:58 -04:00
Thomas Harte
720aba3f2d
Adds an implementation of SBCD and slightly neatens syntax for building programs.
2019-03-14 21:22:02 -04:00
Thomas Harte
f9101de956
This might very well be the 68000's first real gasp: performing an ABCD.
2019-03-14 19:32:15 -04:00
Thomas Harte
bb04981280
I'm still dithering on address management, but this seeks fully to implement ABCD and SUBD bus programs.
2019-03-13 21:08:13 -04:00
Thomas Harte
57898ed6dd
This is where my thinking now resides. Two levels of indirection, and consolidated collections.
2019-03-12 22:46:31 -04:00
Thomas Harte
33b53e7605
Settles upon disassembly as the route in, and begins work in that direction.
2019-03-11 22:47:58 -04:00
Thomas Harte
89c71f9119
Introduces EmuTOS, and starts constructing test cases around it.
2019-03-10 18:40:12 -04:00
Thomas Harte
98aa597510
A theoretical 68000 could now perform its /RESET. That's all though.
2019-03-10 17:42:13 -04:00
Thomas Harte
de56d48b2f
Embraces a more communicative 68000 bus.
2019-03-10 17:27:34 -04:00
Thomas Harte
4aeb9a7c56
Genericises RegisterPair.
2019-03-09 21:16:11 -05:00
Thomas Harte
b9b52b7c8b
Begins some very early sketching out of a 68000.
2019-03-09 00:00:23 -05:00
Thomas Harte
d97348dd38
Eliminates dangling uses of printf
.
2019-03-02 18:07:05 -05:00
Thomas Harte
ee89be6730
Removes many stray spaces.
2018-11-23 22:32:32 -05:00
Thomas Harte
364859467f
Corrects Rockwell and WDC references.
...
Also shuffles the NES CPU type up into the top position, so this is a strict progression in terms of functionality.
2018-09-27 22:36:45 -04:00
Thomas Harte
8787d85e64
Eliminates #undefs as being (i) unnecessary, now this is a source file; and (ii) incomplete in any case.
2018-08-17 22:24:42 -04:00
Thomas Harte
0e7f54f375
Implements STP and WAI, and ensures all unimplemented 65C02 instructions are NOP for all 65C02s.
2018-08-17 21:49:06 -04:00
Thomas Harte
b3bdfa9f46
Corrected: it's three-cycle 65C02 branches that ignore interrupts, not two.
2018-08-16 20:47:49 -04:00
Thomas Harte
592ec69d36
Causes the 65C02 not to accept interrupts immediately after untaken branches.
2018-08-15 22:42:04 -04:00
Thomas Harte
60e00ddd02
Correction: the test for not skipping an operand fetch requires a 65C02.
2018-08-15 22:07:17 -04:00
Thomas Harte
6806193dc2
Ensures that "Read/Modify/Write instructions absolute indexed in same page" take only six cycles on a 65C02.
2018-08-15 19:17:37 -04:00
Thomas Harte
c35dca783f
Ensures that page-crossing indexing no longer causes an extra read of an invalid address on the 65C02.
...
It rereads the last byte of the instruction stream instead.
2018-08-15 18:47:53 -04:00
Thomas Harte
901e0d65b9
Documents all 6502 micro-operations.
...
Also makes sure 1-cycle NOPs really, definitely are one cycle only on a 65C02 and eliminates OperationCopyOperandFromA as a redundant copy of OperationSTA.
2018-08-14 22:17:53 -04:00
Thomas Harte
ddf45a0010
Ensures NMI and RST reset D on 65C02s.
2018-08-14 19:49:14 -04:00
Thomas Harte
1eca4463b3
Ensures NMI can no longer usurp BRK on 65C02s.
2018-08-14 19:33:48 -04:00
Thomas Harte
be01203cc1
Starts to expand the range of supported 6502s.
...
This fully implements the NES 6502 because, well, it's virtually no extra work, and ensures that RDY takes effect on write cycles on 65C02s.
2018-08-13 22:17:22 -04:00
Thomas Harte
4b91910fab
Removes erroneous addition.
2018-08-10 23:27:09 -04:00
Thomas Harte
878c63dcd2
Ensures ADC and SBC decimal take an extra cycle on the 65C02.
2018-08-10 22:52:55 -04:00
Thomas Harte
261fb3d4f8
Implements proper test for ADC/SBC 65C02 NZ, though not yet the proper timing.
...
This gets Klaus Dorman's test to pass.
2018-08-10 22:42:35 -04:00
Thomas Harte
5d6e479338
Implements RMB and SMB, and fixes SBC (zero).
2018-08-10 22:13:51 -04:00
Thomas Harte
90094529a5
Implements TSB and TRB, and adds the extra BIT instructions.
2018-08-10 22:04:45 -04:00
Thomas Harte
aed4c0539e
Implements STZ.
2018-08-10 21:17:02 -04:00
Thomas Harte
8b50ab2593
Corrects (zero) behaviour.
2018-08-10 21:12:55 -04:00
Thomas Harte
95164b79c9
Attempted implementation of (zp) addressing mode.
2018-08-09 21:51:14 -04:00
Thomas Harte
6f838fe190
Implements INA and DEA.
2018-08-08 22:30:19 -04:00
Thomas Harte
bb680b40d8
Implements the 65C02's JMPs.
2018-08-08 22:26:57 -04:00
Thomas Harte
e3f6da6994
Implements the 65C02 NOPs.
2018-08-08 20:00:14 -04:00
Thomas Harte
e46bde35f5
Implements BBS and BBR.
2018-08-07 21:52:17 -04:00
Thomas Harte
32338bea4d
Implements BRA.
2018-08-06 22:37:30 -04:00
Thomas Harte
5c881bd19d
Implements PLX, PLY, PHX and PHY.
2018-08-06 22:00:23 -04:00
Thomas Harte
1a44ef0469
Introduces Klaus Dorman's 65C02 tests. All failing.
2018-08-06 21:48:43 -04:00
Thomas Harte
ebce9a2e51
Fixes test target.
2018-08-06 21:15:13 -04:00
Thomas Harte
633af4d404
The operations table is now per-instance.
2018-08-06 20:47:14 -04:00
Thomas Harte
76a73c835c
Forces 6502 consumers to declare which model — the original, 65C02 or 65SC02.
...
All present machines use a regular 6502.
2018-08-06 20:06:07 -04:00
Thomas Harte
0b14850467
Corrects some comments.
2018-06-24 23:02:36 -04:00
Thomas Harte
9a91ae38c1
Differentiates reasons for a read to be four cycles.
...
Specifically, puts the enforced wait either before or after checking the wait line. More research may be required; it feels more likely to me that a forced post wait should complete the read then wait, but would that still count as a single machine cycle?
2018-06-20 21:34:21 -04:00
Thomas Harte
ad9b0cd4e3
Eliminates all endashes.
2018-05-13 15:43:03 -04:00
Thomas Harte
5d6b5d9f10
Eliminates all emdashes in cross-platform code.
2018-05-13 15:34:31 -04:00
Thomas Harte
0b771ce61a
Removes all instances of the copyright symbol.
2018-05-13 15:19:52 -04:00
Thomas Harte
45be1c19df
Resolves undefined behaviour of a signed shift left.
2018-03-22 21:59:39 -04:00
Thomas Harte
0e73ba4b3e
Introduces proper 5/3 SCF/CCF behaviour for the Z80.
...
While also `const`ing a bunch of things.
2018-03-09 09:47:00 -05:00
Thomas Harte
f0f9d5a6af
Corrects memptr leakage via BIT, and ld (de/bc/nn), A behaviour.
2018-03-08 20:30:22 -05:00
Thomas Harte
74dfe56d2b
Expands documentation of NMI setting.
...
Given that it was previously incorrect, explains logic behind request_status_ and last_request_status_ setting. Also takes the opportunity to ensure that NMI is 'sampled' at the same time as IRQ; whether the next thing should be the NMI routine now occurs one cycle before the end of any instruction. That's an assumption for now. Testing to come.
2018-03-02 11:10:02 -05:00
Thomas Harte
b02e4fbbf6
Corrects NMI receipt to be genuinely edge triggered.
...
Previously a caller that signalled NMI set multiple times would trigger multiple NMIs.
2018-03-01 22:04:56 -05:00
Thomas Harte
23c47e21de
Proceeds the ColecoVision to booting.
2018-02-24 18:14:38 -05:00
Thomas Harte
7dfbe4bb93
Ensures proper Boolean startup values for IFF1 and IFF2.
2017-11-29 20:32:55 -05:00
Thomas Harte
5aef81cf24
Commutes cross-platform #pragma mark
s to //MARK:
s.
2017-11-12 15:59:11 -05:00
Thomas Harte
2e15fab651
Doubles down on <cX> over <X.h> for C includes, and usage of the namespace for those types and functions.
2017-11-11 15:28:40 -05:00
Thomas Harte
cb0f58ab7a
Corrects order-of-initialisation errors in the CPC (again), TextureBuilder, TextureTarget, Z80, MFM parser and binary tape player.
2017-11-10 22:57:03 -05:00
Thomas Harte
4cbc87a17d
Corrects out-of-order initialisations for the 1770, Atari 2600 joystick, Pitfall II bus extender, Microdisc and 6502.
2017-11-10 22:20:44 -05:00
Thomas Harte
c0055a5a5f
Further builds up SConstruct, correcting many missed imports and a couple of improper uses of C99 in C++ code.
2017-11-09 22:04:49 -05:00
Thomas Harte
6e1d69581c
Eliminates a variety of end-of-line spaces.
2017-11-07 22:54:22 -05:00
Thomas Harte
ad9df4bb90
Commutes uint8_t *
, uint16_t *
, uint32_t *
, size_t
, off_t
and long
to functional-style casts.
2017-10-21 22:30:15 -04:00
Thomas Harte
e983854e71
Converts all uint8_t
and uint16_t
casts to the functional style.
2017-10-21 21:50:53 -04:00
Thomas Harte
ab2bcb939f
Separates 6502Base into its constituent parts.
2017-09-04 11:08:33 -04:00
Thomas Harte
45499050b6
Separates Z80Base.cpp into its component classes.
2017-09-04 11:04:01 -04:00
Thomas Harte
a1e200cc65
Further strips back the amount exposed in Z80-related headers.
...
Almost all opcode table generation macros and code now resides neatly in the world of .CPP.
2017-09-01 22:19:16 -04:00
Thomas Harte
e6ac939ae0
Reintroduces missing noexcept specifier.
2017-09-01 20:51:31 -04:00
Thomas Harte
b034d4e6f8
Refactors the Z80 to separate out interface and implementation.
...
Following the pattern just established by the 6502, puts all implementation specifics beyond the visibility of a human reading Z80.hpp and in subfolders so as to promote the idea that they shouldn't go out of their way.
2017-09-01 20:50:24 -04:00
Thomas Harte
de218611e4
Corrects possible confusion as documentation recommends Cycles(0) as default, but then gives Cycles(1).
2017-09-01 20:49:24 -04:00
Thomas Harte
b306776ba9
Removes from 6502.hpp all remaining implementation details, making it purely an interface document.
...
Though those details remain visible to files including 6502.hpp through necessity.
2017-09-01 19:46:29 -04:00
Thomas Harte
4af333d5ec
Tidies the 6502 template and folder hierarchy.
...
Specifically: there's now just the one .h file at the top level, giving a clear indication of what a user should read. That separates implementation from interface. It also devolves a lot more to the base class because doing so makes debug builds less of a hassle. The all-RAM 6502 has been shuffled off into a subfolder, to indicate that it's not something you necessarily need know about. Also general documentation improvements have been applied: incorrect citing of the recurring-template pattern has been removed and the meaning of the two BusHandler methods has now accrued at the bus handler.
2017-08-31 22:10:27 -04:00
Thomas Harte
fab6908129
Corrects the all-RAM Z80 to declare that it needs the wait line to be implemented.
2017-08-26 23:18:11 -04:00
Thomas Harte
57bfec285f
Makes it optional whether the Z80 supports the wait line. If the wait line isn't in use, runtime costs are decreased because the optional wait cycles need not be iterated over.
2017-08-26 23:08:57 -04:00
Thomas Harte
fa19e2d9c2
Removes some detritus.
2017-08-24 22:00:21 -04:00
Thomas Harte
95d360251d
Makes all of PartialMachineCycle const, with the exception of the target of *value, since that's intended to be writeable by recipients.
2017-08-24 21:32:33 -04:00
Thomas Harte
7af3de010e
Suspected my mode 1 interrupt timing might be off. Reminded myself of the sources. Persuaded myself that it wasn't. Added appropriate comments.
2017-08-23 22:25:31 -04:00
Thomas Harte
ee71be0e7e
Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.
2017-08-21 21:56:42 -04:00
Thomas Harte
e1aded0d95
Allows Z80 users to opt out of support for the bus request line. Which both now do.
2017-08-21 20:43:12 -04:00
Thomas Harte
6315c22b80
Removed repeated checking of bus_request_line_. It's now checked only after each outward perform_machine_cycle
.
2017-08-20 12:39:45 -04:00
Thomas Harte
42b5b66305
Remove the 6502's use of runtime polymorphism in favour of ordinary templating.
2017-08-16 11:56:52 -04:00
Thomas Harte
039811ce6a
Switched the Z80 to being something a machine has, not something a machine is.
2017-08-02 22:09:59 -04:00
Thomas Harte
4abd62e62b
Standardises on const [Half]Cycles
as the thing called and returned, rather than const [Half]Cycles &
as it's explicitly defined to be only one int
in size, so using a reference is overly weighty.
2017-07-27 22:05:29 -04:00
Thomas Harte
9ef232157b
Revoked the operator bool() on WrappedInt as providing an indirect means for implicit but incorrect assignment to unwrapped ints. Got explicit about run_for
intention and simplified HalfClockReceiver slightly by building a lossy and a flushing conversion to Cycles into HalfCycles. Adapted the all-RAM Z80 properly to return HalfCycles.
2017-07-27 21:38:50 -04:00
Thomas Harte
8848ebbd4f
Formalised set_interrupt_line's optional parameter as being a count of HalfCycles; corrected PartialMachineCycle.is_wait and effected the proper timing for counter reset on a ZX81.
2017-07-27 21:10:14 -04:00
Thomas Harte
37950143fc
Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.
2017-07-27 20:17:13 -04:00
Thomas Harte
60e374dca3
Merge branch 'master' into Memptr
2017-07-27 07:54:25 -04:00
Thomas Harte
8361756dc4
Switched definitively to the works-for-now approach of requiring an explicit opt-in where somebody wants to clock a whole-cycle receiver from a half-cycle clock.
2017-07-27 07:40:02 -04:00
Thomas Harte
847e49ccdf
Corrected timestamp reporting by the all-RAM Z80.
2017-07-26 19:47:39 -04:00
Thomas Harte
81a3899381
Adjusted the Z80 formally to communicate in terms of half cycles rather than whole.
2017-07-26 19:42:00 -04:00
Thomas Harte
9257a3f6d7
Added test for 16-bit arithmetic, and fixed implementation.
2017-07-26 19:04:52 -04:00
Thomas Harte
6ec4e4e3d7
Merge branch 'master' into Memptr
2017-07-25 23:01:34 -04:00
Thomas Harte
966b5e6372
Adapted the Z80's perform_machine_cycle
to return Cycles
.
2017-07-25 22:25:44 -04:00
Thomas Harte
279c369a1f
Switched to Cycles as the result from the 6502 perform_bus_operation
, helping slightly to clarify what you're intended to return and reducing type jumping within the 6502 implementation.
2017-07-25 22:21:09 -04:00
Thomas Harte
75d67ee770
Relocated ClockReceiver.hpp as it's a dependency for parts of the static analyser, and therefore needs to be distinct from the actual emulation parts.
2017-07-25 20:20:55 -04:00
Thomas Harte
a1e9a54765
Eliminated redundant uses of ClockReceiver
and sought to ensure that proper run_for
s are inherited all the way down.
2017-07-25 20:09:13 -04:00
Thomas Harte
677ed463f0
Updated comment per new method name.
2017-07-24 21:19:49 -04:00
Thomas Harte
9bff787ee1
Corrected for the new, non-integral type.
2017-07-24 21:05:07 -04:00
Thomas Harte
b82bef95f3
Decided to follow through on Cycles
and HalfCycles
as complete integer-alikes. Which means giving them the interesting range of operators. Also killed the implicit conversion to int as likely to lead to type confusion.
2017-07-24 20:10:05 -04:00
Thomas Harte
ace8e30818
Bubbled the Z80's move into clock receiver territory up into the Z80 test machine.
2017-07-23 22:21:39 -04:00
Thomas Harte
ec3aa06caf
Removed dangling reference.
2017-07-23 22:16:00 -04:00
Thomas Harte
ba088e5545
Adapted the Z80 into a clock receiver, which also vends Cycles
rather than a raw int within its PartialMachineCycle
struct. The objective is to update it to vend HalfCycles within its struct, but I think I need to do some work on cycle/half-cycle arithmetic first.
2017-07-23 22:15:04 -04:00
Thomas Harte
2ff157cf7a
Switched CRTMachine over to use Cycles
as an explicit statement of units, and followed through on the effects of that.
2017-07-22 22:17:29 -04:00
Thomas Harte
83628b285b
Experimentally turned the 6502 into a clock receiver. No problem encountered.
2017-07-22 21:52:21 -04:00
Thomas Harte
20a6bcc676
Added tests for the various LD (nn), rr
instructions and corrected implementation to pass.
2017-07-22 11:39:13 -04:00
Thomas Harte
eaf313b0f6
Added a test on LD A, (DE) and LD A, (BC), and adjusted implementation to pass.
2017-07-22 11:20:21 -04:00
Thomas Harte
d51b66c204
Expanded test to hit all 65536 possibilities (and not to allocate a fresh Z80 test machine each time, as that's unnecessary and slow), and fixed implementation to pass test.
2017-07-21 23:01:35 -04:00
Thomas Harte
540a03f75c
Exposed the memptr register.
2017-07-21 22:31:42 -04:00