Richard Osborne
70ad3951e4
Move various XCore tests to FileCheck
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143457 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-01 10:41:28 +00:00
Richard Osborne
a1d16b53e8
Associate a MemOperand with LDWCP nodes introduced during ISel.
...
This information is required if we want LDWCP to be hoisted out of loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139495 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 14:43:23 +00:00
Duncan Sands
4a544a79bd
Split the init.trampoline intrinsic, which currently combines GCC's
...
init.trampoline and adjust.trampoline intrinsics, into two intrinsics
like in GCC. While having one combined intrinsic is tempting, it is
not natural because typically the trampoline initialization needs to
be done in one function, and the result of adjust trampoline is needed
in a different (nested) function. To get around this llvm-gcc hacks the
nested function lowering code to insert an additional parent variable
holding the adjust.trampoline result that can be accessed from the child
function. Dragonegg doesn't have the luxury of tweaking GCC code, so it
stored the result of adjust.trampoline in the memory GCC set aside for
the trampoline itself (this is always available in the child function),
and set up some new memory (using an alloca) to hold the trampoline.
Unfortunately this breaks Go which allocates trampoline memory on the
heap and wants to use it even after the parent has exited (!). Rather
than doing even more hacks to get Go working, it seemed best to just use
two intrinsics like in GCC. Patch mostly by Sanjoy Das.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139140 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 13:37:06 +00:00
Richard Osborne
8f9c5cca4f
Add Uses=[SP] to call instructions. This fixes a miscompilation with a
...
variable sized alloca.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138433 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 13:32:43 +00:00
Richard Osborne
c4dcf323cc
Add intrinsics for SETEV, GETED, GETET.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137938 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18 13:00:48 +00:00
Richard Osborne
965b891762
Fix crash with varargs function with no named parameters.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136623 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-01 16:45:59 +00:00
Richard Osborne
c8007ab582
Add intrinsics for the zext / sext instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135476 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 13:28:50 +00:00
Richard Osborne
829bef1a46
Add intrinsics for the testct, testwct instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135475 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 13:00:40 +00:00
Richard Osborne
dee3dd9129
Add intrinsics for the peek and endin instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135474 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 12:50:25 +00:00
Chris Lattner
d589099eec
make the asmparser reject function and type redefinitions. 'Merging' hasn't been
...
needed since llvm-gcc 3.4 days.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133248 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-17 07:06:44 +00:00
Richard Osborne
9497466190
Add XCore intrinsic for crc8.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132340 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-31 16:24:49 +00:00
Richard Osborne
7736c37c14
Add XCore intrinsic for crc32.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132336 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-31 14:47:36 +00:00
Richard Osborne
bc5fd67b53
Convert test to FileCheck.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132335 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-31 14:00:05 +00:00
Jakob Stoklund Olesen
22d28d2372
Fix register-dependent XCore tests
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130816 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-04 01:01:41 +00:00
Jakob Stoklund Olesen
a6f7499244
Fix Mips, Sparc, and XCore tests that were dependent on register allocation.
...
Add an extra run with -regalloc=basic to keep them honest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128654 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 18:42:43 +00:00
Richard Osborne
e8f3533323
Add XCore intrinsics for initializing / starting / synchronizing threads.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128633 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 15:13:13 +00:00
Richard Osborne
11bd0784d9
Add XCore intrinsic for setpsc.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127821 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-17 18:42:05 +00:00
Richard Osborne
e17139b3e9
Add XCore intrinsics for setclk, setrdy.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127761 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 21:56:00 +00:00
Richard Osborne
bb057453db
Add checkevent intrinsic to check if any resources owned by the current thread
...
can event.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127741 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 18:34:00 +00:00
Richard Osborne
8ae8cf4559
On the XCore the scavenging slot should be closest to the SP.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127680 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 15:10:11 +00:00
Richard Osborne
5aad8b3e78
Add XCore intrinsics for getps, setps, setsr and clrsr.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127678 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 13:45:47 +00:00
Benjamin Kramer
7bff3e7c1b
Fix mistyped CHECK lines.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127366 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-09 22:07:31 +00:00
Joerg Sonnenberger
89e0f386f3
Be nice to Xcore and the XMOS assembler and avoid quoting section names
...
that contain only letters, digits and the characters "_" and ".".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127028 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04 20:03:14 +00:00
Joerg Sonnenberger
ea83b13350
Bug#9033: For the ELF assembler output, always quote the section name.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126963 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03 22:31:08 +00:00
Richard Osborne
21d7eb3f3b
Add XCore intrinsic for eeu instruction.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126384 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-24 13:39:18 +00:00
Richard Osborne
d04b4937d1
Add XCore intrinsic for clre instruction.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126322 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-23 18:52:05 +00:00
Richard Osborne
9935bd0819
Add llvm.xcore.waitevent intrinsic. The effect of this intrinsic is to enable
...
events on the thread and wait until a resource is ready to event. The vector
of the resource that is ready is returned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126320 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-23 18:35:59 +00:00
Richard Osborne
292f62e06f
Add XCore intrinsic for the setv instruction.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126315 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-23 16:46:37 +00:00
Richard Osborne
2a2cb28526
Add XCore intrinsic for settw instruction.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126313 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-23 14:45:03 +00:00
Richard Osborne
d83318450b
Add XCore intrinsics for various instructions on ports.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126132 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-21 18:23:30 +00:00
Richard Osborne
59982f3ffc
Add intrinsic for setc instruction on the XCore.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125186 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-09 13:22:12 +00:00
Richard Osborne
17c1e51d22
Add XCore intrinsics for resource instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124794 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-03 13:14:25 +00:00
Richard Osborne
ff0c5014b2
Add support for trampolines on the XCore.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124722 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-02 14:57:41 +00:00
Richard Osborne
4e3740ee6d
Fix bug where ReduceLoadWidth was creating illegal ZEXTLOAD instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124587 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-31 17:41:44 +00:00
Rafael Espindola
1c10db3da9
Update tests.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123591 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-16 18:02:57 +00:00
Devang Patel
afeaae7a94
If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG message instead of creating DBG_VALUE for undefined value in reg0.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121059 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-06 22:39:26 +00:00
Evan Cheng
44be1a8d66
Enable machine sinking critical edge splitting. e.g.
...
define double @foo(double %x, double %y, i1 %c) nounwind {
%a = fdiv double %x, 3.2
%z = select i1 %c, double %a, double %y
ret double %z
}
Was:
_foo:
divsd LCPI0_0(%rip), %xmm0
testb $1, %dil
jne LBB0_2
movaps %xmm1, %xmm0
LBB0_2:
ret
Now:
_foo:
testb $1, %dil
je LBB0_2
divsd LCPI0_0(%rip), %xmm0
ret
LBB0_2:
movaps %xmm1, %xmm0
ret
This avoids the divsd when early exit is taken.
rdar://8454886
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114372 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-20 22:52:00 +00:00
Dan Gohman
9f23dee08c
Start function numbering at 0.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101638 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 16:29:15 +00:00
Dale Johannesen
b39b7e5ebf
Split big test into multiple directories to cater to
...
those who don't build all targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100688 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 20:43:35 +00:00
Chris Lattner
3b9d6216a4
fix AsmPrinter::GetBlockAddressSymbol to always return a unique
...
label instead of trying to form one based on the BB name (which
causes collisions if the name is empty). This fixes PR6608
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98495 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14 17:53:23 +00:00
Richard Osborne
79a73fbeb3
Add dag combine to simplify lmul(x, 0, a, b)
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98258 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-11 16:26:35 +00:00
Richard Osborne
850f1cd3c0
Handle MVT::i64 type in DAG combine for ISD::ADD. Fold 64 bit
...
expression add(add(mul(x,y),a),b) -> lmul(x,y,a,b) if all
operands are zero extended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98168 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-10 18:12:27 +00:00
Richard Osborne
2dacd1e987
Fold add(add(mul(x,y),a),b) -> lmul(x,y,a,b) if the intermediate
...
results are unused elsewhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98157 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-10 16:19:31 +00:00
Richard Osborne
a2cc0613d0
Prefer LMUL to MACCU as LMUL has no tied operands.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98153 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-10 13:27:10 +00:00
Richard Osborne
a7e78402b8
Custom lower (S|U)MUL_LOHI -> MACC(S|U)
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98152 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-10 13:20:07 +00:00
Richard Osborne
ebc64cf780
Lower add (mul a, b), c into MACCU / MACCS nodes which translate
...
directly to the maccu / maccs instructions. We handle this in
ExpandADDSUB since after type legalisation it is messy to
recognise these operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98150 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-10 11:41:08 +00:00
Richard Osborne
1250ac8a09
Convert test to FileCheck.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98148 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-10 11:24:03 +00:00
Richard Osborne
ad4f66c76f
In cases where the carry / borrow unused converted ladd / lsub
...
to an add or a sub.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98059 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-09 16:34:25 +00:00
Richard Osborne
7b871b3464
Add DAG combine for ladd / lsub.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98057 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-09 16:07:47 +00:00
Richard Osborne
d712783492
Fix XCoreTargetLowering::isLegalAddressingMode() to handle VoidTy.
...
Previously LoopStrengthReduce would sometimes be unable to find
a legal formula, causing an assertion failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97226 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26 16:44:51 +00:00
Richard Osborne
78700b0c55
Lower BR_JT on the XCore to a jump into a series of jump instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96942 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-23 13:25:07 +00:00
Chris Lattner
a34103f6fa
convert the last 3 targets to use EmitFunctionBody() now that
...
it has before/end body hooks.
lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp | 49 ++-----------
lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp | 87 ++++++------------------
lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp | 56 +++------------
test/CodeGen/XCore/ashr.ll | 2
4 files changed, 48 insertions(+), 146 deletions(-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94741 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-28 06:22:43 +00:00
Dan Gohman
aceba31b7a
Delete useless trailing semicolons.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92740 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-05 17:55:26 +00:00
Richard Osborne
bea7df56ce
Add XCore support for indirectbr / blockaddress.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89273 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-18 23:20:42 +00:00
Richard Osborne
13c4fabf99
Add XCore support for arbitrary-sized aggregate returns.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88802 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-14 19:33:35 +00:00
Richard Osborne
c96c8e0e81
Add some peepholes for signed comparisons using ashr X, X, 32.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83549 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 15:38:17 +00:00
Dan Gohman
fce288fc91
Eliminate more uses of llvm-as and llvm-dis.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81293 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-09 00:09:15 +00:00
Richard Osborne
1123135dbf
Add support for mergeable sections back into the XCore backend.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79368 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-18 21:14:31 +00:00
Richard Osborne
a9e8334877
Put data with relocations in the same sections as data without relocations.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79351 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-18 17:58:17 +00:00
Richard Osborne
2a5e23b44d
Update getSectionForConstant() to to allow mergable sections to be nulled out
...
if not supported by the ELF subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79249 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-17 16:37:11 +00:00
Chris Lattner
760e24cd05
use XCore-specific section with xcore specific cp/dp flags to restore
...
support for globals going into the appropriate sections with the flags.
This hopefully finishes unbreaking the previous behavior that I broke before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79079 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-15 06:09:35 +00:00
Richard Osborne
d558ea5e0a
Add extra SEXT pattern.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77920 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-02 22:45:24 +00:00
Chris Lattner
a87dea4f8c
switch off of 'Section' onto MCSection. We're not properly using
...
MCSection subclasses yet, but this is a step in the right direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77708 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-31 18:48:30 +00:00
Richard Osborne
e23e0976c7
Add tests for handling of globals and tls on the XCore. These currently fail
...
but pass when run against r76652.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76923 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-24 00:38:20 +00:00
Richard Osborne
db9e697725
Combine an unaligned store of unaligned load into a memmove.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75908 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 12:50:48 +00:00
Richard Osborne
ccb7e96ef0
Expand unaligned 32 bit loads from an address which is a constant
...
offset from a 32 bit aligned base as follows:
ldw low, base[offset >> 2]
ldw high, base[(offset >> 2) + 1]
shr low_shifted, low, (offset & 0x3) * 8
shl high_shifted, high, 32 - (offset & 0x3) * 8
or result, low_shifted, high_shifted
Expand 32 bit loads / stores with 16 bit alignment into two 16 bit
loads / stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75902 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 10:42:35 +00:00
Richard Osborne
7f47ce9662
Custom lower unaligned 32 bit stores and loads into libcalls. This is
...
a big code size win since before they were expanding to upto 16
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75901 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 10:21:18 +00:00
Richard Osborne
1d05b237a5
Fix pattern for LD16S_3r, add basic tests to check load / store instructions
...
are being properly selected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75797 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 17:06:59 +00:00
Richard Osborne
3af282f16a
Fix XCoreTargetLowering::isLegalAddressingMode to handle non simple VTs.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75788 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 15:46:56 +00:00
Dan Gohman
ae3a0be92e
Split the Add, Sub, and Mul instruction opcodes into separate
...
integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.
For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.
This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04 22:49:04 +00:00
Eli Friedman
2ac8b324eb
Fix for PR4235: to build a floating-point value from integer parts,
...
build an integer and cast that to a float. This fixes a crash
caused by trying to split an f32 into two f16's.
This changes the behavior in test/CodeGen/XCore/fneg.ll because that
testcase now triggers a DAGCombine which converts the fneg into an integer
operation. If someone is interested, it's probably possible to tweak
the test to generate an actual fneg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72162 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-20 06:02:09 +00:00
Chris Lattner
9dcab2fe8e
testcase for PR3898
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69473 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-18 20:49:22 +00:00
Rafael Espindola
bb46f52027
Add the private linkage.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62279 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-15 20:18:42 +00:00
Richard Osborne
cfb1ae87c6
Don't fold address calculations which use negative offsets into
...
the ADDRspii addressing mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62258 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-15 11:32:30 +00:00
Richard Osborne
29cab5f0ee
Add pseudo instructions to the XCore for (load|store|load address) of a
...
frame index. eliminateFrameIndex will replace these instructions with
(LDWSP|STWSP|LDAWSP) or (LDW|STW|LDAWF) if a frame pointer is in use.
This fixes PR 3324. Previously we used LDWSP, STWSP, LDAWSP before frame
pointer elimination. However since they were marked as implicitly using
SP they could not be rematerialised.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62238 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-14 18:26:46 +00:00
Richard Osborne
269bc0042f
Add support for ISD::TRAP to the XCore backend
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60479 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-03 10:59:16 +00:00
Duncan Sands
51d83fdd89
Reapply r59464, this time using the correct type
...
when softening FNEG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59513 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-18 09:15:03 +00:00
Bill Wendling
8f55b3d67d
Revert r59464. It was causing this failure:
...
Running /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/test/CodeGen/XCore/dg.exp ...
FAIL: /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/test/CodeGen/XCore/fneg.ll
Failed with signal(SIGABRT) at line 1
while running: llvm-as < /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/test/CodeGen/XCore/fneg.ll | llc -march=xcore > fneg.ll.tmp1.s
Assertion failed: (VT.isFloatingPoint() && "Cannot create integer FP constant!"), function getConstantFP, file /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/SelectionDAG/SelectionDAG.cpp, line 913.
0 llc 0x0092115c _ZN4llvm3sys18RemoveFileOnSignalERKNS0_4PathEPSs + 844
1 libSystem.B.dylib 0x9217809b _sigtramp + 43
2 ??? 0xffffffff 0x0 + 4294967295
3 libSystem.B.dylib 0x921f0ec2 raise + 26
4 libSystem.B.dylib 0x9220047f abort + 73
5 libSystem.B.dylib 0x921f2063 __assert_rtn + 101
6 llc 0x005a5b0a _ZN4llvm12SelectionDAG13getConmake[1]: *** [check-local] Error 1
make: *** [check] Error 2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59487 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-18 01:49:24 +00:00
Duncan Sands
7fed65a68d
Add soft float support for a bunch more operations. Original
...
patch by Richard Osborne, tweaked and extended by your humble
servant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59464 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-17 20:52:38 +00:00
Richard Osborne
104de6cf7b
Don't produce ADDC/ADDE when expanding SHL unless they are legal
...
for the target. This fixes PR3080.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59450 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-17 17:34:31 +00:00
Richard Osborne
223fd6efc8
[XCore] Fix expansion of 64 bit add/sub. Don't custom expand
...
these operations if ladd/lsub are not available on the current
subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-14 15:59:19 +00:00
Richard Osborne
1d8f975890
Add XCore intrinsics for getid (returns thread id) and bitrev (reverses
...
bits in a word).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59296 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-14 10:12:16 +00:00
Richard Osborne
b7ee8c4c1f
Add basic test for XCore backend
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58841 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-07 11:24:12 +00:00