6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-09-04 09:30:13 +00:00
Code Issues Projects Releases Wiki Activity
73,390 Commits 39 Branches 0 Tags 277 MiB
73f50d9bc3
Commit Graph

4621 Commits

Author SHA1 Message Date
Owen Anderson
18901d63bf Fix encoding of Thumb BLX register instructions. Patch by Koan-Sin Tan. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131189 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-11 17:00:48 +00:00
Bill Wendling
61512ba251 Give the 'eh.sjlj.dispatchsetup' intrinsic call the value coming from the setjmp 
intrinsic call. This prevents it from being reordered so that it appears
*before* the setjmp intrinsic (thus making it completely useless).
<rdar://problem/9409683>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131174 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-11 01:11:55 +00:00
Jason W Kim
f4351ceb93 First cut at getting debugging support for ARM/MC/ELF/.o 
DWARF stuff also gets fixed up by ELFARMAsmBackend::ApplyFixup(),
but the offset is not guaranteed to be mod 4 == 0 as in text/data. 




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131137 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-10 18:07:25 +00:00
Mon P Wang
183c627d89 Fixed MC encoding for index_align for VLD1/VST1 (single element from one lane) for size 32 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131085 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-09 17:47:27 +00:00
Jakob Stoklund Olesen
ca66226e7e Eliminate the ARM sub-register indexes that are not needed by the sources. 
Tablegen will invent its own names for these indexes, and the register file is a
bit simpler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131059 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-07 21:22:42 +00:00
Eric Christopher
33c110e602 Fix the non-MC encoding of pkhbt and pkhtb. 
Patch by Stephen Hines.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131045 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-07 04:37:27 +00:00
Eli Friedman
fc5d305597 Make the logic for determining function alignment more explicit. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131012 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-06 20:34:06 +00:00
Rafael Espindola
f2b0423200 Dead code elimination. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130984 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-06 14:56:22 +00:00
Devang Patel
64915dec28 Do not emit location expression size twice. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130854 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-04 19:00:57 +00:00
Jakob Stoklund Olesen
2944b4fe05 Mark ultra-super-registers QQQQ as call-clobbered instead of the D sub-registers. 
LiveVariables doesn't understand that clobbering D0 and D1 completely overwrites
Q0, so if Q0 is live-in to a function, its live range will extend beyond a
function call that only clobbers D0 and D1. This shows up in the
ARM/2009-11-01-NeonMoves test case.

LiveVariables should probably implement the much stricter rules for physreg
liveness that RAFast imposes - a physreg is killed by the first use of any
alias.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130801 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-03 22:31:24 +00:00
Bob Wilson
e1a56ae747 Temporarily disable use of divmod compiler-rt functions for iOS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130766 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-03 17:33:22 +00:00
Bruno Cardoso Lopes
0a69ba309f Fold ARM coprocessor intrinsics patterns into the instructions defs whenever 
it's possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130764 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-03 17:29:29 +00:00
Bruno Cardoso Lopes
54ad87ab78 Add a few ARM coprocessor intrinsics. Testcases included 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130763 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-03 17:29:22 +00:00
Dan Gohman
cca82149ad Add an unfolded offset field to LSR's Formula record. This is used to 
model constants which can be added to base registers via add-immediate
instructions which don't require an additional register to materialize
the immediate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130743 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-03 00:46:49 +00:00
Eric Christopher
52f6c03a45 Apparently the check for direct calls is unnecessary. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130716 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-02 20:16:33 +00:00
Eric Christopher
5ac179ccd2 80-col. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130558 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 23:12:01 +00:00
Eli Friedman
b451770b26 Zap a couple now-unused functions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130557 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 22:56:48 +00:00
Eli Friedman
c573e2c7ea Switch to ImmLeaf (which can be used by FastISel) for a few more common ARM/Thumb2 patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130552 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 22:48:03 +00:00
Eric Christopher
d94bc549fc Add FastEmitInst_ii for the arm fast isel generator. It doesn't use it, but 
if it ever did it needs the def machinery.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130549 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 22:07:50 +00:00
Eric Christopher
632ae892e6 Some cleanup and optimize fallthrough more. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130546 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 21:56:31 +00:00
Eli Friedman
9ebf57ae13 Re-committing r130454, which does not in fact break anything. 
Fix a rather obscure crash caused by ARM fast-isel generating code which redefines a register.
rdar://problem/9338332 .



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130539 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 21:22:56 +00:00
Eric Christopher
bcf26aee86 Add trunc->branch support, this won't help with clang's i8->i1 truncations 
for bools, but is a start.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130534 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 20:02:39 +00:00
Daniel Dunbar
0eab5c4d85 MCExpr: Add FindAssociatedSection, which attempts to mirror the 'as' semantics 
that associate sections with expressions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130517 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 18:00:03 +00:00
Andrew Trick
d49ffe8284 Teach Thumb2 isel to fold and->rotr ==> ROR. 
Generalization of Nate Begeman's patch!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130502 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 14:18:15 +00:00
Chris Lattner
d7d030a447 use the MachineInstrBuilder operator-> to simplify some code. 
There are probably more instances of this floating around.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130474 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 05:24:29 +00:00
Eric Christopher
6344a5f146 Update comments and checks to match reality. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130464 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 00:07:20 +00:00
Eric Christopher
299bbb23a4 Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130463 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 00:03:10 +00:00
Eli Friedman
6e6014cfb3 Revert r130454; apparently this doesn't actually work. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130462 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-28 23:55:14 +00:00
Eli Friedman
2f7fcd7198 Fix a rather obscure crash caused by ARM fast-isel generating code which redefines a register. 
rdar://problem/9338332 .



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130454 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-28 23:03:25 +00:00
Eric Christopher
7a20a37bac Be more layout aware here and swap the successor and branch condition 
if it means we get a fallthrough.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130404 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-28 16:52:09 +00:00
Eric Christopher
8f232d307a Let the immediate leaf pattern take transforms and switch the signed 
immediate patterns in arm to using the pattern.

Handles rdar://9299434


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130386 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-28 05:49:04 +00:00
Devang Patel
c26f5447e3 Teach dwarf writer to handle complex address expression for .debug_loc entries. 
This fixes clang generated blocks' variables' debug info.
Radar 9279956.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130373 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-28 02:22:40 +00:00
Kevin Enderby
e23aea28f9 Fix a bug in the case that there is no add or subtract symbol and the offset 
value is zero so it does not add a NULL expr operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130330 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-27 21:02:27 +00:00
Devang Patel
0be77dff11 Revert r130178. It turned out to be not the optimal path to emit complex location expressions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130326 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-27 20:29:27 +00:00
Jim Grosbach
f7da8821b4 ARM and Thumb2 support for atomic MIN/MAX/UMIN/UMAX loads. 
rdar://9326019


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130234 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-26 19:44:18 +00:00
Jakob Stoklund Olesen
c9e5015dec Add a TRI::getLargestLegalSuperClass hook to provide an upper limit on register class inflation. 
The hook will be used by the register allocator when recomputing register
classes after removing constraints.

Thumb1 code doesn't allow anything larger than tGPR, and x86 needs to ensure
that the spill size doesn't change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130228 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-26 18:52:33 +00:00
Devang Patel
0c99861836 Let dwarf writer allocate extra space in the debug location expression. This space, if requested, will be used for complex addresses of the Blocks' variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130178 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-26 00:12:46 +00:00
Sebastian Redl
dac4b9267b Fix Target/ARM/Thumb1FrameLowering.h header guard. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130097 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-24 15:47:01 +00:00
Andrew Trick
1c3af779fc Thumb2 and ARM add/subtract with carry fixes. 
Fixes Thumb2 ADCS and SBCS lowering: <rdar://problem/9275821>.
t2ADCS/t2SBCS are now pseudo instructions, consistent with ARM, so the
assembly printer correctly prints the 's' suffix.

Fixes Thumb2 adde -> SBC matching to check for live/dead carry flags.

Fixes the internal ARM machine opcode mnemonic for ADCS/SBCS.
Fixes ARM SBC lowering to check for live carry (potential bug).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130048 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-23 03:55:32 +00:00
Andrew Trick
5adfba283d whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130046 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-23 03:24:11 +00:00
Johnny Chen
597fa65373 Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should 
print out ldr, not ldr.n.

rdar://problem/9267772


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130008 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-22 19:12:43 +00:00
Devang Patel
0a6ea83f39 Add asserts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129995 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-22 16:44:29 +00:00
Evan Cheng
db6cbe1ff1 In Thumb2 mode, lower frame indix references to: 
add <rd>, sp, #<imm8>
ldr <rd>, [sp, #<imm8>]
When the offset from sp is multiple of 4 and in range of 0-1020.
This saves code size by utilizing 16-bit instructions.

rdar://9321541


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129971 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-22 01:42:52 +00:00
Devang Patel
71f3f1146f Fix DWARF description of Q registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129952 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-21 23:22:35 +00:00
Devang Patel
27f5acb7d4 Fix DWARF description of S registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129947 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-21 22:48:26 +00:00
Devang Patel
64d3d12f37 As per ARM docs, register Dx is described as DW_OP_regx(256+x) in DWARF. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129922 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-21 17:51:06 +00:00
Evan Cheng
c8578948c9 Remove -use-divmod-libcall. Let targets opt in when they are available. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129884 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-20 22:20:12 +00:00
Jakob Stoklund Olesen
6bfba2e5af Prefer cheap registers for busy live ranges. 
On the x86-64 and thumb2 targets, some registers are more expensive to encode
than others in the same register class.

Add a CostPerUse field to the TableGen register description, and make it
available from TRI->getCostPerUse. This represents the cost of a REX prefix or a
32-bit instruction encoding required by choosing a high register.

Teach the greedy register allocator to prefer cheap registers for busy live
ranges (as indicated by spill weight).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129864 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-20 18:19:48 +00:00
Stuart Hastings
e341e8ce1a Excise unintended hunk in 129858. <rdar://problem/7662569> 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129862 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-20 18:09:26 +00:00
Stuart Hastings
c73158730d ARM byval support. Will be enabled by another patch to the FE. <rdar://problem/7662569> 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129858 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-20 16:47:52 +00:00
Johnny Chen
4aaf3465f7 Fix typo in the comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129837 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-19 23:58:52 +00:00
Daniel Dunbar
912225e185 ADT/Triple: Move a variety of clients to using isOSDarwin() and isOSWindows() 
predicates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129816 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-19 21:14:45 +00:00
Eric Christopher
2cc4013853 Remove some duplicate op action entries and reorganize. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129781 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-19 18:49:19 +00:00
Bob Wilson
84c5eed15b This patch combines several changes from Evan Cheng for rdar://8659675. 
Making use of VFP / NEON floating point multiply-accumulate / subtraction is
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
   of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
   additional pipeline stall. So it's frequently better to single codegen
   vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
   stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
   vmla + vmla is very bad. But this isn't ideal either:
     vmul
     vadd
     vmla
   Instead, we want to expand the second vmla:
     vmla
     vmul
     vadd
   Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
   faster.

Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.

A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
   compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
   fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
   vmla / vmls will trigger one of the special hazards.

Enable these fp vmlx codegen changes for Cortex-A9.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129775 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-19 18:11:57 +00:00
Bob Wilson
cd70496ad1 Add -mcpu=cortex-a9-mp. It's cortex-a9 with MP extension. rdar://8648637. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129774 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-19 18:11:52 +00:00
Bob Wilson
5dde893c2b Avoid some 's' 16-bit instruction which partially update CPSR 
(and add false dependency) when it isn't dependent on last CPSR defining
instruction. rdar://8928208

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129773 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-19 18:11:49 +00:00
Bob Wilson
f6a4d3c2f3 Avoid write-after-write issue hazards for Cortex-A9. 
Add a avoidWriteAfterWrite() target hook to identify register classes that
suffer from write-after-write hazards. For those register classes, try to avoid
writing the same register in two consecutive instructions.

This is currently disabled by default.  We should not spill to avoid hazards!
The command line flag -avoid-waw-hazard can be used to enable waw avoidance.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129772 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-19 18:11:45 +00:00
Bob Wilson
b34d837397 Some single-precision VFP instructions can execute in either the VPF or Neon 
pipelines, at least on Cortex-A9.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129771 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-19 18:11:38 +00:00
Bob Wilson
11334dbd66 Improvements for the Cortex-A9 scheduling itineraries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129770 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-19 18:11:36 +00:00
Evan Cheng
75b41f1540 Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That 
is, it assumes addresses are 64-bit aligned (which should be the more common
case). If the alignment is found not to be aligned, then getOperandLatency()
would adjust the operand latency computation by one to compensate for it.
rdar://9294833


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129742 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-19 01:21:49 +00:00
Evan Cheng
b58a340fa2 Do not lose mem_operands while lowering VLD / VST intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129738 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-19 00:04:03 +00:00
Jim Grosbach
0d062c1e14 Trim a few unneeded includes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129723 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-18 21:35:54 +00:00
Sean Callanan
f6d9109124 Small fix to the ARM AsmParser to ensure that a 
superclass variable is instantiated properly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129713 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-18 20:20:44 +00:00
Stuart Hastings
c5eecbc4ec Correct result when a branch condition is live across a block 
boundary.  <rdar://problem/8933028>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129634 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-16 03:31:26 +00:00
Johnny Chen
3a96122c4a Thumb2 BFC was insufficiently encoded. 
rdar://problem/9292717


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129619 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 22:52:15 +00:00
Johnny Chen
a704bc9354 A8.6.315 VLD3 (single 3-element structure to all lanes) 
The a bit must be encoded as 0.

rdar://problem/9292625


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129618 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 22:49:08 +00:00
Cameron Zwarich
0cb11ac32f Add ORR and EOR to the CMP peephole optimizer. It's hard to get isel to generate 
a case involving EOR, so I only added a test for ORR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129610 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 21:24:38 +00:00
Cameron Zwarich
b485de5d8c The AND instruction leaves the V flag unmodified, so it falls victim to the same 
problem as all of the other instructions we fold with CMPs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129602 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 20:45:00 +00:00
Cameron Zwarich
ca3f6a3925 Add missing register forms of instructions to the ARM CMP-folding code. This 
fixes <rdar://problem/9287901>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129599 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 20:28:28 +00:00
Chris Lattner
7a2bdde0a0 Fix a ton of comment typos found by codespell. Patch by 
Luis Felipe Strano Moraes!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 05:18:47 +00:00
Evan Cheng
9eec66e604 Fix another fcopysign lowering bug. If src is f64 and destination is f32, don't 
forget to right shift the source by 32 first. rdar://9287902


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129556 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 01:31:00 +00:00
Johnny Chen
188ce9c78b For t2BFI, both Inst{26} and Inst{5} "should" be 0. 
Ref: I.1 Instruction encoding diagrams and pseudocode


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129552 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 00:35:08 +00:00
Johnny Chen
de29a52940 The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions 
(single element or n-element structure to all lanes).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129550 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 00:10:45 +00:00
Evan Cheng
06b2a60ef9 Follow up on r127913. Fix Thumb revsh isel. rdar://9286766 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129548 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-14 23:27:44 +00:00
Johnny Chen
cd695fdac1 Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129531 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-14 19:13:28 +00:00
Johnny Chen
e8d087ad35 Thumb disassembler did not handle tBRIND (indirect branch) properly. 
rdar://problem/9280370


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129480 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-13 21:59:01 +00:00
Johnny Chen
6c7e4147dc Check for unallocated instruction encodings when disassembling Thumb Branch instructions (tBcc and t2Bcc). 
rdar://problem/9280470


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129471 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-13 21:35:49 +00:00
Johnny Chen
471d73d5d3 The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt. 
rdar://problem/9279440


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129469 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-13 21:04:32 +00:00
Cameron Zwarich
5af60ce2a8 Fix a typo in an ARM-specific DAG combine. This fixes <rdar://problem/9278274>. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129468 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-13 21:01:19 +00:00
Johnny Chen
9bb386a933 Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings as such. 
rdar://problem/9276651


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129462 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-13 19:46:05 +00:00
Johnny Chen
119af20c7b Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was not properly handled. 
rdar://problem/9276427


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129456 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-13 17:51:02 +00:00
Johnny Chen
6e3ccc3c85 Forgot to add this change for http://llvm.org/viewvc/llvm-project?view=rev&revision=129387. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129451 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-13 16:56:08 +00:00
Cameron Zwarich
5876db7a66 Fix a typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129429 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-13 06:39:16 +00:00
Johnny Chen
55e6419b12 Add sanity check for Ld/St Dual forms of Thumb2 instructions. 
rdar://problem/9273947


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129411 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 23:31:00 +00:00
Jakob Stoklund Olesen
836a7de159 Add @earlyclobber constraints to the writeback register of all ARM store instructions. 
The ARMARM specifies these instructions as unpredictable when storing the
writeback register. This shouldn't affect code generation much since storing a
pointer to itself is quite rare.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129409 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 23:27:48 +00:00
Johnny Chen
ec51a6225c The Thumb2 RFE instructions need to have their second halfword fully specified. 
In addition, the base register is not rGPR, but GPR with th exception that:

    if n == 15 then UNPREDICTABLE

rdar://problem/9273836


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129391 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 21:41:51 +00:00
Johnny Chen
32cefad4b3 Add bad register checks for Thumb2 Ld/St instructions. 
rdar://problem/9269047


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129387 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 21:17:51 +00:00
Johnny Chen
f9ce2cba42 The Thumb2 Ld, St, and Preload instructions with the i12 forms should have its Inst{23} 
be specified as '1' (add = TRUE).

Also add a utility function for Thumb2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129377 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 18:48:00 +00:00
Johnny Chen
49fdfe3ce5 Print out a debug message when the reglist fails the sanity check for Thumb Ld/St Multiple. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129365 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 17:09:04 +00:00
Cameron Zwarich
d0aacbcc2e Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and ARM 
stores of arguments in the same cache line. This fixes the second half of
<rdar://problem/8674845>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129345 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 02:24:17 +00:00
Johnny Chen
e77f72d7d2 A8.6.16 B 
Encoding T1 (tBcc)
if cond == '1110' then UNDEFINED;

rdar://problem/9268681


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129325 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 00:14:49 +00:00
Johnny Chen
de16508955 Thumb disassembler was erroneously rejecting "blx sp" instruction. 
rdar://problem/9267838


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129320 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 23:33:30 +00:00
Johnny Chen
35563fee7b Fix the bug where the immediate shift amount for Thumb logical shift instructions are incorrectly disassembled. 
rdar://problem/9266265


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129298 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 21:14:35 +00:00
Owen Anderson
78a546936d Fix another using-CPSR-twice bug in my ADCS/SBCS cleanups, and make proper use of the Commutable bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129294 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 20:12:19 +00:00
Johnny Chen
f18dfc3a31 Trivial comment fix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129288 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 18:51:50 +00:00
Johnny Chen
e679d3331b Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as 
invalid instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129286 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 18:34:12 +00:00
Kevin Enderby
bd3327654b Adding support for printing operands symbolically to llvm's public 'C' 
disassembler API.  Hooked this up to the ARM target so such tools as Darwin's
otool(1) can now print things like branch targets for example this:
  blx _puts
instead of this:
  blx #-36
And even print the expression encoded in the Mach-O relocation entried for
things like this:
  movt r0, :upper16:((_foo-_bar)+1234)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129284 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 18:08:50 +00:00
Jay Foad
562b84b3ae Don't include Operator.h from InstrTypes.h. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129271 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 09:35:34 +00:00
Matt Beaumont-Gay
7c90e46622 Fix an apparent typo that made GCC complain 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129160 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-08 21:59:49 +00:00
Evan Cheng
4da0c7c0c9 Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap is lowered into a call to the specified trap function at sdisel time. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129152 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-08 21:37:21 +00:00
Johnny Chen
ee10b13a44 Check opcoe (dmb, dsb) instead of bitfields matching. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129148 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-08 20:03:46 +00:00
Johnny Chen
c636074afc Hanlde the checking of bad regs for SMMLAR properly, instead of asserting. 
PR9650
rdar://problem/9257565


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129147 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-08 19:41:22 +00:00
Johnny Chen
40de2b3f15 Sanity check the option operand for DMB/DSB. 
PR9648
rdar://problem/9257634


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129146 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-08 19:18:07 +00:00
Jim Grosbach
5b03a3a59a Mark hasExtraDefRegAllocReq=1 on LDRD. 
The previous cleanup of LDRD got overzealous and removed it, causing post-RA
scheduling to get overzealous in breaking antidependencies and invalidate these instructions. Hilarity and invalid assembly ensued.

rdar://9244161


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129144 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-08 18:47:05 +00:00
Johnny Chen
97fdff1d3f Add sanity checking for bad register specifier(s) for the DPFrm instructions. 
Add more test cases to exercise the logical branches related to the above change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129117 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-08 00:29:09 +00:00
Evan Cheng
274d8d4eba Add option to emit @llvm.trap as a function call instead of a trap instruction. rdar://9249183. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129107 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 20:31:12 +00:00
Mon P Wang
e32cdef38e Fixed encoding for VEXTqf 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129101 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 19:56:12 +00:00
Johnny Chen
22dc4d9f59 Add sanity checking for invalid register encodings for signed/unsigned extend instructions. 
Add some test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129098 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 19:28:58 +00:00
Johnny Chen
8dbda0b51b Add sanity checking for invalid register encodings for saturating instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129096 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 19:02:08 +00:00
Johnny Chen
4d4e25740b Add some more comments about checkings of invalid register numbers. 
And two test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129090 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 18:33:19 +00:00
Tanya Lattner
0433b21c98 Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector type (vectors of size 3). Also included test cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129074 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 15:24:20 +00:00
Johnny Chen
f16f4e09ec Sanity check MSRi for invalid mask values and reject it as invalid. 
rdar://problem/9246844


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129050 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 01:37:34 +00:00
Johnny Chen
8424a60fc9 The ARM disassembler was not recognizing USADA8 instruction. Need to add checking for register values 
for USAD8 and USADA8.

rdar://problem/9247060


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129047 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 01:05:52 +00:00
Evan Cheng
2c69f8eec6 Change -arm-divmod-libcall to a target neutral option. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129045 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 00:58:44 +00:00
Johnny Chen
2455268cdd Should also check SMLAD for invalid register values. 
rdar://problem/9246650


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129042 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 00:50:25 +00:00
Owen Anderson
df298c9ea6 Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for folded comparisons, just like ADD and SUB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129038 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-06 23:35:59 +00:00
Owen Anderson
ef7fb17936 Cleanups from Jim: remove redundant constraints and a dead FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129036 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-06 22:45:55 +00:00
Jim Grosbach
f22eefba68 Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129034 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-06 22:35:47 +00:00
Johnny Chen
d8b4c4d74f A8.6.393 
The ARM disassembler should reject invalid (type, align) encodings as invalid instructions.

So, instead of:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------

	vst2.32	{d0, d2}, [r3, :256], r3

we now have:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------

mc-input.txt:1:1: warning: invalid instruction encoding
0xb3 0x9 0x3 0xf4
^


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129033 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-06 22:14:48 +00:00
Johnny Chen
4d81c9a6ba A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP" 
Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits
specified, if coproc == 10 or 11, we should reject the insn as invalid.

rdar://problem/9239922
rdar://problem/9239596


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129027 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-06 20:49:02 +00:00
Johnny Chen
a9611549fe Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong. 
Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000,
in class NVLaneOp.

rdar://problem/9240648


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129015 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-06 18:27:46 +00:00
Johnny Chen
6a1220eeca Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function. 
Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25})
is 1, Inst{4} should be 0.  Otherwise, we should reject the insn as invalid.

rdar://problem/9239347
rdar://problem/9239467


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128977 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-06 01:18:32 +00:00
Owen Anderson
b48c791515 Reapply r128946 (pseudoization of various instructions), and fix the extra imp-def of CPSR it was adding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128965 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 23:55:28 +00:00
Johnny Chen
2c868d1eef Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal register 
encodings for DisassembleArithMiscFrm().

rdar://problem/9238659


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128958 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 23:28:00 +00:00
Bob Wilson
61f3cf3bc9 Clean up some code for clarity. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128953 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 23:03:25 +00:00
Owen Anderson
493cba1b32 Revert r128946 while I figure out why it broke the buildbots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128951 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 23:03:06 +00:00
Johnny Chen
c3281c10c9 A7.3 register encoding 
Qd -> bit[12] == 0
    Qn -> bit[16] == 0
    Qm -> bit[0]  == 0

If one of these bits is 1, the instruction is UNDEFINED.

rdar://problem/9238399
rdar://problem/9238445


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128949 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 22:57:07 +00:00
Owen Anderson
76634dfabb Give RSBS and RSCS the pseudo treatment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128946 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 22:42:54 +00:00
Johnny Chen
5438d76416 ARM disassembler was erroneously accepting an invalid RSC instruction. 
Added checks for regs which should not be 15.

rdar://problem/9237734


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128945 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 22:18:07 +00:00
Johnny Chen
c584e317e9 ARM disassembler was erroneously accepting an invalid LSL instruction. 
For register-controlled shifts, we should check that the encoding constraint
Inst{7} = 0 and Inst{4} = 1 is satisfied.

rdar://problem/9237693


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128941 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 21:49:44 +00:00
Owen Anderson
7670601313 Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as doing the expansion earlier (using a custom inserter) to allow for the chance of predicating these instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128940 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 21:48:57 +00:00
Johnny Chen
2c2130bc64 The r128085 checkin modified the operand ordering for MRC/MRC2 instructions. 
Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change.

rdar://problem/9236873


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128922 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 20:32:23 +00:00
Johnny Chen
bbc65bbb90 ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128913 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 19:42:11 +00:00
Jim Grosbach
215e4fdbf9 Make second source operand of LDRD pre/post explicit. 
Finish what r128736 started.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128903 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 18:40:13 +00:00
Johnny Chen
12bb2958c4 Constants with multiple encodings (ARM): 
An alternative syntax is available for a modified immediate constant that permits the programmer to specify
the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where:

    <byte> is the numeric value of abcdefgh, in the range 0-255
    <rot> is twice the numeric value of rotation, an even number in the range 0-30.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128897 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 18:02:46 +00:00
Johnny Chen
b26d8d7c49 Check for invalid register encodings for UMAAL and friends where: 
if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
    if dHi == dLo then UNPREDICTABLE;

rdar://problem/9230202


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128895 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 17:43:10 +00:00
Owen Anderson
15b81b51d6 Convert ADCS and SBCS instructions into pseudos that are expanded to the ADC/ABC with the appropriate S-bit input value. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128892 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 17:24:25 +00:00
Bill Wendling
f05b1dcf87 Revamp the SjLj "dispatch setup" intrinsic. 
It needed to be moved closer to the setjmp statement, because the code directly
after the setjmp needs to know about values that are on the stack. Also, the
'bitcast' of the function context was causing a dead load. This wouldn't be too
horrible, except that at -O0 it wasn't optimized out, and because it wasn't
using the correct base pointer (if there is a VLA), it would try to access a
value from a garbage address.
<rdar://problem/9130540>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128873 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 01:37:43 +00:00
Eric Christopher
0435661582 Just use BL all the time. It's safer that way. 
Fixes rdar://9184526


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128869 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 00:39:26 +00:00
Johnny Chen
157536b1fb Fix SRS/SRSW encoding bits. 
rdar://problem/9230801 ARM disassembler discrepancy: erroneously accepting SRS

Plus add invalid-RFEorLDMIA-arm.txt test which should have been checked in with
http://llvm.org/viewvc/llvm-project?view=rev&revision=128859.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128864 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 00:16:18 +00:00
Johnny Chen
597028cc28 A8.6.105 MUL 
Inst{15-12} should be specified as 0b0000.

rdar://problem/9231168 ARM disassembler discrepancy: erroneously accepting MUL


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128862 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-04 23:57:05 +00:00
Johnny Chen
670a456c83 RFE encoding should also specify the "should be" encoding bits. 
rdar://problem/9229922 ARM disassembler discrepancy: erroneously accepting RFE

Also LDC/STC instructions are predicated while LDC2/STC2 instructions are not, fixed while
doing regression testings.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128859 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-04 23:39:08 +00:00
Johnny Chen
2d66cec9dd Fix incorrect alignment for NEON VST2b32_UPD. 
rdar://problem/9225433


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128841 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-04 20:35:31 +00:00
Bruno Cardoso Lopes
ac79e4c82f - Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT 
also fix the encoding of the later.
- Add a new encoding bit to describe the index mode used in AM3.
- Teach printAddrMode3Operand to check by the addressing mode which
  index mode to print.
- Testcases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128832 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-04 17:18:19 +00:00
Cameron Zwarich
4071a71112 Do some peephole optimizations to remove pointless VMOVs from Neon to integer 
registers that arise from argument shuffling with the soft float ABI. These
instructions are particularly slow on Cortex A8. This fixes one half of
<rdar://problem/8674845>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128759 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-02 02:40:43 +00:00
Johnny Chen
04187ecd57 Fixed a bug in disassembly of STR_POST, where the immediate is the second operand in am2offset; 
instead of the second operand in addrmode_imm12.

rdar://problem/9225289


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128757 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-02 02:24:54 +00:00
Johnny Chen
103bf951a4 Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000. 
rdar://problem/9224276


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128749 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 23:30:25 +00:00
Johnny Chen
6da3fe68c6 MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is UNPREDICTABLE. 
rdar://problem/9224120


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128748 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 23:15:50 +00:00
Johnny Chen
857b1939da Fix the instruction table entries for AI1_adde_sube_s_irs multiclass definition so that 
all the instruction have:

    let Inst{31-27} = 0b1110; // non-predicated

Before, the ARM decoder was confusing:

> 0x40 0xf3 0xb8 0x80

as:

Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------

	adcs	pc, r8, r0, asr #6

since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'.

Now, the AR decoder behaves correctly:

> 0x40 0xf3 0xb8 0x80
> END
Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt

Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------

	adcshi	pc, r8, r0, asr #6
> 

rdar://problem/9223094


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128746 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 22:32:51 +00:00
Evan Cheng
0539c159fb Avoid de-referencing pass beginning of a basic block. No small test case possible. rdar://9216009 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128743 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 22:09:28 +00:00