Hao Liu
5025a48f68
AArch64: add missing ACLE intrinsics mapping to general arithmetic operation from VFP instructions.
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E.g. float64x1_t vadd_f64(float64x1_t a, float64x1_t b) -> FADD Dd, Dn, Dm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196208 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-03 05:58:30 +00:00
NAKAMURA Takumi
b26e6ecd8d
Whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196203 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-03 05:28:27 +00:00
Hao Liu
3d69ff4d07
AArch64: Add missing scalar pair intrinsics.
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E.g. "float32_t vaddv_f32(float32x2_t a)" to be matched into "faddp s0, v1.2s".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196198 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-03 03:39:47 +00:00
Jiangning Liu
bbc450c5cf
Add some missing pattern matches for AArch64 Neon intrinsics like vuqadd_s64 and friends.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196192 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-03 01:33:52 +00:00
Jiangning Liu
7f1f8d4146
Add some missing pattern matches for AArch64 Neon intrinsics like vmull_high_n_s16 and friends.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196190 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-03 01:29:32 +00:00
Rafael Espindola
9472fd7403
Refactor the setting of PrivateGlobalPrefix.
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No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196170 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-02 23:39:26 +00:00
Chad Rosier
d4809bb0e3
[AArch64] Implemented vcopy_lane patterns using scalar DUP instruction.
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Patch by Ana Pazos!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196151 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-02 21:05:16 +00:00
Rafael Espindola
15945a0b70
Remove dead code.
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MO_JumpTableIndex and MO_ExternalSymbol don't show up on inline asm.
Keeping parts of the old asm printer just to print inline asm to a string that
we then parse back looks like a hack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196111 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-02 15:36:37 +00:00
Rafael Espindola
4a6855441c
Change the default of AsmWriterClassName and isMCAsmWriter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196065 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-02 04:55:42 +00:00
Hao Liu
7fd70e7b0c
AArch64: The pattern match should check the range of the immediate value.
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Or we can generate some illegal instructions.
E.g. shrn2 v0.4s, v1.2d, #35 . The legal range should be in [1, 16].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195941 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-29 02:11:22 +00:00
Jiangning Liu
3733a6b892
Add missing pattern for supporting intrinsic function vbsl_f64 with
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argument double floating point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195938 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-29 01:37:15 +00:00
Kevin Qin
9224192321
[AArch64 NEON]Fix a assertion failure when disassemble SHLL instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195936 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-29 01:29:16 +00:00
Benjamin Kramer
4e7a22f970
Silence sign-compare warning and reduce nesting.
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No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195932 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-28 19:58:56 +00:00
NAKAMURA Takumi
ad363187c4
[CMake] Let add_public_tablegen_target responsible to provide dependency to CommonTableGen.
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add_public_tablegen_target adds *CommonTableGen to LLVM_COMMON_DEPENDS.
LLVM_COMMON_DEPENDS affects add_llvm_library (and other add_target stuff) within its scope.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195927 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-28 17:04:04 +00:00
NAKAMURA Takumi
9ec9b8434b
[CMake] Prune include_directories() in llvm/lib/Target. add_llvm_target() sets them.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195921 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-28 14:53:30 +00:00
NAKAMURA Takumi
dd290fe960
Add newline at eof.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195920 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-28 14:52:52 +00:00
Jiangning Liu
91e710c3dd
Remove the variable only used by assert to avoid the build failure
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caused by build options [-Werror,-Wunused-variable].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195905 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-28 01:34:55 +00:00
Hao Liu
cdd732cdd3
AArch64: Fix a bug about disassembling post-index load single element to 4 vectors
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195903 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-28 01:07:45 +00:00
Jiangning Liu
35df2e8c7f
Fix the AArch64 NEON bug exposed by checking constant integer argument range of ACLE intrinsics.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195843 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-27 14:02:25 +00:00
Chad Rosier
9fef0370c5
[AArch64] Add support for NEON scalar floating-point absolute difference.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195803 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-27 01:45:58 +00:00
Chad Rosier
48f115aabf
[AArch64] Add support for NEON scalar floating-point to integer convert
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instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195788 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-26 22:17:37 +00:00
Kevin Qin
cf7ed12a1d
Refactored the implementation of AArch64 NEON instruction ZIP, UZP
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and TRN.
Fix a bug when mixed use of vget_high_u8() and vuzp_u8().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195716 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-26 03:26:47 +00:00
Kevin Qin
57f6b2778b
[AArch64]Implement 128 bit register copy with NEON.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195713 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-26 02:33:42 +00:00
Hao Liu
e04ed6b8b1
Fixed a bug about disassembling AArch64 post-index load/store single element instructions.
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ie. echo "0x00 0x04 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble
echo "0x00 0x00 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble
will be disassembled into the same instruction st1 {v0b}[0], [x0], x0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195591 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-25 01:53:26 +00:00
Hao Liu
dd254ea7cb
Fix a Cygwin build failure caused by enum values starting with '_', which is conflicted with some platform macros.
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This patch only renames variables, no functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195432 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-22 09:24:41 +00:00
Hao Liu
e74a644b38
Fix the bugs about AArch64 Load/Store vector types and bitcast between i64 and vector types.
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e.g. "%tmp = load <2 x i64>* %ptr" can't be selected.
"%tmp = bitcast i64 %in to <2 x i32>" can't be selected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195424 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-22 08:47:22 +00:00
Hao Liu
bb3327f3f0
Revert last change by haoliu because of buildbot failure.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195423 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-22 08:34:54 +00:00
Hao Liu
7f5a9ca204
Fix a Cygwin build failure caused by enum values starting with '_', which is conflicted with some platform macros.
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This solution only renames variables, no functional change.
NOTE: This is a candidate for the 3.4 branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195421 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-22 08:17:16 +00:00
Jiangning Liu
0282fe6d91
For AArch64 back-end instruction selection, lower Neon_Lowxxx with EXTRCT_SUBREG.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195408 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-22 02:45:13 +00:00
Ana Pazos
6345249972
Implemented Neon scalar vdup_lane intrinsics.
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Fixed scalar dup alias and added test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195330 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-21 08:16:15 +00:00
Ana Pazos
1c93766aa5
Implemented Neon scalar by element intrinsics.
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Intrinsics implemented: vqdmull_lane, vqdmulh_lane, vqrdmulh_lane,
vqdmlal_lane, vqdmlsl_lane scalar Neon intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195327 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-21 07:37:04 +00:00
Hao Liu
36c7806f4e
Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195078 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 02:17:05 +00:00
Jiangning Liu
f11b55c5cc
Implement AArch64 SISD intrinsics for vget_high and vget_low.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195074 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 01:46:48 +00:00
Kevin Qin
282a979ddd
implement MC layer of AArch64 neon instruction PMULL and PMULL2 with 128 bit integer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195072 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 01:40:25 +00:00
Jiangning Liu
01dd5728cc
Add predicate for AArch64 crypto instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195071 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 01:38:31 +00:00
Juergen Ributzka
354362524a
[weak vtables] Remove a bunch of weak vtables
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This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file. The memory leaks in this version have been fixed. Thanks
Alexey for pointing them out.
Differential Revision: http://llvm-reviews.chandlerc.com/D2068
Reviewed by Andy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195064 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 00:57:56 +00:00
Alexey Samsonov
b21ab43cfc
Revert r194865 and r194874.
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This change is incorrect. If you delete virtual destructor of both a base class
and a subclass, then the following code:
Base *foo = new Child();
delete foo;
will not cause the destructor for members of Child class. As a result, I observe
plently of memory leaks. Notable examples I investigated are:
ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194997 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 09:31:53 +00:00
Kevin Qin
69b2447b6a
[AArch64 NEON]Add mov alias for simd copy instructions.
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Set some unspecified bits of INS/DUP to zero as ARMARM requested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194996 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 09:20:32 +00:00
Hao Liu
97577757c6
Implement the newly added ACLE functions for ld1/st1 with 2/3/4 vectors.
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The functions are like: vst1_s8_x2 ...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194990 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 06:31:53 +00:00
Ana Pazos
a53bf06f7a
Implemented aarch64 Neon scalar vmulx_lane intrinsics
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Implemented aarch64 Neon scalar vfma_lane intrinsics
Implemented aarch64 Neon scalar vfms_lane intrinsics
Implemented legacy vmul_n_f64, vmul_lane_f64, vmul_laneq_f64
intrinsics (v1f64 parameter type) using Neon scalar instructions.
Implemented legacy vfma_lane_f64, vfms_lane_f64,
vfma_laneq_f64, vfms_laneq_f64 intrinsics (v1f64 parameter type)
using Neon scalar instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194888 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 23:32:10 +00:00
Juergen Ributzka
5a364c5561
[weak vtables] Remove a bunch of weak vtables
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This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file.
Differential Revision: http://llvm-reviews.chandlerc.com/D2068
Reviewed by Andy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194865 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 22:34:48 +00:00
Chad Rosier
5758c3c832
[AArch64] Fix the scalar NEON ACLE functions so that they return float/double
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rather than the vector equivalent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194853 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 21:28:10 +00:00
Alexey Samsonov
4215561768
Hopefully fix uninitialized memory read in AArch64AsmParser found by MSan bootstrap bot
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194818 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 15:49:30 +00:00
Chad Rosier
6a1a5e94e2
[AArch64] Remove redundant Neon_immAllOnes/Neon_immAllZeros leaf patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194733 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 22:02:46 +00:00
NAKAMURA Takumi
f116f8a63f
AArch64DAGToDAGISel::SelectVTBL(): Fix a warning. [-Wunused-variable]
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194679 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 07:04:07 +00:00
Kevin Qin
0710afb9af
[AArch64 neon] support poly64 and relevant intrinsic functions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194659 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 03:27:58 +00:00
Kevin Qin
a08063a000
Implement aarch64 neon instruction class SIMD misc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194656 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 02:44:13 +00:00
Jiangning Liu
082ac99cc8
Implement AArch64 NEON instruction set AdvSIMD (table).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194648 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 01:57:32 +00:00
Chad Rosier
11966d7c98
[AArch64] Add support for legacy AArch32 NEON scalar shift by immediate
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instructions. This patch does not include the shift right and accumulate
instructions. A number of non-overloaded intrinsics have been remove in favor
of their overloaded counterparts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194598 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 20:05:37 +00:00
Chad Rosier
13c83a2a09
[AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalar
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copy in MC layer. Added the MC layer tests. Fixed triple setting in test cases.
Patch by Ana Pazos <apazos@codeaurora.org>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194501 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 19:13:08 +00:00
Chad Rosier
4c433cf673
[AArch64] The shift right/left and insert immediate builtins expect 3
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source operands, a vector, an element to insert, and a shift amount.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194406 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 19:11:11 +00:00
Chad Rosier
30b2a19f3b
[AArch64] Add support for NEON scalar floating-point convert to fixed-point instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194394 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 18:04:07 +00:00
Tim Northover
65d1be119b
AArch64: refactor vector list creation to be more uniform
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Instructions taking a vector list (e.g. "ld2 {v0.2d, v1.d2}, [x0]") need a
special register-class to deal with the constraints, and C++ code to support
selection. However, that C++ code can be made reasonably uniform to simplify
the selection process. Hence this patch.
No functionality change, so no tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194361 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 03:35:43 +00:00
Benjamin Kramer
1343fbcb7e
Remove some unnecessary temporary strings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194335 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-09 22:48:13 +00:00
Richard Barton
071a4f1a66
Make PrintAsmOperand call to the superclass to handle 'n' and 'c' operand modifiers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194270 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 18:09:57 +00:00
Amara Emerson
1b484aba80
[AArch64] Remove NEON from "generic" CPU target.
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We can change this back when NEON support is complete and ready to become
enabled by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194152 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 16:19:08 +00:00
Jiangning Liu
8458f371b8
Implement AArch64 Neon instruction set Perm.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194123 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 03:35:27 +00:00
Jiangning Liu
258115258f
Implement AArch64 Neon instruction set Bitwise Extract.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194118 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 02:25:49 +00:00
Jiangning Liu
3ff3a8aa75
Implement AArch64 Neon Crypto instruction classes AES, SHA, and 3 SHA.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194085 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 17:42:05 +00:00
Hao Liu
591c2f738a
Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post).
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Including following 14 instructions:
4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194043 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 03:39:32 +00:00
Kevin Qin
8263dcdf23
Implemented aarch64 neon intrinsic vcopy_lane with float type.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194041 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 02:03:59 +00:00
Tim Northover
627ef0cf5e
AArch64: use default asm operand printing when modifier inapplicable
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If an inline assembly operand has multiple constraints (e.g. "Ir" for immediate
or register) and an operand modifier (E.g. "w" for "print register as wN") then
we need to decide behaviour when the modifier doesn't apply to the constraint.
Previousely produced some combination of an assertion failure and a fatal
error. GCC's behaviour appears to be to ignore the modifier and print the
operand in the default way. This patch should implement that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194024 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 23:04:07 +00:00
Chad Rosier
13034b43ef
[AArch64] Simplify a few of the instruction patterns. No functional change intended.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193867 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-01 17:13:44 +00:00
Chad Rosier
d6e488d197
[AArch64] Fix assembly string formatting and other coding standard violations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193866 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-01 17:13:42 +00:00
Chad Rosier
1a035dd6df
[AArch64] Add support for NEON scalar fixed-point convert to floating-point instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193816 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 22:36:59 +00:00
Chad Rosier
1d28917dc3
[AArch64] Add support for NEON scalar shift immediate instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193790 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 19:28:44 +00:00
Amara Emerson
c2884320fe
[AArch64] Make the use of FP instructions optional, but enabled by default.
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This adds a new subtarget feature called FPARMv8 (implied by NEON), and
predicates the support of the FP instructions and registers on this feature.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193739 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 09:32:11 +00:00
Chad Rosier
f853a034a1
[AArch64] Add support for NEON scalar floating-point compare instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193691 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 15:19:37 +00:00
Rafael Espindola
ffc7dca885
Add a helper getSymbol to AsmPrinter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193627 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 17:07:16 +00:00
Weiming Zhao
160a14e2b1
[AArch64] Implement FrameAddr and ReturnAddr
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Fixes PR17690
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193625 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 17:00:25 +00:00
Tim Northover
fd4937fe2a
AArch64: add 'a' inline asm operand modifier
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This is used in the Linux kernel, and effectively just means "print an
address".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193593 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 08:22:33 +00:00
Nadav Rotem
97541d400e
Optimize concat_vectors(X, undef) -> scalar_to_vector(X).
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This optimization is not SSE specific so I am moving it to DAGco.
The new scalar_to_vector dag node exposed a missing pattern in the AArch64 target that I needed to add.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193393 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-25 06:41:18 +00:00
Amara Emerson
2f21452ba1
[AArch64] Fix NZCV reg live-in bug in F128CSEL codegen.
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When generating the IfTrue basic block during the F128CSEL pseudo-instruction
handling, the NZCV live-in for the newly created BB wasn't being added. This
caused a fault during MI-sched/live range calculation when the predecessor
for the fall-through BB didn't have a live-in for phys-reg as expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193316 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-24 08:28:24 +00:00
Chad Rosier
b5eae81267
[AArch64] Add the constraint to NEON scalar mla/mls instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193117 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-21 20:11:47 +00:00
Chad Rosier
c439c205ba
[AArch64] Add support for NEON scalar extract narrow instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192970 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-18 14:03:24 +00:00
Chad Rosier
3b370a2ac4
[AArch64] Add support for NEON scalar three register different instruction
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class. The instruction class includes the signed saturating doubling
multiply-add long, signed saturating doubling multiply-subtract long, and
the signed saturating doubling multiply long instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192908 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-17 18:12:29 +00:00
Chad Rosier
dceac4c5a6
[AArch64] Add support for NEON scalar negate instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192843 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-16 21:04:39 +00:00
Chad Rosier
a249914462
[AArch64] Add support for NEON scalar absolute value instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192842 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-16 21:04:34 +00:00
Chad Rosier
f4a0567d3c
Fix comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192805 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-16 16:22:15 +00:00
Chad Rosier
a2cd42a0a7
[AArch64] Add support for NEON scalar signed saturating accumulated of unsigned
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value and unsigned saturating accumulate of signed value instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192800 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-16 16:09:02 +00:00
Rafael Espindola
06957f43f6
Add a MCAsmInfoELF class and factor some code into it.
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We had a MCAsmInfoCOFF, but no common class for all the ELF MCAsmInfos before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192760 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-16 01:34:32 +00:00
Chad Rosier
1824bd0ef8
[AArch64] Add support for NEON scalar signed saturating absolute value and
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scalar signed saturating negate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192733 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-15 21:18:44 +00:00
Chad Rosier
942827b113
[AArch64] Add support for NEON scalar integer compare instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192596 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-14 14:37:20 +00:00
Kevin Qin
767f816b92
Implement aarch64 neon instruction set AdvSIMD (copy).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192410 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-11 02:33:55 +00:00
Hao Liu
6a5a667517
Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem).
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Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192361 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-10 17:00:52 +00:00
Rafael Espindola
812ddcc50f
Revert "Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4)."
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This reverts commit r192352. It broke the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192354 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-10 15:15:17 +00:00
Hao Liu
d622bef31d
Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem).
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Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192352 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-10 15:01:24 +00:00
Tim Northover
d29bae8bc9
AArch64: enable MISched by default.
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Substantial SelectionDAG scheduling is going away soon, and is
interfering with Hao's attempts to implement LDn/STn instructions, so
I say we make the leap first.
There were a few reorderings (inevitably) which broke some tests. I
tried to replace them with CHECK-DAG variants mostly, but some too
complex for that to be useful and I just reordered them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192282 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-09 07:53:57 +00:00
Chad Rosier
c976500793
[AArch64] Add support for NEON scalar floating-point reciprocal estimate,
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reciprocal exponent, and reciprocal square root estimate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192242 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-08 22:09:04 +00:00
Chad Rosier
3dfe644f7b
[AArch64] Add support for NEON scalar signed/unsigned integer to floating-point
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convert instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192231 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-08 20:43:30 +00:00
Rafael Espindola
320296a4cf
Add a MCTargetStreamer interface.
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This patch fixes an old FIXME by creating a MCTargetStreamer interface
and moving the target specific functions for ARM, Mips and PPC to it.
The ARM streamer is still declared in a common place because it is
used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are
completely hidden in the corresponding Target directories.
I will send an email to llvmdev with instructions on how to use this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192181 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-08 13:08:17 +00:00
Chad Rosier
2aeb4771a6
[AArch64] Add support for NEON scalar arithmetic instructions:
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SQDMULH, SQRDMULH, FMULX, FRECPS, and FRSQRTS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192107 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 16:36:15 +00:00
Jiangning Liu
beb6afa843
Implement aarch64 neon instruction set AdvSIMD (Across).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192028 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 08:22:10 +00:00
Jiangning Liu
dd518bcc9d
Implement aarch64 neon instruction set AdvSIMD (3V elem).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191944 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-04 09:20:44 +00:00
Jiangning Liu
477fc628b3
Initial support for Neon scalar instructions.
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Patch by Ana Pazos.
1.Added support for v1ix and v1fx types.
2.Added Scalar Pairwise Reduce instructions.
3.Added initial implementation of Scalar Arithmetic instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191263 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-24 02:47:27 +00:00
Tim Northover
3e84ad28d4
ISelDAG: spot chain cycles involving MachineNodes
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Previously, the DAGISel function WalkChainUsers was spotting that it
had entered already-selected territory by whether a node was a
MachineNode (amongst other things). Since it's fairly common practice
to insert MachineNodes during ISelLowering, this was not the correct
check.
Looking around, it seems that other nodes get their NodeId set to -1
upon selection, so this makes sure the same thing happens to all
MachineNodes and uses that characteristic to determine whether we
should stop looking for a loop during selection.
This should fix PR15840.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191165 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-22 08:21:56 +00:00
Richard Mitton
5cc319a42a
Added support for generate DWARF .debug_aranges sections automatically.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191052 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-19 23:21:01 +00:00
Kevin Qin
e54360be01
Implement 3 AArch64 neon instructions : umov smov ins.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190839 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-17 02:21:02 +00:00
Tim Northover
630c5e06d6
AArch64: use RegisterOperand for NEON registers.
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Previously we modelled VPR128 and VPR64 as essentially identical
register-classes containing V0-V31 (which had Q0-Q31 as "sub_alias"
sub-registers). This model is starting to cause significant problems
for code generation, particularly writing EXTRACT/INSERT_SUBREG
patterns for converting between the two.
The change here switches to classifying VPR64 & VPR128 as
RegisterOperands, which are essentially aliases for RegisterClasses
with different parsing and printing behaviour. This fits almost
exactly with their real status (VPR128 == FPR128 printed strangely,
VPR64 == FPR64 printed strangely).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190665 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-13 07:26:52 +00:00
Joey Gouly
715d98d657
Add an instruction deprecation feature to TableGen.
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The 'Deprecated' class allows you to specify a SubtargetFeature that the
instruction is deprecated on.
The 'ComplexDeprecationPredicate' class allows you to define a custom
predicate that is called to check for deprecation.
For example:
ComplexDeprecationPredicate<"MCR">
would mean you would have to define the following function:
bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
std::string &Info)
Which returns 'false' for not deprecated, and 'true' for deprecated
and store the warning message in 'Info'.
The MCTargetAsmParser constructor was chaned to take an extra argument of
the MCInstrInfo class, so out-of-tree targets will need to be changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190598 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-12 10:28:05 +00:00