Dan Gohman
f350b277f3
Move the point at which FastISel taps into the SelectionDAGISel
...
process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.
Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.
To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55219 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-23 02:25:05 +00:00
Dan Gohman
ad3460c3c9
Simplify SelectRoot's interface, and factor out some common code
...
from all targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55124 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-21 16:36:34 +00:00
Dan Gohman
475871a144
Rename SDOperand to SDValue.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54128 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-27 21:46:04 +00:00
Dan Gohman
e8be6c6391
Add a new function, ReplaceAllUsesOfValuesWith, which handles bulk
...
replacement of multiple values. This is slightly more efficient
than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically
could be optimized even further. However, an important property of this
new function is that it handles the case where the source value set and
destination value set overlap. This makes it feasible for isel to use
SelectNodeTo in many very common cases, which is advantageous because
SelectNodeTo avoids a temporary node and it doesn't require CSEMap
updates for users of values that don't change position.
Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to
handle operand lists more efficiently, and to correctly handle a number
of corner cases to which its new wider use exposes it.
This commit also includes a change to the encoding of post-isel opcodes
in SDNodes; now instead of being sandwiched between the target-independent
pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel
opcodes are now represented as negative values. This makes it possible
to test if an opcode is pre-isel or post-isel without having to know
the size of the current target's post-isel instruction set.
These changes speed up llc overall by 3% and reduce memory usage by 10%
on the InstructionCombining.cpp testcase with -fast and -regalloc=local.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53728 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-17 19:10:17 +00:00
Dan Gohman
1002c02034
Add explicit keywords.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53179 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-07 18:00:37 +00:00
Evan Cheng
db8d56b825
Split scheduling from instruction selection.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52923 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-30 20:45:06 +00:00
Duncan Sands
83ec4b6711
Wrap MVT::ValueType in a struct to get type safety
...
and better control the abstraction. Rename the type
to MVT. To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits(). Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-06 12:08:01 +00:00
Evan Cheng
4e3f5a4e9c
Dwarf requires variable entries to be in the source order. Right now, since we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46724 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-04 23:06:48 +00:00
Chris Lattner
3d62d780ab
explicitly include Compiler.h instead of getting it from tblgen in the middle of a class.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46676 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 05:43:57 +00:00
Chris Lattner
a47b9bcbde
don't do ReplaceUses on a result that doesn't exist.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46673 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 03:20:59 +00:00
Evan Cheng
a844bdeab3
SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc.
...
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46659 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-02 04:07:54 +00:00
Dan Gohman
b625f2f896
Factor the addressing mode and the load/store VT out of LoadSDNode
...
and StoreSDNode into their common base class LSBaseSDNode. Member
functions getLoadedVT and getStoredVT are replaced with the common
getMemoryVT to simplify code that will handle both loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46538 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-30 00:15:11 +00:00
Chris Lattner
84bc5427d6
Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
...
that "machine" classes are used to represent the current state of
the code being compiled. Given this expanded name, we can start
moving other stuff into it. For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.
Update all the clients to match.
This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45467 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-31 04:13:23 +00:00
Chris Lattner
4ee451de36
Remove attribution from file headers, per discussion on llvmdev.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-29 20:36:04 +00:00
Dan Gohman
525178cdbf
Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to
...
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42762 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-08 18:33:35 +00:00
Evan Cheng
13ab020ea0
Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38501 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-10 18:08:01 +00:00
Evan Cheng
ee568cf794
Unfortunately we now require C++ code to isel Bcc, conditional moves, etc.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37896 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-05 07:15:27 +00:00
Evan Cheng
44bec52b1b
Add PredicateOperand to all ARM instructions that have the condition field.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37066 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-15 01:29:07 +00:00
Chris Lattner
72939126d4
match a reassociated form of fnmul. This implements CodeGen/ARM/fnmul.ll
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36660 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-03 00:32:00 +00:00
Evan Cheng
9f6636ff0c
Fix naming inconsistencies.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35163 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-19 07:48:02 +00:00
Evan Cheng
fa775d09c6
Special LDR instructions to load from non-pc-relative constantpools. These are
...
rematerializable. Only used for constant generation for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35162 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-19 07:20:03 +00:00
Evan Cheng
a13fd108f2
AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2 ]
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35088 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-13 21:05:54 +00:00
Evan Cheng
8fdbe560a0
Get rid of references to iostream.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34009 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-07 21:18:32 +00:00
Evan Cheng
8c1a73ad3f
Select add FI, c correctly.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33960 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-06 09:11:20 +00:00
Evan Cheng
ad0e465889
- Store val, [sp, c] must be selected to tSTRsp.
...
- If c does not fit in the offset field, materialize sp + c into a register
using tADDhirr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33944 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-06 00:22:06 +00:00
Evan Cheng
cea117d2de
Change the operand orders to t_addrmode_s* to make it easier to morph
...
instructions that use these address modes to instructions that use
t_addrmode_sp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33651 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-30 02:35:32 +00:00
Evan Cheng
012f2d97b7
Use PC relative ldr to load from a constantpool in Thumb mode.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33484 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-24 08:53:17 +00:00
Evan Cheng
e966d6415c
Allow [ fi#c, imm ] as ARM load / store addresses.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33474 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-24 02:45:25 +00:00
Evan Cheng
79d4326b00
Various Thumb mode load / store isel bug fixes.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33472 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-24 02:21:22 +00:00
Evan Cheng
c38f2bc3c2
- Reorg Thumb load / store instructions. Combine each rr and ri pair of
...
instructions into one (e.g. tLDRrr, tLDRri -> tLDR).
- Thumb ldrsb and ldrsh only have the [reg, reg] address format. If the
address is not an add, materialize a 0 immediate into a register and use
it as the offset field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33470 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-23 22:59:13 +00:00
Evan Cheng
a8e2989ece
ARM backend contribution from Apple.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33353 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-19 07:51:42 +00:00
Lauro Ramos Venancio
a38bbf7dd3
Build constants using instructions mov/orr or mvn/eor.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33141 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-12 20:35:49 +00:00
Lauro Ramos Venancio
ca1f66db0d
Expand SELECT (f32/f64) and FCOPYSIGN (f32/f64).
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32870 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-04 14:01:38 +00:00
Rafael Espindola
9985f9f61e
implement missing compares
...
patch by Lauro
bug fixed by me
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32795 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-31 18:52:39 +00:00
Reid Spencer
47857812e2
For PR950:
...
Three changes:
1. Convert signed integer types to signless versions.
2. Implement the @sext and @zext parameter attributes. Previously the
type of an function parameter was used to determine whether it should
be sign extended or zero extended before the call. This information is
now communicated via the function type's parameter attributes.
3. The interface to LowerCallTo had to be changed in order to accommodate
the parameter attribute information. Although it would have been
convenient to pass in the FunctionType itself, there isn't always one
present in the caller. Consequently, a signedness indication for the
result type and for each parameter was provided for in the interface
to this method. All implementations were changed to make the adjustment
necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32788 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-31 05:55:36 +00:00
Rafael Espindola
0cc2bd12d2
fix comment
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32767 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-29 14:28:12 +00:00
Lauro Ramos Venancio
301009a0fc
Implement SELECT_CC (f32/f64) for ARM.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32762 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-28 13:11:14 +00:00
Rafael Espindola
8897a7b02e
avoid using a constant table when a constant can be used inline
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32580 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-14 18:58:37 +00:00
Rafael Espindola
a898ce687a
more general matching of the MVN instruction
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32484 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-12 17:10:13 +00:00
Rafael Espindola
2426775c81
don't use "ordinary" addressing mode 1 when mvn is appropriate
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32482 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-12 14:03:29 +00:00
Rafael Espindola
f64945d83c
use MVN to handle small negative constants
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32459 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-12 01:03:11 +00:00
Bill Wendling
f5da13367f
What should be the last unnecessary <iostream>s in the library.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32333 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-07 22:21:48 +00:00
Rafael Espindola
97815c6b9c
expand memmove and memcpy
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32226 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-05 17:57:23 +00:00
Rafael Espindola
462af9a2e0
add support for the "r" asm constraint
...
patch by Lauro Ramos Venancio
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32224 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-05 17:37:31 +00:00
Rafael Espindola
f819a4999a
implement load effective address similar to the alpha backend
...
remove lea_addri and the now unused memri addressing mode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31592 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-09 13:58:55 +00:00
Evan Cheng
0d53826f36
Match tblegen changes.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31571 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-08 20:34:28 +00:00
Rafael Espindola
6e8c6493f0
initial implementation of addressing mode 2
...
TODO: fix lea_addri
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31552 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-08 17:07:32 +00:00
Rafael Espindola
e931a37a4e
move ARMCondCodeToString to ARMAsmPrinter.cpp
...
remove unused variables from lowerCall
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31378 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-02 15:00:02 +00:00
Evan Cheng
c35497fc2a
All targets expand BR_JT for now.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31294 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-30 08:02:39 +00:00
Rafael Espindola
7ae68ab3bc
initial support for frame pointers
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31197 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-26 13:31:26 +00:00
Rafael Espindola
0e5e3aacbe
expand ISD::VACOPY
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31170 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-24 20:15:21 +00:00
Rafael Espindola
d8ed7f8cde
expand ISD::MEMSET
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31137 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-23 20:08:22 +00:00
Reid Spencer
b83eb6447b
For PR950:
...
This patch implements the first increment for the Signless Types feature.
All changes pertain to removing the ConstantSInt and ConstantUInt classes
in favor of just using ConstantInt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31063 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-20 07:07:24 +00:00
Rafael Espindola
6495bdd8d2
expand SIGN_EXTEND_INREG
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31046 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-19 12:06:50 +00:00
Rafael Espindola
4749aa4ea3
expand brind so that we don't have to implement jump tables right now
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31045 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-19 10:56:43 +00:00
Rafael Espindola
5f1b698aeb
implement CallingConv::Fast as CallingConv::C
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31034 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-18 12:03:07 +00:00
Rafael Espindola
226f8bc38c
expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31014 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-17 21:05:33 +00:00
Rafael Espindola
32bd5f4f6a
initial implementation of addressing mode 5
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31002 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-17 18:04:53 +00:00
Rafael Espindola
0505be03ad
expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30987 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-16 21:10:32 +00:00
Rafael Espindola
d2b5668208
expand ISD::BRCOND
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30963 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-14 17:59:54 +00:00
Rafael Espindola
6c5ae3edd3
fix some fp condition codes
...
use non trapping comparison instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30962 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-14 13:42:53 +00:00
Evan Cheng
8b2794aeff
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30945 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-13 21:14:26 +00:00
Rafael Espindola
26a76d1024
implement calls to functions that return long
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30929 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-13 16:47:22 +00:00
Rafael Espindola
42b62f3f81
implement unordered floating point compares
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30928 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-13 13:14:59 +00:00
Rafael Espindola
493a7fc5c3
uint <-> double conversion
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30862 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-10 20:38:57 +00:00
Rafael Espindola
b47e1d033c
add double <-> int conversion
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30858 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-10 18:55:14 +00:00
Rafael Espindola
0d9fe764df
compare doubles
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30856 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-10 16:33:47 +00:00
Rafael Espindola
4b20fbc01d
initial support for fp compares. Unordered compares not implemented yet
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30854 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-10 12:56:00 +00:00
Evan Cheng
466685d41a
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30844 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-09 20:57:25 +00:00
Rafael Espindola
48bc9fbf19
expand ISD::SELECT
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30829 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-09 16:28:33 +00:00
Rafael Espindola
ad557f9d11
expand ISD::EXTLOAD
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30827 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-09 14:13:40 +00:00
Rafael Espindola
e5bbd6d753
implement FUITOS and FUITOD
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30803 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-07 14:24:52 +00:00
Rafael Espindola
935b1f8fce
add optional input flag to FMRRD
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30774 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-06 20:33:26 +00:00
Rafael Espindola
614057b843
add support for calling functions that return double
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30771 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-06 19:10:05 +00:00
Rafael Espindola
af1dabef35
fix some bugs affecting functions with no arguments
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30767 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-06 17:26:30 +00:00
Rafael Espindola
4a408d46d4
add support for calling functions that have double arguments
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30765 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-06 12:50:22 +00:00
Evan Cheng
786225adf0
Make use of getStore().
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30759 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-05 23:01:46 +00:00
Rafael Espindola
39b5a21259
use a const ref for passing the vector to ArgumentLayout
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30756 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-05 17:46:48 +00:00
Rafael Espindola
a284584352
implement a ArgumentLayout class to factor code common to LowerFORMAL_ARGUMENTS and LowerCALL
...
implement FMDRR
add support for f64 function arguments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30754 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-05 16:48:49 +00:00
Rafael Espindola
cd71da5cf0
Implement floating point constants
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30704 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-03 17:27:58 +00:00
Rafael Espindola
9e071f0ae3
fix the names of the 64bit fp register
...
initial support for returning 64bit floating point numbers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30692 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-02 19:30:56 +00:00
Rafael Espindola
27185190e6
add floating point registers
...
implement SINT_TO_FP
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30673 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-29 21:20:16 +00:00
Rafael Espindola
ebdabda708
more condition codes
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30567 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-21 13:06:26 +00:00
Rafael Espindola
7246d33e2a
if a constant can't be an immediate, add it to the constant pool
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30566 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-21 11:29:52 +00:00
Rafael Espindola
3ad5e5cf99
add shifts to addressing mode 1
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30291 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-13 12:09:43 +00:00
Evan Cheng
c356a572e3
Reflects MachineConstantPoolEntry changes.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30279 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-12 21:04:05 +00:00
Rafael Espindola
1b3956b516
add the correct fallback for ARMDAGToDAGISel::SelectAddrMode1
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30261 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-11 19:23:32 +00:00
Rafael Espindola
7cca7c5317
partial implementation of the ARM Addressing Mode 1
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30252 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-11 17:25:40 +00:00
Rafael Espindola
3a02f020eb
add support for returning 64bit values
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30103 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-04 19:05:01 +00:00
Rafael Espindola
bc4cec9a62
add the SETULT condition code
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30067 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-03 13:19:16 +00:00
Rafael Espindola
5f450d2948
add more condition codes
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30056 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-02 20:24:25 +00:00
Evan Cheng
9ade218533
Select() no longer require Result operand by reference.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29898 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-26 05:34:46 +00:00
Rafael Espindola
755be9b3de
use @ for comments
...
store LR in an arbitrary stack slot
add support for writing varargs functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29876 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-25 17:55:16 +00:00
Rafael Espindola
cdda88cd12
add the "eq" condition code
...
implement a movcond instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29857 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-24 17:19:08 +00:00
Rafael Espindola
6f602de3b6
create a generic bcond instruction that has a conditional code argument
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29856 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-24 16:13:15 +00:00
Rafael Espindola
687bc49d1a
initial support for branches
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29854 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-24 13:45:55 +00:00
Rafael Espindola
3c000bf817
initial support for select
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29802 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-21 22:00:32 +00:00
Rafael Espindola
3717ca965b
call computeRegisterProperties
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29780 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-20 01:49:49 +00:00
Rafael Espindola
f3a335cedf
add a "load effective address"
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29748 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-17 17:09:40 +00:00
Rafael Espindola
ec46ea34dc
Declare the callee saved regs
...
Remove the hard coded store and load of the link register
Implement ARMFrameInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29727 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-16 14:43:33 +00:00